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Commit | Line | Data |
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29310e5e GS |
1 | /* |
2 | * The file intends to implement the platform dependent EEH operations on | |
3 | * powernv platform. Actually, the powernv was created in order to fully | |
4 | * hypervisor support. | |
5 | * | |
6 | * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/atomic.h> | |
4cf17445 | 15 | #include <linux/debugfs.h> |
29310e5e GS |
16 | #include <linux/delay.h> |
17 | #include <linux/export.h> | |
18 | #include <linux/init.h> | |
79231448 | 19 | #include <linux/interrupt.h> |
29310e5e GS |
20 | #include <linux/list.h> |
21 | #include <linux/msi.h> | |
22 | #include <linux/of.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/proc_fs.h> | |
25 | #include <linux/rbtree.h> | |
26 | #include <linux/sched.h> | |
27 | #include <linux/seq_file.h> | |
28 | #include <linux/spinlock.h> | |
29 | ||
30 | #include <asm/eeh.h> | |
31 | #include <asm/eeh_event.h> | |
32 | #include <asm/firmware.h> | |
33 | #include <asm/io.h> | |
34 | #include <asm/iommu.h> | |
35 | #include <asm/machdep.h> | |
36 | #include <asm/msi_bitmap.h> | |
37 | #include <asm/opal.h> | |
38 | #include <asm/ppc-pci.h> | |
39 | ||
40 | #include "powernv.h" | |
41 | #include "pci.h" | |
42 | ||
4cf17445 | 43 | static bool pnv_eeh_nb_init = false; |
79231448 | 44 | static int eeh_event_irq = -EINVAL; |
4cf17445 | 45 | |
01f3bfb7 | 46 | static int pnv_eeh_init(void) |
29310e5e | 47 | { |
dc561fb9 GS |
48 | struct pci_controller *hose; |
49 | struct pnv_phb *phb; | |
50 | ||
e4d54f71 SS |
51 | if (!firmware_has_feature(FW_FEATURE_OPAL)) { |
52 | pr_warn("%s: OPAL is required !\n", | |
0dae2743 | 53 | __func__); |
29310e5e GS |
54 | return -EINVAL; |
55 | } | |
56 | ||
05b1721d GS |
57 | /* Set probe mode */ |
58 | eeh_add_flag(EEH_PROBE_MODE_DEV); | |
29310e5e | 59 | |
dc561fb9 GS |
60 | /* |
61 | * P7IOC blocks PCI config access to frozen PE, but PHB3 | |
62 | * doesn't do that. So we have to selectively enable I/O | |
63 | * prior to collecting error log. | |
64 | */ | |
65 | list_for_each_entry(hose, &hose_list, list_node) { | |
66 | phb = hose->private_data; | |
67 | ||
68 | if (phb->model == PNV_PHB_MODEL_P7IOC) | |
69 | eeh_add_flag(EEH_ENABLE_IO_FOR_LOG); | |
2aa5cf9e GS |
70 | |
71 | /* | |
72 | * PE#0 should be regarded as valid by EEH core | |
73 | * if it's not the reserved one. Currently, we | |
608fb9c2 | 74 | * have the reserved PE#255 and PE#127 for PHB3 |
2aa5cf9e | 75 | * and P7IOC separately. So we should regard |
608fb9c2 | 76 | * PE#0 as valid for PHB3 and P7IOC. |
2aa5cf9e GS |
77 | */ |
78 | if (phb->ioda.reserved_pe != 0) | |
79 | eeh_add_flag(EEH_VALID_PE_ZERO); | |
80 | ||
dc561fb9 GS |
81 | break; |
82 | } | |
83 | ||
29310e5e GS |
84 | return 0; |
85 | } | |
86 | ||
79231448 | 87 | static irqreturn_t pnv_eeh_event(int irq, void *data) |
4cf17445 | 88 | { |
4cf17445 | 89 | /* |
79231448 AP |
90 | * We simply send a special EEH event if EEH has been |
91 | * enabled. We don't care about EEH events until we've | |
92 | * finished processing the outstanding ones. Event processing | |
93 | * gets unmasked in next_error() if EEH is enabled. | |
4cf17445 | 94 | */ |
79231448 | 95 | disable_irq_nosync(irq); |
4cf17445 GS |
96 | |
97 | if (eeh_enabled()) | |
98 | eeh_send_failure_event(NULL); | |
4cf17445 | 99 | |
79231448 | 100 | return IRQ_HANDLED; |
4cf17445 GS |
101 | } |
102 | ||
4cf17445 GS |
103 | #ifdef CONFIG_DEBUG_FS |
104 | static ssize_t pnv_eeh_ei_write(struct file *filp, | |
105 | const char __user *user_buf, | |
106 | size_t count, loff_t *ppos) | |
107 | { | |
108 | struct pci_controller *hose = filp->private_data; | |
109 | struct eeh_dev *edev; | |
110 | struct eeh_pe *pe; | |
111 | int pe_no, type, func; | |
112 | unsigned long addr, mask; | |
113 | char buf[50]; | |
114 | int ret; | |
115 | ||
116 | if (!eeh_ops || !eeh_ops->err_inject) | |
117 | return -ENXIO; | |
118 | ||
119 | /* Copy over argument buffer */ | |
120 | ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count); | |
121 | if (!ret) | |
122 | return -EFAULT; | |
123 | ||
124 | /* Retrieve parameters */ | |
125 | ret = sscanf(buf, "%x:%x:%x:%lx:%lx", | |
126 | &pe_no, &type, &func, &addr, &mask); | |
127 | if (ret != 5) | |
128 | return -EINVAL; | |
129 | ||
130 | /* Retrieve PE */ | |
131 | edev = kzalloc(sizeof(*edev), GFP_KERNEL); | |
132 | if (!edev) | |
133 | return -ENOMEM; | |
134 | edev->phb = hose; | |
135 | edev->pe_config_addr = pe_no; | |
136 | pe = eeh_pe_get(edev); | |
137 | kfree(edev); | |
138 | if (!pe) | |
139 | return -ENODEV; | |
140 | ||
141 | /* Do error injection */ | |
142 | ret = eeh_ops->err_inject(pe, type, func, addr, mask); | |
143 | return ret < 0 ? ret : count; | |
144 | } | |
145 | ||
146 | static const struct file_operations pnv_eeh_ei_fops = { | |
147 | .open = simple_open, | |
148 | .llseek = no_llseek, | |
149 | .write = pnv_eeh_ei_write, | |
150 | }; | |
151 | ||
152 | static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val) | |
153 | { | |
154 | struct pci_controller *hose = data; | |
155 | struct pnv_phb *phb = hose->private_data; | |
156 | ||
157 | out_be64(phb->regs + offset, val); | |
158 | return 0; | |
159 | } | |
160 | ||
161 | static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val) | |
162 | { | |
163 | struct pci_controller *hose = data; | |
164 | struct pnv_phb *phb = hose->private_data; | |
165 | ||
166 | *val = in_be64(phb->regs + offset); | |
167 | return 0; | |
168 | } | |
169 | ||
170 | static int pnv_eeh_outb_dbgfs_set(void *data, u64 val) | |
171 | { | |
172 | return pnv_eeh_dbgfs_set(data, 0xD10, val); | |
173 | } | |
174 | ||
175 | static int pnv_eeh_outb_dbgfs_get(void *data, u64 *val) | |
176 | { | |
177 | return pnv_eeh_dbgfs_get(data, 0xD10, val); | |
178 | } | |
179 | ||
180 | static int pnv_eeh_inbA_dbgfs_set(void *data, u64 val) | |
181 | { | |
182 | return pnv_eeh_dbgfs_set(data, 0xD90, val); | |
183 | } | |
184 | ||
185 | static int pnv_eeh_inbA_dbgfs_get(void *data, u64 *val) | |
186 | { | |
187 | return pnv_eeh_dbgfs_get(data, 0xD90, val); | |
188 | } | |
189 | ||
190 | static int pnv_eeh_inbB_dbgfs_set(void *data, u64 val) | |
191 | { | |
192 | return pnv_eeh_dbgfs_set(data, 0xE10, val); | |
193 | } | |
194 | ||
195 | static int pnv_eeh_inbB_dbgfs_get(void *data, u64 *val) | |
196 | { | |
197 | return pnv_eeh_dbgfs_get(data, 0xE10, val); | |
198 | } | |
199 | ||
200 | DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_outb_dbgfs_ops, pnv_eeh_outb_dbgfs_get, | |
201 | pnv_eeh_outb_dbgfs_set, "0x%llx\n"); | |
202 | DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_inbA_dbgfs_ops, pnv_eeh_inbA_dbgfs_get, | |
203 | pnv_eeh_inbA_dbgfs_set, "0x%llx\n"); | |
204 | DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_inbB_dbgfs_ops, pnv_eeh_inbB_dbgfs_get, | |
205 | pnv_eeh_inbB_dbgfs_set, "0x%llx\n"); | |
206 | #endif /* CONFIG_DEBUG_FS */ | |
207 | ||
29310e5e | 208 | /** |
01f3bfb7 | 209 | * pnv_eeh_post_init - EEH platform dependent post initialization |
29310e5e GS |
210 | * |
211 | * EEH platform dependent post initialization on powernv. When | |
212 | * the function is called, the EEH PEs and devices should have | |
213 | * been built. If the I/O cache staff has been built, EEH is | |
214 | * ready to supply service. | |
215 | */ | |
01f3bfb7 | 216 | static int pnv_eeh_post_init(void) |
29310e5e GS |
217 | { |
218 | struct pci_controller *hose; | |
219 | struct pnv_phb *phb; | |
220 | int ret = 0; | |
221 | ||
4cf17445 GS |
222 | /* Register OPAL event notifier */ |
223 | if (!pnv_eeh_nb_init) { | |
79231448 AP |
224 | eeh_event_irq = opal_event_request(ilog2(OPAL_EVENT_PCI_ERROR)); |
225 | if (eeh_event_irq < 0) { | |
226 | pr_err("%s: Can't register OPAL event interrupt (%d)\n", | |
227 | __func__, eeh_event_irq); | |
228 | return eeh_event_irq; | |
229 | } | |
230 | ||
231 | ret = request_irq(eeh_event_irq, pnv_eeh_event, | |
232 | IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL); | |
233 | if (ret < 0) { | |
234 | irq_dispose_mapping(eeh_event_irq); | |
235 | pr_err("%s: Can't request OPAL event interrupt (%d)\n", | |
236 | __func__, eeh_event_irq); | |
4cf17445 GS |
237 | return ret; |
238 | } | |
239 | ||
240 | pnv_eeh_nb_init = true; | |
241 | } | |
242 | ||
79231448 AP |
243 | if (!eeh_enabled()) |
244 | disable_irq(eeh_event_irq); | |
245 | ||
29310e5e GS |
246 | list_for_each_entry(hose, &hose_list, list_node) { |
247 | phb = hose->private_data; | |
248 | ||
4cf17445 GS |
249 | /* |
250 | * If EEH is enabled, we're going to rely on that. | |
251 | * Otherwise, we restore to conventional mechanism | |
252 | * to clear frozen PE during PCI config access. | |
253 | */ | |
254 | if (eeh_enabled()) | |
255 | phb->flags |= PNV_PHB_FLAG_EEH; | |
256 | else | |
257 | phb->flags &= ~PNV_PHB_FLAG_EEH; | |
258 | ||
259 | /* Create debugfs entries */ | |
260 | #ifdef CONFIG_DEBUG_FS | |
261 | if (phb->has_dbgfs || !phb->dbgfs) | |
262 | continue; | |
263 | ||
264 | phb->has_dbgfs = 1; | |
265 | debugfs_create_file("err_injct", 0200, | |
266 | phb->dbgfs, hose, | |
267 | &pnv_eeh_ei_fops); | |
268 | ||
269 | debugfs_create_file("err_injct_outbound", 0600, | |
270 | phb->dbgfs, hose, | |
271 | &pnv_eeh_outb_dbgfs_ops); | |
272 | debugfs_create_file("err_injct_inboundA", 0600, | |
273 | phb->dbgfs, hose, | |
274 | &pnv_eeh_inbA_dbgfs_ops); | |
275 | debugfs_create_file("err_injct_inboundB", 0600, | |
276 | phb->dbgfs, hose, | |
277 | &pnv_eeh_inbB_dbgfs_ops); | |
278 | #endif /* CONFIG_DEBUG_FS */ | |
29310e5e GS |
279 | } |
280 | ||
281 | return ret; | |
282 | } | |
283 | ||
4d6186ca | 284 | static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap) |
ff57b454 | 285 | { |
4d6186ca GS |
286 | int pos = PCI_CAPABILITY_LIST; |
287 | int cnt = 48; /* Maximal number of capabilities */ | |
288 | u32 status, id; | |
ff57b454 GS |
289 | |
290 | if (!pdn) | |
291 | return 0; | |
292 | ||
4d6186ca | 293 | /* Check if the device supports capabilities */ |
ff57b454 GS |
294 | pnv_pci_cfg_read(pdn, PCI_STATUS, 2, &status); |
295 | if (!(status & PCI_STATUS_CAP_LIST)) | |
296 | return 0; | |
297 | ||
ff57b454 GS |
298 | while (cnt--) { |
299 | pnv_pci_cfg_read(pdn, pos, 1, &pos); | |
300 | if (pos < 0x40) | |
301 | break; | |
302 | ||
303 | pos &= ~3; | |
304 | pnv_pci_cfg_read(pdn, pos + PCI_CAP_LIST_ID, 1, &id); | |
305 | if (id == 0xff) | |
306 | break; | |
307 | ||
308 | /* Found */ | |
309 | if (id == cap) | |
310 | return pos; | |
311 | ||
312 | /* Next one */ | |
313 | pos += PCI_CAP_LIST_NEXT; | |
314 | } | |
315 | ||
316 | return 0; | |
317 | } | |
318 | ||
319 | static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap) | |
320 | { | |
321 | struct eeh_dev *edev = pdn_to_eeh_dev(pdn); | |
322 | u32 header; | |
323 | int pos = 256, ttl = (4096 - 256) / 8; | |
324 | ||
325 | if (!edev || !edev->pcie_cap) | |
326 | return 0; | |
327 | if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) | |
328 | return 0; | |
329 | else if (!header) | |
330 | return 0; | |
331 | ||
332 | while (ttl-- > 0) { | |
333 | if (PCI_EXT_CAP_ID(header) == cap && pos) | |
334 | return pos; | |
335 | ||
336 | pos = PCI_EXT_CAP_NEXT(header); | |
337 | if (pos < 256) | |
338 | break; | |
339 | ||
340 | if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) | |
341 | break; | |
342 | } | |
343 | ||
344 | return 0; | |
345 | } | |
346 | ||
29310e5e | 347 | /** |
ff57b454 GS |
348 | * pnv_eeh_probe - Do probe on PCI device |
349 | * @pdn: PCI device node | |
350 | * @data: unused | |
29310e5e GS |
351 | * |
352 | * When EEH module is installed during system boot, all PCI devices | |
353 | * are checked one by one to see if it supports EEH. The function | |
354 | * is introduced for the purpose. By default, EEH has been enabled | |
355 | * on all PCI devices. That's to say, we only need do necessary | |
356 | * initialization on the corresponding eeh device and create PE | |
357 | * accordingly. | |
358 | * | |
359 | * It's notable that's unsafe to retrieve the EEH device through | |
360 | * the corresponding PCI device. During the PCI device hotplug, which | |
361 | * was possiblly triggered by EEH core, the binding between EEH device | |
362 | * and the PCI device isn't built yet. | |
363 | */ | |
ff57b454 | 364 | static void *pnv_eeh_probe(struct pci_dn *pdn, void *data) |
29310e5e | 365 | { |
ff57b454 | 366 | struct pci_controller *hose = pdn->phb; |
29310e5e | 367 | struct pnv_phb *phb = hose->private_data; |
ff57b454 GS |
368 | struct eeh_dev *edev = pdn_to_eeh_dev(pdn); |
369 | uint32_t pcie_flags; | |
dadcd6d6 | 370 | int ret; |
29310e5e GS |
371 | |
372 | /* | |
373 | * When probing the root bridge, which doesn't have any | |
374 | * subordinate PCI devices. We don't have OF node for | |
375 | * the root bridge. So it's not reasonable to continue | |
376 | * the probing. | |
377 | */ | |
ff57b454 GS |
378 | if (!edev || edev->pe) |
379 | return NULL; | |
29310e5e GS |
380 | |
381 | /* Skip for PCI-ISA bridge */ | |
ff57b454 GS |
382 | if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA) |
383 | return NULL; | |
29310e5e GS |
384 | |
385 | /* Initialize eeh device */ | |
ff57b454 | 386 | edev->class_code = pdn->class_code; |
ab55d218 | 387 | edev->mode &= 0xFFFFFF00; |
ff57b454 GS |
388 | edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX); |
389 | edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP); | |
390 | edev->aer_cap = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR); | |
391 | if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) { | |
4b83bd45 | 392 | edev->mode |= EEH_DEV_BRIDGE; |
ff57b454 GS |
393 | if (edev->pcie_cap) { |
394 | pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS, | |
395 | 2, &pcie_flags); | |
396 | pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4; | |
397 | if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT) | |
398 | edev->mode |= EEH_DEV_ROOT_PORT; | |
399 | else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM) | |
400 | edev->mode |= EEH_DEV_DS_PORT; | |
401 | } | |
4b83bd45 GS |
402 | } |
403 | ||
ff57b454 GS |
404 | edev->config_addr = (pdn->busno << 8) | (pdn->devfn); |
405 | edev->pe_config_addr = phb->ioda.pe_rmap[edev->config_addr]; | |
29310e5e GS |
406 | |
407 | /* Create PE */ | |
dadcd6d6 MQ |
408 | ret = eeh_add_to_parent_pe(edev); |
409 | if (ret) { | |
ff57b454 GS |
410 | pr_warn("%s: Can't add PCI dev %04x:%02x:%02x.%01x to parent PE (%d)\n", |
411 | __func__, hose->global_number, pdn->busno, | |
412 | PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn), ret); | |
413 | return NULL; | |
dadcd6d6 MQ |
414 | } |
415 | ||
b6541db1 GS |
416 | /* |
417 | * If the PE contains any one of following adapters, the | |
418 | * PCI config space can't be accessed when dumping EEH log. | |
419 | * Otherwise, we will run into fenced PHB caused by shortage | |
420 | * of outbound credits in the adapter. The PCI config access | |
421 | * should be blocked until PE reset. MMIO access is dropped | |
422 | * by hardware certainly. In order to drop PCI config requests, | |
423 | * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which | |
424 | * will be checked in the backend for PE state retrival. If | |
425 | * the PE becomes frozen for the first time and the flag has | |
426 | * been set for the PE, we will set EEH_PE_CFG_BLOCKED for | |
427 | * that PE to block its config space. | |
428 | * | |
429 | * Broadcom Austin 4-ports NICs (14e4:1657) | |
353169ac | 430 | * Broadcom Shiner 4-ports 1G NICs (14e4:168a) |
179ea48b | 431 | * Broadcom Shiner 2-ports 10G NICs (14e4:168e) |
b6541db1 | 432 | */ |
ff57b454 GS |
433 | if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && |
434 | pdn->device_id == 0x1657) || | |
353169ac GS |
435 | (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && |
436 | pdn->device_id == 0x168a) || | |
ff57b454 GS |
437 | (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && |
438 | pdn->device_id == 0x168e)) | |
b6541db1 GS |
439 | edev->pe->state |= EEH_PE_CFG_RESTRICTED; |
440 | ||
dadcd6d6 MQ |
441 | /* |
442 | * Cache the PE primary bus, which can't be fetched when | |
443 | * full hotplug is in progress. In that case, all child | |
444 | * PCI devices of the PE are expected to be removed prior | |
445 | * to PE reset. | |
446 | */ | |
05ba75f8 | 447 | if (!(edev->pe->state & EEH_PE_PRI_BUS)) { |
ff57b454 GS |
448 | edev->pe->bus = pci_find_bus(hose->global_number, |
449 | pdn->busno); | |
05ba75f8 GS |
450 | if (edev->pe->bus) |
451 | edev->pe->state |= EEH_PE_PRI_BUS; | |
452 | } | |
29310e5e GS |
453 | |
454 | /* | |
455 | * Enable EEH explicitly so that we will do EEH check | |
456 | * while accessing I/O stuff | |
29310e5e | 457 | */ |
05b1721d | 458 | eeh_add_flag(EEH_ENABLED); |
29310e5e GS |
459 | |
460 | /* Save memory bars */ | |
461 | eeh_save_bars(edev); | |
462 | ||
ff57b454 | 463 | return NULL; |
29310e5e GS |
464 | } |
465 | ||
466 | /** | |
01f3bfb7 | 467 | * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable |
29310e5e GS |
468 | * @pe: EEH PE |
469 | * @option: operation to be issued | |
470 | * | |
471 | * The function is used to control the EEH functionality globally. | |
472 | * Currently, following options are support according to PAPR: | |
473 | * Enable EEH, Disable EEH, Enable MMIO and Enable DMA | |
474 | */ | |
01f3bfb7 | 475 | static int pnv_eeh_set_option(struct eeh_pe *pe, int option) |
29310e5e GS |
476 | { |
477 | struct pci_controller *hose = pe->phb; | |
478 | struct pnv_phb *phb = hose->private_data; | |
7e3e4f8d | 479 | bool freeze_pe = false; |
f9433718 | 480 | int opt; |
7e3e4f8d GS |
481 | s64 rc; |
482 | ||
7e3e4f8d GS |
483 | switch (option) { |
484 | case EEH_OPT_DISABLE: | |
485 | return -EPERM; | |
486 | case EEH_OPT_ENABLE: | |
487 | return 0; | |
488 | case EEH_OPT_THAW_MMIO: | |
489 | opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO; | |
490 | break; | |
491 | case EEH_OPT_THAW_DMA: | |
492 | opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA; | |
493 | break; | |
494 | case EEH_OPT_FREEZE_PE: | |
495 | freeze_pe = true; | |
496 | opt = OPAL_EEH_ACTION_SET_FREEZE_ALL; | |
497 | break; | |
498 | default: | |
499 | pr_warn("%s: Invalid option %d\n", __func__, option); | |
500 | return -EINVAL; | |
501 | } | |
29310e5e | 502 | |
f9433718 | 503 | /* Freeze master and slave PEs if PHB supports compound PEs */ |
7e3e4f8d GS |
504 | if (freeze_pe) { |
505 | if (phb->freeze_pe) { | |
506 | phb->freeze_pe(phb, pe->addr); | |
f9433718 | 507 | return 0; |
7e3e4f8d | 508 | } |
f9433718 GS |
509 | |
510 | rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt); | |
511 | if (rc != OPAL_SUCCESS) { | |
512 | pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", | |
513 | __func__, rc, phb->hose->global_number, | |
514 | pe->addr); | |
515 | return -EIO; | |
7e3e4f8d | 516 | } |
f9433718 GS |
517 | |
518 | return 0; | |
7e3e4f8d | 519 | } |
29310e5e | 520 | |
f9433718 GS |
521 | /* Unfreeze master and slave PEs if PHB supports */ |
522 | if (phb->unfreeze_pe) | |
523 | return phb->unfreeze_pe(phb, pe->addr, opt); | |
524 | ||
525 | rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt); | |
526 | if (rc != OPAL_SUCCESS) { | |
527 | pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n", | |
528 | __func__, rc, option, phb->hose->global_number, | |
529 | pe->addr); | |
530 | return -EIO; | |
531 | } | |
532 | ||
533 | return 0; | |
29310e5e GS |
534 | } |
535 | ||
536 | /** | |
01f3bfb7 | 537 | * pnv_eeh_get_pe_addr - Retrieve PE address |
29310e5e GS |
538 | * @pe: EEH PE |
539 | * | |
540 | * Retrieve the PE address according to the given tranditional | |
541 | * PCI BDF (Bus/Device/Function) address. | |
542 | */ | |
01f3bfb7 | 543 | static int pnv_eeh_get_pe_addr(struct eeh_pe *pe) |
29310e5e GS |
544 | { |
545 | return pe->addr; | |
546 | } | |
547 | ||
40ae5f69 GS |
548 | static void pnv_eeh_get_phb_diag(struct eeh_pe *pe) |
549 | { | |
550 | struct pnv_phb *phb = pe->phb->private_data; | |
551 | s64 rc; | |
552 | ||
553 | rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data, | |
554 | PNV_PCI_DIAG_BUF_SIZE); | |
555 | if (rc != OPAL_SUCCESS) | |
556 | pr_warn("%s: Failure %lld getting PHB#%x diag-data\n", | |
557 | __func__, rc, pe->phb->global_number); | |
558 | } | |
559 | ||
560 | static int pnv_eeh_get_phb_state(struct eeh_pe *pe) | |
561 | { | |
562 | struct pnv_phb *phb = pe->phb->private_data; | |
563 | u8 fstate; | |
564 | __be16 pcierr; | |
565 | s64 rc; | |
566 | int result = 0; | |
567 | ||
568 | rc = opal_pci_eeh_freeze_status(phb->opal_id, | |
569 | pe->addr, | |
570 | &fstate, | |
571 | &pcierr, | |
572 | NULL); | |
573 | if (rc != OPAL_SUCCESS) { | |
574 | pr_warn("%s: Failure %lld getting PHB#%x state\n", | |
575 | __func__, rc, phb->hose->global_number); | |
576 | return EEH_STATE_NOT_SUPPORT; | |
577 | } | |
578 | ||
579 | /* | |
580 | * Check PHB state. If the PHB is frozen for the | |
581 | * first time, to dump the PHB diag-data. | |
582 | */ | |
583 | if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) { | |
584 | result = (EEH_STATE_MMIO_ACTIVE | | |
585 | EEH_STATE_DMA_ACTIVE | | |
586 | EEH_STATE_MMIO_ENABLED | | |
587 | EEH_STATE_DMA_ENABLED); | |
588 | } else if (!(pe->state & EEH_PE_ISOLATED)) { | |
589 | eeh_pe_state_mark(pe, EEH_PE_ISOLATED); | |
590 | pnv_eeh_get_phb_diag(pe); | |
591 | ||
592 | if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) | |
593 | pnv_pci_dump_phb_diag_data(pe->phb, pe->data); | |
594 | } | |
595 | ||
596 | return result; | |
597 | } | |
598 | ||
599 | static int pnv_eeh_get_pe_state(struct eeh_pe *pe) | |
600 | { | |
601 | struct pnv_phb *phb = pe->phb->private_data; | |
602 | u8 fstate; | |
603 | __be16 pcierr; | |
604 | s64 rc; | |
605 | int result; | |
606 | ||
607 | /* | |
608 | * We don't clobber hardware frozen state until PE | |
609 | * reset is completed. In order to keep EEH core | |
610 | * moving forward, we have to return operational | |
611 | * state during PE reset. | |
612 | */ | |
613 | if (pe->state & EEH_PE_RESET) { | |
614 | result = (EEH_STATE_MMIO_ACTIVE | | |
615 | EEH_STATE_DMA_ACTIVE | | |
616 | EEH_STATE_MMIO_ENABLED | | |
617 | EEH_STATE_DMA_ENABLED); | |
618 | return result; | |
619 | } | |
620 | ||
621 | /* | |
622 | * Fetch PE state from hardware. If the PHB | |
623 | * supports compound PE, let it handle that. | |
624 | */ | |
625 | if (phb->get_pe_state) { | |
626 | fstate = phb->get_pe_state(phb, pe->addr); | |
627 | } else { | |
628 | rc = opal_pci_eeh_freeze_status(phb->opal_id, | |
629 | pe->addr, | |
630 | &fstate, | |
631 | &pcierr, | |
632 | NULL); | |
633 | if (rc != OPAL_SUCCESS) { | |
634 | pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n", | |
635 | __func__, rc, phb->hose->global_number, | |
636 | pe->addr); | |
637 | return EEH_STATE_NOT_SUPPORT; | |
638 | } | |
639 | } | |
640 | ||
641 | /* Figure out state */ | |
642 | switch (fstate) { | |
643 | case OPAL_EEH_STOPPED_NOT_FROZEN: | |
644 | result = (EEH_STATE_MMIO_ACTIVE | | |
645 | EEH_STATE_DMA_ACTIVE | | |
646 | EEH_STATE_MMIO_ENABLED | | |
647 | EEH_STATE_DMA_ENABLED); | |
648 | break; | |
649 | case OPAL_EEH_STOPPED_MMIO_FREEZE: | |
650 | result = (EEH_STATE_DMA_ACTIVE | | |
651 | EEH_STATE_DMA_ENABLED); | |
652 | break; | |
653 | case OPAL_EEH_STOPPED_DMA_FREEZE: | |
654 | result = (EEH_STATE_MMIO_ACTIVE | | |
655 | EEH_STATE_MMIO_ENABLED); | |
656 | break; | |
657 | case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE: | |
658 | result = 0; | |
659 | break; | |
660 | case OPAL_EEH_STOPPED_RESET: | |
661 | result = EEH_STATE_RESET_ACTIVE; | |
662 | break; | |
663 | case OPAL_EEH_STOPPED_TEMP_UNAVAIL: | |
664 | result = EEH_STATE_UNAVAILABLE; | |
665 | break; | |
666 | case OPAL_EEH_STOPPED_PERM_UNAVAIL: | |
667 | result = EEH_STATE_NOT_SUPPORT; | |
668 | break; | |
669 | default: | |
670 | result = EEH_STATE_NOT_SUPPORT; | |
671 | pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n", | |
672 | __func__, phb->hose->global_number, | |
673 | pe->addr, fstate); | |
674 | } | |
675 | ||
676 | /* | |
677 | * If PHB supports compound PE, to freeze all | |
678 | * slave PEs for consistency. | |
679 | * | |
680 | * If the PE is switching to frozen state for the | |
681 | * first time, to dump the PHB diag-data. | |
682 | */ | |
683 | if (!(result & EEH_STATE_NOT_SUPPORT) && | |
684 | !(result & EEH_STATE_UNAVAILABLE) && | |
685 | !(result & EEH_STATE_MMIO_ACTIVE) && | |
686 | !(result & EEH_STATE_DMA_ACTIVE) && | |
687 | !(pe->state & EEH_PE_ISOLATED)) { | |
688 | if (phb->freeze_pe) | |
689 | phb->freeze_pe(phb, pe->addr); | |
690 | ||
691 | eeh_pe_state_mark(pe, EEH_PE_ISOLATED); | |
692 | pnv_eeh_get_phb_diag(pe); | |
693 | ||
694 | if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) | |
695 | pnv_pci_dump_phb_diag_data(pe->phb, pe->data); | |
696 | } | |
697 | ||
698 | return result; | |
699 | } | |
700 | ||
29310e5e | 701 | /** |
01f3bfb7 | 702 | * pnv_eeh_get_state - Retrieve PE state |
29310e5e GS |
703 | * @pe: EEH PE |
704 | * @delay: delay while PE state is temporarily unavailable | |
705 | * | |
706 | * Retrieve the state of the specified PE. For IODA-compitable | |
707 | * platform, it should be retrieved from IODA table. Therefore, | |
708 | * we prefer passing down to hardware implementation to handle | |
709 | * it. | |
710 | */ | |
01f3bfb7 | 711 | static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay) |
29310e5e | 712 | { |
40ae5f69 | 713 | int ret; |
29310e5e | 714 | |
40ae5f69 GS |
715 | if (pe->type & EEH_PE_PHB) |
716 | ret = pnv_eeh_get_phb_state(pe); | |
717 | else | |
718 | ret = pnv_eeh_get_pe_state(pe); | |
29310e5e | 719 | |
40ae5f69 GS |
720 | if (!delay) |
721 | return ret; | |
722 | ||
723 | /* | |
724 | * If the PE state is temporarily unavailable, | |
725 | * to inform the EEH core delay for default | |
726 | * period (1 second) | |
727 | */ | |
728 | *delay = 0; | |
729 | if (ret & EEH_STATE_UNAVAILABLE) | |
730 | *delay = 1000; | |
29310e5e GS |
731 | |
732 | return ret; | |
733 | } | |
734 | ||
cadf364d GS |
735 | static s64 pnv_eeh_phb_poll(struct pnv_phb *phb) |
736 | { | |
737 | s64 rc = OPAL_HARDWARE; | |
738 | ||
739 | while (1) { | |
740 | rc = opal_pci_poll(phb->opal_id); | |
741 | if (rc <= 0) | |
742 | break; | |
743 | ||
744 | if (system_state < SYSTEM_RUNNING) | |
745 | udelay(1000 * rc); | |
746 | else | |
747 | msleep(rc); | |
748 | } | |
749 | ||
750 | return rc; | |
751 | } | |
752 | ||
753 | int pnv_eeh_phb_reset(struct pci_controller *hose, int option) | |
754 | { | |
755 | struct pnv_phb *phb = hose->private_data; | |
756 | s64 rc = OPAL_HARDWARE; | |
757 | ||
758 | pr_debug("%s: Reset PHB#%x, option=%d\n", | |
759 | __func__, hose->global_number, option); | |
760 | ||
761 | /* Issue PHB complete reset request */ | |
762 | if (option == EEH_RESET_FUNDAMENTAL || | |
763 | option == EEH_RESET_HOT) | |
764 | rc = opal_pci_reset(phb->opal_id, | |
765 | OPAL_RESET_PHB_COMPLETE, | |
766 | OPAL_ASSERT_RESET); | |
767 | else if (option == EEH_RESET_DEACTIVATE) | |
768 | rc = opal_pci_reset(phb->opal_id, | |
769 | OPAL_RESET_PHB_COMPLETE, | |
770 | OPAL_DEASSERT_RESET); | |
771 | if (rc < 0) | |
772 | goto out; | |
773 | ||
774 | /* | |
775 | * Poll state of the PHB until the request is done | |
776 | * successfully. The PHB reset is usually PHB complete | |
777 | * reset followed by hot reset on root bus. So we also | |
778 | * need the PCI bus settlement delay. | |
779 | */ | |
780 | rc = pnv_eeh_phb_poll(phb); | |
781 | if (option == EEH_RESET_DEACTIVATE) { | |
782 | if (system_state < SYSTEM_RUNNING) | |
783 | udelay(1000 * EEH_PE_RST_SETTLE_TIME); | |
784 | else | |
785 | msleep(EEH_PE_RST_SETTLE_TIME); | |
786 | } | |
787 | out: | |
788 | if (rc != OPAL_SUCCESS) | |
789 | return -EIO; | |
790 | ||
791 | return 0; | |
792 | } | |
793 | ||
794 | static int pnv_eeh_root_reset(struct pci_controller *hose, int option) | |
795 | { | |
796 | struct pnv_phb *phb = hose->private_data; | |
797 | s64 rc = OPAL_HARDWARE; | |
798 | ||
799 | pr_debug("%s: Reset PHB#%x, option=%d\n", | |
800 | __func__, hose->global_number, option); | |
801 | ||
802 | /* | |
803 | * During the reset deassert time, we needn't care | |
804 | * the reset scope because the firmware does nothing | |
805 | * for fundamental or hot reset during deassert phase. | |
806 | */ | |
807 | if (option == EEH_RESET_FUNDAMENTAL) | |
808 | rc = opal_pci_reset(phb->opal_id, | |
809 | OPAL_RESET_PCI_FUNDAMENTAL, | |
810 | OPAL_ASSERT_RESET); | |
811 | else if (option == EEH_RESET_HOT) | |
812 | rc = opal_pci_reset(phb->opal_id, | |
813 | OPAL_RESET_PCI_HOT, | |
814 | OPAL_ASSERT_RESET); | |
815 | else if (option == EEH_RESET_DEACTIVATE) | |
816 | rc = opal_pci_reset(phb->opal_id, | |
817 | OPAL_RESET_PCI_HOT, | |
818 | OPAL_DEASSERT_RESET); | |
819 | if (rc < 0) | |
820 | goto out; | |
821 | ||
822 | /* Poll state of the PHB until the request is done */ | |
823 | rc = pnv_eeh_phb_poll(phb); | |
824 | if (option == EEH_RESET_DEACTIVATE) | |
825 | msleep(EEH_PE_RST_SETTLE_TIME); | |
826 | out: | |
827 | if (rc != OPAL_SUCCESS) | |
828 | return -EIO; | |
829 | ||
830 | return 0; | |
831 | } | |
832 | ||
833 | static int pnv_eeh_bridge_reset(struct pci_dev *dev, int option) | |
834 | { | |
0bd78587 GS |
835 | struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn); |
836 | struct eeh_dev *edev = pdn_to_eeh_dev(pdn); | |
cadf364d GS |
837 | int aer = edev ? edev->aer_cap : 0; |
838 | u32 ctrl; | |
839 | ||
840 | pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n", | |
841 | __func__, pci_domain_nr(dev->bus), | |
842 | dev->bus->number, option); | |
843 | ||
844 | switch (option) { | |
845 | case EEH_RESET_FUNDAMENTAL: | |
846 | case EEH_RESET_HOT: | |
847 | /* Don't report linkDown event */ | |
848 | if (aer) { | |
0bd78587 | 849 | eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, |
cadf364d GS |
850 | 4, &ctrl); |
851 | ctrl |= PCI_ERR_UNC_SURPDN; | |
0bd78587 | 852 | eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, |
cadf364d GS |
853 | 4, ctrl); |
854 | } | |
855 | ||
0bd78587 | 856 | eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); |
cadf364d | 857 | ctrl |= PCI_BRIDGE_CTL_BUS_RESET; |
0bd78587 | 858 | eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); |
cadf364d GS |
859 | |
860 | msleep(EEH_PE_RST_HOLD_TIME); | |
861 | break; | |
862 | case EEH_RESET_DEACTIVATE: | |
0bd78587 | 863 | eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); |
cadf364d | 864 | ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; |
0bd78587 | 865 | eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); |
cadf364d GS |
866 | |
867 | msleep(EEH_PE_RST_SETTLE_TIME); | |
868 | ||
869 | /* Continue reporting linkDown event */ | |
870 | if (aer) { | |
0bd78587 | 871 | eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, |
cadf364d GS |
872 | 4, &ctrl); |
873 | ctrl &= ~PCI_ERR_UNC_SURPDN; | |
0bd78587 | 874 | eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, |
cadf364d GS |
875 | 4, ctrl); |
876 | } | |
877 | ||
878 | break; | |
879 | } | |
880 | ||
881 | return 0; | |
882 | } | |
883 | ||
884 | void pnv_pci_reset_secondary_bus(struct pci_dev *dev) | |
885 | { | |
886 | struct pci_controller *hose; | |
887 | ||
888 | if (pci_is_root_bus(dev->bus)) { | |
889 | hose = pci_bus_to_host(dev->bus); | |
890 | pnv_eeh_root_reset(hose, EEH_RESET_HOT); | |
891 | pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE); | |
892 | } else { | |
893 | pnv_eeh_bridge_reset(dev, EEH_RESET_HOT); | |
894 | pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE); | |
895 | } | |
896 | } | |
897 | ||
29310e5e | 898 | /** |
01f3bfb7 | 899 | * pnv_eeh_reset - Reset the specified PE |
29310e5e GS |
900 | * @pe: EEH PE |
901 | * @option: reset option | |
902 | * | |
cadf364d GS |
903 | * Do reset on the indicated PE. For PCI bus sensitive PE, |
904 | * we need to reset the parent p2p bridge. The PHB has to | |
905 | * be reinitialized if the p2p bridge is root bridge. For | |
906 | * PCI device sensitive PE, we will try to reset the device | |
907 | * through FLR. For now, we don't have OPAL APIs to do HARD | |
908 | * reset yet, so all reset would be SOFT (HOT) reset. | |
29310e5e | 909 | */ |
01f3bfb7 | 910 | static int pnv_eeh_reset(struct eeh_pe *pe, int option) |
29310e5e GS |
911 | { |
912 | struct pci_controller *hose = pe->phb; | |
cadf364d GS |
913 | struct pci_bus *bus; |
914 | int ret; | |
915 | ||
916 | /* | |
917 | * For PHB reset, we always have complete reset. For those PEs whose | |
918 | * primary bus derived from root complex (root bus) or root port | |
919 | * (usually bus#1), we apply hot or fundamental reset on the root port. | |
920 | * For other PEs, we always have hot reset on the PE primary bus. | |
921 | * | |
922 | * Here, we have different design to pHyp, which always clear the | |
923 | * frozen state during PE reset. However, the good idea here from | |
924 | * benh is to keep frozen state before we get PE reset done completely | |
925 | * (until BAR restore). With the frozen state, HW drops illegal IO | |
926 | * or MMIO access, which can incur recrusive frozen PE during PE | |
927 | * reset. The side effect is that EEH core has to clear the frozen | |
928 | * state explicitly after BAR restore. | |
929 | */ | |
930 | if (pe->type & EEH_PE_PHB) { | |
931 | ret = pnv_eeh_phb_reset(hose, option); | |
932 | } else { | |
933 | struct pnv_phb *phb; | |
934 | s64 rc; | |
29310e5e | 935 | |
cadf364d GS |
936 | /* |
937 | * The frozen PE might be caused by PAPR error injection | |
938 | * registers, which are expected to be cleared after hitting | |
939 | * frozen PE as stated in the hardware spec. Unfortunately, | |
940 | * that's not true on P7IOC. So we have to clear it manually | |
941 | * to avoid recursive EEH errors during recovery. | |
942 | */ | |
943 | phb = hose->private_data; | |
944 | if (phb->model == PNV_PHB_MODEL_P7IOC && | |
945 | (option == EEH_RESET_HOT || | |
946 | option == EEH_RESET_FUNDAMENTAL)) { | |
947 | rc = opal_pci_reset(phb->opal_id, | |
948 | OPAL_RESET_PHB_ERROR, | |
949 | OPAL_ASSERT_RESET); | |
950 | if (rc != OPAL_SUCCESS) { | |
951 | pr_warn("%s: Failure %lld clearing " | |
952 | "error injection registers\n", | |
953 | __func__, rc); | |
954 | return -EIO; | |
955 | } | |
956 | } | |
957 | ||
958 | bus = eeh_pe_bus_get(pe); | |
959 | if (pci_is_root_bus(bus) || | |
960 | pci_is_root_bus(bus->parent)) | |
961 | ret = pnv_eeh_root_reset(hose, option); | |
962 | else | |
963 | ret = pnv_eeh_bridge_reset(bus->self, option); | |
964 | } | |
29310e5e GS |
965 | |
966 | return ret; | |
967 | } | |
968 | ||
969 | /** | |
01f3bfb7 | 970 | * pnv_eeh_wait_state - Wait for PE state |
29310e5e | 971 | * @pe: EEH PE |
2ac3990c | 972 | * @max_wait: maximal period in millisecond |
29310e5e GS |
973 | * |
974 | * Wait for the state of associated PE. It might take some time | |
975 | * to retrieve the PE's state. | |
976 | */ | |
01f3bfb7 | 977 | static int pnv_eeh_wait_state(struct eeh_pe *pe, int max_wait) |
29310e5e GS |
978 | { |
979 | int ret; | |
980 | int mwait; | |
981 | ||
982 | while (1) { | |
01f3bfb7 | 983 | ret = pnv_eeh_get_state(pe, &mwait); |
29310e5e GS |
984 | |
985 | /* | |
986 | * If the PE's state is temporarily unavailable, | |
987 | * we have to wait for the specified time. Otherwise, | |
988 | * the PE's state will be returned immediately. | |
989 | */ | |
990 | if (ret != EEH_STATE_UNAVAILABLE) | |
991 | return ret; | |
992 | ||
29310e5e | 993 | if (max_wait <= 0) { |
0dae2743 GS |
994 | pr_warn("%s: Timeout getting PE#%x's state (%d)\n", |
995 | __func__, pe->addr, max_wait); | |
29310e5e GS |
996 | return EEH_STATE_NOT_SUPPORT; |
997 | } | |
998 | ||
e17866d5 | 999 | max_wait -= mwait; |
29310e5e GS |
1000 | msleep(mwait); |
1001 | } | |
1002 | ||
1003 | return EEH_STATE_NOT_SUPPORT; | |
1004 | } | |
1005 | ||
1006 | /** | |
01f3bfb7 | 1007 | * pnv_eeh_get_log - Retrieve error log |
29310e5e GS |
1008 | * @pe: EEH PE |
1009 | * @severity: temporary or permanent error log | |
1010 | * @drv_log: driver log to be combined with retrieved error log | |
1011 | * @len: length of driver log | |
1012 | * | |
1013 | * Retrieve the temporary or permanent error from the PE. | |
1014 | */ | |
01f3bfb7 GS |
1015 | static int pnv_eeh_get_log(struct eeh_pe *pe, int severity, |
1016 | char *drv_log, unsigned long len) | |
29310e5e | 1017 | { |
95edcdea GS |
1018 | if (!eeh_has_flag(EEH_EARLY_DUMP_LOG)) |
1019 | pnv_pci_dump_phb_diag_data(pe->phb, pe->data); | |
29310e5e | 1020 | |
95edcdea | 1021 | return 0; |
29310e5e GS |
1022 | } |
1023 | ||
1024 | /** | |
01f3bfb7 | 1025 | * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE |
29310e5e GS |
1026 | * @pe: EEH PE |
1027 | * | |
1028 | * The function will be called to reconfigure the bridges included | |
1029 | * in the specified PE so that the mulfunctional PE would be recovered | |
1030 | * again. | |
1031 | */ | |
01f3bfb7 | 1032 | static int pnv_eeh_configure_bridge(struct eeh_pe *pe) |
29310e5e | 1033 | { |
bbe170ed | 1034 | return 0; |
29310e5e GS |
1035 | } |
1036 | ||
131c123a | 1037 | /** |
01f3bfb7 | 1038 | * pnv_pe_err_inject - Inject specified error to the indicated PE |
131c123a GS |
1039 | * @pe: the indicated PE |
1040 | * @type: error type | |
1041 | * @func: specific error type | |
1042 | * @addr: address | |
1043 | * @mask: address mask | |
1044 | * | |
1045 | * The routine is called to inject specified error, which is | |
1046 | * determined by @type and @func, to the indicated PE for | |
1047 | * testing purpose. | |
1048 | */ | |
01f3bfb7 GS |
1049 | static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func, |
1050 | unsigned long addr, unsigned long mask) | |
131c123a GS |
1051 | { |
1052 | struct pci_controller *hose = pe->phb; | |
1053 | struct pnv_phb *phb = hose->private_data; | |
fa646c3c GS |
1054 | s64 rc; |
1055 | ||
fa646c3c GS |
1056 | if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR && |
1057 | type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) { | |
1058 | pr_warn("%s: Invalid error type %d\n", | |
1059 | __func__, type); | |
1060 | return -ERANGE; | |
1061 | } | |
131c123a | 1062 | |
fa646c3c GS |
1063 | if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR || |
1064 | func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) { | |
1065 | pr_warn("%s: Invalid error function %d\n", | |
1066 | __func__, func); | |
1067 | return -ERANGE; | |
1068 | } | |
131c123a | 1069 | |
fa646c3c GS |
1070 | /* Firmware supports error injection ? */ |
1071 | if (!opal_check_token(OPAL_PCI_ERR_INJECT)) { | |
1072 | pr_warn("%s: Firmware doesn't support error injection\n", | |
1073 | __func__); | |
1074 | return -ENXIO; | |
1075 | } | |
1076 | ||
1077 | /* Do error injection */ | |
1078 | rc = opal_pci_err_inject(phb->opal_id, pe->addr, | |
1079 | type, func, addr, mask); | |
1080 | if (rc != OPAL_SUCCESS) { | |
1081 | pr_warn("%s: Failure %lld injecting error " | |
1082 | "%d-%d to PHB#%x-PE#%x\n", | |
1083 | __func__, rc, type, func, | |
1084 | hose->global_number, pe->addr); | |
1085 | return -EIO; | |
1086 | } | |
1087 | ||
1088 | return 0; | |
131c123a GS |
1089 | } |
1090 | ||
0bd78587 | 1091 | static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn) |
d2cfbcd7 | 1092 | { |
0bd78587 | 1093 | struct eeh_dev *edev = pdn_to_eeh_dev(pdn); |
d2cfbcd7 GS |
1094 | |
1095 | if (!edev || !edev->pe) | |
1096 | return false; | |
1097 | ||
1098 | if (edev->pe->state & EEH_PE_CFG_BLOCKED) | |
1099 | return true; | |
1100 | ||
1101 | return false; | |
1102 | } | |
1103 | ||
0bd78587 | 1104 | static int pnv_eeh_read_config(struct pci_dn *pdn, |
01f3bfb7 | 1105 | int where, int size, u32 *val) |
d2cfbcd7 | 1106 | { |
3532a741 GS |
1107 | if (!pdn) |
1108 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1109 | ||
0bd78587 | 1110 | if (pnv_eeh_cfg_blocked(pdn)) { |
d2cfbcd7 GS |
1111 | *val = 0xFFFFFFFF; |
1112 | return PCIBIOS_SET_FAILED; | |
1113 | } | |
1114 | ||
3532a741 | 1115 | return pnv_pci_cfg_read(pdn, where, size, val); |
d2cfbcd7 GS |
1116 | } |
1117 | ||
0bd78587 | 1118 | static int pnv_eeh_write_config(struct pci_dn *pdn, |
01f3bfb7 | 1119 | int where, int size, u32 val) |
d2cfbcd7 | 1120 | { |
3532a741 GS |
1121 | if (!pdn) |
1122 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1123 | ||
0bd78587 | 1124 | if (pnv_eeh_cfg_blocked(pdn)) |
d2cfbcd7 GS |
1125 | return PCIBIOS_SET_FAILED; |
1126 | ||
3532a741 | 1127 | return pnv_pci_cfg_write(pdn, where, size, val); |
d2cfbcd7 GS |
1128 | } |
1129 | ||
2a485ad7 GS |
1130 | static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data) |
1131 | { | |
1132 | /* GEM */ | |
1133 | if (data->gemXfir || data->gemRfir || | |
1134 | data->gemRirqfir || data->gemMask || data->gemRwof) | |
1135 | pr_info(" GEM: %016llx %016llx %016llx %016llx %016llx\n", | |
1136 | be64_to_cpu(data->gemXfir), | |
1137 | be64_to_cpu(data->gemRfir), | |
1138 | be64_to_cpu(data->gemRirqfir), | |
1139 | be64_to_cpu(data->gemMask), | |
1140 | be64_to_cpu(data->gemRwof)); | |
1141 | ||
1142 | /* LEM */ | |
1143 | if (data->lemFir || data->lemErrMask || | |
1144 | data->lemAction0 || data->lemAction1 || data->lemWof) | |
1145 | pr_info(" LEM: %016llx %016llx %016llx %016llx %016llx\n", | |
1146 | be64_to_cpu(data->lemFir), | |
1147 | be64_to_cpu(data->lemErrMask), | |
1148 | be64_to_cpu(data->lemAction0), | |
1149 | be64_to_cpu(data->lemAction1), | |
1150 | be64_to_cpu(data->lemWof)); | |
1151 | } | |
1152 | ||
1153 | static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose) | |
1154 | { | |
1155 | struct pnv_phb *phb = hose->private_data; | |
1156 | struct OpalIoP7IOCErrorData *data = &phb->diag.hub_diag; | |
1157 | long rc; | |
1158 | ||
1159 | rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data)); | |
1160 | if (rc != OPAL_SUCCESS) { | |
1161 | pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n", | |
1162 | __func__, phb->hub_id, rc); | |
1163 | return; | |
1164 | } | |
1165 | ||
1166 | switch (data->type) { | |
1167 | case OPAL_P7IOC_DIAG_TYPE_RGC: | |
1168 | pr_info("P7IOC diag-data for RGC\n\n"); | |
1169 | pnv_eeh_dump_hub_diag_common(data); | |
1170 | if (data->rgc.rgcStatus || data->rgc.rgcLdcp) | |
1171 | pr_info(" RGC: %016llx %016llx\n", | |
1172 | be64_to_cpu(data->rgc.rgcStatus), | |
1173 | be64_to_cpu(data->rgc.rgcLdcp)); | |
1174 | break; | |
1175 | case OPAL_P7IOC_DIAG_TYPE_BI: | |
1176 | pr_info("P7IOC diag-data for BI %s\n\n", | |
1177 | data->bi.biDownbound ? "Downbound" : "Upbound"); | |
1178 | pnv_eeh_dump_hub_diag_common(data); | |
1179 | if (data->bi.biLdcp0 || data->bi.biLdcp1 || | |
1180 | data->bi.biLdcp2 || data->bi.biFenceStatus) | |
1181 | pr_info(" BI: %016llx %016llx %016llx %016llx\n", | |
1182 | be64_to_cpu(data->bi.biLdcp0), | |
1183 | be64_to_cpu(data->bi.biLdcp1), | |
1184 | be64_to_cpu(data->bi.biLdcp2), | |
1185 | be64_to_cpu(data->bi.biFenceStatus)); | |
1186 | break; | |
1187 | case OPAL_P7IOC_DIAG_TYPE_CI: | |
1188 | pr_info("P7IOC diag-data for CI Port %d\n\n", | |
1189 | data->ci.ciPort); | |
1190 | pnv_eeh_dump_hub_diag_common(data); | |
1191 | if (data->ci.ciPortStatus || data->ci.ciPortLdcp) | |
1192 | pr_info(" CI: %016llx %016llx\n", | |
1193 | be64_to_cpu(data->ci.ciPortStatus), | |
1194 | be64_to_cpu(data->ci.ciPortLdcp)); | |
1195 | break; | |
1196 | case OPAL_P7IOC_DIAG_TYPE_MISC: | |
1197 | pr_info("P7IOC diag-data for MISC\n\n"); | |
1198 | pnv_eeh_dump_hub_diag_common(data); | |
1199 | break; | |
1200 | case OPAL_P7IOC_DIAG_TYPE_I2C: | |
1201 | pr_info("P7IOC diag-data for I2C\n\n"); | |
1202 | pnv_eeh_dump_hub_diag_common(data); | |
1203 | break; | |
1204 | default: | |
1205 | pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n", | |
1206 | __func__, phb->hub_id, data->type); | |
1207 | } | |
1208 | } | |
1209 | ||
1210 | static int pnv_eeh_get_pe(struct pci_controller *hose, | |
1211 | u16 pe_no, struct eeh_pe **pe) | |
1212 | { | |
1213 | struct pnv_phb *phb = hose->private_data; | |
1214 | struct pnv_ioda_pe *pnv_pe; | |
1215 | struct eeh_pe *dev_pe; | |
1216 | struct eeh_dev edev; | |
1217 | ||
1218 | /* | |
1219 | * If PHB supports compound PE, to fetch | |
1220 | * the master PE because slave PE is invisible | |
1221 | * to EEH core. | |
1222 | */ | |
1223 | pnv_pe = &phb->ioda.pe_array[pe_no]; | |
1224 | if (pnv_pe->flags & PNV_IODA_PE_SLAVE) { | |
1225 | pnv_pe = pnv_pe->master; | |
1226 | WARN_ON(!pnv_pe || | |
1227 | !(pnv_pe->flags & PNV_IODA_PE_MASTER)); | |
1228 | pe_no = pnv_pe->pe_number; | |
1229 | } | |
1230 | ||
1231 | /* Find the PE according to PE# */ | |
1232 | memset(&edev, 0, sizeof(struct eeh_dev)); | |
1233 | edev.phb = hose; | |
1234 | edev.pe_config_addr = pe_no; | |
1235 | dev_pe = eeh_pe_get(&edev); | |
1236 | if (!dev_pe) | |
1237 | return -EEXIST; | |
1238 | ||
1239 | /* Freeze the (compound) PE */ | |
1240 | *pe = dev_pe; | |
1241 | if (!(dev_pe->state & EEH_PE_ISOLATED)) | |
1242 | phb->freeze_pe(phb, pe_no); | |
1243 | ||
1244 | /* | |
1245 | * At this point, we're sure the (compound) PE should | |
1246 | * have been frozen. However, we still need poke until | |
1247 | * hitting the frozen PE on top level. | |
1248 | */ | |
1249 | dev_pe = dev_pe->parent; | |
1250 | while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) { | |
1251 | int ret; | |
1252 | int active_flags = (EEH_STATE_MMIO_ACTIVE | | |
1253 | EEH_STATE_DMA_ACTIVE); | |
1254 | ||
1255 | ret = eeh_ops->get_state(dev_pe, NULL); | |
1256 | if (ret <= 0 || (ret & active_flags) == active_flags) { | |
1257 | dev_pe = dev_pe->parent; | |
1258 | continue; | |
1259 | } | |
1260 | ||
1261 | /* Frozen parent PE */ | |
1262 | *pe = dev_pe; | |
1263 | if (!(dev_pe->state & EEH_PE_ISOLATED)) | |
1264 | phb->freeze_pe(phb, dev_pe->addr); | |
1265 | ||
1266 | /* Next one */ | |
1267 | dev_pe = dev_pe->parent; | |
1268 | } | |
1269 | ||
1270 | return 0; | |
1271 | } | |
1272 | ||
29310e5e | 1273 | /** |
01f3bfb7 | 1274 | * pnv_eeh_next_error - Retrieve next EEH error to handle |
29310e5e GS |
1275 | * @pe: Affected PE |
1276 | * | |
2a485ad7 GS |
1277 | * The function is expected to be called by EEH core while it gets |
1278 | * special EEH event (without binding PE). The function calls to | |
1279 | * OPAL APIs for next error to handle. The informational error is | |
1280 | * handled internally by platform. However, the dead IOC, dead PHB, | |
1281 | * fenced PHB and frozen PE should be handled by EEH core eventually. | |
29310e5e | 1282 | */ |
01f3bfb7 | 1283 | static int pnv_eeh_next_error(struct eeh_pe **pe) |
29310e5e GS |
1284 | { |
1285 | struct pci_controller *hose; | |
2a485ad7 GS |
1286 | struct pnv_phb *phb; |
1287 | struct eeh_pe *phb_pe, *parent_pe; | |
1288 | __be64 frozen_pe_no; | |
1289 | __be16 err_type, severity; | |
1290 | int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); | |
1291 | long rc; | |
1292 | int state, ret = EEH_NEXT_ERR_NONE; | |
1293 | ||
1294 | /* | |
79231448 AP |
1295 | * While running here, it's safe to purge the event queue. The |
1296 | * event should still be masked. | |
2a485ad7 GS |
1297 | */ |
1298 | eeh_remove_event(NULL, false); | |
29310e5e GS |
1299 | |
1300 | list_for_each_entry(hose, &hose_list, list_node) { | |
2a485ad7 GS |
1301 | /* |
1302 | * If the subordinate PCI buses of the PHB has been | |
1303 | * removed or is exactly under error recovery, we | |
1304 | * needn't take care of it any more. | |
1305 | */ | |
29310e5e | 1306 | phb = hose->private_data; |
2a485ad7 GS |
1307 | phb_pe = eeh_phb_pe_get(hose); |
1308 | if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED)) | |
1309 | continue; | |
1310 | ||
1311 | rc = opal_pci_next_error(phb->opal_id, | |
1312 | &frozen_pe_no, &err_type, &severity); | |
1313 | if (rc != OPAL_SUCCESS) { | |
1314 | pr_devel("%s: Invalid return value on " | |
1315 | "PHB#%x (0x%lx) from opal_pci_next_error", | |
1316 | __func__, hose->global_number, rc); | |
1317 | continue; | |
1318 | } | |
1319 | ||
1320 | /* If the PHB doesn't have error, stop processing */ | |
1321 | if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR || | |
1322 | be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) { | |
1323 | pr_devel("%s: No error found on PHB#%x\n", | |
1324 | __func__, hose->global_number); | |
1325 | continue; | |
1326 | } | |
29310e5e | 1327 | |
2a485ad7 GS |
1328 | /* |
1329 | * Processing the error. We're expecting the error with | |
1330 | * highest priority reported upon multiple errors on the | |
1331 | * specific PHB. | |
1332 | */ | |
1333 | pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n", | |
1334 | __func__, be16_to_cpu(err_type), | |
1335 | be16_to_cpu(severity), be64_to_cpu(frozen_pe_no), | |
1336 | hose->global_number); | |
1337 | switch (be16_to_cpu(err_type)) { | |
1338 | case OPAL_EEH_IOC_ERROR: | |
1339 | if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) { | |
1340 | pr_err("EEH: dead IOC detected\n"); | |
1341 | ret = EEH_NEXT_ERR_DEAD_IOC; | |
1342 | } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { | |
1343 | pr_info("EEH: IOC informative error " | |
1344 | "detected\n"); | |
1345 | pnv_eeh_get_and_dump_hub_diag(hose); | |
1346 | ret = EEH_NEXT_ERR_NONE; | |
1347 | } | |
1348 | ||
1349 | break; | |
1350 | case OPAL_EEH_PHB_ERROR: | |
1351 | if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) { | |
1352 | *pe = phb_pe; | |
1353 | pr_err("EEH: dead PHB#%x detected, " | |
1354 | "location: %s\n", | |
1355 | hose->global_number, | |
1356 | eeh_pe_loc_get(phb_pe)); | |
1357 | ret = EEH_NEXT_ERR_DEAD_PHB; | |
1358 | } else if (be16_to_cpu(severity) == | |
1359 | OPAL_EEH_SEV_PHB_FENCED) { | |
1360 | *pe = phb_pe; | |
1361 | pr_err("EEH: Fenced PHB#%x detected, " | |
1362 | "location: %s\n", | |
1363 | hose->global_number, | |
1364 | eeh_pe_loc_get(phb_pe)); | |
1365 | ret = EEH_NEXT_ERR_FENCED_PHB; | |
1366 | } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { | |
1367 | pr_info("EEH: PHB#%x informative error " | |
1368 | "detected, location: %s\n", | |
1369 | hose->global_number, | |
1370 | eeh_pe_loc_get(phb_pe)); | |
1371 | pnv_eeh_get_phb_diag(phb_pe); | |
1372 | pnv_pci_dump_phb_diag_data(hose, phb_pe->data); | |
1373 | ret = EEH_NEXT_ERR_NONE; | |
1374 | } | |
29310e5e | 1375 | |
2a485ad7 GS |
1376 | break; |
1377 | case OPAL_EEH_PE_ERROR: | |
1378 | /* | |
1379 | * If we can't find the corresponding PE, we | |
1380 | * just try to unfreeze. | |
1381 | */ | |
1382 | if (pnv_eeh_get_pe(hose, | |
1383 | be64_to_cpu(frozen_pe_no), pe)) { | |
2a485ad7 | 1384 | pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n", |
0f36db77 | 1385 | hose->global_number, be64_to_cpu(frozen_pe_no)); |
2a485ad7 GS |
1386 | pr_info("EEH: PHB location: %s\n", |
1387 | eeh_pe_loc_get(phb_pe)); | |
79cd9520 GS |
1388 | |
1389 | /* Dump PHB diag-data */ | |
1390 | rc = opal_pci_get_phb_diag_data2(phb->opal_id, | |
1391 | phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE); | |
1392 | if (rc == OPAL_SUCCESS) | |
1393 | pnv_pci_dump_phb_diag_data(hose, | |
1394 | phb->diag.blob); | |
1395 | ||
1396 | /* Try best to clear it */ | |
2a485ad7 GS |
1397 | opal_pci_eeh_freeze_clear(phb->opal_id, |
1398 | frozen_pe_no, | |
1399 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); | |
1400 | ret = EEH_NEXT_ERR_NONE; | |
1401 | } else if ((*pe)->state & EEH_PE_ISOLATED || | |
1402 | eeh_pe_passed(*pe)) { | |
1403 | ret = EEH_NEXT_ERR_NONE; | |
1404 | } else { | |
1405 | pr_err("EEH: Frozen PE#%x " | |
1406 | "on PHB#%x detected\n", | |
1407 | (*pe)->addr, | |
1408 | (*pe)->phb->global_number); | |
1409 | pr_err("EEH: PE location: %s, " | |
1410 | "PHB location: %s\n", | |
1411 | eeh_pe_loc_get(*pe), | |
1412 | eeh_pe_loc_get(phb_pe)); | |
1413 | ret = EEH_NEXT_ERR_FROZEN_PE; | |
1414 | } | |
1415 | ||
1416 | break; | |
1417 | default: | |
1418 | pr_warn("%s: Unexpected error type %d\n", | |
1419 | __func__, be16_to_cpu(err_type)); | |
1420 | } | |
1421 | ||
1422 | /* | |
1423 | * EEH core will try recover from fenced PHB or | |
1424 | * frozen PE. In the time for frozen PE, EEH core | |
1425 | * enable IO path for that before collecting logs, | |
1426 | * but it ruins the site. So we have to dump the | |
1427 | * log in advance here. | |
1428 | */ | |
1429 | if ((ret == EEH_NEXT_ERR_FROZEN_PE || | |
1430 | ret == EEH_NEXT_ERR_FENCED_PHB) && | |
1431 | !((*pe)->state & EEH_PE_ISOLATED)) { | |
1432 | eeh_pe_state_mark(*pe, EEH_PE_ISOLATED); | |
1433 | pnv_eeh_get_phb_diag(*pe); | |
1434 | ||
1435 | if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) | |
1436 | pnv_pci_dump_phb_diag_data((*pe)->phb, | |
1437 | (*pe)->data); | |
1438 | } | |
1439 | ||
1440 | /* | |
1441 | * We probably have the frozen parent PE out there and | |
1442 | * we need have to handle frozen parent PE firstly. | |
1443 | */ | |
1444 | if (ret == EEH_NEXT_ERR_FROZEN_PE) { | |
1445 | parent_pe = (*pe)->parent; | |
1446 | while (parent_pe) { | |
1447 | /* Hit the ceiling ? */ | |
1448 | if (parent_pe->type & EEH_PE_PHB) | |
1449 | break; | |
1450 | ||
1451 | /* Frozen parent PE ? */ | |
1452 | state = eeh_ops->get_state(parent_pe, NULL); | |
1453 | if (state > 0 && | |
1454 | (state & active_flags) != active_flags) | |
1455 | *pe = parent_pe; | |
1456 | ||
1457 | /* Next parent level */ | |
1458 | parent_pe = parent_pe->parent; | |
1459 | } | |
1460 | ||
1461 | /* We possibly migrate to another PE */ | |
1462 | eeh_pe_state_mark(*pe, EEH_PE_ISOLATED); | |
1463 | } | |
1464 | ||
1465 | /* | |
1466 | * If we have no errors on the specific PHB or only | |
1467 | * informative error there, we continue poking it. | |
1468 | * Otherwise, we need actions to be taken by upper | |
1469 | * layer. | |
1470 | */ | |
1471 | if (ret > EEH_NEXT_ERR_INF) | |
1472 | break; | |
1473 | } | |
1474 | ||
79231448 | 1475 | /* Unmask the event */ |
b8d65e96 | 1476 | if (ret == EEH_NEXT_ERR_NONE && eeh_enabled()) |
79231448 AP |
1477 | enable_irq(eeh_event_irq); |
1478 | ||
2a485ad7 | 1479 | return ret; |
29310e5e GS |
1480 | } |
1481 | ||
0bd78587 | 1482 | static int pnv_eeh_restore_config(struct pci_dn *pdn) |
9be3becc | 1483 | { |
0bd78587 | 1484 | struct eeh_dev *edev = pdn_to_eeh_dev(pdn); |
9be3becc GS |
1485 | struct pnv_phb *phb; |
1486 | s64 ret; | |
1487 | ||
1488 | if (!edev) | |
1489 | return -EEXIST; | |
1490 | ||
1491 | phb = edev->phb->private_data; | |
1492 | ret = opal_pci_reinit(phb->opal_id, | |
1493 | OPAL_REINIT_PCI_DEV, edev->config_addr); | |
1494 | if (ret) { | |
1495 | pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n", | |
1496 | __func__, edev->config_addr, ret); | |
1497 | return -EIO; | |
1498 | } | |
1499 | ||
1500 | return 0; | |
1501 | } | |
1502 | ||
01f3bfb7 | 1503 | static struct eeh_ops pnv_eeh_ops = { |
29310e5e | 1504 | .name = "powernv", |
01f3bfb7 GS |
1505 | .init = pnv_eeh_init, |
1506 | .post_init = pnv_eeh_post_init, | |
ff57b454 | 1507 | .probe = pnv_eeh_probe, |
01f3bfb7 GS |
1508 | .set_option = pnv_eeh_set_option, |
1509 | .get_pe_addr = pnv_eeh_get_pe_addr, | |
1510 | .get_state = pnv_eeh_get_state, | |
1511 | .reset = pnv_eeh_reset, | |
1512 | .wait_state = pnv_eeh_wait_state, | |
1513 | .get_log = pnv_eeh_get_log, | |
1514 | .configure_bridge = pnv_eeh_configure_bridge, | |
1515 | .err_inject = pnv_eeh_err_inject, | |
1516 | .read_config = pnv_eeh_read_config, | |
1517 | .write_config = pnv_eeh_write_config, | |
1518 | .next_error = pnv_eeh_next_error, | |
1519 | .restore_config = pnv_eeh_restore_config | |
29310e5e GS |
1520 | }; |
1521 | ||
1522 | /** | |
1523 | * eeh_powernv_init - Register platform dependent EEH operations | |
1524 | * | |
1525 | * EEH initialization on powernv platform. This function should be | |
1526 | * called before any EEH related functions. | |
1527 | */ | |
1528 | static int __init eeh_powernv_init(void) | |
1529 | { | |
1530 | int ret = -EINVAL; | |
1531 | ||
bb593c00 | 1532 | eeh_set_pe_aux_size(PNV_PCI_DIAG_BUF_SIZE); |
01f3bfb7 | 1533 | ret = eeh_ops_register(&pnv_eeh_ops); |
29310e5e GS |
1534 | if (!ret) |
1535 | pr_info("EEH: PowerNV platform initialized\n"); | |
1536 | else | |
1537 | pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret); | |
1538 | ||
1539 | return ret; | |
1540 | } | |
b14726c5 | 1541 | machine_early_initcall(powernv, eeh_powernv_init); |