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184cd4a3 BH |
1 | /* |
2 | * Support PCI/PCIe on PowerNV platforms | |
3 | * | |
4 | * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
cee72d5b | 12 | #undef DEBUG |
184cd4a3 BH |
13 | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/pci.h> | |
361f2a2a | 16 | #include <linux/crash_dump.h> |
37c367f2 | 17 | #include <linux/debugfs.h> |
184cd4a3 BH |
18 | #include <linux/delay.h> |
19 | #include <linux/string.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/bootmem.h> | |
22 | #include <linux/irq.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/msi.h> | |
cd15b048 | 25 | #include <linux/memblock.h> |
ac9a5889 | 26 | #include <linux/iommu.h> |
184cd4a3 BH |
27 | |
28 | #include <asm/sections.h> | |
29 | #include <asm/io.h> | |
30 | #include <asm/prom.h> | |
31 | #include <asm/pci-bridge.h> | |
32 | #include <asm/machdep.h> | |
fb1b55d6 | 33 | #include <asm/msi_bitmap.h> |
184cd4a3 BH |
34 | #include <asm/ppc-pci.h> |
35 | #include <asm/opal.h> | |
36 | #include <asm/iommu.h> | |
37 | #include <asm/tce.h> | |
137436c9 | 38 | #include <asm/xics.h> |
37c367f2 | 39 | #include <asm/debug.h> |
262af557 | 40 | #include <asm/firmware.h> |
80c49c7e IM |
41 | #include <asm/pnv-pci.h> |
42 | ||
ec249dd8 | 43 | #include <misc/cxl-base.h> |
184cd4a3 BH |
44 | |
45 | #include "powernv.h" | |
46 | #include "pci.h" | |
47 | ||
781a868f WY |
48 | /* 256M DMA window, 4K TCE pages, 8 bytes TCE */ |
49 | #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8) | |
50 | ||
6d31c2fa JP |
51 | static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, |
52 | const char *fmt, ...) | |
53 | { | |
54 | struct va_format vaf; | |
55 | va_list args; | |
56 | char pfix[32]; | |
57 | ||
58 | va_start(args, fmt); | |
59 | ||
60 | vaf.fmt = fmt; | |
61 | vaf.va = &args; | |
62 | ||
781a868f | 63 | if (pe->flags & PNV_IODA_PE_DEV) |
6d31c2fa | 64 | strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); |
781a868f | 65 | else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) |
6d31c2fa JP |
66 | sprintf(pfix, "%04x:%02x ", |
67 | pci_domain_nr(pe->pbus), pe->pbus->number); | |
781a868f WY |
68 | #ifdef CONFIG_PCI_IOV |
69 | else if (pe->flags & PNV_IODA_PE_VF) | |
70 | sprintf(pfix, "%04x:%02x:%2x.%d", | |
71 | pci_domain_nr(pe->parent_dev->bus), | |
72 | (pe->rid & 0xff00) >> 8, | |
73 | PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); | |
74 | #endif /* CONFIG_PCI_IOV*/ | |
6d31c2fa JP |
75 | |
76 | printk("%spci %s: [PE# %.3d] %pV", | |
77 | level, pfix, pe->pe_number, &vaf); | |
78 | ||
79 | va_end(args); | |
80 | } | |
184cd4a3 | 81 | |
6d31c2fa JP |
82 | #define pe_err(pe, fmt, ...) \ |
83 | pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) | |
84 | #define pe_warn(pe, fmt, ...) \ | |
85 | pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) | |
86 | #define pe_info(pe, fmt, ...) \ | |
87 | pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) | |
184cd4a3 | 88 | |
4e287840 TLSC |
89 | static bool pnv_iommu_bypass_disabled __read_mostly; |
90 | ||
91 | static int __init iommu_setup(char *str) | |
92 | { | |
93 | if (!str) | |
94 | return -EINVAL; | |
95 | ||
96 | while (*str) { | |
97 | if (!strncmp(str, "nobypass", 8)) { | |
98 | pnv_iommu_bypass_disabled = true; | |
99 | pr_info("PowerNV: IOMMU bypass window disabled.\n"); | |
100 | break; | |
101 | } | |
102 | str += strcspn(str, ","); | |
103 | if (*str == ',') | |
104 | str++; | |
105 | } | |
106 | ||
107 | return 0; | |
108 | } | |
109 | early_param("iommu", iommu_setup); | |
110 | ||
8e0a1611 AK |
111 | /* |
112 | * stdcix is only supposed to be used in hypervisor real mode as per | |
113 | * the architecture spec | |
114 | */ | |
115 | static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr) | |
116 | { | |
117 | __asm__ __volatile__("stdcix %0,0,%1" | |
118 | : : "r" (val), "r" (paddr) : "memory"); | |
119 | } | |
120 | ||
262af557 GC |
121 | static inline bool pnv_pci_is_mem_pref_64(unsigned long flags) |
122 | { | |
123 | return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) == | |
124 | (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)); | |
125 | } | |
126 | ||
4b82ab18 GS |
127 | static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) |
128 | { | |
129 | if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe)) { | |
130 | pr_warn("%s: Invalid PE %d on PHB#%x\n", | |
131 | __func__, pe_no, phb->hose->global_number); | |
132 | return; | |
133 | } | |
134 | ||
135 | if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) { | |
136 | pr_warn("%s: PE %d was assigned on PHB#%x\n", | |
137 | __func__, pe_no, phb->hose->global_number); | |
138 | return; | |
139 | } | |
140 | ||
141 | phb->ioda.pe_array[pe_no].phb = phb; | |
142 | phb->ioda.pe_array[pe_no].pe_number = pe_no; | |
143 | } | |
144 | ||
cad5cef6 | 145 | static int pnv_ioda_alloc_pe(struct pnv_phb *phb) |
184cd4a3 BH |
146 | { |
147 | unsigned long pe; | |
148 | ||
149 | do { | |
150 | pe = find_next_zero_bit(phb->ioda.pe_alloc, | |
151 | phb->ioda.total_pe, 0); | |
152 | if (pe >= phb->ioda.total_pe) | |
153 | return IODA_INVALID_PE; | |
154 | } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); | |
155 | ||
4cce9550 | 156 | phb->ioda.pe_array[pe].phb = phb; |
184cd4a3 BH |
157 | phb->ioda.pe_array[pe].pe_number = pe; |
158 | return pe; | |
159 | } | |
160 | ||
cad5cef6 | 161 | static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe) |
184cd4a3 BH |
162 | { |
163 | WARN_ON(phb->ioda.pe_array[pe].pdev); | |
164 | ||
165 | memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe)); | |
166 | clear_bit(pe, phb->ioda.pe_alloc); | |
167 | } | |
168 | ||
262af557 GC |
169 | /* The default M64 BAR is shared by all PEs */ |
170 | static int pnv_ioda2_init_m64(struct pnv_phb *phb) | |
171 | { | |
172 | const char *desc; | |
173 | struct resource *r; | |
174 | s64 rc; | |
175 | ||
176 | /* Configure the default M64 BAR */ | |
177 | rc = opal_pci_set_phb_mem_window(phb->opal_id, | |
178 | OPAL_M64_WINDOW_TYPE, | |
179 | phb->ioda.m64_bar_idx, | |
180 | phb->ioda.m64_base, | |
181 | 0, /* unused */ | |
182 | phb->ioda.m64_size); | |
183 | if (rc != OPAL_SUCCESS) { | |
184 | desc = "configuring"; | |
185 | goto fail; | |
186 | } | |
187 | ||
188 | /* Enable the default M64 BAR */ | |
189 | rc = opal_pci_phb_mmio_enable(phb->opal_id, | |
190 | OPAL_M64_WINDOW_TYPE, | |
191 | phb->ioda.m64_bar_idx, | |
192 | OPAL_ENABLE_M64_SPLIT); | |
193 | if (rc != OPAL_SUCCESS) { | |
194 | desc = "enabling"; | |
195 | goto fail; | |
196 | } | |
197 | ||
198 | /* Mark the M64 BAR assigned */ | |
199 | set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc); | |
200 | ||
201 | /* | |
202 | * Strip off the segment used by the reserved PE, which is | |
203 | * expected to be 0 or last one of PE capabicity. | |
204 | */ | |
205 | r = &phb->hose->mem_resources[1]; | |
206 | if (phb->ioda.reserved_pe == 0) | |
207 | r->start += phb->ioda.m64_segsize; | |
208 | else if (phb->ioda.reserved_pe == (phb->ioda.total_pe - 1)) | |
209 | r->end -= phb->ioda.m64_segsize; | |
210 | else | |
211 | pr_warn(" Cannot strip M64 segment for reserved PE#%d\n", | |
212 | phb->ioda.reserved_pe); | |
213 | ||
214 | return 0; | |
215 | ||
216 | fail: | |
217 | pr_warn(" Failure %lld %s M64 BAR#%d\n", | |
218 | rc, desc, phb->ioda.m64_bar_idx); | |
219 | opal_pci_phb_mmio_enable(phb->opal_id, | |
220 | OPAL_M64_WINDOW_TYPE, | |
221 | phb->ioda.m64_bar_idx, | |
222 | OPAL_DISABLE_M64); | |
223 | return -EIO; | |
224 | } | |
225 | ||
5ef73567 | 226 | static void pnv_ioda2_reserve_m64_pe(struct pnv_phb *phb) |
262af557 GC |
227 | { |
228 | resource_size_t sgsz = phb->ioda.m64_segsize; | |
229 | struct pci_dev *pdev; | |
230 | struct resource *r; | |
231 | int base, step, i; | |
232 | ||
233 | /* | |
234 | * Root bus always has full M64 range and root port has | |
235 | * M64 range used in reality. So we're checking root port | |
236 | * instead of root bus. | |
237 | */ | |
238 | list_for_each_entry(pdev, &phb->hose->bus->devices, bus_list) { | |
4b82ab18 GS |
239 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { |
240 | r = &pdev->resource[PCI_BRIDGE_RESOURCES + i]; | |
262af557 GC |
241 | if (!r->parent || |
242 | !pnv_pci_is_mem_pref_64(r->flags)) | |
243 | continue; | |
244 | ||
245 | base = (r->start - phb->ioda.m64_base) / sgsz; | |
246 | for (step = 0; step < resource_size(r) / sgsz; step++) | |
4b82ab18 | 247 | pnv_ioda_reserve_pe(phb, base + step); |
262af557 GC |
248 | } |
249 | } | |
250 | } | |
251 | ||
252 | static int pnv_ioda2_pick_m64_pe(struct pnv_phb *phb, | |
253 | struct pci_bus *bus, int all) | |
254 | { | |
255 | resource_size_t segsz = phb->ioda.m64_segsize; | |
256 | struct pci_dev *pdev; | |
257 | struct resource *r; | |
258 | struct pnv_ioda_pe *master_pe, *pe; | |
259 | unsigned long size, *pe_alloc; | |
260 | bool found; | |
261 | int start, i, j; | |
262 | ||
263 | /* Root bus shouldn't use M64 */ | |
264 | if (pci_is_root_bus(bus)) | |
265 | return IODA_INVALID_PE; | |
266 | ||
267 | /* We support only one M64 window on each bus */ | |
268 | found = false; | |
269 | pci_bus_for_each_resource(bus, r, i) { | |
270 | if (r && r->parent && | |
271 | pnv_pci_is_mem_pref_64(r->flags)) { | |
272 | found = true; | |
273 | break; | |
274 | } | |
275 | } | |
276 | ||
277 | /* No M64 window found ? */ | |
278 | if (!found) | |
279 | return IODA_INVALID_PE; | |
280 | ||
281 | /* Allocate bitmap */ | |
282 | size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); | |
283 | pe_alloc = kzalloc(size, GFP_KERNEL); | |
284 | if (!pe_alloc) { | |
285 | pr_warn("%s: Out of memory !\n", | |
286 | __func__); | |
287 | return IODA_INVALID_PE; | |
288 | } | |
289 | ||
290 | /* | |
291 | * Figure out reserved PE numbers by the PE | |
292 | * the its child PEs. | |
293 | */ | |
294 | start = (r->start - phb->ioda.m64_base) / segsz; | |
295 | for (i = 0; i < resource_size(r) / segsz; i++) | |
296 | set_bit(start + i, pe_alloc); | |
297 | ||
298 | if (all) | |
299 | goto done; | |
300 | ||
301 | /* | |
302 | * If the PE doesn't cover all subordinate buses, | |
303 | * we need subtract from reserved PEs for children. | |
304 | */ | |
305 | list_for_each_entry(pdev, &bus->devices, bus_list) { | |
306 | if (!pdev->subordinate) | |
307 | continue; | |
308 | ||
309 | pci_bus_for_each_resource(pdev->subordinate, r, i) { | |
310 | if (!r || !r->parent || | |
311 | !pnv_pci_is_mem_pref_64(r->flags)) | |
312 | continue; | |
313 | ||
314 | start = (r->start - phb->ioda.m64_base) / segsz; | |
315 | for (j = 0; j < resource_size(r) / segsz ; j++) | |
316 | clear_bit(start + j, pe_alloc); | |
317 | } | |
318 | } | |
319 | ||
320 | /* | |
321 | * the current bus might not own M64 window and that's all | |
322 | * contributed by its child buses. For the case, we needn't | |
323 | * pick M64 dependent PE#. | |
324 | */ | |
325 | if (bitmap_empty(pe_alloc, phb->ioda.total_pe)) { | |
326 | kfree(pe_alloc); | |
327 | return IODA_INVALID_PE; | |
328 | } | |
329 | ||
330 | /* | |
331 | * Figure out the master PE and put all slave PEs to master | |
332 | * PE's list to form compound PE. | |
333 | */ | |
334 | done: | |
335 | master_pe = NULL; | |
336 | i = -1; | |
337 | while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe, i + 1)) < | |
338 | phb->ioda.total_pe) { | |
339 | pe = &phb->ioda.pe_array[i]; | |
262af557 GC |
340 | |
341 | if (!master_pe) { | |
342 | pe->flags |= PNV_IODA_PE_MASTER; | |
343 | INIT_LIST_HEAD(&pe->slaves); | |
344 | master_pe = pe; | |
345 | } else { | |
346 | pe->flags |= PNV_IODA_PE_SLAVE; | |
347 | pe->master = master_pe; | |
348 | list_add_tail(&pe->list, &master_pe->slaves); | |
349 | } | |
350 | } | |
351 | ||
352 | kfree(pe_alloc); | |
353 | return master_pe->pe_number; | |
354 | } | |
355 | ||
356 | static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) | |
357 | { | |
358 | struct pci_controller *hose = phb->hose; | |
359 | struct device_node *dn = hose->dn; | |
360 | struct resource *res; | |
361 | const u32 *r; | |
362 | u64 pci_addr; | |
363 | ||
1665c4a8 GS |
364 | /* FIXME: Support M64 for P7IOC */ |
365 | if (phb->type != PNV_PHB_IODA2) { | |
366 | pr_info(" Not support M64 window\n"); | |
367 | return; | |
368 | } | |
369 | ||
262af557 GC |
370 | if (!firmware_has_feature(FW_FEATURE_OPALv3)) { |
371 | pr_info(" Firmware too old to support M64 window\n"); | |
372 | return; | |
373 | } | |
374 | ||
375 | r = of_get_property(dn, "ibm,opal-m64-window", NULL); | |
376 | if (!r) { | |
377 | pr_info(" No <ibm,opal-m64-window> on %s\n", | |
378 | dn->full_name); | |
379 | return; | |
380 | } | |
381 | ||
262af557 GC |
382 | res = &hose->mem_resources[1]; |
383 | res->start = of_translate_address(dn, r + 2); | |
384 | res->end = res->start + of_read_number(r + 4, 2) - 1; | |
385 | res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); | |
386 | pci_addr = of_read_number(r, 2); | |
387 | hose->mem_offset[1] = res->start - pci_addr; | |
388 | ||
389 | phb->ioda.m64_size = resource_size(res); | |
390 | phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe; | |
391 | phb->ioda.m64_base = pci_addr; | |
392 | ||
e9863e68 WY |
393 | pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n", |
394 | res->start, res->end, pci_addr); | |
395 | ||
262af557 GC |
396 | /* Use last M64 BAR to cover M64 window */ |
397 | phb->ioda.m64_bar_idx = 15; | |
398 | phb->init_m64 = pnv_ioda2_init_m64; | |
5ef73567 | 399 | phb->reserve_m64_pe = pnv_ioda2_reserve_m64_pe; |
262af557 GC |
400 | phb->pick_m64_pe = pnv_ioda2_pick_m64_pe; |
401 | } | |
402 | ||
49dec922 GS |
403 | static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) |
404 | { | |
405 | struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; | |
406 | struct pnv_ioda_pe *slave; | |
407 | s64 rc; | |
408 | ||
409 | /* Fetch master PE */ | |
410 | if (pe->flags & PNV_IODA_PE_SLAVE) { | |
411 | pe = pe->master; | |
ec8e4e9d GS |
412 | if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) |
413 | return; | |
414 | ||
49dec922 GS |
415 | pe_no = pe->pe_number; |
416 | } | |
417 | ||
418 | /* Freeze master PE */ | |
419 | rc = opal_pci_eeh_freeze_set(phb->opal_id, | |
420 | pe_no, | |
421 | OPAL_EEH_ACTION_SET_FREEZE_ALL); | |
422 | if (rc != OPAL_SUCCESS) { | |
423 | pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", | |
424 | __func__, rc, phb->hose->global_number, pe_no); | |
425 | return; | |
426 | } | |
427 | ||
428 | /* Freeze slave PEs */ | |
429 | if (!(pe->flags & PNV_IODA_PE_MASTER)) | |
430 | return; | |
431 | ||
432 | list_for_each_entry(slave, &pe->slaves, list) { | |
433 | rc = opal_pci_eeh_freeze_set(phb->opal_id, | |
434 | slave->pe_number, | |
435 | OPAL_EEH_ACTION_SET_FREEZE_ALL); | |
436 | if (rc != OPAL_SUCCESS) | |
437 | pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", | |
438 | __func__, rc, phb->hose->global_number, | |
439 | slave->pe_number); | |
440 | } | |
441 | } | |
442 | ||
e51df2c1 | 443 | static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) |
49dec922 GS |
444 | { |
445 | struct pnv_ioda_pe *pe, *slave; | |
446 | s64 rc; | |
447 | ||
448 | /* Find master PE */ | |
449 | pe = &phb->ioda.pe_array[pe_no]; | |
450 | if (pe->flags & PNV_IODA_PE_SLAVE) { | |
451 | pe = pe->master; | |
452 | WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); | |
453 | pe_no = pe->pe_number; | |
454 | } | |
455 | ||
456 | /* Clear frozen state for master PE */ | |
457 | rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); | |
458 | if (rc != OPAL_SUCCESS) { | |
459 | pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", | |
460 | __func__, rc, opt, phb->hose->global_number, pe_no); | |
461 | return -EIO; | |
462 | } | |
463 | ||
464 | if (!(pe->flags & PNV_IODA_PE_MASTER)) | |
465 | return 0; | |
466 | ||
467 | /* Clear frozen state for slave PEs */ | |
468 | list_for_each_entry(slave, &pe->slaves, list) { | |
469 | rc = opal_pci_eeh_freeze_clear(phb->opal_id, | |
470 | slave->pe_number, | |
471 | opt); | |
472 | if (rc != OPAL_SUCCESS) { | |
473 | pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", | |
474 | __func__, rc, opt, phb->hose->global_number, | |
475 | slave->pe_number); | |
476 | return -EIO; | |
477 | } | |
478 | } | |
479 | ||
480 | return 0; | |
481 | } | |
482 | ||
483 | static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) | |
484 | { | |
485 | struct pnv_ioda_pe *slave, *pe; | |
486 | u8 fstate, state; | |
487 | __be16 pcierr; | |
488 | s64 rc; | |
489 | ||
490 | /* Sanity check on PE number */ | |
491 | if (pe_no < 0 || pe_no >= phb->ioda.total_pe) | |
492 | return OPAL_EEH_STOPPED_PERM_UNAVAIL; | |
493 | ||
494 | /* | |
495 | * Fetch the master PE and the PE instance might be | |
496 | * not initialized yet. | |
497 | */ | |
498 | pe = &phb->ioda.pe_array[pe_no]; | |
499 | if (pe->flags & PNV_IODA_PE_SLAVE) { | |
500 | pe = pe->master; | |
501 | WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); | |
502 | pe_no = pe->pe_number; | |
503 | } | |
504 | ||
505 | /* Check the master PE */ | |
506 | rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, | |
507 | &state, &pcierr, NULL); | |
508 | if (rc != OPAL_SUCCESS) { | |
509 | pr_warn("%s: Failure %lld getting " | |
510 | "PHB#%x-PE#%x state\n", | |
511 | __func__, rc, | |
512 | phb->hose->global_number, pe_no); | |
513 | return OPAL_EEH_STOPPED_TEMP_UNAVAIL; | |
514 | } | |
515 | ||
516 | /* Check the slave PE */ | |
517 | if (!(pe->flags & PNV_IODA_PE_MASTER)) | |
518 | return state; | |
519 | ||
520 | list_for_each_entry(slave, &pe->slaves, list) { | |
521 | rc = opal_pci_eeh_freeze_status(phb->opal_id, | |
522 | slave->pe_number, | |
523 | &fstate, | |
524 | &pcierr, | |
525 | NULL); | |
526 | if (rc != OPAL_SUCCESS) { | |
527 | pr_warn("%s: Failure %lld getting " | |
528 | "PHB#%x-PE#%x state\n", | |
529 | __func__, rc, | |
530 | phb->hose->global_number, slave->pe_number); | |
531 | return OPAL_EEH_STOPPED_TEMP_UNAVAIL; | |
532 | } | |
533 | ||
534 | /* | |
535 | * Override the result based on the ascending | |
536 | * priority. | |
537 | */ | |
538 | if (fstate > state) | |
539 | state = fstate; | |
540 | } | |
541 | ||
542 | return state; | |
543 | } | |
544 | ||
184cd4a3 BH |
545 | /* Currently those 2 are only used when MSIs are enabled, this will change |
546 | * but in the meantime, we need to protect them to avoid warnings | |
547 | */ | |
548 | #ifdef CONFIG_PCI_MSI | |
cad5cef6 | 549 | static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) |
184cd4a3 BH |
550 | { |
551 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
552 | struct pnv_phb *phb = hose->private_data; | |
b72c1f65 | 553 | struct pci_dn *pdn = pci_get_pdn(dev); |
184cd4a3 BH |
554 | |
555 | if (!pdn) | |
556 | return NULL; | |
557 | if (pdn->pe_number == IODA_INVALID_PE) | |
558 | return NULL; | |
559 | return &phb->ioda.pe_array[pdn->pe_number]; | |
560 | } | |
184cd4a3 BH |
561 | #endif /* CONFIG_PCI_MSI */ |
562 | ||
b131a842 GS |
563 | static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, |
564 | struct pnv_ioda_pe *parent, | |
565 | struct pnv_ioda_pe *child, | |
566 | bool is_add) | |
567 | { | |
568 | const char *desc = is_add ? "adding" : "removing"; | |
569 | uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : | |
570 | OPAL_REMOVE_PE_FROM_DOMAIN; | |
571 | struct pnv_ioda_pe *slave; | |
572 | long rc; | |
573 | ||
574 | /* Parent PE affects child PE */ | |
575 | rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, | |
576 | child->pe_number, op); | |
577 | if (rc != OPAL_SUCCESS) { | |
578 | pe_warn(child, "OPAL error %ld %s to parent PELTV\n", | |
579 | rc, desc); | |
580 | return -ENXIO; | |
581 | } | |
582 | ||
583 | if (!(child->flags & PNV_IODA_PE_MASTER)) | |
584 | return 0; | |
585 | ||
586 | /* Compound case: parent PE affects slave PEs */ | |
587 | list_for_each_entry(slave, &child->slaves, list) { | |
588 | rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, | |
589 | slave->pe_number, op); | |
590 | if (rc != OPAL_SUCCESS) { | |
591 | pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", | |
592 | rc, desc); | |
593 | return -ENXIO; | |
594 | } | |
595 | } | |
596 | ||
597 | return 0; | |
598 | } | |
599 | ||
600 | static int pnv_ioda_set_peltv(struct pnv_phb *phb, | |
601 | struct pnv_ioda_pe *pe, | |
602 | bool is_add) | |
603 | { | |
604 | struct pnv_ioda_pe *slave; | |
781a868f | 605 | struct pci_dev *pdev = NULL; |
b131a842 GS |
606 | int ret; |
607 | ||
608 | /* | |
609 | * Clear PE frozen state. If it's master PE, we need | |
610 | * clear slave PE frozen state as well. | |
611 | */ | |
612 | if (is_add) { | |
613 | opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, | |
614 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); | |
615 | if (pe->flags & PNV_IODA_PE_MASTER) { | |
616 | list_for_each_entry(slave, &pe->slaves, list) | |
617 | opal_pci_eeh_freeze_clear(phb->opal_id, | |
618 | slave->pe_number, | |
619 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); | |
620 | } | |
621 | } | |
622 | ||
623 | /* | |
624 | * Associate PE in PELT. We need add the PE into the | |
625 | * corresponding PELT-V as well. Otherwise, the error | |
626 | * originated from the PE might contribute to other | |
627 | * PEs. | |
628 | */ | |
629 | ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); | |
630 | if (ret) | |
631 | return ret; | |
632 | ||
633 | /* For compound PEs, any one affects all of them */ | |
634 | if (pe->flags & PNV_IODA_PE_MASTER) { | |
635 | list_for_each_entry(slave, &pe->slaves, list) { | |
636 | ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); | |
637 | if (ret) | |
638 | return ret; | |
639 | } | |
640 | } | |
641 | ||
642 | if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) | |
643 | pdev = pe->pbus->self; | |
781a868f | 644 | else if (pe->flags & PNV_IODA_PE_DEV) |
b131a842 | 645 | pdev = pe->pdev->bus->self; |
781a868f WY |
646 | #ifdef CONFIG_PCI_IOV |
647 | else if (pe->flags & PNV_IODA_PE_VF) | |
648 | pdev = pe->parent_dev->bus->self; | |
649 | #endif /* CONFIG_PCI_IOV */ | |
b131a842 GS |
650 | while (pdev) { |
651 | struct pci_dn *pdn = pci_get_pdn(pdev); | |
652 | struct pnv_ioda_pe *parent; | |
653 | ||
654 | if (pdn && pdn->pe_number != IODA_INVALID_PE) { | |
655 | parent = &phb->ioda.pe_array[pdn->pe_number]; | |
656 | ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); | |
657 | if (ret) | |
658 | return ret; | |
659 | } | |
660 | ||
661 | pdev = pdev->bus->self; | |
662 | } | |
663 | ||
664 | return 0; | |
665 | } | |
666 | ||
781a868f WY |
667 | #ifdef CONFIG_PCI_IOV |
668 | static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) | |
669 | { | |
670 | struct pci_dev *parent; | |
671 | uint8_t bcomp, dcomp, fcomp; | |
672 | int64_t rc; | |
673 | long rid_end, rid; | |
674 | ||
675 | /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ | |
676 | if (pe->pbus) { | |
677 | int count; | |
678 | ||
679 | dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; | |
680 | fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; | |
681 | parent = pe->pbus->self; | |
682 | if (pe->flags & PNV_IODA_PE_BUS_ALL) | |
683 | count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; | |
684 | else | |
685 | count = 1; | |
686 | ||
687 | switch(count) { | |
688 | case 1: bcomp = OpalPciBusAll; break; | |
689 | case 2: bcomp = OpalPciBus7Bits; break; | |
690 | case 4: bcomp = OpalPciBus6Bits; break; | |
691 | case 8: bcomp = OpalPciBus5Bits; break; | |
692 | case 16: bcomp = OpalPciBus4Bits; break; | |
693 | case 32: bcomp = OpalPciBus3Bits; break; | |
694 | default: | |
695 | dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", | |
696 | count); | |
697 | /* Do an exact match only */ | |
698 | bcomp = OpalPciBusAll; | |
699 | } | |
700 | rid_end = pe->rid + (count << 8); | |
701 | } else { | |
702 | if (pe->flags & PNV_IODA_PE_VF) | |
703 | parent = pe->parent_dev; | |
704 | else | |
705 | parent = pe->pdev->bus->self; | |
706 | bcomp = OpalPciBusAll; | |
707 | dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; | |
708 | fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; | |
709 | rid_end = pe->rid + 1; | |
710 | } | |
711 | ||
712 | /* Clear the reverse map */ | |
713 | for (rid = pe->rid; rid < rid_end; rid++) | |
714 | phb->ioda.pe_rmap[rid] = 0; | |
715 | ||
716 | /* Release from all parents PELT-V */ | |
717 | while (parent) { | |
718 | struct pci_dn *pdn = pci_get_pdn(parent); | |
719 | if (pdn && pdn->pe_number != IODA_INVALID_PE) { | |
720 | rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, | |
721 | pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); | |
722 | /* XXX What to do in case of error ? */ | |
723 | } | |
724 | parent = parent->bus->self; | |
725 | } | |
726 | ||
727 | opal_pci_eeh_freeze_set(phb->opal_id, pe->pe_number, | |
728 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); | |
729 | ||
730 | /* Disassociate PE in PELT */ | |
731 | rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, | |
732 | pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); | |
733 | if (rc) | |
734 | pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); | |
735 | rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, | |
736 | bcomp, dcomp, fcomp, OPAL_UNMAP_PE); | |
737 | if (rc) | |
738 | pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); | |
739 | ||
740 | pe->pbus = NULL; | |
741 | pe->pdev = NULL; | |
742 | pe->parent_dev = NULL; | |
743 | ||
744 | return 0; | |
745 | } | |
746 | #endif /* CONFIG_PCI_IOV */ | |
747 | ||
cad5cef6 | 748 | static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) |
184cd4a3 BH |
749 | { |
750 | struct pci_dev *parent; | |
751 | uint8_t bcomp, dcomp, fcomp; | |
752 | long rc, rid_end, rid; | |
753 | ||
754 | /* Bus validation ? */ | |
755 | if (pe->pbus) { | |
756 | int count; | |
757 | ||
758 | dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; | |
759 | fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; | |
760 | parent = pe->pbus->self; | |
fb446ad0 GS |
761 | if (pe->flags & PNV_IODA_PE_BUS_ALL) |
762 | count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; | |
763 | else | |
764 | count = 1; | |
765 | ||
184cd4a3 BH |
766 | switch(count) { |
767 | case 1: bcomp = OpalPciBusAll; break; | |
768 | case 2: bcomp = OpalPciBus7Bits; break; | |
769 | case 4: bcomp = OpalPciBus6Bits; break; | |
770 | case 8: bcomp = OpalPciBus5Bits; break; | |
771 | case 16: bcomp = OpalPciBus4Bits; break; | |
772 | case 32: bcomp = OpalPciBus3Bits; break; | |
773 | default: | |
781a868f WY |
774 | dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", |
775 | count); | |
184cd4a3 BH |
776 | /* Do an exact match only */ |
777 | bcomp = OpalPciBusAll; | |
778 | } | |
779 | rid_end = pe->rid + (count << 8); | |
780 | } else { | |
781a868f WY |
781 | #ifdef CONFIG_PCI_IOV |
782 | if (pe->flags & PNV_IODA_PE_VF) | |
783 | parent = pe->parent_dev; | |
784 | else | |
785 | #endif /* CONFIG_PCI_IOV */ | |
786 | parent = pe->pdev->bus->self; | |
184cd4a3 BH |
787 | bcomp = OpalPciBusAll; |
788 | dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; | |
789 | fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; | |
790 | rid_end = pe->rid + 1; | |
791 | } | |
792 | ||
631ad691 GS |
793 | /* |
794 | * Associate PE in PELT. We need add the PE into the | |
795 | * corresponding PELT-V as well. Otherwise, the error | |
796 | * originated from the PE might contribute to other | |
797 | * PEs. | |
798 | */ | |
184cd4a3 BH |
799 | rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, |
800 | bcomp, dcomp, fcomp, OPAL_MAP_PE); | |
801 | if (rc) { | |
802 | pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); | |
803 | return -ENXIO; | |
804 | } | |
631ad691 | 805 | |
b131a842 GS |
806 | /* Configure PELTV */ |
807 | pnv_ioda_set_peltv(phb, pe, true); | |
184cd4a3 | 808 | |
184cd4a3 BH |
809 | /* Setup reverse map */ |
810 | for (rid = pe->rid; rid < rid_end; rid++) | |
811 | phb->ioda.pe_rmap[rid] = pe->pe_number; | |
812 | ||
813 | /* Setup one MVTs on IODA1 */ | |
4773f76b GS |
814 | if (phb->type != PNV_PHB_IODA1) { |
815 | pe->mve_number = 0; | |
816 | goto out; | |
817 | } | |
818 | ||
819 | pe->mve_number = pe->pe_number; | |
820 | rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); | |
821 | if (rc != OPAL_SUCCESS) { | |
822 | pe_err(pe, "OPAL error %ld setting up MVE %d\n", | |
823 | rc, pe->mve_number); | |
824 | pe->mve_number = -1; | |
825 | } else { | |
826 | rc = opal_pci_set_mve_enable(phb->opal_id, | |
827 | pe->mve_number, OPAL_ENABLE_MVE); | |
184cd4a3 | 828 | if (rc) { |
4773f76b | 829 | pe_err(pe, "OPAL error %ld enabling MVE %d\n", |
184cd4a3 BH |
830 | rc, pe->mve_number); |
831 | pe->mve_number = -1; | |
184cd4a3 | 832 | } |
4773f76b | 833 | } |
184cd4a3 | 834 | |
4773f76b | 835 | out: |
184cd4a3 BH |
836 | return 0; |
837 | } | |
838 | ||
cad5cef6 GKH |
839 | static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb, |
840 | struct pnv_ioda_pe *pe) | |
184cd4a3 BH |
841 | { |
842 | struct pnv_ioda_pe *lpe; | |
843 | ||
7ebdf956 | 844 | list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) { |
184cd4a3 | 845 | if (lpe->dma_weight < pe->dma_weight) { |
7ebdf956 | 846 | list_add_tail(&pe->dma_link, &lpe->dma_link); |
184cd4a3 BH |
847 | return; |
848 | } | |
849 | } | |
7ebdf956 | 850 | list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list); |
184cd4a3 BH |
851 | } |
852 | ||
853 | static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev) | |
854 | { | |
855 | /* This is quite simplistic. The "base" weight of a device | |
856 | * is 10. 0 means no DMA is to be accounted for it. | |
857 | */ | |
858 | ||
859 | /* If it's a bridge, no DMA */ | |
860 | if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) | |
861 | return 0; | |
862 | ||
863 | /* Reduce the weight of slow USB controllers */ | |
864 | if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || | |
865 | dev->class == PCI_CLASS_SERIAL_USB_OHCI || | |
866 | dev->class == PCI_CLASS_SERIAL_USB_EHCI) | |
867 | return 3; | |
868 | ||
869 | /* Increase the weight of RAID (includes Obsidian) */ | |
870 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) | |
871 | return 15; | |
872 | ||
873 | /* Default */ | |
874 | return 10; | |
875 | } | |
876 | ||
781a868f WY |
877 | #ifdef CONFIG_PCI_IOV |
878 | static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) | |
879 | { | |
880 | struct pci_dn *pdn = pci_get_pdn(dev); | |
881 | int i; | |
882 | struct resource *res, res2; | |
883 | resource_size_t size; | |
884 | u16 num_vfs; | |
885 | ||
886 | if (!dev->is_physfn) | |
887 | return -EINVAL; | |
888 | ||
889 | /* | |
890 | * "offset" is in VFs. The M64 windows are sized so that when they | |
891 | * are segmented, each segment is the same size as the IOV BAR. | |
892 | * Each segment is in a separate PE, and the high order bits of the | |
893 | * address are the PE number. Therefore, each VF's BAR is in a | |
894 | * separate PE, and changing the IOV BAR start address changes the | |
895 | * range of PEs the VFs are in. | |
896 | */ | |
897 | num_vfs = pdn->num_vfs; | |
898 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { | |
899 | res = &dev->resource[i + PCI_IOV_RESOURCES]; | |
900 | if (!res->flags || !res->parent) | |
901 | continue; | |
902 | ||
903 | if (!pnv_pci_is_mem_pref_64(res->flags)) | |
904 | continue; | |
905 | ||
906 | /* | |
907 | * The actual IOV BAR range is determined by the start address | |
908 | * and the actual size for num_vfs VFs BAR. This check is to | |
909 | * make sure that after shifting, the range will not overlap | |
910 | * with another device. | |
911 | */ | |
912 | size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); | |
913 | res2.flags = res->flags; | |
914 | res2.start = res->start + (size * offset); | |
915 | res2.end = res2.start + (size * num_vfs) - 1; | |
916 | ||
917 | if (res2.end > res->end) { | |
918 | dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", | |
919 | i, &res2, res, num_vfs, offset); | |
920 | return -EBUSY; | |
921 | } | |
922 | } | |
923 | ||
924 | /* | |
925 | * After doing so, there would be a "hole" in the /proc/iomem when | |
926 | * offset is a positive value. It looks like the device return some | |
927 | * mmio back to the system, which actually no one could use it. | |
928 | */ | |
929 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { | |
930 | res = &dev->resource[i + PCI_IOV_RESOURCES]; | |
931 | if (!res->flags || !res->parent) | |
932 | continue; | |
933 | ||
934 | if (!pnv_pci_is_mem_pref_64(res->flags)) | |
935 | continue; | |
936 | ||
937 | size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); | |
938 | res2 = *res; | |
939 | res->start += size * offset; | |
940 | ||
941 | dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (enabling %d VFs shifted by %d)\n", | |
942 | i, &res2, res, num_vfs, offset); | |
943 | pci_update_resource(dev, i + PCI_IOV_RESOURCES); | |
944 | } | |
945 | return 0; | |
946 | } | |
947 | #endif /* CONFIG_PCI_IOV */ | |
948 | ||
fb446ad0 | 949 | #if 0 |
cad5cef6 | 950 | static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) |
184cd4a3 BH |
951 | { |
952 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
953 | struct pnv_phb *phb = hose->private_data; | |
b72c1f65 | 954 | struct pci_dn *pdn = pci_get_pdn(dev); |
184cd4a3 BH |
955 | struct pnv_ioda_pe *pe; |
956 | int pe_num; | |
957 | ||
958 | if (!pdn) { | |
959 | pr_err("%s: Device tree node not associated properly\n", | |
960 | pci_name(dev)); | |
961 | return NULL; | |
962 | } | |
963 | if (pdn->pe_number != IODA_INVALID_PE) | |
964 | return NULL; | |
965 | ||
966 | /* PE#0 has been pre-set */ | |
967 | if (dev->bus->number == 0) | |
968 | pe_num = 0; | |
969 | else | |
970 | pe_num = pnv_ioda_alloc_pe(phb); | |
971 | if (pe_num == IODA_INVALID_PE) { | |
972 | pr_warning("%s: Not enough PE# available, disabling device\n", | |
973 | pci_name(dev)); | |
974 | return NULL; | |
975 | } | |
976 | ||
977 | /* NOTE: We get only one ref to the pci_dev for the pdn, not for the | |
978 | * pointer in the PE data structure, both should be destroyed at the | |
979 | * same time. However, this needs to be looked at more closely again | |
980 | * once we actually start removing things (Hotplug, SR-IOV, ...) | |
981 | * | |
982 | * At some point we want to remove the PDN completely anyways | |
983 | */ | |
984 | pe = &phb->ioda.pe_array[pe_num]; | |
985 | pci_dev_get(dev); | |
986 | pdn->pcidev = dev; | |
987 | pdn->pe_number = pe_num; | |
988 | pe->pdev = dev; | |
989 | pe->pbus = NULL; | |
990 | pe->tce32_seg = -1; | |
991 | pe->mve_number = -1; | |
992 | pe->rid = dev->bus->number << 8 | pdn->devfn; | |
993 | ||
994 | pe_info(pe, "Associated device to PE\n"); | |
995 | ||
996 | if (pnv_ioda_configure_pe(phb, pe)) { | |
997 | /* XXX What do we do here ? */ | |
998 | if (pe_num) | |
999 | pnv_ioda_free_pe(phb, pe_num); | |
1000 | pdn->pe_number = IODA_INVALID_PE; | |
1001 | pe->pdev = NULL; | |
1002 | pci_dev_put(dev); | |
1003 | return NULL; | |
1004 | } | |
1005 | ||
1006 | /* Assign a DMA weight to the device */ | |
1007 | pe->dma_weight = pnv_ioda_dma_weight(dev); | |
1008 | if (pe->dma_weight != 0) { | |
1009 | phb->ioda.dma_weight += pe->dma_weight; | |
1010 | phb->ioda.dma_pe_count++; | |
1011 | } | |
1012 | ||
1013 | /* Link the PE */ | |
1014 | pnv_ioda_link_pe_by_weight(phb, pe); | |
1015 | ||
1016 | return pe; | |
1017 | } | |
fb446ad0 | 1018 | #endif /* Useful for SRIOV case */ |
184cd4a3 BH |
1019 | |
1020 | static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) | |
1021 | { | |
1022 | struct pci_dev *dev; | |
1023 | ||
1024 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
b72c1f65 | 1025 | struct pci_dn *pdn = pci_get_pdn(dev); |
184cd4a3 BH |
1026 | |
1027 | if (pdn == NULL) { | |
1028 | pr_warn("%s: No device node associated with device !\n", | |
1029 | pci_name(dev)); | |
1030 | continue; | |
1031 | } | |
184cd4a3 BH |
1032 | pdn->pe_number = pe->pe_number; |
1033 | pe->dma_weight += pnv_ioda_dma_weight(dev); | |
fb446ad0 | 1034 | if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) |
184cd4a3 BH |
1035 | pnv_ioda_setup_same_PE(dev->subordinate, pe); |
1036 | } | |
1037 | } | |
1038 | ||
fb446ad0 GS |
1039 | /* |
1040 | * There're 2 types of PCI bus sensitive PEs: One that is compromised of | |
1041 | * single PCI bus. Another one that contains the primary PCI bus and its | |
1042 | * subordinate PCI devices and buses. The second type of PE is normally | |
1043 | * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. | |
1044 | */ | |
cad5cef6 | 1045 | static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all) |
184cd4a3 | 1046 | { |
fb446ad0 | 1047 | struct pci_controller *hose = pci_bus_to_host(bus); |
184cd4a3 | 1048 | struct pnv_phb *phb = hose->private_data; |
184cd4a3 | 1049 | struct pnv_ioda_pe *pe; |
262af557 GC |
1050 | int pe_num = IODA_INVALID_PE; |
1051 | ||
1052 | /* Check if PE is determined by M64 */ | |
1053 | if (phb->pick_m64_pe) | |
1054 | pe_num = phb->pick_m64_pe(phb, bus, all); | |
1055 | ||
1056 | /* The PE number isn't pinned by M64 */ | |
1057 | if (pe_num == IODA_INVALID_PE) | |
1058 | pe_num = pnv_ioda_alloc_pe(phb); | |
184cd4a3 | 1059 | |
184cd4a3 | 1060 | if (pe_num == IODA_INVALID_PE) { |
fb446ad0 GS |
1061 | pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", |
1062 | __func__, pci_domain_nr(bus), bus->number); | |
184cd4a3 BH |
1063 | return; |
1064 | } | |
1065 | ||
1066 | pe = &phb->ioda.pe_array[pe_num]; | |
262af557 | 1067 | pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); |
184cd4a3 BH |
1068 | pe->pbus = bus; |
1069 | pe->pdev = NULL; | |
1070 | pe->tce32_seg = -1; | |
1071 | pe->mve_number = -1; | |
b918c62e | 1072 | pe->rid = bus->busn_res.start << 8; |
184cd4a3 BH |
1073 | pe->dma_weight = 0; |
1074 | ||
fb446ad0 GS |
1075 | if (all) |
1076 | pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", | |
1077 | bus->busn_res.start, bus->busn_res.end, pe_num); | |
1078 | else | |
1079 | pe_info(pe, "Secondary bus %d associated with PE#%d\n", | |
1080 | bus->busn_res.start, pe_num); | |
184cd4a3 BH |
1081 | |
1082 | if (pnv_ioda_configure_pe(phb, pe)) { | |
1083 | /* XXX What do we do here ? */ | |
1084 | if (pe_num) | |
1085 | pnv_ioda_free_pe(phb, pe_num); | |
1086 | pe->pbus = NULL; | |
1087 | return; | |
1088 | } | |
1089 | ||
1090 | /* Associate it with all child devices */ | |
1091 | pnv_ioda_setup_same_PE(bus, pe); | |
1092 | ||
7ebdf956 GS |
1093 | /* Put PE to the list */ |
1094 | list_add_tail(&pe->list, &phb->ioda.pe_list); | |
1095 | ||
184cd4a3 BH |
1096 | /* Account for one DMA PE if at least one DMA capable device exist |
1097 | * below the bridge | |
1098 | */ | |
1099 | if (pe->dma_weight != 0) { | |
1100 | phb->ioda.dma_weight += pe->dma_weight; | |
1101 | phb->ioda.dma_pe_count++; | |
1102 | } | |
1103 | ||
1104 | /* Link the PE */ | |
1105 | pnv_ioda_link_pe_by_weight(phb, pe); | |
1106 | } | |
1107 | ||
cad5cef6 | 1108 | static void pnv_ioda_setup_PEs(struct pci_bus *bus) |
184cd4a3 BH |
1109 | { |
1110 | struct pci_dev *dev; | |
fb446ad0 GS |
1111 | |
1112 | pnv_ioda_setup_bus_PE(bus, 0); | |
184cd4a3 BH |
1113 | |
1114 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
fb446ad0 GS |
1115 | if (dev->subordinate) { |
1116 | if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) | |
1117 | pnv_ioda_setup_bus_PE(dev->subordinate, 1); | |
1118 | else | |
1119 | pnv_ioda_setup_PEs(dev->subordinate); | |
1120 | } | |
1121 | } | |
1122 | } | |
1123 | ||
1124 | /* | |
1125 | * Configure PEs so that the downstream PCI buses and devices | |
1126 | * could have their associated PE#. Unfortunately, we didn't | |
1127 | * figure out the way to identify the PLX bridge yet. So we | |
1128 | * simply put the PCI bus and the subordinate behind the root | |
1129 | * port to PE# here. The game rule here is expected to be changed | |
1130 | * as soon as we can detected PLX bridge correctly. | |
1131 | */ | |
cad5cef6 | 1132 | static void pnv_pci_ioda_setup_PEs(void) |
fb446ad0 GS |
1133 | { |
1134 | struct pci_controller *hose, *tmp; | |
262af557 | 1135 | struct pnv_phb *phb; |
fb446ad0 GS |
1136 | |
1137 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
262af557 GC |
1138 | phb = hose->private_data; |
1139 | ||
1140 | /* M64 layout might affect PE allocation */ | |
5ef73567 GS |
1141 | if (phb->reserve_m64_pe) |
1142 | phb->reserve_m64_pe(phb); | |
262af557 | 1143 | |
fb446ad0 | 1144 | pnv_ioda_setup_PEs(hose->bus); |
184cd4a3 BH |
1145 | } |
1146 | } | |
1147 | ||
a8b2f828 | 1148 | #ifdef CONFIG_PCI_IOV |
781a868f WY |
1149 | static int pnv_pci_vf_release_m64(struct pci_dev *pdev) |
1150 | { | |
1151 | struct pci_bus *bus; | |
1152 | struct pci_controller *hose; | |
1153 | struct pnv_phb *phb; | |
1154 | struct pci_dn *pdn; | |
02639b0e | 1155 | int i, j; |
781a868f WY |
1156 | |
1157 | bus = pdev->bus; | |
1158 | hose = pci_bus_to_host(bus); | |
1159 | phb = hose->private_data; | |
1160 | pdn = pci_get_pdn(pdev); | |
1161 | ||
02639b0e WY |
1162 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) |
1163 | for (j = 0; j < M64_PER_IOV; j++) { | |
1164 | if (pdn->m64_wins[i][j] == IODA_INVALID_M64) | |
1165 | continue; | |
1166 | opal_pci_phb_mmio_enable(phb->opal_id, | |
1167 | OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 0); | |
1168 | clear_bit(pdn->m64_wins[i][j], &phb->ioda.m64_bar_alloc); | |
1169 | pdn->m64_wins[i][j] = IODA_INVALID_M64; | |
1170 | } | |
781a868f WY |
1171 | |
1172 | return 0; | |
1173 | } | |
1174 | ||
02639b0e | 1175 | static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) |
781a868f WY |
1176 | { |
1177 | struct pci_bus *bus; | |
1178 | struct pci_controller *hose; | |
1179 | struct pnv_phb *phb; | |
1180 | struct pci_dn *pdn; | |
1181 | unsigned int win; | |
1182 | struct resource *res; | |
02639b0e | 1183 | int i, j; |
781a868f | 1184 | int64_t rc; |
02639b0e WY |
1185 | int total_vfs; |
1186 | resource_size_t size, start; | |
1187 | int pe_num; | |
1188 | int vf_groups; | |
1189 | int vf_per_group; | |
781a868f WY |
1190 | |
1191 | bus = pdev->bus; | |
1192 | hose = pci_bus_to_host(bus); | |
1193 | phb = hose->private_data; | |
1194 | pdn = pci_get_pdn(pdev); | |
02639b0e | 1195 | total_vfs = pci_sriov_get_totalvfs(pdev); |
781a868f WY |
1196 | |
1197 | /* Initialize the m64_wins to IODA_INVALID_M64 */ | |
1198 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) | |
02639b0e WY |
1199 | for (j = 0; j < M64_PER_IOV; j++) |
1200 | pdn->m64_wins[i][j] = IODA_INVALID_M64; | |
1201 | ||
1202 | if (pdn->m64_per_iov == M64_PER_IOV) { | |
1203 | vf_groups = (num_vfs <= M64_PER_IOV) ? num_vfs: M64_PER_IOV; | |
1204 | vf_per_group = (num_vfs <= M64_PER_IOV)? 1: | |
1205 | roundup_pow_of_two(num_vfs) / pdn->m64_per_iov; | |
1206 | } else { | |
1207 | vf_groups = 1; | |
1208 | vf_per_group = 1; | |
1209 | } | |
781a868f WY |
1210 | |
1211 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { | |
1212 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; | |
1213 | if (!res->flags || !res->parent) | |
1214 | continue; | |
1215 | ||
1216 | if (!pnv_pci_is_mem_pref_64(res->flags)) | |
1217 | continue; | |
1218 | ||
02639b0e WY |
1219 | for (j = 0; j < vf_groups; j++) { |
1220 | do { | |
1221 | win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, | |
1222 | phb->ioda.m64_bar_idx + 1, 0); | |
1223 | ||
1224 | if (win >= phb->ioda.m64_bar_idx + 1) | |
1225 | goto m64_failed; | |
1226 | } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); | |
1227 | ||
1228 | pdn->m64_wins[i][j] = win; | |
1229 | ||
1230 | if (pdn->m64_per_iov == M64_PER_IOV) { | |
1231 | size = pci_iov_resource_size(pdev, | |
1232 | PCI_IOV_RESOURCES + i); | |
1233 | size = size * vf_per_group; | |
1234 | start = res->start + size * j; | |
1235 | } else { | |
1236 | size = resource_size(res); | |
1237 | start = res->start; | |
1238 | } | |
1239 | ||
1240 | /* Map the M64 here */ | |
1241 | if (pdn->m64_per_iov == M64_PER_IOV) { | |
1242 | pe_num = pdn->offset + j; | |
1243 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, | |
1244 | pe_num, OPAL_M64_WINDOW_TYPE, | |
1245 | pdn->m64_wins[i][j], 0); | |
1246 | } | |
1247 | ||
1248 | rc = opal_pci_set_phb_mem_window(phb->opal_id, | |
1249 | OPAL_M64_WINDOW_TYPE, | |
1250 | pdn->m64_wins[i][j], | |
1251 | start, | |
1252 | 0, /* unused */ | |
1253 | size); | |
781a868f | 1254 | |
781a868f | 1255 | |
02639b0e WY |
1256 | if (rc != OPAL_SUCCESS) { |
1257 | dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", | |
1258 | win, rc); | |
1259 | goto m64_failed; | |
1260 | } | |
781a868f | 1261 | |
02639b0e WY |
1262 | if (pdn->m64_per_iov == M64_PER_IOV) |
1263 | rc = opal_pci_phb_mmio_enable(phb->opal_id, | |
1264 | OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 2); | |
1265 | else | |
1266 | rc = opal_pci_phb_mmio_enable(phb->opal_id, | |
1267 | OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 1); | |
781a868f | 1268 | |
02639b0e WY |
1269 | if (rc != OPAL_SUCCESS) { |
1270 | dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", | |
1271 | win, rc); | |
1272 | goto m64_failed; | |
1273 | } | |
781a868f WY |
1274 | } |
1275 | } | |
1276 | return 0; | |
1277 | ||
1278 | m64_failed: | |
1279 | pnv_pci_vf_release_m64(pdev); | |
1280 | return -EBUSY; | |
1281 | } | |
1282 | ||
1283 | static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) | |
1284 | { | |
1285 | struct pci_bus *bus; | |
1286 | struct pci_controller *hose; | |
1287 | struct pnv_phb *phb; | |
1288 | struct iommu_table *tbl; | |
1289 | unsigned long addr; | |
1290 | int64_t rc; | |
b348aa65 | 1291 | struct iommu_table_group *table_group; |
781a868f WY |
1292 | |
1293 | bus = dev->bus; | |
1294 | hose = pci_bus_to_host(bus); | |
1295 | phb = hose->private_data; | |
b348aa65 | 1296 | tbl = pe->table_group.tables[0]; |
781a868f WY |
1297 | addr = tbl->it_base; |
1298 | ||
1299 | opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, | |
1300 | pe->pe_number << 1, 1, __pa(addr), | |
1301 | 0, 0x1000); | |
1302 | ||
1303 | rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, | |
1304 | pe->pe_number, | |
1305 | (pe->pe_number << 1) + 1, | |
1306 | pe->tce_bypass_base, | |
1307 | 0); | |
1308 | if (rc) | |
1309 | pe_warn(pe, "OPAL error %ld release DMA window\n", rc); | |
1310 | ||
b348aa65 AK |
1311 | table_group = tbl->it_table_group; |
1312 | if (table_group->group) { | |
1313 | iommu_group_put(table_group->group); | |
1314 | BUG_ON(table_group->group); | |
ac9a5889 | 1315 | } |
781a868f WY |
1316 | iommu_free_table(tbl, of_node_full_name(dev->dev.of_node)); |
1317 | free_pages(addr, get_order(TCE32_TABLE_SIZE)); | |
b348aa65 | 1318 | pe->table_group.tables[0] = NULL; |
781a868f WY |
1319 | } |
1320 | ||
02639b0e | 1321 | static void pnv_ioda_release_vf_PE(struct pci_dev *pdev, u16 num_vfs) |
781a868f WY |
1322 | { |
1323 | struct pci_bus *bus; | |
1324 | struct pci_controller *hose; | |
1325 | struct pnv_phb *phb; | |
1326 | struct pnv_ioda_pe *pe, *pe_n; | |
1327 | struct pci_dn *pdn; | |
02639b0e WY |
1328 | u16 vf_index; |
1329 | int64_t rc; | |
781a868f WY |
1330 | |
1331 | bus = pdev->bus; | |
1332 | hose = pci_bus_to_host(bus); | |
1333 | phb = hose->private_data; | |
02639b0e | 1334 | pdn = pci_get_pdn(pdev); |
781a868f WY |
1335 | |
1336 | if (!pdev->is_physfn) | |
1337 | return; | |
1338 | ||
02639b0e WY |
1339 | if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) { |
1340 | int vf_group; | |
1341 | int vf_per_group; | |
1342 | int vf_index1; | |
1343 | ||
1344 | vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov; | |
1345 | ||
1346 | for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++) | |
1347 | for (vf_index = vf_group * vf_per_group; | |
1348 | vf_index < (vf_group + 1) * vf_per_group && | |
1349 | vf_index < num_vfs; | |
1350 | vf_index++) | |
1351 | for (vf_index1 = vf_group * vf_per_group; | |
1352 | vf_index1 < (vf_group + 1) * vf_per_group && | |
1353 | vf_index1 < num_vfs; | |
1354 | vf_index1++){ | |
1355 | ||
1356 | rc = opal_pci_set_peltv(phb->opal_id, | |
1357 | pdn->offset + vf_index, | |
1358 | pdn->offset + vf_index1, | |
1359 | OPAL_REMOVE_PE_FROM_DOMAIN); | |
1360 | ||
1361 | if (rc) | |
1362 | dev_warn(&pdev->dev, "%s: Failed to unlink same group PE#%d(%lld)\n", | |
1363 | __func__, | |
1364 | pdn->offset + vf_index1, rc); | |
1365 | } | |
1366 | } | |
1367 | ||
781a868f WY |
1368 | list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { |
1369 | if (pe->parent_dev != pdev) | |
1370 | continue; | |
1371 | ||
1372 | pnv_pci_ioda2_release_dma_pe(pdev, pe); | |
1373 | ||
1374 | /* Remove from list */ | |
1375 | mutex_lock(&phb->ioda.pe_list_mutex); | |
1376 | list_del(&pe->list); | |
1377 | mutex_unlock(&phb->ioda.pe_list_mutex); | |
1378 | ||
1379 | pnv_ioda_deconfigure_pe(phb, pe); | |
1380 | ||
1381 | pnv_ioda_free_pe(phb, pe->pe_number); | |
1382 | } | |
1383 | } | |
1384 | ||
1385 | void pnv_pci_sriov_disable(struct pci_dev *pdev) | |
1386 | { | |
1387 | struct pci_bus *bus; | |
1388 | struct pci_controller *hose; | |
1389 | struct pnv_phb *phb; | |
1390 | struct pci_dn *pdn; | |
1391 | struct pci_sriov *iov; | |
1392 | u16 num_vfs; | |
1393 | ||
1394 | bus = pdev->bus; | |
1395 | hose = pci_bus_to_host(bus); | |
1396 | phb = hose->private_data; | |
1397 | pdn = pci_get_pdn(pdev); | |
1398 | iov = pdev->sriov; | |
1399 | num_vfs = pdn->num_vfs; | |
1400 | ||
1401 | /* Release VF PEs */ | |
02639b0e | 1402 | pnv_ioda_release_vf_PE(pdev, num_vfs); |
781a868f WY |
1403 | |
1404 | if (phb->type == PNV_PHB_IODA2) { | |
02639b0e WY |
1405 | if (pdn->m64_per_iov == 1) |
1406 | pnv_pci_vf_resource_shift(pdev, -pdn->offset); | |
781a868f WY |
1407 | |
1408 | /* Release M64 windows */ | |
1409 | pnv_pci_vf_release_m64(pdev); | |
1410 | ||
1411 | /* Release PE numbers */ | |
1412 | bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs); | |
1413 | pdn->offset = 0; | |
1414 | } | |
1415 | } | |
1416 | ||
1417 | static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, | |
1418 | struct pnv_ioda_pe *pe); | |
1419 | static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) | |
1420 | { | |
1421 | struct pci_bus *bus; | |
1422 | struct pci_controller *hose; | |
1423 | struct pnv_phb *phb; | |
1424 | struct pnv_ioda_pe *pe; | |
1425 | int pe_num; | |
1426 | u16 vf_index; | |
1427 | struct pci_dn *pdn; | |
02639b0e | 1428 | int64_t rc; |
781a868f WY |
1429 | |
1430 | bus = pdev->bus; | |
1431 | hose = pci_bus_to_host(bus); | |
1432 | phb = hose->private_data; | |
1433 | pdn = pci_get_pdn(pdev); | |
1434 | ||
1435 | if (!pdev->is_physfn) | |
1436 | return; | |
1437 | ||
1438 | /* Reserve PE for each VF */ | |
1439 | for (vf_index = 0; vf_index < num_vfs; vf_index++) { | |
1440 | pe_num = pdn->offset + vf_index; | |
1441 | ||
1442 | pe = &phb->ioda.pe_array[pe_num]; | |
1443 | pe->pe_number = pe_num; | |
1444 | pe->phb = phb; | |
1445 | pe->flags = PNV_IODA_PE_VF; | |
1446 | pe->pbus = NULL; | |
1447 | pe->parent_dev = pdev; | |
1448 | pe->tce32_seg = -1; | |
1449 | pe->mve_number = -1; | |
1450 | pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | | |
1451 | pci_iov_virtfn_devfn(pdev, vf_index); | |
1452 | ||
1453 | pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n", | |
1454 | hose->global_number, pdev->bus->number, | |
1455 | PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), | |
1456 | PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); | |
1457 | ||
1458 | if (pnv_ioda_configure_pe(phb, pe)) { | |
1459 | /* XXX What do we do here ? */ | |
1460 | if (pe_num) | |
1461 | pnv_ioda_free_pe(phb, pe_num); | |
1462 | pe->pdev = NULL; | |
1463 | continue; | |
1464 | } | |
1465 | ||
781a868f WY |
1466 | /* Put PE to the list */ |
1467 | mutex_lock(&phb->ioda.pe_list_mutex); | |
1468 | list_add_tail(&pe->list, &phb->ioda.pe_list); | |
1469 | mutex_unlock(&phb->ioda.pe_list_mutex); | |
1470 | ||
1471 | pnv_pci_ioda2_setup_dma_pe(phb, pe); | |
1472 | } | |
02639b0e WY |
1473 | |
1474 | if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) { | |
1475 | int vf_group; | |
1476 | int vf_per_group; | |
1477 | int vf_index1; | |
1478 | ||
1479 | vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov; | |
1480 | ||
1481 | for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++) { | |
1482 | for (vf_index = vf_group * vf_per_group; | |
1483 | vf_index < (vf_group + 1) * vf_per_group && | |
1484 | vf_index < num_vfs; | |
1485 | vf_index++) { | |
1486 | for (vf_index1 = vf_group * vf_per_group; | |
1487 | vf_index1 < (vf_group + 1) * vf_per_group && | |
1488 | vf_index1 < num_vfs; | |
1489 | vf_index1++) { | |
1490 | ||
1491 | rc = opal_pci_set_peltv(phb->opal_id, | |
1492 | pdn->offset + vf_index, | |
1493 | pdn->offset + vf_index1, | |
1494 | OPAL_ADD_PE_TO_DOMAIN); | |
1495 | ||
1496 | if (rc) | |
1497 | dev_warn(&pdev->dev, "%s: Failed to link same group PE#%d(%lld)\n", | |
1498 | __func__, | |
1499 | pdn->offset + vf_index1, rc); | |
1500 | } | |
1501 | } | |
1502 | } | |
1503 | } | |
781a868f WY |
1504 | } |
1505 | ||
1506 | int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) | |
1507 | { | |
1508 | struct pci_bus *bus; | |
1509 | struct pci_controller *hose; | |
1510 | struct pnv_phb *phb; | |
1511 | struct pci_dn *pdn; | |
1512 | int ret; | |
1513 | ||
1514 | bus = pdev->bus; | |
1515 | hose = pci_bus_to_host(bus); | |
1516 | phb = hose->private_data; | |
1517 | pdn = pci_get_pdn(pdev); | |
1518 | ||
1519 | if (phb->type == PNV_PHB_IODA2) { | |
1520 | /* Calculate available PE for required VFs */ | |
1521 | mutex_lock(&phb->ioda.pe_alloc_mutex); | |
1522 | pdn->offset = bitmap_find_next_zero_area( | |
1523 | phb->ioda.pe_alloc, phb->ioda.total_pe, | |
1524 | 0, num_vfs, 0); | |
1525 | if (pdn->offset >= phb->ioda.total_pe) { | |
1526 | mutex_unlock(&phb->ioda.pe_alloc_mutex); | |
1527 | dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); | |
1528 | pdn->offset = 0; | |
1529 | return -EBUSY; | |
1530 | } | |
1531 | bitmap_set(phb->ioda.pe_alloc, pdn->offset, num_vfs); | |
1532 | pdn->num_vfs = num_vfs; | |
1533 | mutex_unlock(&phb->ioda.pe_alloc_mutex); | |
1534 | ||
1535 | /* Assign M64 window accordingly */ | |
02639b0e | 1536 | ret = pnv_pci_vf_assign_m64(pdev, num_vfs); |
781a868f WY |
1537 | if (ret) { |
1538 | dev_info(&pdev->dev, "Not enough M64 window resources\n"); | |
1539 | goto m64_failed; | |
1540 | } | |
1541 | ||
1542 | /* | |
1543 | * When using one M64 BAR to map one IOV BAR, we need to shift | |
1544 | * the IOV BAR according to the PE# allocated to the VFs. | |
1545 | * Otherwise, the PE# for the VF will conflict with others. | |
1546 | */ | |
02639b0e WY |
1547 | if (pdn->m64_per_iov == 1) { |
1548 | ret = pnv_pci_vf_resource_shift(pdev, pdn->offset); | |
1549 | if (ret) | |
1550 | goto m64_failed; | |
1551 | } | |
781a868f WY |
1552 | } |
1553 | ||
1554 | /* Setup VF PEs */ | |
1555 | pnv_ioda_setup_vf_PE(pdev, num_vfs); | |
1556 | ||
1557 | return 0; | |
1558 | ||
1559 | m64_failed: | |
1560 | bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs); | |
1561 | pdn->offset = 0; | |
1562 | ||
1563 | return ret; | |
1564 | } | |
1565 | ||
a8b2f828 GS |
1566 | int pcibios_sriov_disable(struct pci_dev *pdev) |
1567 | { | |
781a868f WY |
1568 | pnv_pci_sriov_disable(pdev); |
1569 | ||
a8b2f828 GS |
1570 | /* Release PCI data */ |
1571 | remove_dev_pci_data(pdev); | |
1572 | return 0; | |
1573 | } | |
1574 | ||
1575 | int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) | |
1576 | { | |
1577 | /* Allocate PCI data */ | |
1578 | add_dev_pci_data(pdev); | |
781a868f WY |
1579 | |
1580 | pnv_pci_sriov_enable(pdev, num_vfs); | |
a8b2f828 GS |
1581 | return 0; |
1582 | } | |
1583 | #endif /* CONFIG_PCI_IOV */ | |
1584 | ||
959c9bdd | 1585 | static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) |
184cd4a3 | 1586 | { |
b72c1f65 | 1587 | struct pci_dn *pdn = pci_get_pdn(pdev); |
959c9bdd | 1588 | struct pnv_ioda_pe *pe; |
184cd4a3 | 1589 | |
959c9bdd GS |
1590 | /* |
1591 | * The function can be called while the PE# | |
1592 | * hasn't been assigned. Do nothing for the | |
1593 | * case. | |
1594 | */ | |
1595 | if (!pdn || pdn->pe_number == IODA_INVALID_PE) | |
1596 | return; | |
184cd4a3 | 1597 | |
959c9bdd | 1598 | pe = &phb->ioda.pe_array[pdn->pe_number]; |
cd15b048 | 1599 | WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); |
b348aa65 | 1600 | set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); |
4617082e AK |
1601 | /* |
1602 | * Note: iommu_add_device() will fail here as | |
1603 | * for physical PE: the device is already added by now; | |
1604 | * for virtual PE: sysfs entries are not ready yet and | |
1605 | * tce_iommu_bus_notifier will add the device to a group later. | |
1606 | */ | |
184cd4a3 BH |
1607 | } |
1608 | ||
763d2d8d | 1609 | static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) |
cd15b048 | 1610 | { |
763d2d8d DA |
1611 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
1612 | struct pnv_phb *phb = hose->private_data; | |
cd15b048 BH |
1613 | struct pci_dn *pdn = pci_get_pdn(pdev); |
1614 | struct pnv_ioda_pe *pe; | |
1615 | uint64_t top; | |
1616 | bool bypass = false; | |
1617 | ||
1618 | if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) | |
1619 | return -ENODEV;; | |
1620 | ||
1621 | pe = &phb->ioda.pe_array[pdn->pe_number]; | |
1622 | if (pe->tce_bypass_enabled) { | |
1623 | top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; | |
1624 | bypass = (dma_mask >= top); | |
1625 | } | |
1626 | ||
1627 | if (bypass) { | |
1628 | dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); | |
1629 | set_dma_ops(&pdev->dev, &dma_direct_ops); | |
1630 | set_dma_offset(&pdev->dev, pe->tce_bypass_base); | |
1631 | } else { | |
1632 | dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); | |
1633 | set_dma_ops(&pdev->dev, &dma_iommu_ops); | |
b348aa65 | 1634 | set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); |
cd15b048 | 1635 | } |
a32305bf | 1636 | *pdev->dev.dma_mask = dma_mask; |
cd15b048 BH |
1637 | return 0; |
1638 | } | |
1639 | ||
fe7e85c6 GS |
1640 | static u64 pnv_pci_ioda_dma_get_required_mask(struct pnv_phb *phb, |
1641 | struct pci_dev *pdev) | |
1642 | { | |
1643 | struct pci_dn *pdn = pci_get_pdn(pdev); | |
1644 | struct pnv_ioda_pe *pe; | |
1645 | u64 end, mask; | |
1646 | ||
1647 | if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) | |
1648 | return 0; | |
1649 | ||
1650 | pe = &phb->ioda.pe_array[pdn->pe_number]; | |
1651 | if (!pe->tce_bypass_enabled) | |
1652 | return __dma_get_required_mask(&pdev->dev); | |
1653 | ||
1654 | ||
1655 | end = pe->tce_bypass_base + memblock_end_of_DRAM(); | |
1656 | mask = 1ULL << (fls64(end) - 1); | |
1657 | mask += mask - 1; | |
1658 | ||
1659 | return mask; | |
1660 | } | |
1661 | ||
dff4a39e | 1662 | static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, |
ea30e99e | 1663 | struct pci_bus *bus) |
74251fe2 BH |
1664 | { |
1665 | struct pci_dev *dev; | |
1666 | ||
1667 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
b348aa65 | 1668 | set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); |
4617082e | 1669 | iommu_add_device(&dev->dev); |
dff4a39e | 1670 | |
74251fe2 | 1671 | if (dev->subordinate) |
ea30e99e | 1672 | pnv_ioda_setup_bus_dma(pe, dev->subordinate); |
74251fe2 BH |
1673 | } |
1674 | } | |
1675 | ||
decbda25 AK |
1676 | static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl, |
1677 | unsigned long index, unsigned long npages, bool rm) | |
4cce9550 | 1678 | { |
b348aa65 AK |
1679 | struct pnv_ioda_pe *pe = container_of(tbl->it_table_group, |
1680 | struct pnv_ioda_pe, table_group); | |
3ad26e5c BH |
1681 | __be64 __iomem *invalidate = rm ? |
1682 | (__be64 __iomem *)pe->tce_inval_reg_phys : | |
1683 | (__be64 __iomem *)tbl->it_index; | |
4cce9550 | 1684 | unsigned long start, end, inc; |
b0376c9b | 1685 | const unsigned shift = tbl->it_page_shift; |
4cce9550 | 1686 | |
decbda25 AK |
1687 | start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); |
1688 | end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + | |
1689 | npages - 1); | |
4cce9550 GS |
1690 | |
1691 | /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ | |
1692 | if (tbl->it_busno) { | |
b0376c9b AK |
1693 | start <<= shift; |
1694 | end <<= shift; | |
1695 | inc = 128ull << shift; | |
4cce9550 GS |
1696 | start |= tbl->it_busno; |
1697 | end |= tbl->it_busno; | |
1698 | } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { | |
1699 | /* p7ioc-style invalidation, 2 TCEs per write */ | |
1700 | start |= (1ull << 63); | |
1701 | end |= (1ull << 63); | |
1702 | inc = 16; | |
1703 | } else { | |
1704 | /* Default (older HW) */ | |
1705 | inc = 128; | |
1706 | } | |
1707 | ||
1708 | end |= inc - 1; /* round up end to be different than start */ | |
1709 | ||
1710 | mb(); /* Ensure above stores are visible */ | |
1711 | while (start <= end) { | |
8e0a1611 | 1712 | if (rm) |
3ad26e5c | 1713 | __raw_rm_writeq(cpu_to_be64(start), invalidate); |
8e0a1611 | 1714 | else |
3ad26e5c | 1715 | __raw_writeq(cpu_to_be64(start), invalidate); |
4cce9550 GS |
1716 | start += inc; |
1717 | } | |
1718 | ||
1719 | /* | |
1720 | * The iommu layer will do another mb() for us on build() | |
1721 | * and we don't care on free() | |
1722 | */ | |
1723 | } | |
1724 | ||
decbda25 AK |
1725 | static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, |
1726 | long npages, unsigned long uaddr, | |
1727 | enum dma_data_direction direction, | |
1728 | struct dma_attrs *attrs) | |
1729 | { | |
1730 | int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, | |
1731 | attrs); | |
1732 | ||
1733 | if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) | |
1734 | pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); | |
1735 | ||
1736 | return ret; | |
1737 | } | |
1738 | ||
1739 | static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, | |
1740 | long npages) | |
1741 | { | |
1742 | pnv_tce_free(tbl, index, npages); | |
1743 | ||
1744 | if (tbl->it_type & TCE_PCI_SWINV_FREE) | |
1745 | pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); | |
1746 | } | |
1747 | ||
da004c36 | 1748 | static struct iommu_table_ops pnv_ioda1_iommu_ops = { |
decbda25 AK |
1749 | .set = pnv_ioda1_tce_build, |
1750 | .clear = pnv_ioda1_tce_free, | |
da004c36 AK |
1751 | .get = pnv_tce_get, |
1752 | }; | |
1753 | ||
decbda25 AK |
1754 | static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, |
1755 | unsigned long index, unsigned long npages, bool rm) | |
4cce9550 | 1756 | { |
b348aa65 AK |
1757 | struct pnv_ioda_pe *pe = container_of(tbl->it_table_group, |
1758 | struct pnv_ioda_pe, table_group); | |
4cce9550 | 1759 | unsigned long start, end, inc; |
3ad26e5c BH |
1760 | __be64 __iomem *invalidate = rm ? |
1761 | (__be64 __iomem *)pe->tce_inval_reg_phys : | |
1762 | (__be64 __iomem *)tbl->it_index; | |
b0376c9b | 1763 | const unsigned shift = tbl->it_page_shift; |
4cce9550 GS |
1764 | |
1765 | /* We'll invalidate DMA address in PE scope */ | |
b0376c9b | 1766 | start = 0x2ull << 60; |
4cce9550 GS |
1767 | start |= (pe->pe_number & 0xFF); |
1768 | end = start; | |
1769 | ||
1770 | /* Figure out the start, end and step */ | |
decbda25 AK |
1771 | start |= (index << shift); |
1772 | end |= ((index + npages - 1) << shift); | |
b0376c9b | 1773 | inc = (0x1ull << shift); |
4cce9550 GS |
1774 | mb(); |
1775 | ||
1776 | while (start <= end) { | |
8e0a1611 | 1777 | if (rm) |
3ad26e5c | 1778 | __raw_rm_writeq(cpu_to_be64(start), invalidate); |
8e0a1611 | 1779 | else |
3ad26e5c | 1780 | __raw_writeq(cpu_to_be64(start), invalidate); |
4cce9550 GS |
1781 | start += inc; |
1782 | } | |
1783 | } | |
1784 | ||
decbda25 AK |
1785 | static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, |
1786 | long npages, unsigned long uaddr, | |
1787 | enum dma_data_direction direction, | |
1788 | struct dma_attrs *attrs) | |
4cce9550 | 1789 | { |
decbda25 AK |
1790 | int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, |
1791 | attrs); | |
4cce9550 | 1792 | |
decbda25 AK |
1793 | if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) |
1794 | pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); | |
1795 | ||
1796 | return ret; | |
1797 | } | |
1798 | ||
1799 | static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, | |
1800 | long npages) | |
1801 | { | |
1802 | pnv_tce_free(tbl, index, npages); | |
1803 | ||
1804 | if (tbl->it_type & TCE_PCI_SWINV_FREE) | |
1805 | pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); | |
4cce9550 GS |
1806 | } |
1807 | ||
da004c36 | 1808 | static struct iommu_table_ops pnv_ioda2_iommu_ops = { |
decbda25 AK |
1809 | .set = pnv_ioda2_tce_build, |
1810 | .clear = pnv_ioda2_tce_free, | |
da004c36 AK |
1811 | .get = pnv_tce_get, |
1812 | }; | |
1813 | ||
cad5cef6 GKH |
1814 | static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, |
1815 | struct pnv_ioda_pe *pe, unsigned int base, | |
1816 | unsigned int segs) | |
184cd4a3 BH |
1817 | { |
1818 | ||
1819 | struct page *tce_mem = NULL; | |
1820 | const __be64 *swinvp; | |
1821 | struct iommu_table *tbl; | |
1822 | unsigned int i; | |
1823 | int64_t rc; | |
1824 | void *addr; | |
1825 | ||
184cd4a3 BH |
1826 | /* XXX FIXME: Handle 64-bit only DMA devices */ |
1827 | /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ | |
1828 | /* XXX FIXME: Allocate multi-level tables on PHB3 */ | |
1829 | ||
1830 | /* We shouldn't already have a 32-bit DMA associated */ | |
1831 | if (WARN_ON(pe->tce32_seg >= 0)) | |
1832 | return; | |
1833 | ||
b348aa65 AK |
1834 | tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, |
1835 | phb->hose->node); | |
1836 | tbl->it_table_group = &pe->table_group; | |
1837 | pe->table_group.tables[0] = tbl; | |
1838 | iommu_register_group(&pe->table_group, phb->hose->global_number, | |
1839 | pe->pe_number); | |
c5773822 | 1840 | |
184cd4a3 BH |
1841 | /* Grab a 32-bit TCE table */ |
1842 | pe->tce32_seg = base; | |
1843 | pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", | |
1844 | (base << 28), ((base + segs) << 28) - 1); | |
1845 | ||
1846 | /* XXX Currently, we allocate one big contiguous table for the | |
1847 | * TCEs. We only really need one chunk per 256M of TCE space | |
1848 | * (ie per segment) but that's an optimization for later, it | |
1849 | * requires some added smarts with our get/put_tce implementation | |
1850 | */ | |
1851 | tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, | |
1852 | get_order(TCE32_TABLE_SIZE * segs)); | |
1853 | if (!tce_mem) { | |
1854 | pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); | |
1855 | goto fail; | |
1856 | } | |
1857 | addr = page_address(tce_mem); | |
1858 | memset(addr, 0, TCE32_TABLE_SIZE * segs); | |
1859 | ||
1860 | /* Configure HW */ | |
1861 | for (i = 0; i < segs; i++) { | |
1862 | rc = opal_pci_map_pe_dma_window(phb->opal_id, | |
1863 | pe->pe_number, | |
1864 | base + i, 1, | |
1865 | __pa(addr) + TCE32_TABLE_SIZE * i, | |
1866 | TCE32_TABLE_SIZE, 0x1000); | |
1867 | if (rc) { | |
1868 | pe_err(pe, " Failed to configure 32-bit TCE table," | |
1869 | " err %ld\n", rc); | |
1870 | goto fail; | |
1871 | } | |
1872 | } | |
1873 | ||
1874 | /* Setup linux iommu table */ | |
184cd4a3 | 1875 | pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs, |
8fa5d454 | 1876 | base << 28, IOMMU_PAGE_SHIFT_4K); |
184cd4a3 BH |
1877 | |
1878 | /* OPAL variant of P7IOC SW invalidated TCEs */ | |
1879 | swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); | |
1880 | if (swinvp) { | |
1881 | /* We need a couple more fields -- an address and a data | |
1882 | * to or. Since the bus is only printed out on table free | |
1883 | * errors, and on the first pass the data will be a relative | |
1884 | * bus number, print that out instead. | |
1885 | */ | |
8e0a1611 AK |
1886 | pe->tce_inval_reg_phys = be64_to_cpup(swinvp); |
1887 | tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys, | |
1888 | 8); | |
65fd766b GS |
1889 | tbl->it_type |= (TCE_PCI_SWINV_CREATE | |
1890 | TCE_PCI_SWINV_FREE | | |
1891 | TCE_PCI_SWINV_PAIR); | |
184cd4a3 | 1892 | } |
da004c36 | 1893 | tbl->it_ops = &pnv_ioda1_iommu_ops; |
184cd4a3 BH |
1894 | iommu_init_table(tbl, phb->hose->node); |
1895 | ||
781a868f | 1896 | if (pe->flags & PNV_IODA_PE_DEV) { |
4617082e AK |
1897 | /* |
1898 | * Setting table base here only for carrying iommu_group | |
1899 | * further down to let iommu_add_device() do the job. | |
1900 | * pnv_pci_ioda_dma_dev_setup will override it later anyway. | |
1901 | */ | |
1902 | set_iommu_table_base(&pe->pdev->dev, tbl); | |
1903 | iommu_add_device(&pe->pdev->dev); | |
c5773822 | 1904 | } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) |
ea30e99e | 1905 | pnv_ioda_setup_bus_dma(pe, pe->pbus); |
74251fe2 | 1906 | |
184cd4a3 BH |
1907 | return; |
1908 | fail: | |
1909 | /* XXX Failure: Try to fallback to 64-bit only ? */ | |
1910 | if (pe->tce32_seg >= 0) | |
1911 | pe->tce32_seg = -1; | |
1912 | if (tce_mem) | |
1913 | __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs)); | |
1914 | } | |
1915 | ||
cd15b048 BH |
1916 | static void pnv_pci_ioda2_set_bypass(struct iommu_table *tbl, bool enable) |
1917 | { | |
b348aa65 AK |
1918 | struct pnv_ioda_pe *pe = container_of(tbl->it_table_group, |
1919 | struct pnv_ioda_pe, table_group); | |
cd15b048 BH |
1920 | uint16_t window_id = (pe->pe_number << 1 ) + 1; |
1921 | int64_t rc; | |
1922 | ||
1923 | pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); | |
1924 | if (enable) { | |
1925 | phys_addr_t top = memblock_end_of_DRAM(); | |
1926 | ||
1927 | top = roundup_pow_of_two(top); | |
1928 | rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, | |
1929 | pe->pe_number, | |
1930 | window_id, | |
1931 | pe->tce_bypass_base, | |
1932 | top); | |
1933 | } else { | |
1934 | rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, | |
1935 | pe->pe_number, | |
1936 | window_id, | |
1937 | pe->tce_bypass_base, | |
1938 | 0); | |
cd15b048 BH |
1939 | } |
1940 | if (rc) | |
1941 | pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); | |
1942 | else | |
1943 | pe->tce_bypass_enabled = enable; | |
1944 | } | |
1945 | ||
1946 | static void pnv_pci_ioda2_setup_bypass_pe(struct pnv_phb *phb, | |
1947 | struct pnv_ioda_pe *pe) | |
1948 | { | |
1949 | /* TVE #1 is selected by PCI address bit 59 */ | |
1950 | pe->tce_bypass_base = 1ull << 59; | |
1951 | ||
1952 | /* Install set_bypass callback for VFIO */ | |
b348aa65 | 1953 | pe->table_group.tables[0]->set_bypass = pnv_pci_ioda2_set_bypass; |
cd15b048 BH |
1954 | |
1955 | /* Enable bypass by default */ | |
b348aa65 | 1956 | pnv_pci_ioda2_set_bypass(pe->table_group.tables[0], true); |
cd15b048 BH |
1957 | } |
1958 | ||
373f5657 GS |
1959 | static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, |
1960 | struct pnv_ioda_pe *pe) | |
1961 | { | |
1962 | struct page *tce_mem = NULL; | |
1963 | void *addr; | |
1964 | const __be64 *swinvp; | |
1965 | struct iommu_table *tbl; | |
1966 | unsigned int tce_table_size, end; | |
1967 | int64_t rc; | |
1968 | ||
1969 | /* We shouldn't already have a 32-bit DMA associated */ | |
1970 | if (WARN_ON(pe->tce32_seg >= 0)) | |
1971 | return; | |
1972 | ||
b348aa65 AK |
1973 | tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, |
1974 | phb->hose->node); | |
1975 | tbl->it_table_group = &pe->table_group; | |
1976 | pe->table_group.tables[0] = tbl; | |
1977 | iommu_register_group(&pe->table_group, phb->hose->global_number, | |
1978 | pe->pe_number); | |
c5773822 | 1979 | |
373f5657 GS |
1980 | /* The PE will reserve all possible 32-bits space */ |
1981 | pe->tce32_seg = 0; | |
1982 | end = (1 << ilog2(phb->ioda.m32_pci_base)); | |
1983 | tce_table_size = (end / 0x1000) * 8; | |
1984 | pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", | |
1985 | end); | |
1986 | ||
1987 | /* Allocate TCE table */ | |
1988 | tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, | |
1989 | get_order(tce_table_size)); | |
1990 | if (!tce_mem) { | |
1991 | pe_err(pe, "Failed to allocate a 32-bit TCE memory\n"); | |
1992 | goto fail; | |
1993 | } | |
1994 | addr = page_address(tce_mem); | |
1995 | memset(addr, 0, tce_table_size); | |
1996 | ||
1997 | /* | |
1998 | * Map TCE table through TVT. The TVE index is the PE number | |
1999 | * shifted by 1 bit for 32-bits DMA space. | |
2000 | */ | |
2001 | rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, | |
2002 | pe->pe_number << 1, 1, __pa(addr), | |
2003 | tce_table_size, 0x1000); | |
2004 | if (rc) { | |
2005 | pe_err(pe, "Failed to configure 32-bit TCE table," | |
2006 | " err %ld\n", rc); | |
2007 | goto fail; | |
2008 | } | |
2009 | ||
2010 | /* Setup linux iommu table */ | |
8fa5d454 AK |
2011 | pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0, |
2012 | IOMMU_PAGE_SHIFT_4K); | |
373f5657 GS |
2013 | |
2014 | /* OPAL variant of PHB3 invalidated TCEs */ | |
2015 | swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); | |
2016 | if (swinvp) { | |
2017 | /* We need a couple more fields -- an address and a data | |
2018 | * to or. Since the bus is only printed out on table free | |
2019 | * errors, and on the first pass the data will be a relative | |
2020 | * bus number, print that out instead. | |
2021 | */ | |
8e0a1611 AK |
2022 | pe->tce_inval_reg_phys = be64_to_cpup(swinvp); |
2023 | tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys, | |
2024 | 8); | |
65fd766b | 2025 | tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); |
373f5657 | 2026 | } |
da004c36 | 2027 | tbl->it_ops = &pnv_ioda2_iommu_ops; |
373f5657 GS |
2028 | iommu_init_table(tbl, phb->hose->node); |
2029 | ||
781a868f | 2030 | if (pe->flags & PNV_IODA_PE_DEV) { |
4617082e AK |
2031 | /* |
2032 | * Setting table base here only for carrying iommu_group | |
2033 | * further down to let iommu_add_device() do the job. | |
2034 | * pnv_pci_ioda_dma_dev_setup will override it later anyway. | |
2035 | */ | |
2036 | set_iommu_table_base(&pe->pdev->dev, tbl); | |
2037 | iommu_add_device(&pe->pdev->dev); | |
c5773822 | 2038 | } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) |
ea30e99e | 2039 | pnv_ioda_setup_bus_dma(pe, pe->pbus); |
74251fe2 | 2040 | |
cd15b048 | 2041 | /* Also create a bypass window */ |
4e287840 TLSC |
2042 | if (!pnv_iommu_bypass_disabled) |
2043 | pnv_pci_ioda2_setup_bypass_pe(phb, pe); | |
2044 | ||
373f5657 GS |
2045 | return; |
2046 | fail: | |
2047 | if (pe->tce32_seg >= 0) | |
2048 | pe->tce32_seg = -1; | |
2049 | if (tce_mem) | |
2050 | __free_pages(tce_mem, get_order(tce_table_size)); | |
2051 | } | |
2052 | ||
cad5cef6 | 2053 | static void pnv_ioda_setup_dma(struct pnv_phb *phb) |
184cd4a3 BH |
2054 | { |
2055 | struct pci_controller *hose = phb->hose; | |
2056 | unsigned int residual, remaining, segs, tw, base; | |
2057 | struct pnv_ioda_pe *pe; | |
2058 | ||
2059 | /* If we have more PE# than segments available, hand out one | |
2060 | * per PE until we run out and let the rest fail. If not, | |
2061 | * then we assign at least one segment per PE, plus more based | |
2062 | * on the amount of devices under that PE | |
2063 | */ | |
2064 | if (phb->ioda.dma_pe_count > phb->ioda.tce32_count) | |
2065 | residual = 0; | |
2066 | else | |
2067 | residual = phb->ioda.tce32_count - | |
2068 | phb->ioda.dma_pe_count; | |
2069 | ||
2070 | pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n", | |
2071 | hose->global_number, phb->ioda.tce32_count); | |
2072 | pr_info("PCI: %d PE# for a total weight of %d\n", | |
2073 | phb->ioda.dma_pe_count, phb->ioda.dma_weight); | |
2074 | ||
2075 | /* Walk our PE list and configure their DMA segments, hand them | |
2076 | * out one base segment plus any residual segments based on | |
2077 | * weight | |
2078 | */ | |
2079 | remaining = phb->ioda.tce32_count; | |
2080 | tw = phb->ioda.dma_weight; | |
2081 | base = 0; | |
7ebdf956 | 2082 | list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { |
184cd4a3 BH |
2083 | if (!pe->dma_weight) |
2084 | continue; | |
2085 | if (!remaining) { | |
2086 | pe_warn(pe, "No DMA32 resources available\n"); | |
2087 | continue; | |
2088 | } | |
2089 | segs = 1; | |
2090 | if (residual) { | |
2091 | segs += ((pe->dma_weight * residual) + (tw / 2)) / tw; | |
2092 | if (segs > remaining) | |
2093 | segs = remaining; | |
2094 | } | |
373f5657 GS |
2095 | |
2096 | /* | |
2097 | * For IODA2 compliant PHB3, we needn't care about the weight. | |
2098 | * The all available 32-bits DMA space will be assigned to | |
2099 | * the specific PE. | |
2100 | */ | |
2101 | if (phb->type == PNV_PHB_IODA1) { | |
2102 | pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", | |
2103 | pe->dma_weight, segs); | |
2104 | pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs); | |
2105 | } else { | |
2106 | pe_info(pe, "Assign DMA32 space\n"); | |
2107 | segs = 0; | |
2108 | pnv_pci_ioda2_setup_dma_pe(phb, pe); | |
2109 | } | |
2110 | ||
184cd4a3 BH |
2111 | remaining -= segs; |
2112 | base += segs; | |
2113 | } | |
2114 | } | |
2115 | ||
2116 | #ifdef CONFIG_PCI_MSI | |
137436c9 GS |
2117 | static void pnv_ioda2_msi_eoi(struct irq_data *d) |
2118 | { | |
2119 | unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); | |
2120 | struct irq_chip *chip = irq_data_get_irq_chip(d); | |
2121 | struct pnv_phb *phb = container_of(chip, struct pnv_phb, | |
2122 | ioda.irq_chip); | |
2123 | int64_t rc; | |
2124 | ||
2125 | rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); | |
2126 | WARN_ON_ONCE(rc); | |
2127 | ||
2128 | icp_native_eoi(d); | |
2129 | } | |
2130 | ||
fd9a1c26 IM |
2131 | |
2132 | static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) | |
2133 | { | |
2134 | struct irq_data *idata; | |
2135 | struct irq_chip *ichip; | |
2136 | ||
2137 | if (phb->type != PNV_PHB_IODA2) | |
2138 | return; | |
2139 | ||
2140 | if (!phb->ioda.irq_chip_init) { | |
2141 | /* | |
2142 | * First time we setup an MSI IRQ, we need to setup the | |
2143 | * corresponding IRQ chip to route correctly. | |
2144 | */ | |
2145 | idata = irq_get_irq_data(virq); | |
2146 | ichip = irq_data_get_irq_chip(idata); | |
2147 | phb->ioda.irq_chip_init = 1; | |
2148 | phb->ioda.irq_chip = *ichip; | |
2149 | phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; | |
2150 | } | |
2151 | irq_set_chip(virq, &phb->ioda.irq_chip); | |
2152 | } | |
2153 | ||
80c49c7e IM |
2154 | #ifdef CONFIG_CXL_BASE |
2155 | ||
6f963ec2 | 2156 | struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev) |
80c49c7e IM |
2157 | { |
2158 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
2159 | ||
6f963ec2 | 2160 | return of_node_get(hose->dn); |
80c49c7e | 2161 | } |
6f963ec2 | 2162 | EXPORT_SYMBOL(pnv_pci_get_phb_node); |
80c49c7e | 2163 | |
1212aa1c | 2164 | int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode) |
80c49c7e IM |
2165 | { |
2166 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
2167 | struct pnv_phb *phb = hose->private_data; | |
2168 | struct pnv_ioda_pe *pe; | |
2169 | int rc; | |
2170 | ||
2171 | pe = pnv_ioda_get_pe(dev); | |
2172 | if (!pe) | |
2173 | return -ENODEV; | |
2174 | ||
2175 | pe_info(pe, "Switching PHB to CXL\n"); | |
2176 | ||
1212aa1c | 2177 | rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number); |
80c49c7e IM |
2178 | if (rc) |
2179 | dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc); | |
2180 | ||
2181 | return rc; | |
2182 | } | |
1212aa1c | 2183 | EXPORT_SYMBOL(pnv_phb_to_cxl_mode); |
80c49c7e IM |
2184 | |
2185 | /* Find PHB for cxl dev and allocate MSI hwirqs? | |
2186 | * Returns the absolute hardware IRQ number | |
2187 | */ | |
2188 | int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num) | |
2189 | { | |
2190 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
2191 | struct pnv_phb *phb = hose->private_data; | |
2192 | int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num); | |
2193 | ||
2194 | if (hwirq < 0) { | |
2195 | dev_warn(&dev->dev, "Failed to find a free MSI\n"); | |
2196 | return -ENOSPC; | |
2197 | } | |
2198 | ||
2199 | return phb->msi_base + hwirq; | |
2200 | } | |
2201 | EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs); | |
2202 | ||
2203 | void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num) | |
2204 | { | |
2205 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
2206 | struct pnv_phb *phb = hose->private_data; | |
2207 | ||
2208 | msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num); | |
2209 | } | |
2210 | EXPORT_SYMBOL(pnv_cxl_release_hwirqs); | |
2211 | ||
2212 | void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs, | |
2213 | struct pci_dev *dev) | |
2214 | { | |
2215 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
2216 | struct pnv_phb *phb = hose->private_data; | |
2217 | int i, hwirq; | |
2218 | ||
2219 | for (i = 1; i < CXL_IRQ_RANGES; i++) { | |
2220 | if (!irqs->range[i]) | |
2221 | continue; | |
2222 | pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n", | |
2223 | i, irqs->offset[i], | |
2224 | irqs->range[i]); | |
2225 | hwirq = irqs->offset[i] - phb->msi_base; | |
2226 | msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, | |
2227 | irqs->range[i]); | |
2228 | } | |
2229 | } | |
2230 | EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges); | |
2231 | ||
2232 | int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs, | |
2233 | struct pci_dev *dev, int num) | |
2234 | { | |
2235 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
2236 | struct pnv_phb *phb = hose->private_data; | |
2237 | int i, hwirq, try; | |
2238 | ||
2239 | memset(irqs, 0, sizeof(struct cxl_irq_ranges)); | |
2240 | ||
2241 | /* 0 is reserved for the multiplexed PSL DSI interrupt */ | |
2242 | for (i = 1; i < CXL_IRQ_RANGES && num; i++) { | |
2243 | try = num; | |
2244 | while (try) { | |
2245 | hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try); | |
2246 | if (hwirq >= 0) | |
2247 | break; | |
2248 | try /= 2; | |
2249 | } | |
2250 | if (!try) | |
2251 | goto fail; | |
2252 | ||
2253 | irqs->offset[i] = phb->msi_base + hwirq; | |
2254 | irqs->range[i] = try; | |
2255 | pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n", | |
2256 | i, irqs->offset[i], irqs->range[i]); | |
2257 | num -= try; | |
2258 | } | |
2259 | if (num) | |
2260 | goto fail; | |
2261 | ||
2262 | return 0; | |
2263 | fail: | |
2264 | pnv_cxl_release_hwirq_ranges(irqs, dev); | |
2265 | return -ENOSPC; | |
2266 | } | |
2267 | EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges); | |
2268 | ||
2269 | int pnv_cxl_get_irq_count(struct pci_dev *dev) | |
2270 | { | |
2271 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
2272 | struct pnv_phb *phb = hose->private_data; | |
2273 | ||
2274 | return phb->msi_bmp.irq_count; | |
2275 | } | |
2276 | EXPORT_SYMBOL(pnv_cxl_get_irq_count); | |
2277 | ||
2278 | int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq, | |
2279 | unsigned int virq) | |
2280 | { | |
2281 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
2282 | struct pnv_phb *phb = hose->private_data; | |
2283 | unsigned int xive_num = hwirq - phb->msi_base; | |
2284 | struct pnv_ioda_pe *pe; | |
2285 | int rc; | |
2286 | ||
2287 | if (!(pe = pnv_ioda_get_pe(dev))) | |
2288 | return -ENODEV; | |
2289 | ||
2290 | /* Assign XIVE to PE */ | |
2291 | rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); | |
2292 | if (rc) { | |
2293 | pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x " | |
2294 | "hwirq 0x%x XIVE 0x%x PE\n", | |
2295 | pci_name(dev), rc, phb->msi_base, hwirq, xive_num); | |
2296 | return -EIO; | |
2297 | } | |
2298 | set_msi_irq_chip(phb, virq); | |
2299 | ||
2300 | return 0; | |
2301 | } | |
2302 | EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup); | |
2303 | #endif | |
2304 | ||
184cd4a3 | 2305 | static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, |
137436c9 GS |
2306 | unsigned int hwirq, unsigned int virq, |
2307 | unsigned int is_64, struct msi_msg *msg) | |
184cd4a3 BH |
2308 | { |
2309 | struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); | |
2310 | unsigned int xive_num = hwirq - phb->msi_base; | |
3a1a4661 | 2311 | __be32 data; |
184cd4a3 BH |
2312 | int rc; |
2313 | ||
2314 | /* No PE assigned ? bail out ... no MSI for you ! */ | |
2315 | if (pe == NULL) | |
2316 | return -ENXIO; | |
2317 | ||
2318 | /* Check if we have an MVE */ | |
2319 | if (pe->mve_number < 0) | |
2320 | return -ENXIO; | |
2321 | ||
b72c1f65 | 2322 | /* Force 32-bit MSI on some broken devices */ |
36074381 | 2323 | if (dev->no_64bit_msi) |
b72c1f65 BH |
2324 | is_64 = 0; |
2325 | ||
184cd4a3 BH |
2326 | /* Assign XIVE to PE */ |
2327 | rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); | |
2328 | if (rc) { | |
2329 | pr_warn("%s: OPAL error %d setting XIVE %d PE\n", | |
2330 | pci_name(dev), rc, xive_num); | |
2331 | return -EIO; | |
2332 | } | |
2333 | ||
2334 | if (is_64) { | |
3a1a4661 BH |
2335 | __be64 addr64; |
2336 | ||
184cd4a3 BH |
2337 | rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, |
2338 | &addr64, &data); | |
2339 | if (rc) { | |
2340 | pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", | |
2341 | pci_name(dev), rc); | |
2342 | return -EIO; | |
2343 | } | |
3a1a4661 BH |
2344 | msg->address_hi = be64_to_cpu(addr64) >> 32; |
2345 | msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; | |
184cd4a3 | 2346 | } else { |
3a1a4661 BH |
2347 | __be32 addr32; |
2348 | ||
184cd4a3 BH |
2349 | rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, |
2350 | &addr32, &data); | |
2351 | if (rc) { | |
2352 | pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", | |
2353 | pci_name(dev), rc); | |
2354 | return -EIO; | |
2355 | } | |
2356 | msg->address_hi = 0; | |
3a1a4661 | 2357 | msg->address_lo = be32_to_cpu(addr32); |
184cd4a3 | 2358 | } |
3a1a4661 | 2359 | msg->data = be32_to_cpu(data); |
184cd4a3 | 2360 | |
fd9a1c26 | 2361 | set_msi_irq_chip(phb, virq); |
137436c9 | 2362 | |
184cd4a3 BH |
2363 | pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," |
2364 | " address=%x_%08x data=%x PE# %d\n", | |
2365 | pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, | |
2366 | msg->address_hi, msg->address_lo, data, pe->pe_number); | |
2367 | ||
2368 | return 0; | |
2369 | } | |
2370 | ||
2371 | static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) | |
2372 | { | |
fb1b55d6 | 2373 | unsigned int count; |
184cd4a3 BH |
2374 | const __be32 *prop = of_get_property(phb->hose->dn, |
2375 | "ibm,opal-msi-ranges", NULL); | |
2376 | if (!prop) { | |
2377 | /* BML Fallback */ | |
2378 | prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); | |
2379 | } | |
2380 | if (!prop) | |
2381 | return; | |
2382 | ||
2383 | phb->msi_base = be32_to_cpup(prop); | |
fb1b55d6 GS |
2384 | count = be32_to_cpup(prop + 1); |
2385 | if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { | |
184cd4a3 BH |
2386 | pr_err("PCI %d: Failed to allocate MSI bitmap !\n", |
2387 | phb->hose->global_number); | |
2388 | return; | |
2389 | } | |
fb1b55d6 | 2390 | |
184cd4a3 BH |
2391 | phb->msi_setup = pnv_pci_ioda_msi_setup; |
2392 | phb->msi32_support = 1; | |
2393 | pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", | |
fb1b55d6 | 2394 | count, phb->msi_base); |
184cd4a3 BH |
2395 | } |
2396 | #else | |
2397 | static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } | |
2398 | #endif /* CONFIG_PCI_MSI */ | |
2399 | ||
6e628c7d WY |
2400 | #ifdef CONFIG_PCI_IOV |
2401 | static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) | |
2402 | { | |
2403 | struct pci_controller *hose; | |
2404 | struct pnv_phb *phb; | |
2405 | struct resource *res; | |
2406 | int i; | |
2407 | resource_size_t size; | |
2408 | struct pci_dn *pdn; | |
5b88ec22 | 2409 | int mul, total_vfs; |
6e628c7d WY |
2410 | |
2411 | if (!pdev->is_physfn || pdev->is_added) | |
2412 | return; | |
2413 | ||
2414 | hose = pci_bus_to_host(pdev->bus); | |
2415 | phb = hose->private_data; | |
2416 | ||
2417 | pdn = pci_get_pdn(pdev); | |
2418 | pdn->vfs_expanded = 0; | |
2419 | ||
5b88ec22 WY |
2420 | total_vfs = pci_sriov_get_totalvfs(pdev); |
2421 | pdn->m64_per_iov = 1; | |
2422 | mul = phb->ioda.total_pe; | |
2423 | ||
2424 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { | |
2425 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; | |
2426 | if (!res->flags || res->parent) | |
2427 | continue; | |
2428 | if (!pnv_pci_is_mem_pref_64(res->flags)) { | |
2429 | dev_warn(&pdev->dev, " non M64 VF BAR%d: %pR\n", | |
2430 | i, res); | |
2431 | continue; | |
2432 | } | |
2433 | ||
2434 | size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); | |
2435 | ||
2436 | /* bigger than 64M */ | |
2437 | if (size > (1 << 26)) { | |
2438 | dev_info(&pdev->dev, "PowerNV: VF BAR%d: %pR IOV size is bigger than 64M, roundup power2\n", | |
2439 | i, res); | |
2440 | pdn->m64_per_iov = M64_PER_IOV; | |
2441 | mul = roundup_pow_of_two(total_vfs); | |
2442 | break; | |
2443 | } | |
2444 | } | |
2445 | ||
6e628c7d WY |
2446 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { |
2447 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; | |
2448 | if (!res->flags || res->parent) | |
2449 | continue; | |
2450 | if (!pnv_pci_is_mem_pref_64(res->flags)) { | |
2451 | dev_warn(&pdev->dev, "Skipping expanding VF BAR%d: %pR\n", | |
2452 | i, res); | |
2453 | continue; | |
2454 | } | |
2455 | ||
2456 | dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); | |
2457 | size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); | |
5b88ec22 | 2458 | res->end = res->start + size * mul - 1; |
6e628c7d WY |
2459 | dev_dbg(&pdev->dev, " %pR\n", res); |
2460 | dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", | |
5b88ec22 | 2461 | i, res, mul); |
6e628c7d | 2462 | } |
5b88ec22 | 2463 | pdn->vfs_expanded = mul; |
6e628c7d WY |
2464 | } |
2465 | #endif /* CONFIG_PCI_IOV */ | |
2466 | ||
11685bec GS |
2467 | /* |
2468 | * This function is supposed to be called on basis of PE from top | |
2469 | * to bottom style. So the the I/O or MMIO segment assigned to | |
2470 | * parent PE could be overrided by its child PEs if necessary. | |
2471 | */ | |
cad5cef6 GKH |
2472 | static void pnv_ioda_setup_pe_seg(struct pci_controller *hose, |
2473 | struct pnv_ioda_pe *pe) | |
11685bec GS |
2474 | { |
2475 | struct pnv_phb *phb = hose->private_data; | |
2476 | struct pci_bus_region region; | |
2477 | struct resource *res; | |
2478 | int i, index; | |
2479 | int rc; | |
2480 | ||
2481 | /* | |
2482 | * NOTE: We only care PCI bus based PE for now. For PCI | |
2483 | * device based PE, for example SRIOV sensitive VF should | |
2484 | * be figured out later. | |
2485 | */ | |
2486 | BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); | |
2487 | ||
2488 | pci_bus_for_each_resource(pe->pbus, res, i) { | |
2489 | if (!res || !res->flags || | |
2490 | res->start > res->end) | |
2491 | continue; | |
2492 | ||
2493 | if (res->flags & IORESOURCE_IO) { | |
2494 | region.start = res->start - phb->ioda.io_pci_base; | |
2495 | region.end = res->end - phb->ioda.io_pci_base; | |
2496 | index = region.start / phb->ioda.io_segsize; | |
2497 | ||
2498 | while (index < phb->ioda.total_pe && | |
2499 | region.start <= region.end) { | |
2500 | phb->ioda.io_segmap[index] = pe->pe_number; | |
2501 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, | |
2502 | pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); | |
2503 | if (rc != OPAL_SUCCESS) { | |
2504 | pr_err("%s: OPAL error %d when mapping IO " | |
2505 | "segment #%d to PE#%d\n", | |
2506 | __func__, rc, index, pe->pe_number); | |
2507 | break; | |
2508 | } | |
2509 | ||
2510 | region.start += phb->ioda.io_segsize; | |
2511 | index++; | |
2512 | } | |
027fa02f GS |
2513 | } else if ((res->flags & IORESOURCE_MEM) && |
2514 | !pnv_pci_is_mem_pref_64(res->flags)) { | |
11685bec | 2515 | region.start = res->start - |
3fd47f06 | 2516 | hose->mem_offset[0] - |
11685bec GS |
2517 | phb->ioda.m32_pci_base; |
2518 | region.end = res->end - | |
3fd47f06 | 2519 | hose->mem_offset[0] - |
11685bec GS |
2520 | phb->ioda.m32_pci_base; |
2521 | index = region.start / phb->ioda.m32_segsize; | |
2522 | ||
2523 | while (index < phb->ioda.total_pe && | |
2524 | region.start <= region.end) { | |
2525 | phb->ioda.m32_segmap[index] = pe->pe_number; | |
2526 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, | |
2527 | pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); | |
2528 | if (rc != OPAL_SUCCESS) { | |
2529 | pr_err("%s: OPAL error %d when mapping M32 " | |
2530 | "segment#%d to PE#%d", | |
2531 | __func__, rc, index, pe->pe_number); | |
2532 | break; | |
2533 | } | |
2534 | ||
2535 | region.start += phb->ioda.m32_segsize; | |
2536 | index++; | |
2537 | } | |
2538 | } | |
2539 | } | |
2540 | } | |
2541 | ||
cad5cef6 | 2542 | static void pnv_pci_ioda_setup_seg(void) |
11685bec GS |
2543 | { |
2544 | struct pci_controller *tmp, *hose; | |
2545 | struct pnv_phb *phb; | |
2546 | struct pnv_ioda_pe *pe; | |
2547 | ||
2548 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
2549 | phb = hose->private_data; | |
2550 | list_for_each_entry(pe, &phb->ioda.pe_list, list) { | |
2551 | pnv_ioda_setup_pe_seg(hose, pe); | |
2552 | } | |
2553 | } | |
2554 | } | |
2555 | ||
cad5cef6 | 2556 | static void pnv_pci_ioda_setup_DMA(void) |
13395c48 GS |
2557 | { |
2558 | struct pci_controller *hose, *tmp; | |
db1266c8 | 2559 | struct pnv_phb *phb; |
13395c48 GS |
2560 | |
2561 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
2562 | pnv_ioda_setup_dma(hose->private_data); | |
db1266c8 GS |
2563 | |
2564 | /* Mark the PHB initialization done */ | |
2565 | phb = hose->private_data; | |
2566 | phb->initialized = 1; | |
13395c48 GS |
2567 | } |
2568 | } | |
2569 | ||
37c367f2 GS |
2570 | static void pnv_pci_ioda_create_dbgfs(void) |
2571 | { | |
2572 | #ifdef CONFIG_DEBUG_FS | |
2573 | struct pci_controller *hose, *tmp; | |
2574 | struct pnv_phb *phb; | |
2575 | char name[16]; | |
2576 | ||
2577 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
2578 | phb = hose->private_data; | |
2579 | ||
2580 | sprintf(name, "PCI%04x", hose->global_number); | |
2581 | phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); | |
2582 | if (!phb->dbgfs) | |
2583 | pr_warning("%s: Error on creating debugfs on PHB#%x\n", | |
2584 | __func__, hose->global_number); | |
2585 | } | |
2586 | #endif /* CONFIG_DEBUG_FS */ | |
2587 | } | |
2588 | ||
cad5cef6 | 2589 | static void pnv_pci_ioda_fixup(void) |
fb446ad0 GS |
2590 | { |
2591 | pnv_pci_ioda_setup_PEs(); | |
11685bec | 2592 | pnv_pci_ioda_setup_seg(); |
13395c48 | 2593 | pnv_pci_ioda_setup_DMA(); |
e9cc17d4 | 2594 | |
37c367f2 GS |
2595 | pnv_pci_ioda_create_dbgfs(); |
2596 | ||
e9cc17d4 | 2597 | #ifdef CONFIG_EEH |
e9cc17d4 | 2598 | eeh_init(); |
dadcd6d6 | 2599 | eeh_addr_cache_build(); |
e9cc17d4 | 2600 | #endif |
fb446ad0 GS |
2601 | } |
2602 | ||
271fd03a GS |
2603 | /* |
2604 | * Returns the alignment for I/O or memory windows for P2P | |
2605 | * bridges. That actually depends on how PEs are segmented. | |
2606 | * For now, we return I/O or M32 segment size for PE sensitive | |
2607 | * P2P bridges. Otherwise, the default values (4KiB for I/O, | |
2608 | * 1MiB for memory) will be returned. | |
2609 | * | |
2610 | * The current PCI bus might be put into one PE, which was | |
2611 | * create against the parent PCI bridge. For that case, we | |
2612 | * needn't enlarge the alignment so that we can save some | |
2613 | * resources. | |
2614 | */ | |
2615 | static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, | |
2616 | unsigned long type) | |
2617 | { | |
2618 | struct pci_dev *bridge; | |
2619 | struct pci_controller *hose = pci_bus_to_host(bus); | |
2620 | struct pnv_phb *phb = hose->private_data; | |
2621 | int num_pci_bridges = 0; | |
2622 | ||
2623 | bridge = bus->self; | |
2624 | while (bridge) { | |
2625 | if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { | |
2626 | num_pci_bridges++; | |
2627 | if (num_pci_bridges >= 2) | |
2628 | return 1; | |
2629 | } | |
2630 | ||
2631 | bridge = bridge->bus->self; | |
2632 | } | |
2633 | ||
262af557 GC |
2634 | /* We fail back to M32 if M64 isn't supported */ |
2635 | if (phb->ioda.m64_segsize && | |
2636 | pnv_pci_is_mem_pref_64(type)) | |
2637 | return phb->ioda.m64_segsize; | |
271fd03a GS |
2638 | if (type & IORESOURCE_MEM) |
2639 | return phb->ioda.m32_segsize; | |
2640 | ||
2641 | return phb->ioda.io_segsize; | |
2642 | } | |
2643 | ||
5350ab3f WY |
2644 | #ifdef CONFIG_PCI_IOV |
2645 | static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, | |
2646 | int resno) | |
2647 | { | |
2648 | struct pci_dn *pdn = pci_get_pdn(pdev); | |
2649 | resource_size_t align, iov_align; | |
2650 | ||
2651 | iov_align = resource_size(&pdev->resource[resno]); | |
2652 | if (iov_align) | |
2653 | return iov_align; | |
2654 | ||
2655 | align = pci_iov_resource_size(pdev, resno); | |
2656 | if (pdn->vfs_expanded) | |
2657 | return pdn->vfs_expanded * align; | |
2658 | ||
2659 | return align; | |
2660 | } | |
2661 | #endif /* CONFIG_PCI_IOV */ | |
2662 | ||
184cd4a3 BH |
2663 | /* Prevent enabling devices for which we couldn't properly |
2664 | * assign a PE | |
2665 | */ | |
c88c2a18 | 2666 | static bool pnv_pci_enable_device_hook(struct pci_dev *dev) |
184cd4a3 | 2667 | { |
db1266c8 GS |
2668 | struct pci_controller *hose = pci_bus_to_host(dev->bus); |
2669 | struct pnv_phb *phb = hose->private_data; | |
2670 | struct pci_dn *pdn; | |
184cd4a3 | 2671 | |
db1266c8 GS |
2672 | /* The function is probably called while the PEs have |
2673 | * not be created yet. For example, resource reassignment | |
2674 | * during PCI probe period. We just skip the check if | |
2675 | * PEs isn't ready. | |
2676 | */ | |
2677 | if (!phb->initialized) | |
c88c2a18 | 2678 | return true; |
db1266c8 | 2679 | |
b72c1f65 | 2680 | pdn = pci_get_pdn(dev); |
184cd4a3 | 2681 | if (!pdn || pdn->pe_number == IODA_INVALID_PE) |
c88c2a18 | 2682 | return false; |
db1266c8 | 2683 | |
c88c2a18 | 2684 | return true; |
184cd4a3 BH |
2685 | } |
2686 | ||
2687 | static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus, | |
2688 | u32 devfn) | |
2689 | { | |
2690 | return phb->ioda.pe_rmap[(bus->number << 8) | devfn]; | |
2691 | } | |
2692 | ||
7a8e6bbf | 2693 | static void pnv_pci_ioda_shutdown(struct pci_controller *hose) |
73ed148a | 2694 | { |
7a8e6bbf MN |
2695 | struct pnv_phb *phb = hose->private_data; |
2696 | ||
d1a85eee | 2697 | opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, |
73ed148a BH |
2698 | OPAL_ASSERT_RESET); |
2699 | } | |
2700 | ||
92ae0353 DA |
2701 | static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { |
2702 | .dma_dev_setup = pnv_pci_dma_dev_setup, | |
2703 | #ifdef CONFIG_PCI_MSI | |
2704 | .setup_msi_irqs = pnv_setup_msi_irqs, | |
2705 | .teardown_msi_irqs = pnv_teardown_msi_irqs, | |
2706 | #endif | |
2707 | .enable_device_hook = pnv_pci_enable_device_hook, | |
2708 | .window_alignment = pnv_pci_window_alignment, | |
2709 | .reset_secondary_bus = pnv_pci_reset_secondary_bus, | |
763d2d8d | 2710 | .dma_set_mask = pnv_pci_ioda_dma_set_mask, |
7a8e6bbf | 2711 | .shutdown = pnv_pci_ioda_shutdown, |
92ae0353 DA |
2712 | }; |
2713 | ||
e51df2c1 AB |
2714 | static void __init pnv_pci_init_ioda_phb(struct device_node *np, |
2715 | u64 hub_id, int ioda_type) | |
184cd4a3 BH |
2716 | { |
2717 | struct pci_controller *hose; | |
184cd4a3 | 2718 | struct pnv_phb *phb; |
8184616f | 2719 | unsigned long size, m32map_off, pemap_off, iomap_off = 0; |
c681b93c | 2720 | const __be64 *prop64; |
3a1a4661 | 2721 | const __be32 *prop32; |
f1b7cc3e | 2722 | int len; |
184cd4a3 BH |
2723 | u64 phb_id; |
2724 | void *aux; | |
2725 | long rc; | |
2726 | ||
58d714ec | 2727 | pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); |
184cd4a3 BH |
2728 | |
2729 | prop64 = of_get_property(np, "ibm,opal-phbid", NULL); | |
2730 | if (!prop64) { | |
2731 | pr_err(" Missing \"ibm,opal-phbid\" property !\n"); | |
2732 | return; | |
2733 | } | |
2734 | phb_id = be64_to_cpup(prop64); | |
2735 | pr_debug(" PHB-ID : 0x%016llx\n", phb_id); | |
2736 | ||
e39f223f | 2737 | phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); |
58d714ec GS |
2738 | |
2739 | /* Allocate PCI controller */ | |
58d714ec GS |
2740 | phb->hose = hose = pcibios_alloc_controller(np); |
2741 | if (!phb->hose) { | |
2742 | pr_err(" Can't allocate PCI controller for %s\n", | |
184cd4a3 | 2743 | np->full_name); |
e39f223f | 2744 | memblock_free(__pa(phb), sizeof(struct pnv_phb)); |
184cd4a3 BH |
2745 | return; |
2746 | } | |
2747 | ||
2748 | spin_lock_init(&phb->lock); | |
f1b7cc3e GS |
2749 | prop32 = of_get_property(np, "bus-range", &len); |
2750 | if (prop32 && len == 8) { | |
3a1a4661 BH |
2751 | hose->first_busno = be32_to_cpu(prop32[0]); |
2752 | hose->last_busno = be32_to_cpu(prop32[1]); | |
f1b7cc3e GS |
2753 | } else { |
2754 | pr_warn(" Broken <bus-range> on %s\n", np->full_name); | |
2755 | hose->first_busno = 0; | |
2756 | hose->last_busno = 0xff; | |
2757 | } | |
184cd4a3 | 2758 | hose->private_data = phb; |
e9cc17d4 | 2759 | phb->hub_id = hub_id; |
184cd4a3 | 2760 | phb->opal_id = phb_id; |
aa0c033f | 2761 | phb->type = ioda_type; |
781a868f | 2762 | mutex_init(&phb->ioda.pe_alloc_mutex); |
184cd4a3 | 2763 | |
cee72d5b BH |
2764 | /* Detect specific models for error handling */ |
2765 | if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) | |
2766 | phb->model = PNV_PHB_MODEL_P7IOC; | |
f3d40c25 | 2767 | else if (of_device_is_compatible(np, "ibm,power8-pciex")) |
aa0c033f | 2768 | phb->model = PNV_PHB_MODEL_PHB3; |
cee72d5b BH |
2769 | else |
2770 | phb->model = PNV_PHB_MODEL_UNKNOWN; | |
2771 | ||
aa0c033f | 2772 | /* Parse 32-bit and IO ranges (if any) */ |
2f1ec02e | 2773 | pci_process_bridge_OF_ranges(hose, np, !hose->global_number); |
184cd4a3 | 2774 | |
aa0c033f | 2775 | /* Get registers */ |
184cd4a3 BH |
2776 | phb->regs = of_iomap(np, 0); |
2777 | if (phb->regs == NULL) | |
2778 | pr_err(" Failed to map registers !\n"); | |
2779 | ||
184cd4a3 | 2780 | /* Initialize more IODA stuff */ |
36954dc7 | 2781 | phb->ioda.total_pe = 1; |
aa0c033f | 2782 | prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); |
36954dc7 | 2783 | if (prop32) |
3a1a4661 | 2784 | phb->ioda.total_pe = be32_to_cpup(prop32); |
36954dc7 GS |
2785 | prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); |
2786 | if (prop32) | |
2787 | phb->ioda.reserved_pe = be32_to_cpup(prop32); | |
262af557 GC |
2788 | |
2789 | /* Parse 64-bit MMIO range */ | |
2790 | pnv_ioda_parse_m64_window(phb); | |
2791 | ||
184cd4a3 | 2792 | phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); |
aa0c033f | 2793 | /* FW Has already off top 64k of M32 space (MSI space) */ |
184cd4a3 BH |
2794 | phb->ioda.m32_size += 0x10000; |
2795 | ||
2796 | phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe; | |
3fd47f06 | 2797 | phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; |
184cd4a3 BH |
2798 | phb->ioda.io_size = hose->pci_io_size; |
2799 | phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe; | |
2800 | phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ | |
2801 | ||
c35d2a8c | 2802 | /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ |
184cd4a3 BH |
2803 | size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); |
2804 | m32map_off = size; | |
e47747f4 | 2805 | size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]); |
c35d2a8c GS |
2806 | if (phb->type == PNV_PHB_IODA1) { |
2807 | iomap_off = size; | |
2808 | size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]); | |
2809 | } | |
184cd4a3 BH |
2810 | pemap_off = size; |
2811 | size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe); | |
e39f223f | 2812 | aux = memblock_virt_alloc(size, 0); |
184cd4a3 BH |
2813 | phb->ioda.pe_alloc = aux; |
2814 | phb->ioda.m32_segmap = aux + m32map_off; | |
c35d2a8c GS |
2815 | if (phb->type == PNV_PHB_IODA1) |
2816 | phb->ioda.io_segmap = aux + iomap_off; | |
184cd4a3 | 2817 | phb->ioda.pe_array = aux + pemap_off; |
36954dc7 | 2818 | set_bit(phb->ioda.reserved_pe, phb->ioda.pe_alloc); |
184cd4a3 | 2819 | |
7ebdf956 | 2820 | INIT_LIST_HEAD(&phb->ioda.pe_dma_list); |
184cd4a3 | 2821 | INIT_LIST_HEAD(&phb->ioda.pe_list); |
781a868f | 2822 | mutex_init(&phb->ioda.pe_list_mutex); |
184cd4a3 BH |
2823 | |
2824 | /* Calculate how many 32-bit TCE segments we have */ | |
2825 | phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28; | |
2826 | ||
aa0c033f | 2827 | #if 0 /* We should really do that ... */ |
184cd4a3 BH |
2828 | rc = opal_pci_set_phb_mem_window(opal->phb_id, |
2829 | window_type, | |
2830 | window_num, | |
2831 | starting_real_address, | |
2832 | starting_pci_address, | |
2833 | segment_size); | |
2834 | #endif | |
2835 | ||
262af557 GC |
2836 | pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", |
2837 | phb->ioda.total_pe, phb->ioda.reserved_pe, | |
2838 | phb->ioda.m32_size, phb->ioda.m32_segsize); | |
2839 | if (phb->ioda.m64_size) | |
2840 | pr_info(" M64: 0x%lx [segment=0x%lx]\n", | |
2841 | phb->ioda.m64_size, phb->ioda.m64_segsize); | |
2842 | if (phb->ioda.io_size) | |
2843 | pr_info(" IO: 0x%x [segment=0x%x]\n", | |
2844 | phb->ioda.io_size, phb->ioda.io_segsize); | |
2845 | ||
184cd4a3 | 2846 | |
184cd4a3 | 2847 | phb->hose->ops = &pnv_pci_ops; |
49dec922 GS |
2848 | phb->get_pe_state = pnv_ioda_get_pe_state; |
2849 | phb->freeze_pe = pnv_ioda_freeze_pe; | |
2850 | phb->unfreeze_pe = pnv_ioda_unfreeze_pe; | |
184cd4a3 BH |
2851 | |
2852 | /* Setup RID -> PE mapping function */ | |
2853 | phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe; | |
2854 | ||
2855 | /* Setup TCEs */ | |
2856 | phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; | |
fe7e85c6 | 2857 | phb->dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask; |
184cd4a3 BH |
2858 | |
2859 | /* Setup MSI support */ | |
2860 | pnv_pci_init_ioda_msis(phb); | |
2861 | ||
c40a4210 GS |
2862 | /* |
2863 | * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here | |
2864 | * to let the PCI core do resource assignment. It's supposed | |
2865 | * that the PCI core will do correct I/O and MMIO alignment | |
2866 | * for the P2P bridge bars so that each PCI bus (excluding | |
2867 | * the child P2P bridges) can form individual PE. | |
184cd4a3 | 2868 | */ |
fb446ad0 | 2869 | ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; |
92ae0353 | 2870 | hose->controller_ops = pnv_pci_ioda_controller_ops; |
ad30cb99 | 2871 | |
6e628c7d WY |
2872 | #ifdef CONFIG_PCI_IOV |
2873 | ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; | |
5350ab3f | 2874 | ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; |
ad30cb99 ME |
2875 | #endif |
2876 | ||
c40a4210 | 2877 | pci_add_flags(PCI_REASSIGN_ALL_RSRC); |
184cd4a3 BH |
2878 | |
2879 | /* Reset IODA tables to a clean state */ | |
d1a85eee | 2880 | rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); |
184cd4a3 | 2881 | if (rc) |
f11fe552 | 2882 | pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); |
361f2a2a GS |
2883 | |
2884 | /* If we're running in kdump kerenl, the previous kerenl never | |
2885 | * shutdown PCI devices correctly. We already got IODA table | |
2886 | * cleaned out. So we have to issue PHB reset to stop all PCI | |
2887 | * transactions from previous kerenl. | |
2888 | */ | |
2889 | if (is_kdump_kernel()) { | |
2890 | pr_info(" Issue PHB reset ...\n"); | |
cadf364d GS |
2891 | pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); |
2892 | pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); | |
361f2a2a | 2893 | } |
262af557 | 2894 | |
9e9e8935 GS |
2895 | /* Remove M64 resource if we can't configure it successfully */ |
2896 | if (!phb->init_m64 || phb->init_m64(phb)) | |
262af557 | 2897 | hose->mem_resources[1].flags = 0; |
aa0c033f GS |
2898 | } |
2899 | ||
67975005 | 2900 | void __init pnv_pci_init_ioda2_phb(struct device_node *np) |
aa0c033f | 2901 | { |
e9cc17d4 | 2902 | pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); |
184cd4a3 BH |
2903 | } |
2904 | ||
2905 | void __init pnv_pci_init_ioda_hub(struct device_node *np) | |
2906 | { | |
2907 | struct device_node *phbn; | |
c681b93c | 2908 | const __be64 *prop64; |
184cd4a3 BH |
2909 | u64 hub_id; |
2910 | ||
2911 | pr_info("Probing IODA IO-Hub %s\n", np->full_name); | |
2912 | ||
2913 | prop64 = of_get_property(np, "ibm,opal-hubid", NULL); | |
2914 | if (!prop64) { | |
2915 | pr_err(" Missing \"ibm,opal-hubid\" property !\n"); | |
2916 | return; | |
2917 | } | |
2918 | hub_id = be64_to_cpup(prop64); | |
2919 | pr_devel(" HUB-ID : 0x%016llx\n", hub_id); | |
2920 | ||
2921 | /* Count child PHBs */ | |
2922 | for_each_child_of_node(np, phbn) { | |
2923 | /* Look for IODA1 PHBs */ | |
2924 | if (of_device_is_compatible(phbn, "ibm,ioda-phb")) | |
e9cc17d4 | 2925 | pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); |
184cd4a3 BH |
2926 | } |
2927 | } |