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1da177e4 LT |
1 | /* |
2 | * arch/ppc64/kernel/u3_iommu.c | |
3 | * | |
4 | * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation | |
5 | * | |
6 | * Based on pSeries_iommu.c: | |
7 | * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation | |
8 | * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation | |
9 | * | |
10 | * Dynamic DMA mapping support, Apple U3 & IBM CPC925 "DART" iommu. | |
11 | * | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License as published by | |
15 | * the Free Software Foundation; either version 2 of the License, or | |
16 | * (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
26 | */ | |
27 | ||
28 | #include <linux/config.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/types.h> | |
31 | #include <linux/slab.h> | |
32 | #include <linux/mm.h> | |
33 | #include <linux/spinlock.h> | |
34 | #include <linux/string.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/dma-mapping.h> | |
37 | #include <linux/vmalloc.h> | |
38 | #include <asm/io.h> | |
39 | #include <asm/prom.h> | |
40 | #include <asm/ppcdebug.h> | |
41 | #include <asm/iommu.h> | |
42 | #include <asm/pci-bridge.h> | |
43 | #include <asm/machdep.h> | |
44 | #include <asm/abs_addr.h> | |
45 | #include <asm/cacheflush.h> | |
46 | #include <asm/lmb.h> | |
c707ffcf | 47 | #include <asm/dart.h> |
1da177e4 LT |
48 | |
49 | #include "pci.h" | |
50 | ||
51 | extern int iommu_force_on; | |
52 | ||
1da177e4 LT |
53 | /* Physical base address and size of the DART table */ |
54 | unsigned long dart_tablebase; /* exported to htab_initialize */ | |
55 | static unsigned long dart_tablesize; | |
56 | ||
57 | /* Virtual base address of the DART table */ | |
58 | static u32 *dart_vbase; | |
59 | ||
60 | /* Mapped base address for the dart */ | |
61 | static unsigned int *dart; | |
62 | ||
63 | /* Dummy val that entries are set to when unused */ | |
64 | static unsigned int dart_emptyval; | |
65 | ||
66 | static struct iommu_table iommu_table_u3; | |
67 | static int iommu_table_u3_inited; | |
68 | static int dart_dirty; | |
69 | ||
70 | #define DBG(...) | |
71 | ||
72 | static inline void dart_tlb_invalidate_all(void) | |
73 | { | |
74 | unsigned long l = 0; | |
75 | unsigned int reg; | |
76 | unsigned long limit; | |
77 | ||
78 | DBG("dart: flush\n"); | |
79 | ||
80 | /* To invalidate the DART, set the DARTCNTL_FLUSHTLB bit in the | |
81 | * control register and wait for it to clear. | |
82 | * | |
83 | * Gotcha: Sometimes, the DART won't detect that the bit gets | |
84 | * set. If so, clear it and set it again. | |
85 | */ | |
86 | ||
87 | limit = 0; | |
88 | ||
89 | retry: | |
90 | reg = in_be32((unsigned int *)dart+DARTCNTL); | |
91 | reg |= DARTCNTL_FLUSHTLB; | |
92 | out_be32((unsigned int *)dart+DARTCNTL, reg); | |
93 | ||
94 | l = 0; | |
95 | while ((in_be32((unsigned int *)dart+DARTCNTL) & DARTCNTL_FLUSHTLB) && | |
96 | l < (1L<<limit)) { | |
97 | l++; | |
98 | } | |
99 | if (l == (1L<<limit)) { | |
100 | if (limit < 4) { | |
101 | limit++; | |
102 | reg = in_be32((unsigned int *)dart+DARTCNTL); | |
103 | reg &= ~DARTCNTL_FLUSHTLB; | |
104 | out_be32((unsigned int *)dart+DARTCNTL, reg); | |
105 | goto retry; | |
106 | } else | |
107 | panic("U3-DART: TLB did not flush after waiting a long " | |
108 | "time. Buggy U3 ?"); | |
109 | } | |
110 | } | |
111 | ||
112 | static void dart_flush(struct iommu_table *tbl) | |
113 | { | |
114 | if (dart_dirty) | |
115 | dart_tlb_invalidate_all(); | |
116 | dart_dirty = 0; | |
117 | } | |
118 | ||
119 | static void dart_build(struct iommu_table *tbl, long index, | |
120 | long npages, unsigned long uaddr, | |
121 | enum dma_data_direction direction) | |
122 | { | |
123 | unsigned int *dp; | |
124 | unsigned int rpn; | |
125 | ||
126 | DBG("dart: build at: %lx, %lx, addr: %x\n", index, npages, uaddr); | |
127 | ||
d0035c62 OJ |
128 | index <<= DART_PAGE_FACTOR; |
129 | npages <<= DART_PAGE_FACTOR; | |
130 | ||
1da177e4 LT |
131 | dp = ((unsigned int*)tbl->it_base) + index; |
132 | ||
133 | /* On U3, all memory is contigous, so we can move this | |
134 | * out of the loop. | |
135 | */ | |
136 | while (npages--) { | |
d0035c62 | 137 | rpn = virt_to_abs(uaddr) >> DART_PAGE_SHIFT; |
1da177e4 LT |
138 | |
139 | *(dp++) = DARTMAP_VALID | (rpn & DARTMAP_RPNMASK); | |
140 | ||
141 | rpn++; | |
d0035c62 | 142 | uaddr += DART_PAGE_SIZE; |
1da177e4 LT |
143 | } |
144 | ||
145 | dart_dirty = 1; | |
146 | } | |
147 | ||
148 | ||
149 | static void dart_free(struct iommu_table *tbl, long index, long npages) | |
150 | { | |
151 | unsigned int *dp; | |
152 | ||
153 | /* We don't worry about flushing the TLB cache. The only drawback of | |
154 | * not doing it is that we won't catch buggy device drivers doing | |
155 | * bad DMAs, but then no 32-bit architecture ever does either. | |
156 | */ | |
157 | ||
158 | DBG("dart: free at: %lx, %lx\n", index, npages); | |
159 | ||
d0035c62 OJ |
160 | index <<= DART_PAGE_FACTOR; |
161 | npages <<= DART_PAGE_FACTOR; | |
162 | ||
1da177e4 LT |
163 | dp = ((unsigned int *)tbl->it_base) + index; |
164 | ||
165 | while (npages--) | |
166 | *(dp++) = dart_emptyval; | |
167 | } | |
168 | ||
169 | ||
170 | static int dart_init(struct device_node *dart_node) | |
171 | { | |
172 | unsigned int regword; | |
173 | unsigned int i; | |
174 | unsigned long tmp; | |
175 | ||
176 | if (dart_tablebase == 0 || dart_tablesize == 0) { | |
177 | printk(KERN_INFO "U3-DART: table not allocated, using direct DMA\n"); | |
178 | return -ENODEV; | |
179 | } | |
180 | ||
181 | /* Make sure nothing from the DART range remains in the CPU cache | |
182 | * from a previous mapping that existed before the kernel took | |
183 | * over | |
184 | */ | |
185 | flush_dcache_phys_range(dart_tablebase, dart_tablebase + dart_tablesize); | |
186 | ||
187 | /* Allocate a spare page to map all invalid DART pages. We need to do | |
188 | * that to work around what looks like a problem with the HT bridge | |
189 | * prefetching into invalid pages and corrupting data | |
190 | */ | |
d0035c62 | 191 | tmp = lmb_alloc(DART_PAGE_SIZE, DART_PAGE_SIZE); |
1da177e4 LT |
192 | if (!tmp) |
193 | panic("U3-DART: Cannot allocate spare page!"); | |
d0035c62 | 194 | dart_emptyval = DARTMAP_VALID | ((tmp >> DART_PAGE_SHIFT) & DARTMAP_RPNMASK); |
1da177e4 LT |
195 | |
196 | /* Map in DART registers. FIXME: Use device node to get base address */ | |
197 | dart = ioremap(DART_BASE, 0x7000); | |
198 | if (dart == NULL) | |
199 | panic("U3-DART: Cannot map registers!"); | |
200 | ||
201 | /* Set initial control register contents: table base, | |
202 | * table size and enable bit | |
203 | */ | |
204 | regword = DARTCNTL_ENABLE | | |
d0035c62 OJ |
205 | ((dart_tablebase >> DART_PAGE_SHIFT) << DARTCNTL_BASE_SHIFT) | |
206 | (((dart_tablesize >> DART_PAGE_SHIFT) & DARTCNTL_SIZE_MASK) | |
1da177e4 LT |
207 | << DARTCNTL_SIZE_SHIFT); |
208 | dart_vbase = ioremap(virt_to_abs(dart_tablebase), dart_tablesize); | |
209 | ||
210 | /* Fill initial table */ | |
211 | for (i = 0; i < dart_tablesize/4; i++) | |
212 | dart_vbase[i] = dart_emptyval; | |
213 | ||
214 | /* Initialize DART with table base and enable it. */ | |
215 | out_be32((unsigned int *)dart, regword); | |
216 | ||
217 | /* Invalidate DART to get rid of possible stale TLBs */ | |
218 | dart_tlb_invalidate_all(); | |
219 | ||
220 | printk(KERN_INFO "U3/CPC925 DART IOMMU initialized\n"); | |
221 | ||
222 | return 0; | |
223 | } | |
224 | ||
225 | static void iommu_table_u3_setup(void) | |
226 | { | |
227 | iommu_table_u3.it_busno = 0; | |
228 | iommu_table_u3.it_offset = 0; | |
229 | /* it_size is in number of entries */ | |
230 | iommu_table_u3.it_size = dart_tablesize / sizeof(u32); | |
231 | ||
232 | /* Initialize the common IOMMU code */ | |
233 | iommu_table_u3.it_base = (unsigned long)dart_vbase; | |
234 | iommu_table_u3.it_index = 0; | |
235 | iommu_table_u3.it_blocksize = 1; | |
236 | iommu_init_table(&iommu_table_u3); | |
237 | ||
238 | /* Reserve the last page of the DART to avoid possible prefetch | |
239 | * past the DART mapped area | |
240 | */ | |
241 | set_bit(iommu_table_u3.it_size - 1, iommu_table_u3.it_map); | |
242 | } | |
243 | ||
244 | static void iommu_dev_setup_u3(struct pci_dev *dev) | |
245 | { | |
246 | struct device_node *dn; | |
247 | ||
248 | /* We only have one iommu table on the mac for now, which makes | |
249 | * things simple. Setup all PCI devices to point to this table | |
250 | * | |
251 | * We must use pci_device_to_OF_node() to make sure that | |
252 | * we get the real "final" pointer to the device in the | |
253 | * pci_dev sysdata and not the temporary PHB one | |
254 | */ | |
255 | dn = pci_device_to_OF_node(dev); | |
256 | ||
257 | if (dn) | |
1635317f | 258 | PCI_DN(dn)->iommu_table = &iommu_table_u3; |
1da177e4 LT |
259 | } |
260 | ||
261 | static void iommu_bus_setup_u3(struct pci_bus *bus) | |
262 | { | |
263 | struct device_node *dn; | |
264 | ||
265 | if (!iommu_table_u3_inited) { | |
266 | iommu_table_u3_inited = 1; | |
267 | iommu_table_u3_setup(); | |
268 | } | |
269 | ||
270 | dn = pci_bus_to_OF_node(bus); | |
271 | ||
272 | if (dn) | |
1635317f | 273 | PCI_DN(dn)->iommu_table = &iommu_table_u3; |
1da177e4 LT |
274 | } |
275 | ||
276 | static void iommu_dev_setup_null(struct pci_dev *dev) { } | |
277 | static void iommu_bus_setup_null(struct pci_bus *bus) { } | |
278 | ||
279 | void iommu_init_early_u3(void) | |
280 | { | |
281 | struct device_node *dn; | |
282 | ||
283 | /* Find the DART in the device-tree */ | |
284 | dn = of_find_compatible_node(NULL, "dart", "u3-dart"); | |
285 | if (dn == NULL) | |
286 | return; | |
287 | ||
288 | /* Setup low level TCE operations for the core IOMMU code */ | |
289 | ppc_md.tce_build = dart_build; | |
290 | ppc_md.tce_free = dart_free; | |
291 | ppc_md.tce_flush = dart_flush; | |
292 | ||
293 | /* Initialize the DART HW */ | |
294 | if (dart_init(dn)) { | |
295 | /* If init failed, use direct iommu and null setup functions */ | |
296 | ppc_md.iommu_dev_setup = iommu_dev_setup_null; | |
297 | ppc_md.iommu_bus_setup = iommu_bus_setup_null; | |
298 | ||
299 | /* Setup pci_dma ops */ | |
300 | pci_direct_iommu_init(); | |
301 | } else { | |
302 | ppc_md.iommu_dev_setup = iommu_dev_setup_u3; | |
303 | ppc_md.iommu_bus_setup = iommu_bus_setup_u3; | |
304 | ||
305 | /* Setup pci_dma ops */ | |
306 | pci_iommu_init(); | |
307 | } | |
308 | } | |
309 | ||
310 | ||
311 | void __init alloc_u3_dart_table(void) | |
312 | { | |
313 | /* Only reserve DART space if machine has more than 2GB of RAM | |
314 | * or if requested with iommu=on on cmdline. | |
315 | */ | |
316 | if (lmb_end_of_DRAM() <= 0x80000000ull && !iommu_force_on) | |
317 | return; | |
318 | ||
319 | /* 512 pages (2MB) is max DART tablesize. */ | |
320 | dart_tablesize = 1UL << 21; | |
321 | /* 16MB (1 << 24) alignment. We allocate a full 16Mb chuck since we | |
322 | * will blow up an entire large page anyway in the kernel mapping | |
323 | */ | |
324 | dart_tablebase = (unsigned long) | |
325 | abs_to_virt(lmb_alloc_base(1UL<<24, 1UL<<24, 0x80000000L)); | |
326 | ||
327 | printk(KERN_INFO "U3-DART allocated at: %lx\n", dart_tablebase); | |
328 | } |