[mirror_ubuntu-zesty-kernel.git] / arch / s390 / include / asm / processor.h

/*
 *  S390 version
 *    Copyright IBM Corp. 1999
 *    Author(s): Hartmut Penner (hp@de.ibm.com),
 *               Martin Schwidefsky (schwidefsky@de.ibm.com)
 *
 *  Derived from "include/asm-i386/processor.h"
 *    Copyright (C) 1994, Linus Torvalds
 */

#ifndef __ASM_S390_PROCESSOR_H
#define __ASM_S390_PROCESSOR_H

#define CIF_MCCK_PENDING	0	/* machine check handling is pending */
#define CIF_ASCE		1	/* user asce needs fixup / uaccess */
#define CIF_NOHZ_DELAY		2	/* delay HZ disable for a tick */
#define CIF_FPU			3	/* restore vector registers */
#define CIF_IGNORE_IRQ		4	/* ignore interrupt (for udelay) */

#define _CIF_MCCK_PENDING	(1<<CIF_MCCK_PENDING)
#define _CIF_ASCE		(1<<CIF_ASCE)
#define _CIF_NOHZ_DELAY		(1<<CIF_NOHZ_DELAY)
#define _CIF_FPU		(1<<CIF_FPU)
#define _CIF_IGNORE_IRQ		(1<<CIF_IGNORE_IRQ)

#ifndef __ASSEMBLY__

#include <linux/linkage.h>
#include <linux/irqflags.h>
#include <asm/cpu.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include <asm/setup.h>
#include <asm/runtime_instr.h>
#include <asm/fpu-internal.h>

static inline void set_cpu_flag(int flag)
{
	S390_lowcore.cpu_flags |= (1U << flag);
}

static inline void clear_cpu_flag(int flag)
{
	S390_lowcore.cpu_flags &= ~(1U << flag);
}

static inline int test_cpu_flag(int flag)
{
	return !!(S390_lowcore.cpu_flags & (1U << flag));
}

#define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)

/*
 * Default implementation of macro that returns current
 * instruction pointer ("program counter").
 */
#define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })

static inline void get_cpu_id(struct cpuid *ptr)
{
	asm volatile("stidp %0" : "=Q" (*ptr));
}

extern void s390_adjust_jiffies(void);
extern const struct seq_operations cpuinfo_op;
extern int sysctl_ieee_emulation_warnings;
extern void execve_tail(void);

/*
 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
 */

#define TASK_SIZE_OF(tsk)	((tsk)->mm->context.asce_limit)
#define TASK_UNMAPPED_BASE	(test_thread_flag(TIF_31BIT) ? \
					(1UL << 30) : (1UL << 41))
#define TASK_SIZE		TASK_SIZE_OF(current)
#define TASK_MAX_SIZE		(1UL << 53)

#define STACK_TOP		(1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
#define STACK_TOP_MAX		(1UL << 42)

#define HAVE_ARCH_PICK_MMAP_LAYOUT

typedef struct {
        __u32 ar4;
} mm_segment_t;

/*
 * Thread structure
 */
struct thread_struct {
	struct fpu fpu;			/* FP and VX register save area */
	unsigned int  acrs[NUM_ACRS];
        unsigned long ksp;              /* kernel stack pointer             */
	mm_segment_t mm_segment;
	unsigned long gmap_addr;	/* address of last gmap fault. */
	unsigned int gmap_pfault;	/* signal of a pending guest pfault */
	struct per_regs per_user;	/* User specified PER registers */
	struct per_event per_event;	/* Cause of the last PER trap */
	unsigned long per_flags;	/* Flags to control debug behavior */
        /* pfault_wait is used to block the process on a pfault event */
	unsigned long pfault_wait;
	struct list_head list;
	/* cpu runtime instrumentation */
	struct runtime_instr_cb *ri_cb;
	int ri_signum;
	unsigned char trap_tdb[256];	/* Transaction abort diagnose block */
};

/* Flag to disable transactions. */
#define PER_FLAG_NO_TE			1UL
/* Flag to enable random transaction aborts. */
#define PER_FLAG_TE_ABORT_RAND		2UL
/* Flag to specify random transaction abort mode:
 * - abort each transaction at a random instruction before TEND if set.
 * - abort random transactions at a random instruction if cleared.
 */
#define PER_FLAG_TE_ABORT_RAND_TEND	4UL

typedef struct thread_struct thread_struct;

/*
 * Stack layout of a C stack frame.
 */
#ifndef __PACK_STACK
struct stack_frame {
	unsigned long back_chain;
	unsigned long empty1[5];
	unsigned long gprs[10];
	unsigned int  empty2[8];
};
#else
struct stack_frame {
	unsigned long empty1[5];
	unsigned int  empty2[8];
	unsigned long gprs[10];
	unsigned long back_chain;
};
#endif

#define ARCH_MIN_TASKALIGN	8

extern __vector128 init_task_fpu_regs[__NUM_VXRS];
#define INIT_THREAD {							\
	.ksp = sizeof(init_stack) + (unsigned long) &init_stack,	\
	.fpu.regs = (void *)&init_task_fpu_regs,			\
}

/*
 * Do necessary setup to start up a new thread.
 */
#define start_thread(regs, new_psw, new_stackp) do {			\
	regs->psw.mask	= PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA;	\
	regs->psw.addr	= new_psw | PSW_ADDR_AMODE;			\
	regs->gprs[15]	= new_stackp;					\
	execve_tail();							\
} while (0)

#define start_thread31(regs, new_psw, new_stackp) do {			\
	regs->psw.mask	= PSW_USER_BITS | PSW_MASK_BA;			\
	regs->psw.addr	= new_psw | PSW_ADDR_AMODE;			\
	regs->gprs[15]	= new_stackp;					\
	crst_table_downgrade(current->mm, 1UL << 31);			\
	execve_tail();							\
} while (0)

/* Forward declaration, a strange C thing */
struct task_struct;
struct mm_struct;
struct seq_file;

void show_cacheinfo(struct seq_file *m);

/* Free all resources held by a thread. */
extern void release_thread(struct task_struct *);

/*
 * Return saved PC of a blocked thread.
 */
extern unsigned long thread_saved_pc(struct task_struct *t);

unsigned long get_wchan(struct task_struct *p);
#define task_pt_regs(tsk) ((struct pt_regs *) \
        (task_stack_page(tsk) + THREAD_SIZE) - 1)
#define KSTK_EIP(tsk)	(task_pt_regs(tsk)->psw.addr)
#define KSTK_ESP(tsk)	(task_pt_regs(tsk)->gprs[15])

/* Has task runtime instrumentation enabled ? */
#define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)

static inline unsigned short stap(void)
{
	unsigned short cpu_address;

	asm volatile("stap %0" : "=m" (cpu_address));
	return cpu_address;
}

/*
 * Give up the time slice of the virtual PU.
 */
void cpu_relax(void);

#define cpu_relax_lowlatency()  barrier()

static inline void psw_set_key(unsigned int key)
{
	asm volatile("spka 0(%0)" : : "d" (key));
}

/*
 * Set PSW to specified value.
 */
static inline void __load_psw(psw_t psw)
{
	asm volatile("lpswe %0" : : "Q" (psw) : "cc");
}

/*
 * Set PSW mask to specified value, while leaving the
 * PSW addr pointing to the next instruction.
 */
static inline void __load_psw_mask (unsigned long mask)
{
	unsigned long addr;
	psw_t psw;

	psw.mask = mask;

	asm volatile(
		"	larl	%0,1f\n"
		"	stg	%0,%O1+8(%R1)\n"
		"	lpswe	%1\n"
		"1:"
		: "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
}

/*
 * Extract current PSW mask
 */
static inline unsigned long __extract_psw(void)
{
	unsigned int reg1, reg2;

	asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2));
	return (((unsigned long) reg1) << 32) | ((unsigned long) reg2);
}

/*
 * Rewind PSW instruction address by specified number of bytes.
 */
static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
{
	unsigned long mask;

	mask = (psw.mask & PSW_MASK_EA) ? -1UL :
	       (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
					  (1UL << 24) - 1;
	return (psw.addr - ilc) & mask;
}

/*
 * Function to stop a processor until the next interrupt occurs
 */
void enabled_wait(void);

/*
 * Function to drop a processor into disabled wait state
 */
static inline void __noreturn disabled_wait(unsigned long code)
{
        unsigned long ctl_buf;
        psw_t dw_psw;

	dw_psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
        dw_psw.addr = code;
        /* 
         * Store status and then load disabled wait psw,
         * the processor is dead afterwards
         */
	asm volatile(
		"	stctg	0,0,0(%2)\n"
		"	ni	4(%2),0xef\n"	/* switch off protection */
		"	lctlg	0,0,0(%2)\n"
		"	lghi	1,0x1000\n"
		"	stpt	0x328(1)\n"	/* store timer */
		"	stckc	0x330(1)\n"	/* store clock comparator */
		"	stpx	0x318(1)\n"	/* store prefix register */
		"	stam	0,15,0x340(1)\n"/* store access registers */
		"	stfpc	0x31c(1)\n"	/* store fpu control */
		"	std	0,0x200(1)\n"	/* store f0 */
		"	std	1,0x208(1)\n"	/* store f1 */
		"	std	2,0x210(1)\n"	/* store f2 */
		"	std	3,0x218(1)\n"	/* store f3 */
		"	std	4,0x220(1)\n"	/* store f4 */
		"	std	5,0x228(1)\n"	/* store f5 */
		"	std	6,0x230(1)\n"	/* store f6 */
		"	std	7,0x238(1)\n"	/* store f7 */
		"	std	8,0x240(1)\n"	/* store f8 */
		"	std	9,0x248(1)\n"	/* store f9 */
		"	std	10,0x250(1)\n"	/* store f10 */
		"	std	11,0x258(1)\n"	/* store f11 */
		"	std	12,0x260(1)\n"	/* store f12 */
		"	std	13,0x268(1)\n"	/* store f13 */
		"	std	14,0x270(1)\n"	/* store f14 */
		"	std	15,0x278(1)\n"	/* store f15 */
		"	stmg	0,15,0x280(1)\n"/* store general registers */
		"	stctg	0,15,0x380(1)\n"/* store control registers */
		"	oi	0x384(1),0x10\n"/* fake protection bit */
		"	lpswe	0(%1)"
		: "=m" (ctl_buf)
		: "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1");
	while (1);
}

/*
 * Use to set psw mask except for the first byte which
 * won't be changed by this function.
 */
static inline void
__set_psw_mask(unsigned long mask)
{
	__load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8)));
}

#define local_mcck_enable() \
	__set_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT | PSW_MASK_MCHECK)
#define local_mcck_disable() \
	__set_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT)

/*
 * Basic Machine Check/Program Check Handler.
 */

extern void s390_base_mcck_handler(void);
extern void s390_base_pgm_handler(void);
extern void s390_base_ext_handler(void);

extern void (*s390_base_mcck_handler_fn)(void);
extern void (*s390_base_pgm_handler_fn)(void);
extern void (*s390_base_ext_handler_fn)(void);

#define ARCH_LOW_ADDRESS_LIMIT	0x7fffffffUL

extern int memcpy_real(void *, void *, size_t);
extern void memcpy_absolute(void *, void *, size_t);

#define mem_assign_absolute(dest, val) {			\
	__typeof__(dest) __tmp = (val);				\
								\
	BUILD_BUG_ON(sizeof(__tmp) != sizeof(val));		\
	memcpy_absolute(&(dest), &__tmp, sizeof(__tmp));	\
}

#endif /* __ASSEMBLY__ */

#endif /* __ASM_S390_PROCESSOR_H */
Commit	Line	Data
1da177e4	1	/*
1da177e4	2	* S390 version
a53c8fab	3	* Copyright IBM Corp. 1999
1da177e4 LT	4	* Author(s): Hartmut Penner (hp@de.ibm.com),
	5	* Martin Schwidefsky (schwidefsky@de.ibm.com)
	6	*
	7	* Derived from "include/asm-i386/processor.h"
	8	* Copyright (C) 1994, Linus Torvalds
	9	*/
	10
	11	#ifndef __ASM_S390_PROCESSOR_H
	12	#define __ASM_S390_PROCESSOR_H
	13
d3a73acb MS	14	#define CIF_MCCK_PENDING 0 /* machine check handling is pending */
d3a73acb MS	15	#define CIF_ASCE 1 /* user asce needs fixup / uaccess */
fe0f4976	16	#define CIF_NOHZ_DELAY 2 /* delay HZ disable for a tick */
9977e886	17	#define CIF_FPU 3 /* restore vector registers */
db7e007f	18	#define CIF_IGNORE_IRQ 4 /* ignore interrupt (for udelay) */
d3a73acb MS	19
	20	#define _CIF_MCCK_PENDING (1<<CIF_MCCK_PENDING)
	21	#define _CIF_ASCE (1<<CIF_ASCE)
fe0f4976	22	#define _CIF_NOHZ_DELAY (1<<CIF_NOHZ_DELAY)
9977e886	23	#define _CIF_FPU (1<<CIF_FPU)
db7e007f	24	#define _CIF_IGNORE_IRQ (1<<CIF_IGNORE_IRQ)
d3a73acb	25
eb608fb3 HC	26	#ifndef __ASSEMBLY__
eb608fb3 HC	27
edd53787	28	#include <linux/linkage.h>
a0616cde	29	#include <linux/irqflags.h>
e86a6ed6	30	#include <asm/cpu.h>
25097bf1	31	#include <asm/page.h>
1da177e4	32	#include <asm/ptrace.h>
25097bf1	33	#include <asm/setup.h>
e4b8b3f3	34	#include <asm/runtime_instr.h>
904818e2	35	#include <asm/fpu-internal.h>
1da177e4	36
d3a73acb MS	37	static inline void set_cpu_flag(int flag)
	38	{
	39	S390_lowcore.cpu_flags \|= (1U << flag);
	40	}
	41
	42	static inline void clear_cpu_flag(int flag)
	43	{
	44	S390_lowcore.cpu_flags &= ~(1U << flag);
	45	}
	46
	47	static inline int test_cpu_flag(int flag)
	48	{
	49	return !!(S390_lowcore.cpu_flags & (1U << flag));
	50	}
	51
fe0f4976 MS	52	#define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)
fe0f4976 MS	53
1da177e4 LT	54	/*
	55	* Default implementation of macro that returns current
	56	* instruction pointer ("program counter").
	57	*/
94c12cc7	58	#define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
1da177e4	59
e86a6ed6	60	static inline void get_cpu_id(struct cpuid *ptr)
72960a02	61	{
987bcdac	62	asm volatile("stidp %0" : "=Q" (*ptr));
72960a02 MH	63	}
72960a02 MH	64
31ee4b2f	65	extern void s390_adjust_jiffies(void);
638ad34a MS	66	extern const struct seq_operations cpuinfo_op;
638ad34a MS	67	extern int sysctl_ieee_emulation_warnings;
65f22a90	68	extern void execve_tail(void);
1da177e4	69
1da177e4	70	/*
f481bfaf	71	* User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
1da177e4	72	*/
1da177e4	73
f481bfaf	74	#define TASK_SIZE_OF(tsk) ((tsk)->mm->context.asce_limit)
5a216a20 MS	75	#define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \
	76	(1UL << 30) : (1UL << 41))
	77	#define TASK_SIZE TASK_SIZE_OF(current)
ee6ee55b	78	#define TASK_MAX_SIZE (1UL << 53)
1da177e4	79
6252d702 MS	80	#define STACK_TOP (1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
6252d702 MS	81	#define STACK_TOP_MAX (1UL << 42)
922a70d3	82
1da177e4 LT	83	#define HAVE_ARCH_PICK_MMAP_LAYOUT
	84
	85	typedef struct {
	86	__u32 ar4;
	87	} mm_segment_t;
	88
	89	/*
	90	* Thread structure
	91	*/
	92	struct thread_struct {
904818e2	93	struct fpu fpu; /* FP and VX register save area */
1da177e4 LT	94	unsigned int acrs[NUM_ACRS];
1da177e4 LT	95	unsigned long ksp; /* kernel stack pointer */
1da177e4	96	mm_segment_t mm_segment;
e5992f2e	97	unsigned long gmap_addr; /* address of last gmap fault. */
24eb3a82	98	unsigned int gmap_pfault; /* signal of a pending guest pfault */
5e9a2692 MS	99	struct per_regs per_user; /* User specified PER registers */
5e9a2692 MS	100	struct per_event per_event; /* Cause of the last PER trap */
d35339a4	101	unsigned long per_flags; /* Flags to control debug behavior */
1da177e4 LT	102	/* pfault_wait is used to block the process on a pfault event */
1da177e4 LT	103	unsigned long pfault_wait;
f2db2e6c	104	struct list_head list;
e4b8b3f3 JG	105	/* cpu runtime instrumentation */
	106	struct runtime_instr_cb *ri_cb;
	107	int ri_signum;
d35339a4	108	unsigned char trap_tdb[256]; /* Transaction abort diagnose block */
1da177e4 LT	109	};
1da177e4 LT	110
64597f9d MM	111	/* Flag to disable transactions. */
	112	#define PER_FLAG_NO_TE 1UL
	113	/* Flag to enable random transaction aborts. */
	114	#define PER_FLAG_TE_ABORT_RAND 2UL
	115	/* Flag to specify random transaction abort mode:
	116	* - abort each transaction at a random instruction before TEND if set.
	117	* - abort random transactions at a random instruction if cleared.
	118	*/
	119	#define PER_FLAG_TE_ABORT_RAND_TEND 4UL
d35339a4	120
1da177e4 LT	121	typedef struct thread_struct thread_struct;
	122
	123	/*
	124	* Stack layout of a C stack frame.
	125	*/
	126	#ifndef __PACK_STACK
	127	struct stack_frame {
	128	unsigned long back_chain;
	129	unsigned long empty1[5];
	130	unsigned long gprs[10];
	131	unsigned int empty2[8];
	132	};
	133	#else
	134	struct stack_frame {
	135	unsigned long empty1[5];
	136	unsigned int empty2[8];
	137	unsigned long gprs[10];
	138	unsigned long back_chain;
	139	};
	140	#endif
	141
	142	#define ARCH_MIN_TASKALIGN 8
	143
0ac27779	144	extern __vector128 init_task_fpu_regs[__NUM_VXRS];
6f3fa3f0 MS	145	#define INIT_THREAD { \
6f3fa3f0 MS	146	.ksp = sizeof(init_stack) + (unsigned long) &init_stack, \
0ac27779	147	.fpu.regs = (void *)&init_task_fpu_regs, \
6f3fa3f0	148	}
1da177e4 LT	149
	150	/*
	151	* Do necessary setup to start up a new thread.
	152	*/
b50511e4	153	#define start_thread(regs, new_psw, new_stackp) do { \
e258d719	154	regs->psw.mask = PSW_USER_BITS \| PSW_MASK_EA \| PSW_MASK_BA; \
b50511e4 MS	155	regs->psw.addr = new_psw \| PSW_ADDR_AMODE; \
b50511e4 MS	156	regs->gprs[15] = new_stackp; \
65f22a90	157	execve_tail(); \
63506c41 MS	158	} while (0)
63506c41 MS	159
b50511e4	160	#define start_thread31(regs, new_psw, new_stackp) do { \
e258d719	161	regs->psw.mask = PSW_USER_BITS \| PSW_MASK_BA; \
b50511e4 MS	162	regs->psw.addr = new_psw \| PSW_ADDR_AMODE; \
	163	regs->gprs[15] = new_stackp; \
	164	crst_table_downgrade(current->mm, 1UL << 31); \
65f22a90	165	execve_tail(); \
1da177e4 LT	166	} while (0)
1da177e4 LT	167
1da177e4 LT	168	/* Forward declaration, a strange C thing */
	169	struct task_struct;
	170	struct mm_struct;
df5f8314	171	struct seq_file;
1da177e4	172
5a79859a	173	void show_cacheinfo(struct seq_file *m);
6668022c	174
1da177e4 LT	175	/* Free all resources held by a thread. */
1da177e4 LT	176	extern void release_thread(struct task_struct *);
1da177e4	177
1da177e4 LT	178	/*
	179	* Return saved PC of a blocked thread.
	180	*/
	181	extern unsigned long thread_saved_pc(struct task_struct *t);
	182
1da177e4	183	unsigned long get_wchan(struct task_struct *p);
c7584fb6	184	#define task_pt_regs(tsk) ((struct pt_regs *) \
30af7120	185	(task_stack_page(tsk) + THREAD_SIZE) - 1)
c7584fb6 AV	186	#define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr)
c7584fb6 AV	187	#define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15])
1da177e4	188
5ebf250d HC	189	/* Has task runtime instrumentation enabled ? */
	190	#define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
	191
a0616cde DH	192	static inline unsigned short stap(void)
	193	{
	194	unsigned short cpu_address;
	195
	196	asm volatile("stap %0" : "=m" (cpu_address));
	197	return cpu_address;
	198	}
	199
1da177e4 LT	200	/*
	201	* Give up the time slice of the virtual PU.
	202	*/
4d92f502	203	void cpu_relax(void);
1da177e4	204
3a6bfbc9	205	#define cpu_relax_lowlatency() barrier()
083986e8	206
dc74d7f9 HC	207	static inline void psw_set_key(unsigned int key)
	208	{
	209	asm volatile("spka 0(%0)" : : "d" (key));
	210	}
	211
77fa2245 HC	212	/*
	213	* Set PSW to specified value.
	214	*/
	215	static inline void __load_psw(psw_t psw)
	216	{
987bcdac	217	asm volatile("lpswe %0" : : "Q" (psw) : "cc");
77fa2245 HC	218	}
77fa2245 HC	219
1da177e4 LT	220	/*
	221	* Set PSW mask to specified value, while leaving the
	222	* PSW addr pointing to the next instruction.
	223	*/
1da177e4 LT	224	static inline void __load_psw_mask (unsigned long mask)
	225	{
	226	unsigned long addr;
1da177e4	227	psw_t psw;
77fa2245	228
1da177e4 LT	229	psw.mask = mask;
1da177e4 LT	230
94c12cc7 MS	231	asm volatile(
94c12cc7 MS	232	" larl %0,1f\n"
987bcdac MS	233	" stg %0,%O1+8(%R1)\n"
987bcdac MS	234	" lpswe %1\n"
1da177e4	235	"1:"
987bcdac	236	: "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
1da177e4	237	}
ccf45caf	238
22362a0e MS	239	/*
	240	* Extract current PSW mask
	241	*/
	242	static inline unsigned long __extract_psw(void)
	243	{
	244	unsigned int reg1, reg2;
	245
	246	asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2));
	247	return (((unsigned long) reg1) << 32) \| ((unsigned long) reg2);
	248	}
	249
ccf45caf MS	250	/*
	251	* Rewind PSW instruction address by specified number of bytes.
	252	*/
	253	static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
	254	{
ccf45caf MS	255	unsigned long mask;
	256
	257	mask = (psw.mask & PSW_MASK_EA) ? -1UL :
	258	(psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
	259	(1UL << 24) - 1;
	260	return (psw.addr - ilc) & mask;
ccf45caf	261	}
b5f87f15 MS	262
	263	/*
	264	* Function to stop a processor until the next interrupt occurs
	265	*/
	266	void enabled_wait(void);
	267
1da177e4 LT	268	/*
	269	* Function to drop a processor into disabled wait state
	270	*/
ff2d8b19	271	static inline void __noreturn disabled_wait(unsigned long code)
1da177e4	272	{
1da177e4	273	unsigned long ctl_buf;
77fa2245	274	psw_t dw_psw;
1da177e4	275
b50511e4	276	dw_psw.mask = PSW_MASK_BASE \| PSW_MASK_WAIT \| PSW_MASK_BA \| PSW_MASK_EA;
77fa2245	277	dw_psw.addr = code;
1da177e4 LT	278	/*
	279	* Store status and then load disabled wait psw,
	280	* the processor is dead afterwards
	281	*/
94c12cc7 MS	282	asm volatile(
	283	" stctg 0,0,0(%2)\n"
	284	" ni 4(%2),0xef\n" /* switch off protection */
	285	" lctlg 0,0,0(%2)\n"
	286	" lghi 1,0x1000\n"
	287	" stpt 0x328(1)\n" /* store timer */
	288	" stckc 0x330(1)\n" /* store clock comparator */
	289	" stpx 0x318(1)\n" /* store prefix register */
	290	" stam 0,15,0x340(1)\n"/* store access registers */
	291	" stfpc 0x31c(1)\n" /* store fpu control */
	292	" std 0,0x200(1)\n" /* store f0 */
	293	" std 1,0x208(1)\n" /* store f1 */
	294	" std 2,0x210(1)\n" /* store f2 */
	295	" std 3,0x218(1)\n" /* store f3 */
	296	" std 4,0x220(1)\n" /* store f4 */
	297	" std 5,0x228(1)\n" /* store f5 */
	298	" std 6,0x230(1)\n" /* store f6 */
	299	" std 7,0x238(1)\n" /* store f7 */
	300	" std 8,0x240(1)\n" /* store f8 */
	301	" std 9,0x248(1)\n" /* store f9 */
	302	" std 10,0x250(1)\n" /* store f10 */
	303	" std 11,0x258(1)\n" /* store f11 */
	304	" std 12,0x260(1)\n" /* store f12 */
	305	" std 13,0x268(1)\n" /* store f13 */
	306	" std 14,0x270(1)\n" /* store f14 */
	307	" std 15,0x278(1)\n" /* store f15 */
	308	" stmg 0,15,0x280(1)\n"/* store general registers */
	309	" stctg 0,15,0x380(1)\n"/* store control registers */
	310	" oi 0x384(1),0x10\n"/* fake protection bit */
	311	" lpswe 0(%1)"
	312	: "=m" (ctl_buf)
bdd42b28	313	: "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1");
edd53787	314	while (1);
1da177e4 LT	315	}
1da177e4 LT	316
a0616cde DH	317	/*
	318	* Use to set psw mask except for the first byte which
	319	* won't be changed by this function.
	320	*/
	321	static inline void
	322	__set_psw_mask(unsigned long mask)
	323	{
	324	__load_psw_mask(mask \| (arch_local_save_flags() & ~(-1UL >> 8)));
	325	}
	326
	327	#define local_mcck_enable() \
e258d719	328	__set_psw_mask(PSW_KERNEL_BITS \| PSW_MASK_DAT \| PSW_MASK_MCHECK)
a0616cde	329	#define local_mcck_disable() \
e258d719	330	__set_psw_mask(PSW_KERNEL_BITS \| PSW_MASK_DAT)
a0616cde	331
ab14de6c HC	332	/*
	333	* Basic Machine Check/Program Check Handler.
	334	*/
	335
	336	extern void s390_base_mcck_handler(void);
	337	extern void s390_base_pgm_handler(void);
	338	extern void s390_base_ext_handler(void);
	339
	340	extern void (*s390_base_mcck_handler_fn)(void);
	341	extern void (*s390_base_pgm_handler_fn)(void);
	342	extern void (*s390_base_ext_handler_fn)(void);
	343
dfd54cbc HC	344	#define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL
dfd54cbc HC	345
fbe76568 HC	346	extern int memcpy_real(void , void , size_t);
	347	extern void memcpy_absolute(void , void , size_t);
	348
	349	#define mem_assign_absolute(dest, val) { \
	350	__typeof__(dest) __tmp = (val); \
	351	\
	352	BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \
	353	memcpy_absolute(&(dest), &__tmp, sizeof(__tmp)); \
	354	}
	355
eb608fb3 HC	356	#endif /* __ASSEMBLY__ */
	357
	358	#endif /* __ASM_S390_PROCESSOR_H */