[mirror_ubuntu-zesty-kernel.git] / arch / s390 / include / asm / processor.h

/*
 *  S390 version
 *    Copyright IBM Corp. 1999
 *    Author(s): Hartmut Penner (hp@de.ibm.com),
 *               Martin Schwidefsky (schwidefsky@de.ibm.com)
 *
 *  Derived from "include/asm-i386/processor.h"
 *    Copyright (C) 1994, Linus Torvalds
 */

#ifndef __ASM_S390_PROCESSOR_H
#define __ASM_S390_PROCESSOR_H

#include <linux/const.h>

#define CIF_MCCK_PENDING	0	/* machine check handling is pending */
#define CIF_ASCE		1	/* user asce needs fixup / uaccess */
#define CIF_NOHZ_DELAY		2	/* delay HZ disable for a tick */
#define CIF_FPU			3	/* restore FPU registers */
#define CIF_IGNORE_IRQ		4	/* ignore interrupt (for udelay) */
#define CIF_ENABLED_WAIT	5	/* in enabled wait state */

#define _CIF_MCCK_PENDING	_BITUL(CIF_MCCK_PENDING)
#define _CIF_ASCE		_BITUL(CIF_ASCE)
#define _CIF_NOHZ_DELAY		_BITUL(CIF_NOHZ_DELAY)
#define _CIF_FPU		_BITUL(CIF_FPU)
#define _CIF_IGNORE_IRQ		_BITUL(CIF_IGNORE_IRQ)
#define _CIF_ENABLED_WAIT	_BITUL(CIF_ENABLED_WAIT)

#ifndef __ASSEMBLY__

#include <linux/linkage.h>
#include <linux/irqflags.h>
#include <asm/cpu.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include <asm/setup.h>
#include <asm/runtime_instr.h>
#include <asm/fpu/types.h>
#include <asm/fpu/internal.h>

static inline void set_cpu_flag(int flag)
{
	S390_lowcore.cpu_flags |= (1UL << flag);
}

static inline void clear_cpu_flag(int flag)
{
	S390_lowcore.cpu_flags &= ~(1UL << flag);
}

static inline int test_cpu_flag(int flag)
{
	return !!(S390_lowcore.cpu_flags & (1UL << flag));
}

/*
 * Test CIF flag of another CPU. The caller needs to ensure that
 * CPU hotplug can not happen, e.g. by disabling preemption.
 */
static inline int test_cpu_flag_of(int flag, int cpu)
{
	struct lowcore *lc = lowcore_ptr[cpu];
	return !!(lc->cpu_flags & (1UL << flag));
}

#define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)

/*
 * Default implementation of macro that returns current
 * instruction pointer ("program counter").
 */
#define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })

static inline void get_cpu_id(struct cpuid *ptr)
{
	asm volatile("stidp %0" : "=Q" (*ptr));
}

void s390_adjust_jiffies(void);
void s390_update_cpu_mhz(void);
void cpu_detect_mhz_feature(void);

extern const struct seq_operations cpuinfo_op;
extern int sysctl_ieee_emulation_warnings;
extern void execve_tail(void);

/*
 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
 */

#define TASK_SIZE_OF(tsk)	((tsk)->mm->context.asce_limit)
#define TASK_UNMAPPED_BASE	(test_thread_flag(TIF_31BIT) ? \
					(1UL << 30) : (1UL << 41))
#define TASK_SIZE		TASK_SIZE_OF(current)
#define TASK_MAX_SIZE		(1UL << 53)

#define STACK_TOP		(1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
#define STACK_TOP_MAX		(1UL << 42)

#define HAVE_ARCH_PICK_MMAP_LAYOUT

typedef struct {
        __u32 ar4;
} mm_segment_t;

/*
 * Thread structure
 */
struct thread_struct {
	unsigned int  acrs[NUM_ACRS];
        unsigned long ksp;              /* kernel stack pointer             */
	mm_segment_t mm_segment;
	unsigned long gmap_addr;	/* address of last gmap fault. */
	unsigned int gmap_write_flag;	/* gmap fault write indication */
	unsigned int gmap_int_code;	/* int code of last gmap fault */
	unsigned int gmap_pfault;	/* signal of a pending guest pfault */
	/* Per-thread information related to debugging */
	struct per_regs per_user;	/* User specified PER registers */
	struct per_event per_event;	/* Cause of the last PER trap */
	unsigned long per_flags;	/* Flags to control debug behavior */
	unsigned int system_call;	/* system call number in signal */
        /* pfault_wait is used to block the process on a pfault event */
	unsigned long pfault_wait;
	struct list_head list;
	/* cpu runtime instrumentation */
	struct runtime_instr_cb *ri_cb;
	unsigned char trap_tdb[256];	/* Transaction abort diagnose block */
	/*
	 * Warning: 'fpu' is dynamically-sized. It *MUST* be at
	 * the end.
	 */
	struct fpu fpu;			/* FP and VX register save area */
};

/* Flag to disable transactions. */
#define PER_FLAG_NO_TE			1UL
/* Flag to enable random transaction aborts. */
#define PER_FLAG_TE_ABORT_RAND		2UL
/* Flag to specify random transaction abort mode:
 * - abort each transaction at a random instruction before TEND if set.
 * - abort random transactions at a random instruction if cleared.
 */
#define PER_FLAG_TE_ABORT_RAND_TEND	4UL

typedef struct thread_struct thread_struct;

/*
 * Stack layout of a C stack frame.
 */
#ifndef __PACK_STACK
struct stack_frame {
	unsigned long back_chain;
	unsigned long empty1[5];
	unsigned long gprs[10];
	unsigned int  empty2[8];
};
#else
struct stack_frame {
	unsigned long empty1[5];
	unsigned int  empty2[8];
	unsigned long gprs[10];
	unsigned long back_chain;
};
#endif

#define ARCH_MIN_TASKALIGN	8

#define INIT_THREAD {							\
	.ksp = sizeof(init_stack) + (unsigned long) &init_stack,	\
	.fpu.regs = (void *) init_task.thread.fpu.fprs,			\
}

/*
 * Do necessary setup to start up a new thread.
 */
#define start_thread(regs, new_psw, new_stackp) do {			\
	regs->psw.mask	= PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA;	\
	regs->psw.addr	= new_psw;					\
	regs->gprs[15]	= new_stackp;					\
	execve_tail();							\
} while (0)

#define start_thread31(regs, new_psw, new_stackp) do {			\
	regs->psw.mask	= PSW_USER_BITS | PSW_MASK_BA;			\
	regs->psw.addr	= new_psw;					\
	regs->gprs[15]	= new_stackp;					\
	crst_table_downgrade(current->mm);				\
	execve_tail();							\
} while (0)

/* Forward declaration, a strange C thing */
struct task_struct;
struct mm_struct;
struct seq_file;

typedef int (*dump_trace_func_t)(void *data, unsigned long address, int reliable);
void dump_trace(dump_trace_func_t func, void *data,
		struct task_struct *task, unsigned long sp);

void show_cacheinfo(struct seq_file *m);

/* Free all resources held by a thread. */
extern void release_thread(struct task_struct *);

/*
 * Return saved PC of a blocked thread.
 */
extern unsigned long thread_saved_pc(struct task_struct *t);

unsigned long get_wchan(struct task_struct *p);
#define task_pt_regs(tsk) ((struct pt_regs *) \
        (task_stack_page(tsk) + THREAD_SIZE) - 1)
#define KSTK_EIP(tsk)	(task_pt_regs(tsk)->psw.addr)
#define KSTK_ESP(tsk)	(task_pt_regs(tsk)->gprs[15])

/* Has task runtime instrumentation enabled ? */
#define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)

static inline unsigned long current_stack_pointer(void)
{
	unsigned long sp;

	asm volatile("la %0,0(15)" : "=a" (sp));
	return sp;
}

static inline unsigned short stap(void)
{
	unsigned short cpu_address;

	asm volatile("stap %0" : "=m" (cpu_address));
	return cpu_address;
}

/*
 * Give up the time slice of the virtual PU.
 */
void cpu_relax(void);

#define cpu_relax_lowlatency()  barrier()

#define ECAG_CACHE_ATTRIBUTE	0
#define ECAG_CPU_ATTRIBUTE	1

static inline unsigned long __ecag(unsigned int asi, unsigned char parm)
{
	unsigned long val;

	asm volatile(".insn	rsy,0xeb000000004c,%0,0,0(%1)" /* ecag */
		     : "=d" (val) : "a" (asi << 8 | parm));
	return val;
}

static inline void psw_set_key(unsigned int key)
{
	asm volatile("spka 0(%0)" : : "d" (key));
}

/*
 * Set PSW to specified value.
 */
static inline void __load_psw(psw_t psw)
{
	asm volatile("lpswe %0" : : "Q" (psw) : "cc");
}

/*
 * Set PSW mask to specified value, while leaving the
 * PSW addr pointing to the next instruction.
 */
static inline void __load_psw_mask(unsigned long mask)
{
	unsigned long addr;
	psw_t psw;

	psw.mask = mask;

	asm volatile(
		"	larl	%0,1f\n"
		"	stg	%0,%O1+8(%R1)\n"
		"	lpswe	%1\n"
		"1:"
		: "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
}

/*
 * Extract current PSW mask
 */
static inline unsigned long __extract_psw(void)
{
	unsigned int reg1, reg2;

	asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2));
	return (((unsigned long) reg1) << 32) | ((unsigned long) reg2);
}

static inline void local_mcck_enable(void)
{
	__load_psw_mask(__extract_psw() | PSW_MASK_MCHECK);
}

static inline void local_mcck_disable(void)
{
	__load_psw_mask(__extract_psw() & ~PSW_MASK_MCHECK);
}

/*
 * Rewind PSW instruction address by specified number of bytes.
 */
static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
{
	unsigned long mask;

	mask = (psw.mask & PSW_MASK_EA) ? -1UL :
	       (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
					  (1UL << 24) - 1;
	return (psw.addr - ilc) & mask;
}

/*
 * Function to stop a processor until the next interrupt occurs
 */
void enabled_wait(void);

/*
 * Function to drop a processor into disabled wait state
 */
static inline void __noreturn disabled_wait(unsigned long code)
{
	psw_t psw;

	psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
	psw.addr = code;
	__load_psw(psw);
	while (1);
}

/*
 * Basic Machine Check/Program Check Handler.
 */

extern void s390_base_mcck_handler(void);
extern void s390_base_pgm_handler(void);
extern void s390_base_ext_handler(void);

extern void (*s390_base_mcck_handler_fn)(void);
extern void (*s390_base_pgm_handler_fn)(void);
extern void (*s390_base_ext_handler_fn)(void);

#define ARCH_LOW_ADDRESS_LIMIT	0x7fffffffUL

extern int memcpy_real(void *, void *, size_t);
extern void memcpy_absolute(void *, void *, size_t);

#define mem_assign_absolute(dest, val) {			\
	__typeof__(dest) __tmp = (val);				\
								\
	BUILD_BUG_ON(sizeof(__tmp) != sizeof(val));		\
	memcpy_absolute(&(dest), &__tmp, sizeof(__tmp));	\
}

#endif /* __ASSEMBLY__ */

#endif /* __ASM_S390_PROCESSOR_H */
Commit	Line	Data
1da177e4	1	/*
1da177e4	2	* S390 version
a53c8fab	3	* Copyright IBM Corp. 1999
1da177e4 LT	4	* Author(s): Hartmut Penner (hp@de.ibm.com),
	5	* Martin Schwidefsky (schwidefsky@de.ibm.com)
	6	*
	7	* Derived from "include/asm-i386/processor.h"
	8	* Copyright (C) 1994, Linus Torvalds
	9	*/
	10
	11	#ifndef __ASM_S390_PROCESSOR_H
	12	#define __ASM_S390_PROCESSOR_H
	13
92778b99 HC	14	#include <linux/const.h>
92778b99 HC	15
d3a73acb MS	16	#define CIF_MCCK_PENDING 0 /* machine check handling is pending */
d3a73acb MS	17	#define CIF_ASCE 1 /* user asce needs fixup / uaccess */
fe0f4976	18	#define CIF_NOHZ_DELAY 2 /* delay HZ disable for a tick */
b0753902	19	#define CIF_FPU 3 /* restore FPU registers */
db7e007f	20	#define CIF_IGNORE_IRQ 4 /* ignore interrupt (for udelay) */
419123f9	21	#define CIF_ENABLED_WAIT 5 /* in enabled wait state */
d3a73acb	22
92778b99 HC	23	#define _CIF_MCCK_PENDING _BITUL(CIF_MCCK_PENDING)
	24	#define _CIF_ASCE _BITUL(CIF_ASCE)
	25	#define _CIF_NOHZ_DELAY _BITUL(CIF_NOHZ_DELAY)
	26	#define _CIF_FPU _BITUL(CIF_FPU)
	27	#define _CIF_IGNORE_IRQ _BITUL(CIF_IGNORE_IRQ)
419123f9	28	#define _CIF_ENABLED_WAIT _BITUL(CIF_ENABLED_WAIT)
d3a73acb	29
eb608fb3 HC	30	#ifndef __ASSEMBLY__
eb608fb3 HC	31
edd53787	32	#include <linux/linkage.h>
a0616cde	33	#include <linux/irqflags.h>
e86a6ed6	34	#include <asm/cpu.h>
25097bf1	35	#include <asm/page.h>
1da177e4	36	#include <asm/ptrace.h>
25097bf1	37	#include <asm/setup.h>
e4b8b3f3	38	#include <asm/runtime_instr.h>
b0753902 HB	39	#include <asm/fpu/types.h>
b0753902 HB	40	#include <asm/fpu/internal.h>
1da177e4	41
d3a73acb MS	42	static inline void set_cpu_flag(int flag)
d3a73acb MS	43	{
ac25e790	44	S390_lowcore.cpu_flags \|= (1UL << flag);
d3a73acb MS	45	}
	46
	47	static inline void clear_cpu_flag(int flag)
	48	{
ac25e790	49	S390_lowcore.cpu_flags &= ~(1UL << flag);
d3a73acb MS	50	}
	51
	52	static inline int test_cpu_flag(int flag)
	53	{
ac25e790	54	return !!(S390_lowcore.cpu_flags & (1UL << flag));
d3a73acb MS	55	}
d3a73acb MS	56
419123f9 MS	57	/*
	58	* Test CIF flag of another CPU. The caller needs to ensure that
	59	* CPU hotplug can not happen, e.g. by disabling preemption.
	60	*/
	61	static inline int test_cpu_flag_of(int flag, int cpu)
	62	{
c667aeac	63	struct lowcore *lc = lowcore_ptr[cpu];
419123f9 MS	64	return !!(lc->cpu_flags & (1UL << flag));
	65	}
	66
fe0f4976 MS	67	#define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)
fe0f4976 MS	68
1da177e4 LT	69	/*
	70	* Default implementation of macro that returns current
	71	* instruction pointer ("program counter").
	72	*/
94c12cc7	73	#define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
1da177e4	74
e86a6ed6	75	static inline void get_cpu_id(struct cpuid *ptr)
72960a02	76	{
987bcdac	77	asm volatile("stidp %0" : "=Q" (*ptr));
72960a02 MH	78	}
72960a02 MH	79
097a116c HC	80	void s390_adjust_jiffies(void);
	81	void s390_update_cpu_mhz(void);
	82	void cpu_detect_mhz_feature(void);
	83
638ad34a MS	84	extern const struct seq_operations cpuinfo_op;
638ad34a MS	85	extern int sysctl_ieee_emulation_warnings;
65f22a90	86	extern void execve_tail(void);
1da177e4	87
1da177e4	88	/*
f481bfaf	89	* User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
1da177e4	90	*/
1da177e4	91
f481bfaf	92	#define TASK_SIZE_OF(tsk) ((tsk)->mm->context.asce_limit)
5a216a20 MS	93	#define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \
	94	(1UL << 30) : (1UL << 41))
	95	#define TASK_SIZE TASK_SIZE_OF(current)
ee6ee55b	96	#define TASK_MAX_SIZE (1UL << 53)
1da177e4	97
6252d702 MS	98	#define STACK_TOP (1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
6252d702 MS	99	#define STACK_TOP_MAX (1UL << 42)
922a70d3	100
1da177e4 LT	101	#define HAVE_ARCH_PICK_MMAP_LAYOUT
	102
	103	typedef struct {
	104	__u32 ar4;
	105	} mm_segment_t;
	106
	107	/*
	108	* Thread structure
	109	*/
	110	struct thread_struct {
1da177e4 LT	111	unsigned int acrs[NUM_ACRS];
1da177e4 LT	112	unsigned long ksp; /* kernel stack pointer */
1da177e4	113	mm_segment_t mm_segment;
e5992f2e	114	unsigned long gmap_addr; /* address of last gmap fault. */
4be130a0	115	unsigned int gmap_write_flag; /* gmap fault write indication */
4a494439	116	unsigned int gmap_int_code; /* int code of last gmap fault */
24eb3a82	117	unsigned int gmap_pfault; /* signal of a pending guest pfault */
f8fc82b4	118	/* Per-thread information related to debugging */
5e9a2692 MS	119	struct per_regs per_user; /* User specified PER registers */
5e9a2692 MS	120	struct per_event per_event; /* Cause of the last PER trap */
d35339a4	121	unsigned long per_flags; /* Flags to control debug behavior */
f8fc82b4	122	unsigned int system_call; /* system call number in signal */
1da177e4 LT	123	/* pfault_wait is used to block the process on a pfault event */
1da177e4 LT	124	unsigned long pfault_wait;
f2db2e6c	125	struct list_head list;
e4b8b3f3 JG	126	/* cpu runtime instrumentation */
e4b8b3f3 JG	127	struct runtime_instr_cb *ri_cb;
d35339a4	128	unsigned char trap_tdb[256]; /* Transaction abort diagnose block */
3f6813b9 MS	129	/*
	130	* Warning: 'fpu' is dynamically-sized. It MUST be at
	131	* the end.
	132	*/
	133	struct fpu fpu; /* FP and VX register save area */
1da177e4 LT	134	};
1da177e4 LT	135
64597f9d MM	136	/* Flag to disable transactions. */
	137	#define PER_FLAG_NO_TE 1UL
	138	/* Flag to enable random transaction aborts. */
	139	#define PER_FLAG_TE_ABORT_RAND 2UL
	140	/* Flag to specify random transaction abort mode:
	141	* - abort each transaction at a random instruction before TEND if set.
	142	* - abort random transactions at a random instruction if cleared.
	143	*/
	144	#define PER_FLAG_TE_ABORT_RAND_TEND 4UL
d35339a4	145
1da177e4 LT	146	typedef struct thread_struct thread_struct;
	147
	148	/*
	149	* Stack layout of a C stack frame.
	150	*/
	151	#ifndef __PACK_STACK
	152	struct stack_frame {
	153	unsigned long back_chain;
	154	unsigned long empty1[5];
	155	unsigned long gprs[10];
	156	unsigned int empty2[8];
	157	};
	158	#else
	159	struct stack_frame {
	160	unsigned long empty1[5];
	161	unsigned int empty2[8];
	162	unsigned long gprs[10];
	163	unsigned long back_chain;
	164	};
	165	#endif
	166
	167	#define ARCH_MIN_TASKALIGN 8
	168
6f3fa3f0 MS	169	#define INIT_THREAD { \
6f3fa3f0 MS	170	.ksp = sizeof(init_stack) + (unsigned long) &init_stack, \
3f6813b9	171	.fpu.regs = (void *) init_task.thread.fpu.fprs, \
6f3fa3f0	172	}
1da177e4 LT	173
	174	/*
	175	* Do necessary setup to start up a new thread.
	176	*/
b50511e4	177	#define start_thread(regs, new_psw, new_stackp) do { \
e258d719	178	regs->psw.mask = PSW_USER_BITS \| PSW_MASK_EA \| PSW_MASK_BA; \
fecc868a	179	regs->psw.addr = new_psw; \
b50511e4	180	regs->gprs[15] = new_stackp; \
65f22a90	181	execve_tail(); \
63506c41 MS	182	} while (0)
63506c41 MS	183
b50511e4	184	#define start_thread31(regs, new_psw, new_stackp) do { \
e258d719	185	regs->psw.mask = PSW_USER_BITS \| PSW_MASK_BA; \
fecc868a	186	regs->psw.addr = new_psw; \
b50511e4	187	regs->gprs[15] = new_stackp; \
723cacbd	188	crst_table_downgrade(current->mm); \
65f22a90	189	execve_tail(); \
1da177e4 LT	190	} while (0)
1da177e4 LT	191
1da177e4 LT	192	/* Forward declaration, a strange C thing */
	193	struct task_struct;
	194	struct mm_struct;
df5f8314	195	struct seq_file;
1da177e4	196
d0208639	197	typedef int (dump_trace_func_t)(void data, unsigned long address, int reliable);
758d39eb HC	198	void dump_trace(dump_trace_func_t func, void *data,
	199	struct task_struct *task, unsigned long sp);
	200
5a79859a	201	void show_cacheinfo(struct seq_file *m);
6668022c	202
1da177e4 LT	203	/* Free all resources held by a thread. */
1da177e4 LT	204	extern void release_thread(struct task_struct *);
1da177e4	205
1da177e4 LT	206	/*
	207	* Return saved PC of a blocked thread.
	208	*/
	209	extern unsigned long thread_saved_pc(struct task_struct *t);
	210
1da177e4	211	unsigned long get_wchan(struct task_struct *p);
c7584fb6	212	#define task_pt_regs(tsk) ((struct pt_regs *) \
30af7120	213	(task_stack_page(tsk) + THREAD_SIZE) - 1)
c7584fb6 AV	214	#define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr)
c7584fb6 AV	215	#define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15])
1da177e4	216
5ebf250d HC	217	/* Has task runtime instrumentation enabled ? */
	218	#define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
	219
76737ce1 HC	220	static inline unsigned long current_stack_pointer(void)
	221	{
	222	unsigned long sp;
	223
	224	asm volatile("la %0,0(15)" : "=a" (sp));
	225	return sp;
	226	}
	227
a0616cde DH	228	static inline unsigned short stap(void)
	229	{
	230	unsigned short cpu_address;
	231
	232	asm volatile("stap %0" : "=m" (cpu_address));
	233	return cpu_address;
	234	}
	235
1da177e4 LT	236	/*
	237	* Give up the time slice of the virtual PU.
	238	*/
4d92f502	239	void cpu_relax(void);
1da177e4	240
3a6bfbc9	241	#define cpu_relax_lowlatency() barrier()
083986e8	242
097a116c HC	243	#define ECAG_CACHE_ATTRIBUTE 0
	244	#define ECAG_CPU_ATTRIBUTE 1
	245
	246	static inline unsigned long __ecag(unsigned int asi, unsigned char parm)
	247	{
	248	unsigned long val;
	249
	250	asm volatile(".insn rsy,0xeb000000004c,%0,0,0(%1)" /* ecag */
	251	: "=d" (val) : "a" (asi << 8 \| parm));
	252	return val;
	253	}
	254
dc74d7f9 HC	255	static inline void psw_set_key(unsigned int key)
	256	{
	257	asm volatile("spka 0(%0)" : : "d" (key));
	258	}
	259
77fa2245 HC	260	/*
	261	* Set PSW to specified value.
	262	*/
	263	static inline void __load_psw(psw_t psw)
	264	{
987bcdac	265	asm volatile("lpswe %0" : : "Q" (psw) : "cc");
77fa2245 HC	266	}
77fa2245 HC	267
1da177e4 LT	268	/*
	269	* Set PSW mask to specified value, while leaving the
	270	* PSW addr pointing to the next instruction.
	271	*/
ecbafda8	272	static inline void __load_psw_mask(unsigned long mask)
1da177e4 LT	273	{
1da177e4 LT	274	unsigned long addr;
1da177e4	275	psw_t psw;
77fa2245	276
1da177e4 LT	277	psw.mask = mask;
1da177e4 LT	278
94c12cc7 MS	279	asm volatile(
94c12cc7 MS	280	" larl %0,1f\n"
987bcdac MS	281	" stg %0,%O1+8(%R1)\n"
987bcdac MS	282	" lpswe %1\n"
1da177e4	283	"1:"
987bcdac	284	: "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
1da177e4	285	}
ccf45caf	286
22362a0e MS	287	/*
	288	* Extract current PSW mask
	289	*/
	290	static inline unsigned long __extract_psw(void)
	291	{
	292	unsigned int reg1, reg2;
	293
	294	asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2));
	295	return (((unsigned long) reg1) << 32) \| ((unsigned long) reg2);
	296	}
	297
ecbafda8 HC	298	static inline void local_mcck_enable(void)
	299	{
	300	__load_psw_mask(__extract_psw() \| PSW_MASK_MCHECK);
	301	}
	302
	303	static inline void local_mcck_disable(void)
	304	{
	305	__load_psw_mask(__extract_psw() & ~PSW_MASK_MCHECK);
	306	}
	307
ccf45caf MS	308	/*
	309	* Rewind PSW instruction address by specified number of bytes.
	310	*/
	311	static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
	312	{
ccf45caf MS	313	unsigned long mask;
	314
	315	mask = (psw.mask & PSW_MASK_EA) ? -1UL :
	316	(psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
	317	(1UL << 24) - 1;
	318	return (psw.addr - ilc) & mask;
ccf45caf	319	}
b5f87f15 MS	320
	321	/*
	322	* Function to stop a processor until the next interrupt occurs
	323	*/
	324	void enabled_wait(void);
	325
1da177e4 LT	326	/*
	327	* Function to drop a processor into disabled wait state
	328	*/
ff2d8b19	329	static inline void __noreturn disabled_wait(unsigned long code)
1da177e4	330	{
f9e6edfb HC	331	psw_t psw;
	332
	333	psw.mask = PSW_MASK_BASE \| PSW_MASK_WAIT \| PSW_MASK_BA \| PSW_MASK_EA;
	334	psw.addr = code;
	335	__load_psw(psw);
edd53787	336	while (1);
1da177e4 LT	337	}
1da177e4 LT	338
ab14de6c HC	339	/*
	340	* Basic Machine Check/Program Check Handler.
	341	*/
	342
	343	extern void s390_base_mcck_handler(void);
	344	extern void s390_base_pgm_handler(void);
	345	extern void s390_base_ext_handler(void);
	346
	347	extern void (*s390_base_mcck_handler_fn)(void);
	348	extern void (*s390_base_pgm_handler_fn)(void);
	349	extern void (*s390_base_ext_handler_fn)(void);
	350
dfd54cbc HC	351	#define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL
dfd54cbc HC	352
fbe76568 HC	353	extern int memcpy_real(void , void , size_t);
	354	extern void memcpy_absolute(void , void , size_t);
	355
	356	#define mem_assign_absolute(dest, val) { \
	357	__typeof__(dest) __tmp = (val); \
	358	\
	359	BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \
	360	memcpy_absolute(&(dest), &__tmp, sizeof(__tmp)); \
	361	}
	362
eb608fb3 HC	363	#endif /* __ASSEMBLY__ */
	364
	365	#endif /* __ASM_S390_PROCESSOR_H */