[mirror_ubuntu-artful-kernel.git] / arch / sh / boards / mach-se / 7722 / irq.c

/*
 * Hitachi UL SolutionEngine 7722 FPGA IRQ Support.
 *
 * Copyright (C) 2007  Nobuhiro Iwamatsu
 * Copyright (C) 2012  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#define DRV_NAME "SE7722-FPGA"
#define pr_fmt(fmt) DRV_NAME ": " fmt

#define irq_reg_readl	ioread16
#define irq_reg_writel	iowrite16

#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/err.h>
#include <asm/sizes.h>
#include <mach-se/mach/se7722.h>

#define IRQ01_BASE_ADDR	0x11800000
#define IRQ01_MODE_REG	0
#define IRQ01_STS_REG	4
#define IRQ01_MASK_REG	8

static void __iomem *se7722_irq_regs;
struct irq_domain *se7722_irq_domain;

static void se7722_irq_demux(unsigned int irq, struct irq_desc *desc)
{
	struct irq_data *data = irq_get_irq_data(irq);
	struct irq_chip *chip = irq_data_get_irq_chip(data);
	unsigned long mask;
	int bit;

	chip->irq_mask_ack(data);

	mask = ioread16(se7722_irq_regs + IRQ01_STS_REG);

	for_each_set_bit(bit, &mask, SE7722_FPGA_IRQ_NR)
		generic_handle_irq(irq_linear_revmap(se7722_irq_domain, bit));

	chip->irq_unmask(data);
}

static void __init se7722_domain_init(void)
{
	int i;

	se7722_irq_domain = irq_domain_add_linear(NULL, SE7722_FPGA_IRQ_NR,
						  &irq_domain_simple_ops, NULL);
	if (unlikely(!se7722_irq_domain)) {
		printk("Failed to get IRQ domain\n");
		return;
	}

	for (i = 0; i < SE7722_FPGA_IRQ_NR; i++) {
		int irq = irq_create_mapping(se7722_irq_domain, i);

		if (unlikely(irq == 0)) {
			printk("Failed to allocate IRQ %d\n", i);
			return;
		}
	}
}

static void __init se7722_gc_init(void)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;
	unsigned int irq_base;

	irq_base = irq_linear_revmap(se7722_irq_domain, 0);

	gc = irq_alloc_generic_chip(DRV_NAME, 1, irq_base, se7722_irq_regs,
				    handle_level_irq);
	if (unlikely(!gc))
		return;

	ct = gc->chip_types;
	ct->chip.irq_mask = irq_gc_mask_set_bit;
	ct->chip.irq_unmask = irq_gc_mask_clr_bit;

	ct->regs.mask = IRQ01_MASK_REG;

	irq_setup_generic_chip(gc, IRQ_MSK(SE7722_FPGA_IRQ_NR),
			       IRQ_GC_INIT_MASK_CACHE,
			       IRQ_NOREQUEST | IRQ_NOPROBE, 0);

	irq_set_chained_handler(IRQ0_IRQ, se7722_irq_demux);
	irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);

	irq_set_chained_handler(IRQ1_IRQ, se7722_irq_demux);
	irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
}

/*
 * Initialize FPGA IRQs
 */
void __init init_se7722_IRQ(void)
{
	se7722_irq_regs = ioremap(IRQ01_BASE_ADDR, SZ_16);
	if (unlikely(!se7722_irq_regs)) {
		printk("Failed to remap IRQ01 regs\n");
		return;
	}

	/*
	 * All FPGA IRQs disabled by default
	 */
	iowrite16(0, se7722_irq_regs + IRQ01_MASK_REG);

	__raw_writew(0x2000, 0xb03fffec);  /* mrshpc irq enable */

	se7722_domain_init();
	se7722_gc_init();
}
Commit	Line	Data
6865f0ea	1	/*
5df38b9b	2	* Hitachi UL SolutionEngine 7722 FPGA IRQ Support.
6865f0ea RS	3	*
6865f0ea RS	4	* Copyright (C) 2007 Nobuhiro Iwamatsu
5df38b9b	5	* Copyright (C) 2012 Paul Mundt
6865f0ea RS	6	*
	7	* This file is subject to the terms and conditions of the GNU General Public
	8	* License. See the file "COPYING" in the main directory of this archive
	9	* for more details.
	10	*/
5df38b9b PM	11	#define DRV_NAME "SE7722-FPGA"
	12	#define pr_fmt(fmt) DRV_NAME ": " fmt
	13
	14	#define irq_reg_readl ioread16
	15	#define irq_reg_writel iowrite16
	16
6865f0ea RS	17	#include <linux/init.h>
	18	#include <linux/irq.h>
	19	#include <linux/interrupt.h>
5df38b9b PM	20	#include <linux/irqdomain.h>
	21	#include <linux/io.h>
	22	#include <linux/err.h>
	23	#include <asm/sizes.h>
939a24a6	24	#include <mach-se/mach/se7722.h>
6865f0ea	25
5df38b9b PM	26	#define IRQ01_BASE_ADDR 0x11800000
	27	#define IRQ01_MODE_REG 0
	28	#define IRQ01_STS_REG 4
	29	#define IRQ01_MASK_REG 8
a37c6c7a	30
5df38b9b PM	31	static void __iomem *se7722_irq_regs;
5df38b9b PM	32	struct irq_domain *se7722_irq_domain;
6865f0ea	33
5df38b9b	34	static void se7722_irq_demux(unsigned int irq, struct irq_desc *desc)
6865f0ea	35	{
5df38b9b PM	36	struct irq_data *data = irq_get_irq_data(irq);
	37	struct irq_chip *chip = irq_data_get_irq_chip(data);
	38	unsigned long mask;
	39	int bit;
6865f0ea	40
5df38b9b	41	chip->irq_mask_ack(data);
6865f0ea	42
5df38b9b PM	43	mask = ioread16(se7722_irq_regs + IRQ01_STS_REG);
	44
	45	for_each_set_bit(bit, &mask, SE7722_FPGA_IRQ_NR)
	46	generic_handle_irq(irq_linear_revmap(se7722_irq_domain, bit));
	47
	48	chip->irq_unmask(data);
	49	}
	50
	51	static void __init se7722_domain_init(void)
6865f0ea	52	{
5df38b9b	53	int i;
493a358e	54
5df38b9b PM	55	se7722_irq_domain = irq_domain_add_linear(NULL, SE7722_FPGA_IRQ_NR,
	56	&irq_domain_simple_ops, NULL);
	57	if (unlikely(!se7722_irq_domain)) {
	58	printk("Failed to get IRQ domain\n");
	59	return;
	60	}
6865f0ea	61
5df38b9b PM	62	for (i = 0; i < SE7722_FPGA_IRQ_NR; i++) {
5df38b9b PM	63	int irq = irq_create_mapping(se7722_irq_domain, i);
a37c6c7a	64
5df38b9b PM	65	if (unlikely(irq == 0)) {
	66	printk("Failed to allocate IRQ %d\n", i);
	67	return;
	68	}
6865f0ea	69	}
6865f0ea	70	}
493a358e	71
5df38b9b	72	static void __init se7722_gc_init(void)
6865f0ea	73	{
5df38b9b PM	74	struct irq_chip_generic *gc;
	75	struct irq_chip_type *ct;
	76	unsigned int irq_base;
493a358e	77
5df38b9b	78	irq_base = irq_linear_revmap(se7722_irq_domain, 0);
6865f0ea	79
5df38b9b PM	80	gc = irq_alloc_generic_chip(DRV_NAME, 1, irq_base, se7722_irq_regs,
	81	handle_level_irq);
	82	if (unlikely(!gc))
	83	return;
a37c6c7a	84
5df38b9b PM	85	ct = gc->chip_types;
	86	ct->chip.irq_mask = irq_gc_mask_set_bit;
	87	ct->chip.irq_unmask = irq_gc_mask_clr_bit;
493a358e	88
5df38b9b PM	89	ct->regs.mask = IRQ01_MASK_REG;
	90
	91	irq_setup_generic_chip(gc, IRQ_MSK(SE7722_FPGA_IRQ_NR),
	92	IRQ_GC_INIT_MASK_CACHE,
	93	IRQ_NOREQUEST \| IRQ_NOPROBE, 0);
a37c6c7a	94
fcb8918f TG	95	irq_set_chained_handler(IRQ0_IRQ, se7722_irq_demux);
fcb8918f TG	96	irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
493a358e	97
fcb8918f TG	98	irq_set_chained_handler(IRQ1_IRQ, se7722_irq_demux);
fcb8918f TG	99	irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
6865f0ea	100	}
5df38b9b PM	101
	102	/*
	103	* Initialize FPGA IRQs
	104	*/
	105	void __init init_se7722_IRQ(void)
	106	{
	107	se7722_irq_regs = ioremap(IRQ01_BASE_ADDR, SZ_16);
	108	if (unlikely(!se7722_irq_regs)) {
	109	printk("Failed to remap IRQ01 regs\n");
	110	return;
	111	}
	112
	113	/*
	114	* All FPGA IRQs disabled by default
	115	*/
	116	iowrite16(0, se7722_irq_regs + IRQ01_MASK_REG);
	117
	118	__raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */
	119
	120	se7722_domain_init();
	121	se7722_gc_init();
	122	}