]>
Commit | Line | Data |
---|---|---|
7dec62e9 PM |
1 | /* |
2 | * SH7705 Setup | |
3 | * | |
0caedb02 | 4 | * Copyright (C) 2006 - 2009 Paul Mundt |
2a8ff459 | 5 | * Copyright (C) 2007 Nobuhiro Iwamatsu |
7dec62e9 PM |
6 | * |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file "COPYING" in the main directory of this archive | |
9 | * for more details. | |
10 | */ | |
11 | #include <linux/platform_device.h> | |
12 | #include <linux/init.h> | |
70e8be0a | 13 | #include <linux/irq.h> |
7dec62e9 | 14 | #include <linux/serial.h> |
96de1a8f | 15 | #include <linux/serial_sci.h> |
acd664ab | 16 | #include <linux/sh_timer.h> |
e91b2a40 | 17 | #include <linux/sh_intc.h> |
ad89f87a | 18 | #include <asm/rtc.h> |
61a6976b | 19 | #include <cpu/serial.h> |
7dec62e9 | 20 | |
ad89f87a | 21 | enum { |
70e8be0a MD |
22 | UNUSED = 0, |
23 | ||
24 | /* interrupt sources */ | |
25 | IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, | |
26 | PINT07, PINT815, | |
0caedb02 PM |
27 | |
28 | DMAC, SCIF0, SCIF2, ADC_ADI, USB, | |
29 | ||
70e8be0a | 30 | TPU0, TPU1, TPU2, TPU3, |
0caedb02 | 31 | TMU0, TMU1, TMU2, |
70e8be0a | 32 | |
0caedb02 | 33 | RTC, WDT, REF_RCMI, |
70e8be0a MD |
34 | }; |
35 | ||
5c37e025 | 36 | static struct intc_vect vectors[] __initdata = { |
a276e588 | 37 | /* IRQ0->5 are handled in setup-sh3.c */ |
70e8be0a | 38 | INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720), |
0caedb02 PM |
39 | INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820), |
40 | INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860), | |
41 | INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0), | |
42 | INTC_VECT(SCIF0, 0x8e0), | |
43 | INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920), | |
44 | INTC_VECT(SCIF2, 0x960), | |
70e8be0a | 45 | INTC_VECT(ADC_ADI, 0x980), |
0caedb02 | 46 | INTC_VECT(USB, 0xa20), INTC_VECT(USB, 0xa40), |
70e8be0a | 47 | INTC_VECT(TPU0, 0xc00), INTC_VECT(TPU1, 0xc20), |
65c07d4b | 48 | INTC_VECT(TPU2, 0xc80), INTC_VECT(TPU3, 0xca0), |
70e8be0a | 49 | INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), |
0caedb02 PM |
50 | INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460), |
51 | INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), | |
52 | INTC_VECT(RTC, 0x4c0), | |
70e8be0a MD |
53 | INTC_VECT(WDT, 0x560), |
54 | INTC_VECT(REF_RCMI, 0x580), | |
55 | }; | |
56 | ||
5c37e025 | 57 | static struct intc_prio_reg prio_registers[] __initdata = { |
6ef5fb2c MD |
58 | { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, |
59 | { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, 0, 0 } }, | |
60 | { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, | |
61 | { 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, IRQ5, IRQ4 } }, | |
62 | { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, SCIF0, SCIF2, ADC_ADI } }, | |
63 | { 0xa4080000, 0, 16, 4, /* IPRF */ { 0, 0, USB } }, | |
64 | { 0xa4080002, 0, 16, 4, /* IPRG */ { TPU0, TPU1 } }, | |
65 | { 0xa4080004, 0, 16, 4, /* IPRH */ { TPU2, TPU3 } }, | |
70e8be0a MD |
66 | |
67 | }; | |
68 | ||
0caedb02 | 69 | static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, NULL, |
7f3edee8 | 70 | NULL, prio_registers, NULL); |
70e8be0a | 71 | |
44658dfb | 72 | static struct plat_sci_port scif0_platform_data = { |
44658dfb | 73 | .flags = UPF_BOOT_AUTOCONF, |
f43dc23d PM |
74 | .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | |
75 | SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0, | |
44658dfb | 76 | .type = PORT_SCIF, |
61a6976b PM |
77 | .ops = &sh770x_sci_port_ops, |
78 | .regtype = SCIx_SH7705_SCIF_REGTYPE, | |
44658dfb MD |
79 | }; |
80 | ||
d850acf9 LP |
81 | static struct resource scif0_resources[] = { |
82 | DEFINE_RES_MEM(0xa4410000, 0x100), | |
83 | DEFINE_RES_IRQ(evt2irq(0x900)), | |
84 | }; | |
85 | ||
44658dfb | 86 | static struct platform_device scif0_device = { |
7dec62e9 | 87 | .name = "sh-sci", |
44658dfb | 88 | .id = 0, |
d850acf9 LP |
89 | .resource = scif0_resources, |
90 | .num_resources = ARRAY_SIZE(scif0_resources), | |
44658dfb MD |
91 | .dev = { |
92 | .platform_data = &scif0_platform_data, | |
93 | }, | |
94 | }; | |
95 | ||
96 | static struct plat_sci_port scif1_platform_data = { | |
44658dfb | 97 | .flags = UPF_BOOT_AUTOCONF, |
f43dc23d | 98 | .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE, |
44658dfb | 99 | .type = PORT_SCIF, |
61a6976b PM |
100 | .ops = &sh770x_sci_port_ops, |
101 | .regtype = SCIx_SH7705_SCIF_REGTYPE, | |
44658dfb MD |
102 | }; |
103 | ||
d850acf9 LP |
104 | static struct resource scif1_resources[] = { |
105 | DEFINE_RES_MEM(0xa4400000, 0x100), | |
106 | DEFINE_RES_IRQ(evt2irq(0x880)), | |
107 | }; | |
108 | ||
44658dfb MD |
109 | static struct platform_device scif1_device = { |
110 | .name = "sh-sci", | |
111 | .id = 1, | |
d850acf9 LP |
112 | .resource = scif1_resources, |
113 | .num_resources = ARRAY_SIZE(scif1_resources), | |
7dec62e9 | 114 | .dev = { |
44658dfb | 115 | .platform_data = &scif1_platform_data, |
7dec62e9 PM |
116 | }, |
117 | }; | |
118 | ||
70e8be0a MD |
119 | static struct resource rtc_resources[] = { |
120 | [0] = { | |
121 | .start = 0xfffffec0, | |
122 | .end = 0xfffffec0 + 0x1e, | |
123 | .flags = IORESOURCE_IO, | |
124 | }, | |
125 | [1] = { | |
e91b2a40 | 126 | .start = evt2irq(0x480), |
70e8be0a MD |
127 | .flags = IORESOURCE_IRQ, |
128 | }, | |
70e8be0a MD |
129 | }; |
130 | ||
ad89f87a PM |
131 | static struct sh_rtc_platform_info rtc_info = { |
132 | .capabilities = RTC_CAP_4_DIGIT_YEAR, | |
133 | }; | |
134 | ||
70e8be0a MD |
135 | static struct platform_device rtc_device = { |
136 | .name = "sh-rtc", | |
137 | .id = -1, | |
138 | .num_resources = ARRAY_SIZE(rtc_resources), | |
139 | .resource = rtc_resources, | |
ad89f87a PM |
140 | .dev = { |
141 | .platform_data = &rtc_info, | |
142 | }, | |
70e8be0a MD |
143 | }; |
144 | ||
acd664ab | 145 | static struct sh_timer_config tmu0_platform_data = { |
acd664ab MD |
146 | .channel_offset = 0x02, |
147 | .timer_bit = 0, | |
acd664ab MD |
148 | .clockevent_rating = 200, |
149 | }; | |
150 | ||
151 | static struct resource tmu0_resources[] = { | |
152 | [0] = { | |
acd664ab MD |
153 | .start = 0xfffffe94, |
154 | .end = 0xfffffe9f, | |
155 | .flags = IORESOURCE_MEM, | |
156 | }, | |
157 | [1] = { | |
e91b2a40 | 158 | .start = evt2irq(0x400), |
acd664ab MD |
159 | .flags = IORESOURCE_IRQ, |
160 | }, | |
161 | }; | |
162 | ||
163 | static struct platform_device tmu0_device = { | |
164 | .name = "sh_tmu", | |
165 | .id = 0, | |
166 | .dev = { | |
167 | .platform_data = &tmu0_platform_data, | |
168 | }, | |
169 | .resource = tmu0_resources, | |
170 | .num_resources = ARRAY_SIZE(tmu0_resources), | |
171 | }; | |
172 | ||
173 | static struct sh_timer_config tmu1_platform_data = { | |
acd664ab MD |
174 | .channel_offset = 0xe, |
175 | .timer_bit = 1, | |
acd664ab MD |
176 | .clocksource_rating = 200, |
177 | }; | |
178 | ||
179 | static struct resource tmu1_resources[] = { | |
180 | [0] = { | |
acd664ab MD |
181 | .start = 0xfffffea0, |
182 | .end = 0xfffffeab, | |
183 | .flags = IORESOURCE_MEM, | |
184 | }, | |
185 | [1] = { | |
e91b2a40 | 186 | .start = evt2irq(0x420), |
acd664ab MD |
187 | .flags = IORESOURCE_IRQ, |
188 | }, | |
189 | }; | |
190 | ||
191 | static struct platform_device tmu1_device = { | |
192 | .name = "sh_tmu", | |
193 | .id = 1, | |
194 | .dev = { | |
195 | .platform_data = &tmu1_platform_data, | |
196 | }, | |
197 | .resource = tmu1_resources, | |
198 | .num_resources = ARRAY_SIZE(tmu1_resources), | |
199 | }; | |
200 | ||
201 | static struct sh_timer_config tmu2_platform_data = { | |
acd664ab MD |
202 | .channel_offset = 0x1a, |
203 | .timer_bit = 2, | |
acd664ab MD |
204 | }; |
205 | ||
206 | static struct resource tmu2_resources[] = { | |
207 | [0] = { | |
acd664ab MD |
208 | .start = 0xfffffeac, |
209 | .end = 0xfffffebb, | |
210 | .flags = IORESOURCE_MEM, | |
211 | }, | |
212 | [1] = { | |
e91b2a40 | 213 | .start = evt2irq(0x440), |
acd664ab MD |
214 | .flags = IORESOURCE_IRQ, |
215 | }, | |
216 | }; | |
217 | ||
218 | static struct platform_device tmu2_device = { | |
219 | .name = "sh_tmu", | |
220 | .id = 2, | |
221 | .dev = { | |
222 | .platform_data = &tmu2_platform_data, | |
223 | }, | |
224 | .resource = tmu2_resources, | |
225 | .num_resources = ARRAY_SIZE(tmu2_resources), | |
226 | }; | |
227 | ||
7dec62e9 | 228 | static struct platform_device *sh7705_devices[] __initdata = { |
44658dfb MD |
229 | &scif0_device, |
230 | &scif1_device, | |
acd664ab MD |
231 | &tmu0_device, |
232 | &tmu1_device, | |
233 | &tmu2_device, | |
70e8be0a | 234 | &rtc_device, |
7dec62e9 PM |
235 | }; |
236 | ||
237 | static int __init sh7705_devices_setup(void) | |
238 | { | |
239 | return platform_add_devices(sh7705_devices, | |
240 | ARRAY_SIZE(sh7705_devices)); | |
241 | } | |
ba9a6337 | 242 | arch_initcall(sh7705_devices_setup); |
2a8ff459 | 243 | |
acd664ab | 244 | static struct platform_device *sh7705_early_devices[] __initdata = { |
44658dfb MD |
245 | &scif0_device, |
246 | &scif1_device, | |
acd664ab MD |
247 | &tmu0_device, |
248 | &tmu1_device, | |
249 | &tmu2_device, | |
250 | }; | |
251 | ||
252 | void __init plat_early_device_setup(void) | |
253 | { | |
254 | early_platform_add_devices(sh7705_early_devices, | |
255 | ARRAY_SIZE(sh7705_early_devices)); | |
256 | } | |
257 | ||
90015c89 | 258 | void __init plat_irq_setup(void) |
2a8ff459 | 259 | { |
70e8be0a | 260 | register_intc_controller(&intc_desc); |
a276e588 | 261 | plat_irq_setup_sh3(); |
2a8ff459 | 262 | } |