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e5723e0e | 1 | /* |
ac919986 | 2 | * SH3 Setup code for SH7710, SH7712 |
e5723e0e | 3 | * |
56d604de | 4 | * Copyright (C) 2006 - 2009 Paul Mundt |
9465a54f | 5 | * Copyright (C) 2007 Nobuhiro Iwamatsu |
e5723e0e PM |
6 | * |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file "COPYING" in the main directory of this archive | |
9 | * for more details. | |
10 | */ | |
11 | #include <linux/platform_device.h> | |
12 | #include <linux/init.h> | |
28b146c8 | 13 | #include <linux/irq.h> |
e5723e0e | 14 | #include <linux/serial.h> |
96de1a8f | 15 | #include <linux/serial_sci.h> |
e5ad0089 | 16 | #include <linux/sh_timer.h> |
5d0af769 | 17 | #include <linux/sh_intc.h> |
ad89f87a | 18 | #include <asm/rtc.h> |
e5723e0e | 19 | |
28b146c8 MD |
20 | enum { |
21 | UNUSED = 0, | |
22 | ||
23 | /* interrupt sources */ | |
24 | IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, | |
56d604de | 25 | DMAC1, SCIF0, SCIF1, DMAC2, IPSEC, |
28b146c8 | 26 | EDMAC0, EDMAC1, EDMAC2, |
56d604de | 27 | SIOF0, SIOF1, |
28b146c8 | 28 | |
56d604de PM |
29 | TMU0, TMU1, TMU2, |
30 | RTC, WDT, REF, | |
28b146c8 MD |
31 | }; |
32 | ||
5c37e025 | 33 | static struct intc_vect vectors[] __initdata = { |
a276e588 | 34 | /* IRQ0->5 are handled in setup-sh3.c */ |
56d604de PM |
35 | INTC_VECT(DMAC1, 0x800), INTC_VECT(DMAC1, 0x820), |
36 | INTC_VECT(DMAC1, 0x840), INTC_VECT(DMAC1, 0x860), | |
37 | INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0), | |
38 | INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0), | |
39 | INTC_VECT(SCIF1, 0x900), INTC_VECT(SCIF1, 0x920), | |
40 | INTC_VECT(SCIF1, 0x940), INTC_VECT(SCIF1, 0x960), | |
41 | INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0), | |
ac919986 | 42 | #ifdef CONFIG_CPU_SUBTYPE_SH7710 |
28b146c8 | 43 | INTC_VECT(IPSEC, 0xbe0), |
ac919986 | 44 | #endif |
28b146c8 MD |
45 | INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20), |
46 | INTC_VECT(EDMAC2, 0xc40), | |
56d604de PM |
47 | INTC_VECT(SIOF0, 0xe00), INTC_VECT(SIOF0, 0xe20), |
48 | INTC_VECT(SIOF0, 0xe40), INTC_VECT(SIOF0, 0xe60), | |
49 | INTC_VECT(SIOF1, 0xe80), INTC_VECT(SIOF1, 0xea0), | |
50 | INTC_VECT(SIOF1, 0xec0), INTC_VECT(SIOF1, 0xee0), | |
28b146c8 MD |
51 | INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), |
52 | INTC_VECT(TMU2, 0x440), | |
56d604de PM |
53 | INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), |
54 | INTC_VECT(RTC, 0x4c0), | |
28b146c8 MD |
55 | INTC_VECT(WDT, 0x560), |
56 | INTC_VECT(REF, 0x580), | |
57 | }; | |
58 | ||
5c37e025 | 59 | static struct intc_prio_reg prio_registers[] __initdata = { |
6ef5fb2c MD |
60 | { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, |
61 | { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } }, | |
62 | { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, | |
63 | { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } }, | |
64 | { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } }, | |
995d538a | 65 | { 0xa4080000, 0, 16, 4, /* IPRF */ { IPSEC, DMAC2 } }, |
6ef5fb2c MD |
66 | { 0xa4080002, 0, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } }, |
67 | { 0xa4080004, 0, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } }, | |
68 | { 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } }, | |
28b146c8 MD |
69 | }; |
70 | ||
56d604de | 71 | static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, NULL, |
7f3edee8 | 72 | NULL, prio_registers, NULL); |
28b146c8 | 73 | |
28b146c8 MD |
74 | static struct resource rtc_resources[] = { |
75 | [0] = { | |
76 | .start = 0xa413fec0, | |
77 | .end = 0xa413fec0 + 0x1e, | |
78 | .flags = IORESOURCE_IO, | |
79 | }, | |
80 | [1] = { | |
5d0af769 | 81 | .start = evt2irq(0x480), |
28b146c8 MD |
82 | .flags = IORESOURCE_IRQ, |
83 | }, | |
28b146c8 MD |
84 | }; |
85 | ||
ad89f87a PM |
86 | static struct sh_rtc_platform_info rtc_info = { |
87 | .capabilities = RTC_CAP_4_DIGIT_YEAR, | |
88 | }; | |
89 | ||
28b146c8 MD |
90 | static struct platform_device rtc_device = { |
91 | .name = "sh-rtc", | |
92 | .id = -1, | |
93 | .num_resources = ARRAY_SIZE(rtc_resources), | |
94 | .resource = rtc_resources, | |
ad89f87a PM |
95 | .dev = { |
96 | .platform_data = &rtc_info, | |
97 | }, | |
28b146c8 MD |
98 | }; |
99 | ||
44658dfb | 100 | static struct plat_sci_port scif0_platform_data = { |
44658dfb | 101 | .flags = UPF_BOOT_AUTOCONF, |
f43dc23d PM |
102 | .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE | |
103 | SCSCR_CKE1 | SCSCR_CKE0, | |
44658dfb | 104 | .type = PORT_SCIF, |
d850acf9 LP |
105 | }; |
106 | ||
107 | static struct resource scif0_resources[] = { | |
108 | DEFINE_RES_MEM(0xa4400000, 0x100), | |
109 | DEFINE_RES_IRQ(evt2irq(0x880)), | |
44658dfb MD |
110 | }; |
111 | ||
112 | static struct platform_device scif0_device = { | |
e5723e0e | 113 | .name = "sh-sci", |
44658dfb | 114 | .id = 0, |
d850acf9 LP |
115 | .resource = scif0_resources, |
116 | .num_resources = ARRAY_SIZE(scif0_resources), | |
44658dfb MD |
117 | .dev = { |
118 | .platform_data = &scif0_platform_data, | |
119 | }, | |
120 | }; | |
121 | ||
122 | static struct plat_sci_port scif1_platform_data = { | |
44658dfb | 123 | .flags = UPF_BOOT_AUTOCONF, |
f43dc23d PM |
124 | .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE | |
125 | SCSCR_CKE1 | SCSCR_CKE0, | |
44658dfb | 126 | .type = PORT_SCIF, |
d850acf9 LP |
127 | }; |
128 | ||
129 | static struct resource scif1_resources[] = { | |
130 | DEFINE_RES_MEM(0xa4410000, 0x100), | |
131 | DEFINE_RES_IRQ(evt2irq(0x900)), | |
44658dfb MD |
132 | }; |
133 | ||
134 | static struct platform_device scif1_device = { | |
135 | .name = "sh-sci", | |
136 | .id = 1, | |
d850acf9 LP |
137 | .resource = scif1_resources, |
138 | .num_resources = ARRAY_SIZE(scif1_resources), | |
e5723e0e | 139 | .dev = { |
44658dfb | 140 | .platform_data = &scif1_platform_data, |
e5723e0e PM |
141 | }, |
142 | }; | |
143 | ||
e5ad0089 | 144 | static struct sh_timer_config tmu0_platform_data = { |
e5ad0089 MD |
145 | .channel_offset = 0x02, |
146 | .timer_bit = 0, | |
e5ad0089 MD |
147 | .clockevent_rating = 200, |
148 | }; | |
149 | ||
150 | static struct resource tmu0_resources[] = { | |
151 | [0] = { | |
e5ad0089 MD |
152 | .start = 0xa412fe94, |
153 | .end = 0xa412fe9f, | |
154 | .flags = IORESOURCE_MEM, | |
155 | }, | |
156 | [1] = { | |
5d0af769 | 157 | .start = evt2irq(0x400), |
e5ad0089 MD |
158 | .flags = IORESOURCE_IRQ, |
159 | }, | |
160 | }; | |
161 | ||
162 | static struct platform_device tmu0_device = { | |
163 | .name = "sh_tmu", | |
164 | .id = 0, | |
165 | .dev = { | |
166 | .platform_data = &tmu0_platform_data, | |
167 | }, | |
168 | .resource = tmu0_resources, | |
169 | .num_resources = ARRAY_SIZE(tmu0_resources), | |
170 | }; | |
171 | ||
172 | static struct sh_timer_config tmu1_platform_data = { | |
e5ad0089 MD |
173 | .channel_offset = 0xe, |
174 | .timer_bit = 1, | |
e5ad0089 MD |
175 | .clocksource_rating = 200, |
176 | }; | |
177 | ||
178 | static struct resource tmu1_resources[] = { | |
179 | [0] = { | |
e5ad0089 MD |
180 | .start = 0xa412fea0, |
181 | .end = 0xa412feab, | |
182 | .flags = IORESOURCE_MEM, | |
183 | }, | |
184 | [1] = { | |
5d0af769 | 185 | .start = evt2irq(0x420), |
e5ad0089 MD |
186 | .flags = IORESOURCE_IRQ, |
187 | }, | |
188 | }; | |
189 | ||
190 | static struct platform_device tmu1_device = { | |
191 | .name = "sh_tmu", | |
192 | .id = 1, | |
193 | .dev = { | |
194 | .platform_data = &tmu1_platform_data, | |
195 | }, | |
196 | .resource = tmu1_resources, | |
197 | .num_resources = ARRAY_SIZE(tmu1_resources), | |
198 | }; | |
199 | ||
200 | static struct sh_timer_config tmu2_platform_data = { | |
e5ad0089 MD |
201 | .channel_offset = 0x1a, |
202 | .timer_bit = 2, | |
e5ad0089 MD |
203 | }; |
204 | ||
205 | static struct resource tmu2_resources[] = { | |
206 | [0] = { | |
e5ad0089 MD |
207 | .start = 0xa412feac, |
208 | .end = 0xa412feb5, | |
209 | .flags = IORESOURCE_MEM, | |
210 | }, | |
211 | [1] = { | |
5d0af769 | 212 | .start = evt2irq(0x440), |
e5ad0089 MD |
213 | .flags = IORESOURCE_IRQ, |
214 | }, | |
215 | }; | |
216 | ||
217 | static struct platform_device tmu2_device = { | |
218 | .name = "sh_tmu", | |
219 | .id = 2, | |
220 | .dev = { | |
221 | .platform_data = &tmu2_platform_data, | |
222 | }, | |
223 | .resource = tmu2_resources, | |
224 | .num_resources = ARRAY_SIZE(tmu2_resources), | |
225 | }; | |
226 | ||
e5723e0e | 227 | static struct platform_device *sh7710_devices[] __initdata = { |
44658dfb MD |
228 | &scif0_device, |
229 | &scif1_device, | |
e5ad0089 MD |
230 | &tmu0_device, |
231 | &tmu1_device, | |
232 | &tmu2_device, | |
28b146c8 | 233 | &rtc_device, |
e5723e0e PM |
234 | }; |
235 | ||
236 | static int __init sh7710_devices_setup(void) | |
237 | { | |
238 | return platform_add_devices(sh7710_devices, | |
239 | ARRAY_SIZE(sh7710_devices)); | |
240 | } | |
ba9a6337 | 241 | arch_initcall(sh7710_devices_setup); |
9465a54f | 242 | |
e5ad0089 | 243 | static struct platform_device *sh7710_early_devices[] __initdata = { |
44658dfb MD |
244 | &scif0_device, |
245 | &scif1_device, | |
e5ad0089 MD |
246 | &tmu0_device, |
247 | &tmu1_device, | |
248 | &tmu2_device, | |
249 | }; | |
250 | ||
251 | void __init plat_early_device_setup(void) | |
252 | { | |
253 | early_platform_add_devices(sh7710_early_devices, | |
254 | ARRAY_SIZE(sh7710_early_devices)); | |
255 | } | |
256 | ||
90015c89 | 257 | void __init plat_irq_setup(void) |
9465a54f | 258 | { |
28b146c8 | 259 | register_intc_controller(&intc_desc); |
a276e588 | 260 | plat_irq_setup_sh3(); |
9465a54f | 261 | } |