[mirror_ubuntu-zesty-kernel.git] / arch / sh / kernel / cpu / sh4a / setup-sh7366.c

/*
 * SH7366 Setup
 *
 *  Copyright (C) 2008 Renesas Solutions
 *
 * Based on linux/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/serial_sci.h>
#include <linux/uio_driver.h>
#include <linux/sh_timer.h>
#include <linux/sh_intc.h>
#include <linux/usb/r8a66597.h>
#include <asm/clock.h>

static struct plat_sci_port scif0_platform_data = {
	.port_reg	= 0xa405013e,
	.flags		= UPF_BOOT_AUTOCONF,
	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
	.type		= PORT_SCIF,
};

static struct resource scif0_resources[] = {
	DEFINE_RES_MEM(0xffe00000, 0x100),
	DEFINE_RES_IRQ(evt2irq(0xc00)),
};

static struct platform_device scif0_device = {
	.name		= "sh-sci",
	.id		= 0,
	.resource	= scif0_resources,
	.num_resources	= ARRAY_SIZE(scif0_resources),
	.dev		= {
		.platform_data	= &scif0_platform_data,
	},
};

static struct resource iic_resources[] = {
	[0] = {
		.name	= "IIC",
		.start  = 0x04470000,
		.end    = 0x04470017,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = evt2irq(0xe00),
		.end    = evt2irq(0xe60),
		.flags  = IORESOURCE_IRQ,
       },
};

static struct platform_device iic_device = {
	.name           = "i2c-sh_mobile",
	.id             = 0, /* "i2c0" clock */
	.num_resources  = ARRAY_SIZE(iic_resources),
	.resource       = iic_resources,
};

static struct r8a66597_platdata r8a66597_data = {
	.on_chip = 1,
};

static struct resource usb_host_resources[] = {
	[0] = {
		.start  = 0xa4d80000,
		.end    = 0xa4d800ff,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = evt2irq(0xa20),
		.end    = evt2irq(0xa20),
		.flags	= IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
	},
};

static struct platform_device usb_host_device = {
	.name	= "r8a66597_hcd",
	.id	= -1,
	.dev = {
		.dma_mask		= NULL,
		.coherent_dma_mask	= 0xffffffff,
		.platform_data		= &r8a66597_data,
	},
	.num_resources	= ARRAY_SIZE(usb_host_resources),
	.resource	= usb_host_resources,
};

static struct uio_info vpu_platform_data = {
	.name = "VPU5",
	.version = "0",
	.irq = evt2irq(0x980),
};

static struct resource vpu_resources[] = {
	[0] = {
		.name	= "VPU",
		.start	= 0xfe900000,
		.end	= 0xfe902807,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device vpu_device = {
	.name		= "uio_pdrv_genirq",
	.id		= 0,
	.dev = {
		.platform_data	= &vpu_platform_data,
	},
	.resource	= vpu_resources,
	.num_resources	= ARRAY_SIZE(vpu_resources),
};

static struct uio_info veu0_platform_data = {
	.name = "VEU",
	.version = "0",
	.irq = evt2irq(0x8c0),
};

static struct resource veu0_resources[] = {
	[0] = {
		.name	= "VEU(1)",
		.start	= 0xfe920000,
		.end	= 0xfe9200b7,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device veu0_device = {
	.name		= "uio_pdrv_genirq",
	.id		= 1,
	.dev = {
		.platform_data	= &veu0_platform_data,
	},
	.resource	= veu0_resources,
	.num_resources	= ARRAY_SIZE(veu0_resources),
};

static struct uio_info veu1_platform_data = {
	.name = "VEU",
	.version = "0",
	.irq = evt2irq(0x560),
};

static struct resource veu1_resources[] = {
	[0] = {
		.name	= "VEU(2)",
		.start	= 0xfe924000,
		.end	= 0xfe9240b7,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device veu1_device = {
	.name		= "uio_pdrv_genirq",
	.id		= 2,
	.dev = {
		.platform_data	= &veu1_platform_data,
	},
	.resource	= veu1_resources,
	.num_resources	= ARRAY_SIZE(veu1_resources),
};

static struct sh_timer_config cmt_platform_data = {
	.channel_offset = 0x60,
	.timer_bit = 5,
	.clockevent_rating = 125,
	.clocksource_rating = 200,
};

static struct resource cmt_resources[] = {
	[0] = {
		.start	= 0x044a0060,
		.end	= 0x044a006b,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= evt2irq(0xf00),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device cmt_device = {
	.name		= "sh_cmt",
	.id		= 0,
	.dev = {
		.platform_data	= &cmt_platform_data,
	},
	.resource	= cmt_resources,
	.num_resources	= ARRAY_SIZE(cmt_resources),
};

static struct sh_timer_config tmu0_platform_data = {
	.channel_offset = 0x04,
	.timer_bit = 0,
	.clockevent_rating = 200,
};

static struct resource tmu0_resources[] = {
	[0] = {
		.start	= 0xffd80008,
		.end	= 0xffd80013,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 16,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu0_device = {
	.name		= "sh_tmu",
	.id		= 0,
	.dev = {
		.platform_data	= &tmu0_platform_data,
	},
	.resource	= tmu0_resources,
	.num_resources	= ARRAY_SIZE(tmu0_resources),
};

static struct sh_timer_config tmu1_platform_data = {
	.channel_offset = 0x10,
	.timer_bit = 1,
	.clocksource_rating = 200,
};

static struct resource tmu1_resources[] = {
	[0] = {
		.start	= 0xffd80014,
		.end	= 0xffd8001f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= evt2irq(0x420),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu1_device = {
	.name		= "sh_tmu",
	.id		= 1,
	.dev = {
		.platform_data	= &tmu1_platform_data,
	},
	.resource	= tmu1_resources,
	.num_resources	= ARRAY_SIZE(tmu1_resources),
};

static struct sh_timer_config tmu2_platform_data = {
	.channel_offset = 0x1c,
	.timer_bit = 2,
};

static struct resource tmu2_resources[] = {
	[0] = {
		.start	= 0xffd80020,
		.end	= 0xffd8002b,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= evt2irq(0x440),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu2_device = {
	.name		= "sh_tmu",
	.id		= 2,
	.dev = {
		.platform_data	= &tmu2_platform_data,
	},
	.resource	= tmu2_resources,
	.num_resources	= ARRAY_SIZE(tmu2_resources),
};

static struct platform_device *sh7366_devices[] __initdata = {
	&scif0_device,
	&cmt_device,
	&tmu0_device,
	&tmu1_device,
	&tmu2_device,
	&iic_device,
	&usb_host_device,
	&vpu_device,
	&veu0_device,
	&veu1_device,
};

static int __init sh7366_devices_setup(void)
{
	platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
	platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
	platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);

	return platform_add_devices(sh7366_devices,
				    ARRAY_SIZE(sh7366_devices));
}
arch_initcall(sh7366_devices_setup);

static struct platform_device *sh7366_early_devices[] __initdata = {
	&scif0_device,
	&cmt_device,
	&tmu0_device,
	&tmu1_device,
	&tmu2_device,
};

void __init plat_early_device_setup(void)
{
	early_platform_add_devices(sh7366_early_devices,
				   ARRAY_SIZE(sh7366_early_devices));
}

enum {
	UNUSED=0,
	ENABLED,
	DISABLED,

	/* interrupt sources */
	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	ICB,
	DMAC0, DMAC1, DMAC2, DMAC3,
	VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
	MFI, VPU, USB,
	MMC_MMC1I, MMC_MMC2I, MMC_MMC3I,
	DMAC4, DMAC5, DMAC_DADERR,
	SCIF, SCIFA1, SCIFA2,
	DENC, MSIOF,
	FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
	I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
	SDHI, CMT, TSIF, SIU,
	TMU0, TMU1, TMU2,
	VEU2, LCDC,

	/* interrupt groups */

	DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C,
};

static struct intc_vect vectors[] __initdata = {
	INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
	INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
	INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
	INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
	INTC_VECT(ICB, 0x700),
	INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
	INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
	INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
	INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
	INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980), INTC_VECT(USB, 0xa20),
	INTC_VECT(MMC_MMC1I, 0xb00), INTC_VECT(MMC_MMC2I, 0xb20),
	INTC_VECT(MMC_MMC3I, 0xb40),
	INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
	INTC_VECT(DMAC_DADERR, 0xbc0),
	INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIFA1, 0xc20),
	INTC_VECT(SCIFA2, 0xc40),
	INTC_VECT(DENC, 0xc60), INTC_VECT(MSIOF, 0xc80),
	INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
	INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
	INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
	INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
	INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
	INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
	INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
	INTC_VECT(SIU, 0xf80),
	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
	INTC_VECT(TMU2, 0x440),
	INTC_VECT(VEU2, 0x560), INTC_VECT(LCDC, 0x580),
};

static struct intc_group groups[] __initdata = {
	INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
	INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
	INTC_GROUP(MMC, MMC_MMC1I, MMC_MMC2I, MMC_MMC3I),
	INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
	INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
		   FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
	INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
};

static struct intc_mask_reg mask_registers[] __initdata = {
	{ 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
	  { } },
	{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
	  { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
	{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
	  { 0, 0, 0, VPU, 0, 0, 0, MFI } },
	{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
	  { 0, 0, 0, ICB } },
	{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
	  { 0, TMU2, TMU1, TMU0, VEU2, 0, 0, LCDC } },
	{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
	  { 0, DMAC_DADERR, DMAC5, DMAC4, DENC, SCIFA2, SCIFA1, SCIF } },
	{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
	  { 0, 0, 0, 0, 0, 0, 0, MSIOF } },
	{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
	  { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
	    FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
	{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
	  { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, 0, SIU } },
	{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
	  { 0, 0, 0, CMT, 0, USB, } },
	{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
	  { 0, MMC_MMC3I, MMC_MMC2I, MMC_MMC1I } },
	{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
	  { 0, 0, 0, 0, 0, 0, 0, TSIF } },
	{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_prio_reg prio_registers[] __initdata = {
	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
	{ 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2, LCDC, ICB } },
	{ 0xa4080008, 0, 16, 4, /* IPRC */ { } },
	{ 0xa408000c, 0, 16, 4, /* IPRD */ { } },
	{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
	{ 0xa4080014, 0, 16, 4, /* IPRF */ { 0, DMAC45, USB, CMT } },
	{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIFA1, SCIFA2, DENC } },
	{ 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF, 0, FLCTL, I2C } },
	{ 0xa4080020, 0, 16, 4, /* IPRI */ { 0, 0, TSIF, } },
	{ 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
	{ 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
	{ 0xa408002c, 0, 16, 4, /* IPRL */ { } },
	{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_sense_reg sense_registers[] __initdata = {
	{ 0xa414001c, 16, 2, /* ICR1 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_mask_reg ack_registers[] __initdata = {
	{ 0xa4140024, 0, 8, /* INTREQ00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_desc intc_desc __initdata = {
	.name = "sh7366",
	.force_enable = ENABLED,
	.force_disable = DISABLED,
	.hw = INTC_HW_DESC(vectors, groups, mask_registers,
			   prio_registers, sense_registers, ack_registers),
};

void __init plat_irq_setup(void)
{
	register_intc_controller(&intc_desc);
}

void __init plat_mem_setup(void)
{
	/* TODO: Register Node 1 */
}
Commit	Line	Data
9109a30e MD	1	/*
	2	* SH7366 Setup
	3	*
	4	* Copyright (C) 2008 Renesas Solutions
	5	*
	6	* Based on linux/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
	7	*
	8	* This file is subject to the terms and conditions of the GNU General Public
	9	* License. See the file "COPYING" in the main directory of this archive
	10	* for more details.
	11	*/
	12	#include <linux/platform_device.h>
	13	#include <linux/init.h>
	14	#include <linux/serial.h>
96de1a8f	15	#include <linux/serial_sci.h>
714750dd	16	#include <linux/uio_driver.h>
46a12f74	17	#include <linux/sh_timer.h>
58749400	18	#include <linux/sh_intc.h>
6b64929c	19	#include <linux/usb/r8a66597.h>
d7f1a9ad	20	#include <asm/clock.h>
9109a30e	21
bcac24d0	22	static struct plat_sci_port scif0_platform_data = {
61a6976b	23	.port_reg = 0xa405013e,
bcac24d0	24	.flags = UPF_BOOT_AUTOCONF,
f43dc23d	25	.scscr = SCSCR_RE \| SCSCR_TE \| SCSCR_REIE,
bcac24d0	26	.type = PORT_SCIF,
d850acf9 LP	27	};
	28
	29	static struct resource scif0_resources[] = {
	30	DEFINE_RES_MEM(0xffe00000, 0x100),
	31	DEFINE_RES_IRQ(evt2irq(0xc00)),
bcac24d0 MD	32	};
	33
	34	static struct platform_device scif0_device = {
	35	.name = "sh-sci",
	36	.id = 0,
d850acf9 LP	37	.resource = scif0_resources,
d850acf9 LP	38	.num_resources = ARRAY_SIZE(scif0_resources),
bcac24d0 MD	39	.dev = {
	40	.platform_data = &scif0_platform_data,
	41	},
	42	};
	43
0fff76f2 MD	44	static struct resource iic_resources[] = {
	45	[0] = {
	46	.name = "IIC",
	47	.start = 0x04470000,
	48	.end = 0x04470017,
	49	.flags = IORESOURCE_MEM,
	50	},
	51	[1] = {
58749400 PM	52	.start = evt2irq(0xe00),
58749400 PM	53	.end = evt2irq(0xe60),
0fff76f2 MD	54	.flags = IORESOURCE_IRQ,
	55	},
	56	};
	57
	58	static struct platform_device iic_device = {
	59	.name = "i2c-sh_mobile",
a5616bd0	60	.id = 0, /* "i2c0" clock */
0fff76f2 MD	61	.num_resources = ARRAY_SIZE(iic_resources),
	62	.resource = iic_resources,
	63	};
	64
6b64929c	65	static struct r8a66597_platdata r8a66597_data = {
719a72b7	66	.on_chip = 1,
6b64929c YS	67	};
6b64929c YS	68
47c2968c KM	69	static struct resource usb_host_resources[] = {
47c2968c KM	70	[0] = {
47c2968c KM	71	.start = 0xa4d80000,
	72	.end = 0xa4d800ff,
	73	.flags = IORESOURCE_MEM,
	74	},
	75	[1] = {
58749400 PM	76	.start = evt2irq(0xa20),
58749400 PM	77	.end = evt2irq(0xa20),
6b64929c	78	.flags = IORESOURCE_IRQ \| IRQF_TRIGGER_LOW,
47c2968c KM	79	},
	80	};
	81
	82	static struct platform_device usb_host_device = {
	83	.name = "r8a66597_hcd",
	84	.id = -1,
	85	.dev = {
	86	.dma_mask = NULL,
	87	.coherent_dma_mask = 0xffffffff,
6b64929c	88	.platform_data = &r8a66597_data,
47c2968c KM	89	},
	90	.num_resources = ARRAY_SIZE(usb_host_resources),
	91	.resource = usb_host_resources,
	92	};
	93
714750dd MD	94	static struct uio_info vpu_platform_data = {
	95	.name = "VPU5",
	96	.version = "0",
58749400	97	.irq = evt2irq(0x980),
714750dd MD	98	};
	99
	100	static struct resource vpu_resources[] = {
	101	[0] = {
	102	.name = "VPU",
	103	.start = 0xfe900000,
	104	.end = 0xfe902807,
	105	.flags = IORESOURCE_MEM,
	106	},
1eca5c92 MD	107	[1] = {
	108	/* place holder for contiguous memory */
	109	},
714750dd MD	110	};
	111
	112	static struct platform_device vpu_device = {
	113	.name = "uio_pdrv_genirq",
	114	.id = 0,
	115	.dev = {
	116	.platform_data = &vpu_platform_data,
	117	},
	118	.resource = vpu_resources,
	119	.num_resources = ARRAY_SIZE(vpu_resources),
	120	};
	121
	122	static struct uio_info veu0_platform_data = {
	123	.name = "VEU",
	124	.version = "0",
58749400	125	.irq = evt2irq(0x8c0),
714750dd MD	126	};
	127
	128	static struct resource veu0_resources[] = {
	129	[0] = {
	130	.name = "VEU(1)",
	131	.start = 0xfe920000,
	132	.end = 0xfe9200b7,
	133	.flags = IORESOURCE_MEM,
	134	},
1eca5c92 MD	135	[1] = {
	136	/* place holder for contiguous memory */
	137	},
714750dd MD	138	};
	139
	140	static struct platform_device veu0_device = {
	141	.name = "uio_pdrv_genirq",
	142	.id = 1,
	143	.dev = {
	144	.platform_data = &veu0_platform_data,
	145	},
	146	.resource = veu0_resources,
	147	.num_resources = ARRAY_SIZE(veu0_resources),
	148	};
	149
	150	static struct uio_info veu1_platform_data = {
	151	.name = "VEU",
	152	.version = "0",
58749400	153	.irq = evt2irq(0x560),
714750dd MD	154	};
	155
	156	static struct resource veu1_resources[] = {
	157	[0] = {
	158	.name = "VEU(2)",
	159	.start = 0xfe924000,
	160	.end = 0xfe9240b7,
	161	.flags = IORESOURCE_MEM,
	162	},
1eca5c92 MD	163	[1] = {
	164	/* place holder for contiguous memory */
	165	},
714750dd MD	166	};
	167
	168	static struct platform_device veu1_device = {
	169	.name = "uio_pdrv_genirq",
	170	.id = 2,
	171	.dev = {
	172	.platform_data = &veu1_platform_data,
	173	},
	174	.resource = veu1_resources,
	175	.num_resources = ARRAY_SIZE(veu1_resources),
	176	};
	177
46a12f74	178	static struct sh_timer_config cmt_platform_data = {
424f59d0 MD	179	.channel_offset = 0x60,
424f59d0 MD	180	.timer_bit = 5,
424f59d0 MD	181	.clockevent_rating = 125,
	182	.clocksource_rating = 200,
	183	};
	184
	185	static struct resource cmt_resources[] = {
	186	[0] = {
424f59d0 MD	187	.start = 0x044a0060,
	188	.end = 0x044a006b,
	189	.flags = IORESOURCE_MEM,
	190	},
	191	[1] = {
58749400	192	.start = evt2irq(0xf00),
424f59d0 MD	193	.flags = IORESOURCE_IRQ,
	194	},
	195	};
	196
	197	static struct platform_device cmt_device = {
	198	.name = "sh_cmt",
	199	.id = 0,
	200	.dev = {
	201	.platform_data = &cmt_platform_data,
	202	},
	203	.resource = cmt_resources,
	204	.num_resources = ARRAY_SIZE(cmt_resources),
	205	};
	206
f2710ebc	207	static struct sh_timer_config tmu0_platform_data = {
f2710ebc MD	208	.channel_offset = 0x04,
f2710ebc MD	209	.timer_bit = 0,
f2710ebc MD	210	.clockevent_rating = 200,
	211	};
	212
	213	static struct resource tmu0_resources[] = {
	214	[0] = {
f2710ebc MD	215	.start = 0xffd80008,
	216	.end = 0xffd80013,
	217	.flags = IORESOURCE_MEM,
	218	},
	219	[1] = {
	220	.start = 16,
	221	.flags = IORESOURCE_IRQ,
	222	},
	223	};
	224
	225	static struct platform_device tmu0_device = {
	226	.name = "sh_tmu",
	227	.id = 0,
	228	.dev = {
	229	.platform_data = &tmu0_platform_data,
	230	},
	231	.resource = tmu0_resources,
	232	.num_resources = ARRAY_SIZE(tmu0_resources),
	233	};
	234
	235	static struct sh_timer_config tmu1_platform_data = {
f2710ebc MD	236	.channel_offset = 0x10,
f2710ebc MD	237	.timer_bit = 1,
f2710ebc MD	238	.clocksource_rating = 200,
	239	};
	240
	241	static struct resource tmu1_resources[] = {
	242	[0] = {
f2710ebc MD	243	.start = 0xffd80014,
	244	.end = 0xffd8001f,
	245	.flags = IORESOURCE_MEM,
	246	},
	247	[1] = {
58749400	248	.start = evt2irq(0x420),
f2710ebc MD	249	.flags = IORESOURCE_IRQ,
	250	},
	251	};
	252
	253	static struct platform_device tmu1_device = {
	254	.name = "sh_tmu",
	255	.id = 1,
	256	.dev = {
	257	.platform_data = &tmu1_platform_data,
	258	},
	259	.resource = tmu1_resources,
	260	.num_resources = ARRAY_SIZE(tmu1_resources),
	261	};
	262
	263	static struct sh_timer_config tmu2_platform_data = {
f2710ebc MD	264	.channel_offset = 0x1c,
f2710ebc MD	265	.timer_bit = 2,
f2710ebc MD	266	};
	267
	268	static struct resource tmu2_resources[] = {
	269	[0] = {
f2710ebc MD	270	.start = 0xffd80020,
	271	.end = 0xffd8002b,
	272	.flags = IORESOURCE_MEM,
	273	},
	274	[1] = {
58749400	275	.start = evt2irq(0x440),
f2710ebc MD	276	.flags = IORESOURCE_IRQ,
	277	},
	278	};
	279
	280	static struct platform_device tmu2_device = {
	281	.name = "sh_tmu",
	282	.id = 2,
	283	.dev = {
	284	.platform_data = &tmu2_platform_data,
	285	},
	286	.resource = tmu2_resources,
	287	.num_resources = ARRAY_SIZE(tmu2_resources),
	288	};
	289
9109a30e	290	static struct platform_device *sh7366_devices[] __initdata = {
bcac24d0	291	&scif0_device,
424f59d0	292	&cmt_device,
f2710ebc MD	293	&tmu0_device,
	294	&tmu1_device,
	295	&tmu2_device,
0fff76f2	296	&iic_device,
47c2968c	297	&usb_host_device,
714750dd MD	298	&vpu_device,
	299	&veu0_device,
	300	&veu1_device,
9109a30e MD	301	};
	302
	303	static int __init sh7366_devices_setup(void)
	304	{
1eca5c92 MD	305	platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
	306	platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
	307	platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
d7f1a9ad	308
9109a30e MD	309	return platform_add_devices(sh7366_devices,
	310	ARRAY_SIZE(sh7366_devices));
	311	}
955c9863	312	arch_initcall(sh7366_devices_setup);
9109a30e	313
28fde686	314	static struct platform_device *sh7366_early_devices[] __initdata = {
bcac24d0	315	&scif0_device,
28fde686	316	&cmt_device,
f2710ebc MD	317	&tmu0_device,
	318	&tmu1_device,
	319	&tmu2_device,
28fde686 MD	320	};
	321
	322	void __init plat_early_device_setup(void)
	323	{
	324	early_platform_add_devices(sh7366_early_devices,
	325	ARRAY_SIZE(sh7366_early_devices));
	326	}
	327
9109a30e MD	328	enum {
9109a30e MD	329	UNUSED=0,
9bbe7b98 MD	330	ENABLED,
9bbe7b98 MD	331	DISABLED,
9109a30e MD	332
	333	/* interrupt sources */
	334	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	335	ICB,
	336	DMAC0, DMAC1, DMAC2, DMAC3,
	337	VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
	338	MFI, VPU, USB,
	339	MMC_MMC1I, MMC_MMC2I, MMC_MMC3I,
	340	DMAC4, DMAC5, DMAC_DADERR,
	341	SCIF, SCIFA1, SCIFA2,
	342	DENC, MSIOF,
	343	FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
	344	I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
9bbe7b98	345	SDHI, CMT, TSIF, SIU,
9109a30e MD	346	TMU0, TMU1, TMU2,
	347	VEU2, LCDC,
	348
	349	/* interrupt groups */
	350
9bbe7b98	351	DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C,
9109a30e MD	352	};
	353
	354	static struct intc_vect vectors[] __initdata = {
	355	INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
	356	INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
	357	INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
	358	INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
	359	INTC_VECT(ICB, 0x700),
	360	INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
	361	INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
	362	INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
	363	INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
	364	INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980), INTC_VECT(USB, 0xa20),
	365	INTC_VECT(MMC_MMC1I, 0xb00), INTC_VECT(MMC_MMC2I, 0xb20),
	366	INTC_VECT(MMC_MMC3I, 0xb40),
	367	INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
	368	INTC_VECT(DMAC_DADERR, 0xbc0),
	369	INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIFA1, 0xc20),
	370	INTC_VECT(SCIFA2, 0xc40),
	371	INTC_VECT(DENC, 0xc60), INTC_VECT(MSIOF, 0xc80),
	372	INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
	373	INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
	374	INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
	375	INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
9bbe7b98 MD	376	INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
9bbe7b98 MD	377	INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
9109a30e MD	378	INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
	379	INTC_VECT(SIU, 0xf80),
	380	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
	381	INTC_VECT(TMU2, 0x440),
714750dd	382	INTC_VECT(VEU2, 0x560), INTC_VECT(LCDC, 0x580),
9109a30e MD	383	};
	384
	385	static struct intc_group groups[] __initdata = {
	386	INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
	387	INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
	388	INTC_GROUP(MMC, MMC_MMC1I, MMC_MMC2I, MMC_MMC3I),
	389	INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
	390	INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
	391	FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
	392	INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
9109a30e MD	393	};
	394
	395	static struct intc_mask_reg mask_registers[] __initdata = {
	396	{ 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
	397	{ } },
	398	{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
	399	{ VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
	400	{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
	401	{ 0, 0, 0, VPU, 0, 0, 0, MFI } },
	402	{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
	403	{ 0, 0, 0, ICB } },
	404	{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
	405	{ 0, TMU2, TMU1, TMU0, VEU2, 0, 0, LCDC } },
	406	{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
	407	{ 0, DMAC_DADERR, DMAC5, DMAC4, DENC, SCIFA2, SCIFA1, SCIF } },
	408	{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
	409	{ 0, 0, 0, 0, 0, 0, 0, MSIOF } },
	410	{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
	411	{ I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
	412	FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
	413	{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
9bbe7b98	414	{ DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, 0, SIU } },
9109a30e MD	415	{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
	416	{ 0, 0, 0, CMT, 0, USB, } },
	417	{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
	418	{ 0, MMC_MMC3I, MMC_MMC2I, MMC_MMC1I } },
	419	{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
	420	{ 0, 0, 0, 0, 0, 0, 0, TSIF } },
	421	{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
	422	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	423	};
	424
	425	static struct intc_prio_reg prio_registers[] __initdata = {
	426	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
	427	{ 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2, LCDC, ICB } },
	428	{ 0xa4080008, 0, 16, 4, /* IPRC */ { } },
	429	{ 0xa408000c, 0, 16, 4, /* IPRD */ { } },
	430	{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
	431	{ 0xa4080014, 0, 16, 4, /* IPRF */ { 0, DMAC45, USB, CMT } },
	432	{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIFA1, SCIFA2, DENC } },
	433	{ 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF, 0, FLCTL, I2C } },
	434	{ 0xa4080020, 0, 16, 4, /* IPRI */ { 0, 0, TSIF, } },
	435	{ 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
	436	{ 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
	437	{ 0xa408002c, 0, 16, 4, /* IPRL */ { } },
	438	{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
	439	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	440	};
	441
	442	static struct intc_sense_reg sense_registers[] __initdata = {
	443	{ 0xa414001c, 16, 2, /* ICR1 */
	444	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	445	};
	446
6bdfb22a YS	447	static struct intc_mask_reg ack_registers[] __initdata = {
	448	{ 0xa4140024, 0, 8, /* INTREQ00 */
	449	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	450	};
	451
9bbe7b98 MD	452	static struct intc_desc intc_desc __initdata = {
	453	.name = "sh7366",
	454	.force_enable = ENABLED,
	455	.force_disable = DISABLED,
	456	.hw = INTC_HW_DESC(vectors, groups, mask_registers,
	457	prio_registers, sense_registers, ack_registers),
	458	};
9109a30e MD	459
	460	void __init plat_irq_setup(void)
	461	{
	462	register_intc_controller(&intc_desc);
	463	}
	464
	465	void __init plat_mem_setup(void)
	466	{
	467	/* TODO: Register Node 1 */
	468	}