[mirror_ubuntu-bionic-kernel.git] / arch / sparc / kernel / setup_64.c

// SPDX-License-Identifier: GPL-2.0
/*
 *  linux/arch/sparc64/kernel/setup.c
 *
 *  Copyright (C) 1995,1996  David S. Miller (davem@caip.rutgers.edu)
 *  Copyright (C) 1997       Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 */

#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/stddef.h>
#include <linux/unistd.h>
#include <linux/ptrace.h>
#include <asm/smp.h>
#include <linux/user.h>
#include <linux/screen_info.h>
#include <linux/delay.h>
#include <linux/fs.h>
#include <linux/seq_file.h>
#include <linux/syscalls.h>
#include <linux/kdev_t.h>
#include <linux/major.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/inet.h>
#include <linux/console.h>
#include <linux/root_dev.h>
#include <linux/interrupt.h>
#include <linux/cpu.h>
#include <linux/initrd.h>
#include <linux/module.h>
#include <linux/start_kernel.h>
#include <linux/bootmem.h>

#include <asm/io.h>
#include <asm/processor.h>
#include <asm/oplib.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/idprom.h>
#include <asm/head.h>
#include <asm/starfire.h>
#include <asm/mmu_context.h>
#include <asm/timer.h>
#include <asm/sections.h>
#include <asm/setup.h>
#include <asm/mmu.h>
#include <asm/ns87303.h>
#include <asm/btext.h>
#include <asm/elf.h>
#include <asm/mdesc.h>
#include <asm/cacheflush.h>
#include <asm/dma.h>
#include <asm/irq.h>

#ifdef CONFIG_IP_PNP
#include <net/ipconfig.h>
#endif

#include "entry.h"
#include "kernel.h"

/* Used to synchronize accesses to NatSemi SUPER I/O chip configure
 * operations in asm/ns87303.h
 */
DEFINE_SPINLOCK(ns87303_lock);
EXPORT_SYMBOL(ns87303_lock);

struct screen_info screen_info = {
	0, 0,			/* orig-x, orig-y */
	0,			/* unused */
	0,			/* orig-video-page */
	0,			/* orig-video-mode */
	128,			/* orig-video-cols */
	0, 0, 0,		/* unused, ega_bx, unused */
	54,			/* orig-video-lines */
	0,                      /* orig-video-isVGA */
	16                      /* orig-video-points */
};

static void
prom_console_write(struct console *con, const char *s, unsigned int n)
{
	prom_write(s, n);
}

/* Exported for mm/init.c:paging_init. */
unsigned long cmdline_memory_size = 0;

static struct console prom_early_console = {
	.name =		"earlyprom",
	.write =	prom_console_write,
	.flags =	CON_PRINTBUFFER | CON_BOOT | CON_ANYTIME,
	.index =	-1,
};

/*
 * Process kernel command line switches that are specific to the
 * SPARC or that require special low-level processing.
 */
static void __init process_switch(char c)
{
	switch (c) {
	case 'd':
	case 's':
		break;
	case 'h':
		prom_printf("boot_flags_init: Halt!\n");
		prom_halt();
		break;
	case 'p':
		prom_early_console.flags &= ~CON_BOOT;
		break;
	case 'P':
		/* Force UltraSPARC-III P-Cache on. */
		if (tlb_type != cheetah) {
			printk("BOOT: Ignoring P-Cache force option.\n");
			break;
		}
		cheetah_pcache_forced_on = 1;
		add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
		cheetah_enable_pcache();
		break;

	default:
		printk("Unknown boot switch (-%c)\n", c);
		break;
	}
}

static void __init boot_flags_init(char *commands)
{
	while (*commands) {
		/* Move to the start of the next "argument". */
		while (*commands == ' ')
			commands++;

		/* Process any command switches, otherwise skip it. */
		if (*commands == '\0')
			break;
		if (*commands == '-') {
			commands++;
			while (*commands && *commands != ' ')
				process_switch(*commands++);
			continue;
		}
		if (!strncmp(commands, "mem=", 4))
			cmdline_memory_size = memparse(commands + 4, &commands);

		while (*commands && *commands != ' ')
			commands++;
	}
}

extern unsigned short root_flags;
extern unsigned short root_dev;
extern unsigned short ram_flags;
#define RAMDISK_IMAGE_START_MASK	0x07FF
#define RAMDISK_PROMPT_FLAG		0x8000
#define RAMDISK_LOAD_FLAG		0x4000

extern int root_mountflags;

char reboot_command[COMMAND_LINE_SIZE];

static struct pt_regs fake_swapper_regs = { { 0, }, 0, 0, 0, 0 };

static void __init per_cpu_patch(void)
{
	struct cpuid_patch_entry *p;
	unsigned long ver;
	int is_jbus;

	if (tlb_type == spitfire && !this_is_starfire)
		return;

	is_jbus = 0;
	if (tlb_type != hypervisor) {
		__asm__ ("rdpr %%ver, %0" : "=r" (ver));
		is_jbus = ((ver >> 32UL) == __JALAPENO_ID ||
			   (ver >> 32UL) == __SERRANO_ID);
	}

	p = &__cpuid_patch;
	while (p < &__cpuid_patch_end) {
		unsigned long addr = p->addr;
		unsigned int *insns;

		switch (tlb_type) {
		case spitfire:
			insns = &p->starfire[0];
			break;
		case cheetah:
		case cheetah_plus:
			if (is_jbus)
				insns = &p->cheetah_jbus[0];
			else
				insns = &p->cheetah_safari[0];
			break;
		case hypervisor:
			insns = &p->sun4v[0];
			break;
		default:
			prom_printf("Unknown cpu type, halting.\n");
			prom_halt();
		}

		*(unsigned int *) (addr +  0) = insns[0];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  0));

		*(unsigned int *) (addr +  4) = insns[1];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  4));

		*(unsigned int *) (addr +  8) = insns[2];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  8));

		*(unsigned int *) (addr + 12) = insns[3];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr + 12));

		p++;
	}
}

void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *start,
			     struct sun4v_1insn_patch_entry *end)
{
	while (start < end) {
		unsigned long addr = start->addr;

		*(unsigned int *) (addr +  0) = start->insn;
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  0));

		start++;
	}
}

void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
			     struct sun4v_2insn_patch_entry *end)
{
	while (start < end) {
		unsigned long addr = start->addr;

		*(unsigned int *) (addr +  0) = start->insns[0];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  0));

		*(unsigned int *) (addr +  4) = start->insns[1];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  4));

		start++;
	}
}

void sun_m7_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
			     struct sun4v_2insn_patch_entry *end)
{
	while (start < end) {
		unsigned long addr = start->addr;

		*(unsigned int *) (addr +  0) = start->insns[0];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  0));

		*(unsigned int *) (addr +  4) = start->insns[1];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  4));

		start++;
	}
}

static void __init sun4v_patch(void)
{
	extern void sun4v_hvapi_init(void);

	if (tlb_type != hypervisor)
		return;

	sun4v_patch_1insn_range(&__sun4v_1insn_patch,
				&__sun4v_1insn_patch_end);

	sun4v_patch_2insn_range(&__sun4v_2insn_patch,
				&__sun4v_2insn_patch_end);

	switch (sun4v_chip_type) {
	case SUN4V_CHIP_SPARC_M7:
	case SUN4V_CHIP_SPARC_M8:
	case SUN4V_CHIP_SPARC_SN:
		sun_m7_patch_2insn_range(&__sun_m7_2insn_patch,
					 &__sun_m7_2insn_patch_end);
		break;
	default:
		break;
	}

	if (sun4v_chip_type != SUN4V_CHIP_NIAGARA1) {
		sun4v_patch_1insn_range(&__fast_win_ctrl_1insn_patch,
					&__fast_win_ctrl_1insn_patch_end);
	}

	sun4v_hvapi_init();
}

static void __init popc_patch(void)
{
	struct popc_3insn_patch_entry *p3;
	struct popc_6insn_patch_entry *p6;

	p3 = &__popc_3insn_patch;
	while (p3 < &__popc_3insn_patch_end) {
		unsigned long i, addr = p3->addr;

		for (i = 0; i < 3; i++) {
			*(unsigned int *) (addr +  (i * 4)) = p3->insns[i];
			wmb();
			__asm__ __volatile__("flush	%0"
					     : : "r" (addr +  (i * 4)));
		}

		p3++;
	}

	p6 = &__popc_6insn_patch;
	while (p6 < &__popc_6insn_patch_end) {
		unsigned long i, addr = p6->addr;

		for (i = 0; i < 6; i++) {
			*(unsigned int *) (addr +  (i * 4)) = p6->insns[i];
			wmb();
			__asm__ __volatile__("flush	%0"
					     : : "r" (addr +  (i * 4)));
		}

		p6++;
	}
}

static void __init pause_patch(void)
{
	struct pause_patch_entry *p;

	p = &__pause_3insn_patch;
	while (p < &__pause_3insn_patch_end) {
		unsigned long i, addr = p->addr;

		for (i = 0; i < 3; i++) {
			*(unsigned int *) (addr +  (i * 4)) = p->insns[i];
			wmb();
			__asm__ __volatile__("flush	%0"
					     : : "r" (addr +  (i * 4)));
		}

		p++;
	}
}

void __init start_early_boot(void)
{
	int cpu;

	check_if_starfire();
	per_cpu_patch();
	sun4v_patch();
	smp_init_cpu_poke();

	cpu = hard_smp_processor_id();
	if (cpu >= NR_CPUS) {
		prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n",
			    cpu, NR_CPUS);
		prom_halt();
	}
	current_thread_info()->cpu = cpu;

	time_init_early();
	prom_init_report();
	start_kernel();
}

/* On Ultra, we support all of the v8 capabilities. */
unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR |
				   HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV |
				   HWCAP_SPARC_V9);
EXPORT_SYMBOL(sparc64_elf_hwcap);

static const char *hwcaps[] = {
	"flush", "stbar", "swap", "muldiv", "v9",
	"ultra3", "blkinit", "n2",

	/* These strings are as they appear in the machine description
	 * 'hwcap-list' property for cpu nodes.
	 */
	"mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2",
	"ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau",
	"ima", "cspare", "pause", "cbcond", NULL /*reserved for crypto */,
	"adp",
};

static const char *crypto_hwcaps[] = {
	"aes", "des", "kasumi", "camellia", "md5", "sha1", "sha256",
	"sha512", "mpmul", "montmul", "montsqr", "crc32c",
};

void cpucap_info(struct seq_file *m)
{
	unsigned long caps = sparc64_elf_hwcap;
	int i, printed = 0;

	seq_puts(m, "cpucaps\t\t: ");
	for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
		unsigned long bit = 1UL << i;
		if (hwcaps[i] && (caps & bit)) {
			seq_printf(m, "%s%s",
				   printed ? "," : "", hwcaps[i]);
			printed++;
		}
	}
	if (caps & HWCAP_SPARC_CRYPTO) {
		unsigned long cfr;

		__asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
		for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
			unsigned long bit = 1UL << i;
			if (cfr & bit) {
				seq_printf(m, "%s%s",
					   printed ? "," : "", crypto_hwcaps[i]);
				printed++;
			}
		}
	}
	seq_putc(m, '\n');
}

static void __init report_one_hwcap(int *printed, const char *name)
{
	if ((*printed) == 0)
		printk(KERN_INFO "CPU CAPS: [");
	printk(KERN_CONT "%s%s",
	       (*printed) ? "," : "", name);
	if (++(*printed) == 8) {
		printk(KERN_CONT "]\n");
		*printed = 0;
	}
}

static void __init report_crypto_hwcaps(int *printed)
{
	unsigned long cfr;
	int i;

	__asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));

	for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
		unsigned long bit = 1UL << i;
		if (cfr & bit)
			report_one_hwcap(printed, crypto_hwcaps[i]);
	}
}

static void __init report_hwcaps(unsigned long caps)
{
	int i, printed = 0;

	for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
		unsigned long bit = 1UL << i;
		if (hwcaps[i] && (caps & bit))
			report_one_hwcap(&printed, hwcaps[i]);
	}
	if (caps & HWCAP_SPARC_CRYPTO)
		report_crypto_hwcaps(&printed);
	if (printed != 0)
		printk(KERN_CONT "]\n");
}

static unsigned long __init mdesc_cpu_hwcap_list(void)
{
	struct mdesc_handle *hp;
	unsigned long caps = 0;
	const char *prop;
	int len;
	u64 pn;

	hp = mdesc_grab();
	if (!hp)
		return 0;

	pn = mdesc_node_by_name(hp, MDESC_NODE_NULL, "cpu");
	if (pn == MDESC_NODE_NULL)
		goto out;

	prop = mdesc_get_property(hp, pn, "hwcap-list", &len);
	if (!prop)
		goto out;

	while (len) {
		int i, plen;

		for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
			unsigned long bit = 1UL << i;

			if (hwcaps[i] && !strcmp(prop, hwcaps[i])) {
				caps |= bit;
				break;
			}
		}
		for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
			if (!strcmp(prop, crypto_hwcaps[i]))
				caps |= HWCAP_SPARC_CRYPTO;
		}

		plen = strlen(prop) + 1;
		prop += plen;
		len -= plen;
	}

out:
	mdesc_release(hp);
	return caps;
}

/* This yields a mask that user programs can use to figure out what
 * instruction set this cpu supports.
 */
static void __init init_sparc64_elf_hwcap(void)
{
	unsigned long cap = sparc64_elf_hwcap;
	unsigned long mdesc_caps;

	if (tlb_type == cheetah || tlb_type == cheetah_plus)
		cap |= HWCAP_SPARC_ULTRA3;
	else if (tlb_type == hypervisor) {
		if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC64X)
			cap |= HWCAP_SPARC_BLKINIT;
		if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC64X)
			cap |= HWCAP_SPARC_N2;
	}

	cap |= (AV_SPARC_MUL32 | AV_SPARC_DIV32 | AV_SPARC_V8PLUS);

	mdesc_caps = mdesc_cpu_hwcap_list();
	if (!mdesc_caps) {
		if (tlb_type == spitfire)
			cap |= AV_SPARC_VIS;
		if (tlb_type == cheetah || tlb_type == cheetah_plus)
			cap |= AV_SPARC_VIS | AV_SPARC_VIS2;
		if (tlb_type == cheetah_plus) {
			unsigned long impl, ver;

			__asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
			impl = ((ver >> 32) & 0xffff);
			if (impl == PANTHER_IMPL)
				cap |= AV_SPARC_POPC;
		}
		if (tlb_type == hypervisor) {
			if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1)
				cap |= AV_SPARC_ASI_BLK_INIT;
			if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
			    sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
			    sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
			    sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC64X)
				cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
					AV_SPARC_ASI_BLK_INIT |
					AV_SPARC_POPC);
			if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
			    sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
			    sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC64X)
				cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
					AV_SPARC_FMAF);
		}
	}
	sparc64_elf_hwcap = cap | mdesc_caps;

	report_hwcaps(sparc64_elf_hwcap);

	if (sparc64_elf_hwcap & AV_SPARC_POPC)
		popc_patch();
	if (sparc64_elf_hwcap & AV_SPARC_PAUSE)
		pause_patch();
}

void __init alloc_irqstack_bootmem(void)
{
	unsigned int i, node;

	for_each_possible_cpu(i) {
		node = cpu_to_node(i);

		softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
							THREAD_SIZE,
							THREAD_SIZE, 0);
		hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
							THREAD_SIZE,
							THREAD_SIZE, 0);
	}
}

void __init setup_arch(char **cmdline_p)
{
	/* Initialize PROM console and command line. */
	*cmdline_p = prom_getbootargs();
	strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
	parse_early_param();

	boot_flags_init(*cmdline_p);
#ifdef CONFIG_EARLYFB
	if (btext_find_display())
#endif
		register_console(&prom_early_console);

	if (tlb_type == hypervisor)
		printk("ARCH: SUN4V\n");
	else
		printk("ARCH: SUN4U\n");

#ifdef CONFIG_DUMMY_CONSOLE
	conswitchp = &dummy_con;
#endif

	idprom_init();

	if (!root_flags)
		root_mountflags &= ~MS_RDONLY;
	ROOT_DEV = old_decode_dev(root_dev);
#ifdef CONFIG_BLK_DEV_RAM
	rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK;
	rd_prompt = ((ram_flags & RAMDISK_PROMPT_FLAG) != 0);
	rd_doload = ((ram_flags & RAMDISK_LOAD_FLAG) != 0);
#endif

	task_thread_info(&init_task)->kregs = &fake_swapper_regs;

#ifdef CONFIG_IP_PNP
	if (!ic_set_manually) {
		phandle chosen = prom_finddevice("/chosen");
		u32 cl, sv, gw;

		cl = prom_getintdefault (chosen, "client-ip", 0);
		sv = prom_getintdefault (chosen, "server-ip", 0);
		gw = prom_getintdefault (chosen, "gateway-ip", 0);
		if (cl && sv) {
			ic_myaddr = cl;
			ic_servaddr = sv;
			if (gw)
				ic_gateway = gw;
#if defined(CONFIG_IP_PNP_BOOTP) || defined(CONFIG_IP_PNP_RARP)
			ic_proto_enabled = 0;
#endif
		}
	}
#endif

	/* Get boot processor trap_block[] setup.  */
	init_cur_cpu_trap(current_thread_info());

	paging_init();
	init_sparc64_elf_hwcap();
	smp_fill_in_cpu_possible_map();
	/*
	 * Once the OF device tree and MDESC have been setup and nr_cpus has
	 * been parsed, we know the list of possible cpus.  Therefore we can
	 * allocate the IRQ stacks.
	 */
	alloc_irqstack_bootmem();
}

extern int stop_a_enabled;

void sun_do_break(void)
{
	if (!stop_a_enabled)
		return;

	prom_printf("\n");
	flush_user_windows();

	prom_cmdline();
}
EXPORT_SYMBOL(sun_do_break);

int stop_a_enabled = 1;
EXPORT_SYMBOL(stop_a_enabled);
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
b00dc837	2	/*
1da177e4 LT	3	* linux/arch/sparc64/kernel/setup.c
	4	*
	5	* Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
	6	* Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
	7	*/
	8
	9	#include <linux/errno.h>
	10	#include <linux/sched.h>
	11	#include <linux/kernel.h>
	12	#include <linux/mm.h>
	13	#include <linux/stddef.h>
	14	#include <linux/unistd.h>
	15	#include <linux/ptrace.h>
1da177e4 LT	16	#include <asm/smp.h>
1da177e4 LT	17	#include <linux/user.h>
894673ee	18	#include <linux/screen_info.h>
1da177e4	19	#include <linux/delay.h>
1da177e4 LT	20	#include <linux/fs.h>
	21	#include <linux/seq_file.h>
	22	#include <linux/syscalls.h>
	23	#include <linux/kdev_t.h>
	24	#include <linux/major.h>
	25	#include <linux/string.h>
	26	#include <linux/init.h>
	27	#include <linux/inet.h>
	28	#include <linux/console.h>
	29	#include <linux/root_dev.h>
	30	#include <linux/interrupt.h>
	31	#include <linux/cpu.h>
	32	#include <linux/initrd.h>
ac85fe8b	33	#include <linux/module.h>
ef3e035c	34	#include <linux/start_kernel.h>
ebb99a4c	35	#include <linux/bootmem.h>
1da177e4	36
1da177e4 LT	37	#include <asm/io.h>
	38	#include <asm/processor.h>
	39	#include <asm/oplib.h>
	40	#include <asm/page.h>
	41	#include <asm/pgtable.h>
	42	#include <asm/idprom.h>
	43	#include <asm/head.h>
	44	#include <asm/starfire.h>
	45	#include <asm/mmu_context.h>
	46	#include <asm/timer.h>
	47	#include <asm/sections.h>
	48	#include <asm/setup.h>
	49	#include <asm/mmu.h>
5cbc3073	50	#include <asm/ns87303.h>
c57ec52f	51	#include <asm/btext.h>
ac85fe8b DM	52	#include <asm/elf.h>
ac85fe8b DM	53	#include <asm/mdesc.h>
d550bbd4	54	#include <asm/cacheflush.h>
ebb99a4c AP	55	#include <asm/dma.h>
ebb99a4c AP	56	#include <asm/irq.h>
1da177e4 LT	57
	58	#ifdef CONFIG_IP_PNP
	59	#include <net/ipconfig.h>
	60	#endif
	61
3d5ae6b6	62	#include "entry.h"
53ae3419	63	#include "kernel.h"
3d5ae6b6	64
5cbc3073 DM	65	/* Used to synchronize accesses to NatSemi SUPER I/O chip configure
	66	* operations in asm/ns87303.h
	67	*/
	68	DEFINE_SPINLOCK(ns87303_lock);
917c3660	69	EXPORT_SYMBOL(ns87303_lock);
5cbc3073	70
1da177e4 LT	71	struct screen_info screen_info = {
	72	0, 0, /* orig-x, orig-y */
	73	0, /* unused */
	74	0, /* orig-video-page */
	75	0, /* orig-video-mode */
	76	128, /* orig-video-cols */
	77	0, 0, 0, /* unused, ega_bx, unused */
	78	54, /* orig-video-lines */
	79	0, /* orig-video-isVGA */
	80	16 /* orig-video-points */
	81	};
	82
1da177e4	83	static void
9ef595d8	84	prom_console_write(struct console con, const char s, unsigned int n)
1da177e4 LT	85	{
	86	prom_write(s, n);
	87	}
	88
1da177e4 LT	89	/* Exported for mm/init.c:paging_init. */
	90	unsigned long cmdline_memory_size = 0;
	91
3c62a2d3 DM	92	static struct console prom_early_console = {
3c62a2d3 DM	93	.name = "earlyprom",
1da177e4	94	.write = prom_console_write,
db9a7fb1	95	.flags = CON_PRINTBUFFER \| CON_BOOT \| CON_ANYTIME,
1da177e4 LT	96	.index = -1,
	97	};
	98
68a79217	99	/*
1da177e4 LT	100	* Process kernel command line switches that are specific to the
	101	* SPARC or that require special low-level processing.
	102	*/
	103	static void __init process_switch(char c)
	104	{
	105	switch (c) {
	106	case 'd':
1da177e4	107	case 's':
1da177e4 LT	108	break;
	109	case 'h':
	110	prom_printf("boot_flags_init: Halt!\n");
	111	prom_halt();
	112	break;
	113	case 'p':
11032c17	114	prom_early_console.flags &= ~CON_BOOT;
1da177e4	115	break;
816242da DM	116	case 'P':
	117	/* Force UltraSPARC-III P-Cache on. */
	118	if (tlb_type != cheetah) {
	119	printk("BOOT: Ignoring P-Cache force option.\n");
	120	break;
	121	}
	122	cheetah_pcache_forced_on = 1;
373d4d09	123	add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
816242da DM	124	cheetah_enable_pcache();
	125	break;
	126
1da177e4 LT	127	default:
	128	printk("Unknown boot switch (-%c)\n", c);
	129	break;
	130	}
	131	}
	132
1da177e4 LT	133	static void __init boot_flags_init(char *commands)
	134	{
	135	while (*commands) {
	136	/* Move to the start of the next "argument". */
8c64415c	137	while (*commands == ' ')
1da177e4 LT	138	commands++;
	139
	140	/* Process any command switches, otherwise skip it. */
	141	if (*commands == '\0')
	142	break;
	143	if (*commands == '-') {
	144	commands++;
	145	while (commands && commands != ' ')
	146	process_switch(*commands++);
	147	continue;
	148	}
7c21d533	149	if (!strncmp(commands, "mem=", 4))
	150	cmdline_memory_size = memparse(commands + 4, &commands);
	151
1da177e4 LT	152	while (commands && commands != ' ')
	153	commands++;
	154	}
	155	}
	156
1da177e4 LT	157	extern unsigned short root_flags;
	158	extern unsigned short root_dev;
	159	extern unsigned short ram_flags;
	160	#define RAMDISK_IMAGE_START_MASK 0x07FF
	161	#define RAMDISK_PROMPT_FLAG 0x8000
	162	#define RAMDISK_LOAD_FLAG 0x4000
	163
	164	extern int root_mountflags;
	165
	166	char reboot_command[COMMAND_LINE_SIZE];
	167
	168	static struct pt_regs fake_swapper_regs = { { 0, }, 0, 0, 0, 0 };
	169
ef3e035c	170	static void __init per_cpu_patch(void)
92704a1c	171	{
92704a1c DM	172	struct cpuid_patch_entry *p;
	173	unsigned long ver;
	174	int is_jbus;
	175
	176	if (tlb_type == spitfire && !this_is_starfire)
	177	return;
	178
d82ace7d DM	179	is_jbus = 0;
	180	if (tlb_type != hypervisor) {
	181	__asm__ ("rdpr %%ver, %0" : "=r" (ver));
ebd8c56c DM	182	is_jbus = ((ver >> 32UL) == __JALAPENO_ID \|\|
ebd8c56c DM	183	(ver >> 32UL) == __SERRANO_ID);
d82ace7d	184	}
92704a1c DM	185
	186	p = &__cpuid_patch;
	187	while (p < &__cpuid_patch_end) {
	188	unsigned long addr = p->addr;
	189	unsigned int *insns;
	190
	191	switch (tlb_type) {
	192	case spitfire:
	193	insns = &p->starfire[0];
	194	break;
	195	case cheetah:
	196	case cheetah_plus:
	197	if (is_jbus)
	198	insns = &p->cheetah_jbus[0];
	199	else
	200	insns = &p->cheetah_safari[0];
	201	break;
d96b8153 DM	202	case hypervisor:
	203	insns = &p->sun4v[0];
	204	break;
92704a1c DM	205	default:
	206	prom_printf("Unknown cpu type, halting.\n");
	207	prom_halt();
6cb79b3f	208	}
92704a1c DM	209
92704a1c DM	210	(unsigned int ) (addr + 0) = insns[0];
840aaef8	211	wmb();
92704a1c DM	212	__asm__ __volatile__("flush %0" : : "r" (addr + 0));
	213
	214	(unsigned int ) (addr + 4) = insns[1];
840aaef8	215	wmb();
92704a1c DM	216	__asm__ __volatile__("flush %0" : : "r" (addr + 4));
	217
	218	(unsigned int ) (addr + 8) = insns[2];
840aaef8	219	wmb();
92704a1c DM	220	__asm__ __volatile__("flush %0" : : "r" (addr + 8));
	221
	222	(unsigned int ) (addr + 12) = insns[3];
840aaef8	223	wmb();
92704a1c DM	224	__asm__ __volatile__("flush %0" : : "r" (addr + 12));
	225
	226	p++;
	227	}
92704a1c DM	228	}
92704a1c DM	229
0b64120c DM	230	void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *start,
0b64120c DM	231	struct sun4v_1insn_patch_entry *end)
936f482a	232	{
0b64120c DM	233	while (start < end) {
0b64120c DM	234	unsigned long addr = start->addr;
936f482a	235
0b64120c	236	(unsigned int ) (addr + 0) = start->insn;
840aaef8	237	wmb();
936f482a DM	238	__asm__ __volatile__("flush %0" : : "r" (addr + 0));
936f482a DM	239
0b64120c	240	start++;
45fec05f	241	}
0b64120c	242	}
45fec05f	243
0b64120c DM	244	void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
	245	struct sun4v_2insn_patch_entry *end)
	246	{
	247	while (start < end) {
	248	unsigned long addr = start->addr;
45fec05f	249
0b64120c	250	(unsigned int ) (addr + 0) = start->insns[0];
840aaef8	251	wmb();
45fec05f DM	252	__asm__ __volatile__("flush %0" : : "r" (addr + 0));
45fec05f DM	253
0b64120c	254	(unsigned int ) (addr + 4) = start->insns[1];
840aaef8	255	wmb();
45fec05f DM	256	__asm__ __volatile__("flush %0" : : "r" (addr + 4));
45fec05f DM	257
0b64120c	258	start++;
936f482a	259	}
0b64120c DM	260	}
0b64120c DM	261
494e5b6f KA	262	void sun_m7_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
	263	struct sun4v_2insn_patch_entry *end)
	264	{
	265	while (start < end) {
	266	unsigned long addr = start->addr;
	267
	268	(unsigned int ) (addr + 0) = start->insns[0];
	269	wmb();
	270	__asm__ __volatile__("flush %0" : : "r" (addr + 0));
	271
	272	(unsigned int ) (addr + 4) = start->insns[1];
	273	wmb();
	274	__asm__ __volatile__("flush %0" : : "r" (addr + 4));
	275
	276	start++;
	277	}
	278	}
	279
ef3e035c	280	static void __init sun4v_patch(void)
0b64120c DM	281	{
	282	extern void sun4v_hvapi_init(void);
	283
	284	if (tlb_type != hypervisor)
	285	return;
	286
	287	sun4v_patch_1insn_range(&__sun4v_1insn_patch,
	288	&__sun4v_1insn_patch_end);
	289
	290	sun4v_patch_2insn_range(&__sun4v_2insn_patch,
	291	&__sun4v_2insn_patch_end);
7d484acb AP	292
	293	switch (sun4v_chip_type) {
	294	case SUN4V_CHIP_SPARC_M7:
	295	case SUN4V_CHIP_SPARC_M8:
	296	case SUN4V_CHIP_SPARC_SN:
494e5b6f KA	297	sun_m7_patch_2insn_range(&__sun_m7_2insn_patch,
494e5b6f KA	298	&__sun_m7_2insn_patch_end);
7d484acb AP	299	break;
	300	default:
	301	break;
	302	}
c7754d46	303
a7159a87 AY	304	if (sun4v_chip_type != SUN4V_CHIP_NIAGARA1) {
	305	sun4v_patch_1insn_range(&__fast_win_ctrl_1insn_patch,
	306	&__fast_win_ctrl_1insn_patch_end);
	307	}
	308
c7754d46	309	sun4v_hvapi_init();
936f482a DM	310	}
936f482a DM	311
ef7c4d46 DM	312	static void __init popc_patch(void)
	313	{
	314	struct popc_3insn_patch_entry *p3;
56d205cc	315	struct popc_6insn_patch_entry *p6;
ef7c4d46 DM	316
	317	p3 = &__popc_3insn_patch;
	318	while (p3 < &__popc_3insn_patch_end) {
56d205cc	319	unsigned long i, addr = p3->addr;
ef7c4d46	320
56d205cc DM	321	for (i = 0; i < 3; i++) {
	322	(unsigned int ) (addr + (i * 4)) = p3->insns[i];
	323	wmb();
	324	__asm__ __volatile__("flush %0"
	325	: : "r" (addr + (i * 4)));
	326	}
ef7c4d46	327
56d205cc DM	328	p3++;
56d205cc DM	329	}
ef7c4d46	330
56d205cc DM	331	p6 = &__popc_6insn_patch;
	332	while (p6 < &__popc_6insn_patch_end) {
	333	unsigned long i, addr = p6->addr;
ef7c4d46	334
56d205cc DM	335	for (i = 0; i < 6; i++) {
	336	(unsigned int ) (addr + (i * 4)) = p6->insns[i];
	337	wmb();
	338	__asm__ __volatile__("flush %0"
	339	: : "r" (addr + (i * 4)));
	340	}
	341
	342	p6++;
ef7c4d46 DM	343	}
	344	}
	345
e9b9eb59 DM	346	static void __init pause_patch(void)
	347	{
	348	struct pause_patch_entry *p;
	349
187818cd DM	350	p = &__pause_3insn_patch;
187818cd DM	351	while (p < &__pause_3insn_patch_end) {
e9b9eb59 DM	352	unsigned long i, addr = p->addr;
	353
	354	for (i = 0; i < 3; i++) {
	355	(unsigned int ) (addr + (i * 4)) = p->insns[i];
	356	wmb();
	357	__asm__ __volatile__("flush %0"
	358	: : "r" (addr + (i * 4)));
	359	}
	360
	361	p++;
	362	}
	363	}
	364
ef3e035c	365	void __init start_early_boot(void)
951bc82c	366	{
ef3e035c DM	367	int cpu;
	368
	369	check_if_starfire();
	370	per_cpu_patch();
	371	sun4v_patch();
8536e02e	372	smp_init_cpu_poke();
ef3e035c DM	373
	374	cpu = hard_smp_processor_id();
	375	if (cpu >= NR_CPUS) {
	376	prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n",
	377	cpu, NR_CPUS);
	378	prom_halt();
	379	}
	380	current_thread_info()->cpu = cpu;
	381
83e8eb99	382	time_init_early();
ef3e035c DM	383	prom_init_report();
ef3e035c DM	384	start_kernel();
951bc82c	385	}
951bc82c	386
ac85fe8b DM	387	/* On Ultra, we support all of the v8 capabilities. */
	388	unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH \| HWCAP_SPARC_STBAR \|
	389	HWCAP_SPARC_SWAP \| HWCAP_SPARC_MULDIV \|
	390	HWCAP_SPARC_V9);
	391	EXPORT_SYMBOL(sparc64_elf_hwcap);
	392
	393	static const char *hwcaps[] = {
	394	"flush", "stbar", "swap", "muldiv", "v9",
	395	"ultra3", "blkinit", "n2",
	396
	397	/* These strings are as they appear in the machine description
	398	* 'hwcap-list' property for cpu nodes.
	399	*/
	400	"mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2",
	401	"ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau",
82924e54 KA	402	"ima", "cspare", "pause", "cbcond", NULL /reserved for crypto /,
82924e54 KA	403	"adp",
6f859c0e DM	404	};
	405
	406	static const char *crypto_hwcaps[] = {
	407	"aes", "des", "kasumi", "camellia", "md5", "sha1", "sha256",
	408	"sha512", "mpmul", "montmul", "montsqr", "crc32c",
ac85fe8b DM	409	};
	410
	411	void cpucap_info(struct seq_file *m)
	412	{
	413	unsigned long caps = sparc64_elf_hwcap;
	414	int i, printed = 0;
	415
	416	seq_puts(m, "cpucaps\t\t: ");
	417	for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
	418	unsigned long bit = 1UL << i;
82924e54	419	if (hwcaps[i] && (caps & bit)) {
ac85fe8b DM	420	seq_printf(m, "%s%s",
	421	printed ? "," : "", hwcaps[i]);
	422	printed++;
	423	}
	424	}
6f859c0e DM	425	if (caps & HWCAP_SPARC_CRYPTO) {
	426	unsigned long cfr;
	427
	428	__asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
	429	for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
	430	unsigned long bit = 1UL << i;
	431	if (cfr & bit) {
	432	seq_printf(m, "%s%s",
	433	printed ? "," : "", crypto_hwcaps[i]);
	434	printed++;
	435	}
	436	}
	437	}
ac85fe8b DM	438	seq_putc(m, '\n');
	439	}
	440
6f859c0e DM	441	static void __init report_one_hwcap(int printed, const char name)
	442	{
	443	if ((*printed) == 0)
	444	printk(KERN_INFO "CPU CAPS: [");
	445	printk(KERN_CONT "%s%s",
	446	(*printed) ? "," : "", name);
	447	if (++(*printed) == 8) {
	448	printk(KERN_CONT "]\n");
	449	*printed = 0;
	450	}
	451	}
	452
	453	static void __init report_crypto_hwcaps(int *printed)
	454	{
	455	unsigned long cfr;
	456	int i;
	457
	458	__asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
	459
	460	for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
	461	unsigned long bit = 1UL << i;
	462	if (cfr & bit)
	463	report_one_hwcap(printed, crypto_hwcaps[i]);
	464	}
	465	}
	466
ac85fe8b DM	467	static void __init report_hwcaps(unsigned long caps)
	468	{
	469	int i, printed = 0;
	470
ac85fe8b DM	471	for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
ac85fe8b DM	472	unsigned long bit = 1UL << i;
82924e54	473	if (hwcaps[i] && (caps & bit))
6f859c0e	474	report_one_hwcap(&printed, hwcaps[i]);
ac85fe8b	475	}
6f859c0e DM	476	if (caps & HWCAP_SPARC_CRYPTO)
	477	report_crypto_hwcaps(&printed);
	478	if (printed != 0)
	479	printk(KERN_CONT "]\n");
ac85fe8b DM	480	}
	481
	482	static unsigned long __init mdesc_cpu_hwcap_list(void)
	483	{
	484	struct mdesc_handle *hp;
	485	unsigned long caps = 0;
	486	const char *prop;
	487	int len;
	488	u64 pn;
	489
	490	hp = mdesc_grab();
	491	if (!hp)
	492	return 0;
	493
	494	pn = mdesc_node_by_name(hp, MDESC_NODE_NULL, "cpu");
	495	if (pn == MDESC_NODE_NULL)
	496	goto out;
	497
	498	prop = mdesc_get_property(hp, pn, "hwcap-list", &len);
	499	if (!prop)
	500	goto out;
	501
	502	while (len) {
	503	int i, plen;
	504
	505	for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
	506	unsigned long bit = 1UL << i;
	507
82924e54	508	if (hwcaps[i] && !strcmp(prop, hwcaps[i])) {
ac85fe8b DM	509	caps \|= bit;
	510	break;
	511	}
	512	}
6f859c0e DM	513	for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
	514	if (!strcmp(prop, crypto_hwcaps[i]))
	515	caps \|= HWCAP_SPARC_CRYPTO;
	516	}
ac85fe8b DM	517
	518	plen = strlen(prop) + 1;
	519	prop += plen;
	520	len -= plen;
	521	}
	522
	523	out:
	524	mdesc_release(hp);
	525	return caps;
	526	}
	527
	528	/* This yields a mask that user programs can use to figure out what
	529	* instruction set this cpu supports.
	530	*/
	531	static void __init init_sparc64_elf_hwcap(void)
	532	{
	533	unsigned long cap = sparc64_elf_hwcap;
	534	unsigned long mdesc_caps;
	535
	536	if (tlb_type == cheetah \|\| tlb_type == cheetah_plus)
	537	cap \|= HWCAP_SPARC_ULTRA3;
	538	else if (tlb_type == hypervisor) {
	539	if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 \|\|
	540	sun4v_chip_type == SUN4V_CHIP_NIAGARA2 \|\|
08cefa9f DM	541	sun4v_chip_type == SUN4V_CHIP_NIAGARA3 \|\|
08cefa9f DM	542	sun4v_chip_type == SUN4V_CHIP_NIAGARA4 \|\|
4e963779	543	sun4v_chip_type == SUN4V_CHIP_NIAGARA5 \|\|
40831625 AP	544	sun4v_chip_type == SUN4V_CHIP_SPARC_M6 \|\|
40831625 AP	545	sun4v_chip_type == SUN4V_CHIP_SPARC_M7 \|\|
7d484acb	546	sun4v_chip_type == SUN4V_CHIP_SPARC_M8 \|\|
c5b8b5be	547	sun4v_chip_type == SUN4V_CHIP_SPARC_SN \|\|
4e963779	548	sun4v_chip_type == SUN4V_CHIP_SPARC64X)
ac85fe8b DM	549	cap \|= HWCAP_SPARC_BLKINIT;
ac85fe8b DM	550	if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 \|\|
08cefa9f DM	551	sun4v_chip_type == SUN4V_CHIP_NIAGARA3 \|\|
08cefa9f DM	552	sun4v_chip_type == SUN4V_CHIP_NIAGARA4 \|\|
4e963779	553	sun4v_chip_type == SUN4V_CHIP_NIAGARA5 \|\|
40831625 AP	554	sun4v_chip_type == SUN4V_CHIP_SPARC_M6 \|\|
40831625 AP	555	sun4v_chip_type == SUN4V_CHIP_SPARC_M7 \|\|
7d484acb	556	sun4v_chip_type == SUN4V_CHIP_SPARC_M8 \|\|
c5b8b5be	557	sun4v_chip_type == SUN4V_CHIP_SPARC_SN \|\|
4e963779	558	sun4v_chip_type == SUN4V_CHIP_SPARC64X)
ac85fe8b DM	559	cap \|= HWCAP_SPARC_N2;
	560	}
	561
	562	cap \|= (AV_SPARC_MUL32 \| AV_SPARC_DIV32 \| AV_SPARC_V8PLUS);
	563
	564	mdesc_caps = mdesc_cpu_hwcap_list();
	565	if (!mdesc_caps) {
	566	if (tlb_type == spitfire)
	567	cap \|= AV_SPARC_VIS;
	568	if (tlb_type == cheetah \|\| tlb_type == cheetah_plus)
	569	cap \|= AV_SPARC_VIS \| AV_SPARC_VIS2;
1a8e0da5 DM	570	if (tlb_type == cheetah_plus) {
	571	unsigned long impl, ver;
	572
	573	__asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
	574	impl = ((ver >> 32) & 0xffff);
	575	if (impl == PANTHER_IMPL)
	576	cap \|= AV_SPARC_POPC;
	577	}
ac85fe8b DM	578	if (tlb_type == hypervisor) {
	579	if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1)
	580	cap \|= AV_SPARC_ASI_BLK_INIT;
	581	if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 \|\|
08cefa9f DM	582	sun4v_chip_type == SUN4V_CHIP_NIAGARA3 \|\|
08cefa9f DM	583	sun4v_chip_type == SUN4V_CHIP_NIAGARA4 \|\|
4e963779	584	sun4v_chip_type == SUN4V_CHIP_NIAGARA5 \|\|
40831625 AP	585	sun4v_chip_type == SUN4V_CHIP_SPARC_M6 \|\|
40831625 AP	586	sun4v_chip_type == SUN4V_CHIP_SPARC_M7 \|\|
7d484acb	587	sun4v_chip_type == SUN4V_CHIP_SPARC_M8 \|\|
c5b8b5be	588	sun4v_chip_type == SUN4V_CHIP_SPARC_SN \|\|
4e963779	589	sun4v_chip_type == SUN4V_CHIP_SPARC64X)
ac85fe8b DM	590	cap \|= (AV_SPARC_VIS \| AV_SPARC_VIS2 \|
	591	AV_SPARC_ASI_BLK_INIT \|
	592	AV_SPARC_POPC);
08cefa9f DM	593	if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 \|\|
08cefa9f DM	594	sun4v_chip_type == SUN4V_CHIP_NIAGARA4 \|\|
4e963779	595	sun4v_chip_type == SUN4V_CHIP_NIAGARA5 \|\|
40831625 AP	596	sun4v_chip_type == SUN4V_CHIP_SPARC_M6 \|\|
40831625 AP	597	sun4v_chip_type == SUN4V_CHIP_SPARC_M7 \|\|
7d484acb	598	sun4v_chip_type == SUN4V_CHIP_SPARC_M8 \|\|
c5b8b5be	599	sun4v_chip_type == SUN4V_CHIP_SPARC_SN \|\|
4e963779	600	sun4v_chip_type == SUN4V_CHIP_SPARC64X)
ac85fe8b DM	601	cap \|= (AV_SPARC_VIS3 \| AV_SPARC_HPC \|
	602	AV_SPARC_FMAF);
	603	}
	604	}
	605	sparc64_elf_hwcap = cap \| mdesc_caps;
	606
	607	report_hwcaps(sparc64_elf_hwcap);
ef7c4d46 DM	608
	609	if (sparc64_elf_hwcap & AV_SPARC_POPC)
	610	popc_patch();
e9b9eb59 DM	611	if (sparc64_elf_hwcap & AV_SPARC_PAUSE)
e9b9eb59 DM	612	pause_patch();
ac85fe8b DM	613	}
ac85fe8b DM	614
ebb99a4c AP	615	void __init alloc_irqstack_bootmem(void)
	616	{
	617	unsigned int i, node;
	618
	619	for_each_possible_cpu(i) {
	620	node = cpu_to_node(i);
	621
	622	softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
	623	THREAD_SIZE,
	624	THREAD_SIZE, 0);
	625	hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
	626	THREAD_SIZE,
	627	THREAD_SIZE, 0);
	628	}
	629	}
	630
1da177e4 LT	631	void __init setup_arch(char **cmdline_p)
1da177e4 LT	632	{
1da177e4 LT	633	/* Initialize PROM console and command line. */
1da177e4 LT	634	*cmdline_p = prom_getbootargs();
117a0c5f	635	strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
ce3b1d47	636	parse_early_param();
1da177e4	637
3c62a2d3	638	boot_flags_init(*cmdline_p);
c57ec52f DM	639	#ifdef CONFIG_EARLYFB
	640	if (btext_find_display())
	641	#endif
	642	register_console(&prom_early_console);
3c62a2d3	643
3a8c069d DM	644	if (tlb_type == hypervisor)
	645	printk("ARCH: SUN4V\n");
	646	else
	647	printk("ARCH: SUN4U\n");
1da177e4 LT	648
	649	#ifdef CONFIG_DUMMY_CONSOLE
	650	conswitchp = &dummy_con;
1da177e4 LT	651	#endif
1da177e4 LT	652
1da177e4	653	idprom_init();
1da177e4 LT	654
	655	if (!root_flags)
	656	root_mountflags &= ~MS_RDONLY;
	657	ROOT_DEV = old_decode_dev(root_dev);
467418f3	658	#ifdef CONFIG_BLK_DEV_RAM
1da177e4 LT	659	rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK;
1da177e4 LT	660	rd_prompt = ((ram_flags & RAMDISK_PROMPT_FLAG) != 0);
68a79217	661	rd_doload = ((ram_flags & RAMDISK_LOAD_FLAG) != 0);
1da177e4 LT	662	#endif
1da177e4 LT	663
f3169641	664	task_thread_info(&init_task)->kregs = &fake_swapper_regs;
1da177e4 LT	665
	666	#ifdef CONFIG_IP_PNP
	667	if (!ic_set_manually) {
8d125562	668	phandle chosen = prom_finddevice("/chosen");
1da177e4	669	u32 cl, sv, gw;
68a79217	670
1da177e4 LT	671	cl = prom_getintdefault (chosen, "client-ip", 0);
	672	sv = prom_getintdefault (chosen, "server-ip", 0);
	673	gw = prom_getintdefault (chosen, "gateway-ip", 0);
	674	if (cl && sv) {
	675	ic_myaddr = cl;
	676	ic_servaddr = sv;
	677	if (gw)
	678	ic_gateway = gw;
	679	#if defined(CONFIG_IP_PNP_BOOTP) \|\| defined(CONFIG_IP_PNP_RARP)
	680	ic_proto_enabled = 0;
	681	#endif
	682	}
	683	}
	684	#endif
	685
56fb4df6	686	/* Get boot processor trap_block[] setup. */
72aff53f	687	init_cur_cpu_trap(current_thread_info());
52845cdb DM	688
52845cdb DM	689	paging_init();
ac85fe8b	690	init_sparc64_elf_hwcap();
9b2f753e	691	smp_fill_in_cpu_possible_map();
ebb99a4c AP	692	/*
	693	* Once the OF device tree and MDESC have been setup and nr_cpus has
	694	* been parsed, we know the list of possible cpus. Therefore we can
	695	* allocate the IRQ stacks.
	696	*/
	697	alloc_irqstack_bootmem();
1da177e4 LT	698	}
1da177e4 LT	699
1da177e4 LT	700	extern int stop_a_enabled;
	701
	702	void sun_do_break(void)
	703	{
	704	if (!stop_a_enabled)
	705	return;
	706
	707	prom_printf("\n");
	708	flush_user_windows();
	709
	710	prom_cmdline();
	711	}
917c3660	712	EXPORT_SYMBOL(sun_do_break);
1da177e4	713
1da177e4	714	int stop_a_enabled = 1;
917c3660	715	EXPORT_SYMBOL(stop_a_enabled);