[mirror_ubuntu-artful-kernel.git] / arch / sparc / kernel / tsb.S

/* tsb.S: Sparc64 TSB table handling.
 *
 * Copyright (C) 2006 David S. Miller <davem@davemloft.net>
 */


#include <asm/tsb.h>
#include <asm/hypervisor.h>
#include <asm/page.h>
#include <asm/cpudata.h>
#include <asm/mmu.h>

	.text
	.align	32

	/* Invoked from TLB miss handler, we are in the
	 * MMU global registers and they are setup like
	 * this:
	 *
	 * %g1: TSB entry pointer
	 * %g2:	available temporary
	 * %g3:	FAULT_CODE_{D,I}TLB
	 * %g4:	available temporary
	 * %g5:	available temporary
	 * %g6: TAG TARGET
	 * %g7:	available temporary, will be loaded by us with
	 *      the physical address base of the linux page
	 *      tables for the current address space
	 */
tsb_miss_dtlb:
	mov		TLB_TAG_ACCESS, %g4
	ldxa		[%g4] ASI_DMMU, %g4
	srlx		%g4, PAGE_SHIFT, %g4
	ba,pt		%xcc, tsb_miss_page_table_walk
	 sllx		%g4, PAGE_SHIFT, %g4

tsb_miss_itlb:
	mov		TLB_TAG_ACCESS, %g4
	ldxa		[%g4] ASI_IMMU, %g4
	srlx		%g4, PAGE_SHIFT, %g4
	ba,pt		%xcc, tsb_miss_page_table_walk
	 sllx		%g4, PAGE_SHIFT, %g4

	/* At this point we have:
	 * %g1 --	PAGE_SIZE TSB entry address
	 * %g3 --	FAULT_CODE_{D,I}TLB
	 * %g4 --	missing virtual address
	 * %g6 --	TAG TARGET (vaddr >> 22)
	 */
tsb_miss_page_table_walk:
	TRAP_LOAD_TRAP_BLOCK(%g7, %g5)

	/* Before committing to a full page table walk,
	 * check the huge page TSB.
	 */
#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)

661:	ldx		[%g7 + TRAP_PER_CPU_TSB_HUGE], %g5
	nop
	.section	.sun4v_2insn_patch, "ax"
	.word		661b
	mov		SCRATCHPAD_UTSBREG2, %g5
	ldxa		[%g5] ASI_SCRATCHPAD, %g5
	.previous

	cmp		%g5, -1
	be,pt		%xcc, 80f
	 nop

	/* We need an aligned pair of registers containing 2 values
	 * which can be easily rematerialized.  %g6 and %g7 foot the
	 * bill just nicely.  We'll save %g6 away into %g2 for the
	 * huge page TSB TAG comparison.
	 *
	 * Perform a huge page TSB lookup.
	 */
	mov		%g6, %g2
	and		%g5, 0x7, %g6
	mov		512, %g7
	andn		%g5, 0x7, %g5
	sllx		%g7, %g6, %g7
	srlx		%g4, REAL_HPAGE_SHIFT, %g6
	sub		%g7, 1, %g7
	and		%g6, %g7, %g6
	sllx		%g6, 4, %g6
	add		%g5, %g6, %g5

	TSB_LOAD_QUAD(%g5, %g6)
	cmp		%g6, %g2
	be,a,pt		%xcc, tsb_tlb_reload
	 mov		%g7, %g5

	/* No match, remember the huge page TSB entry address,
	 * and restore %g6 and %g7.
	 */
	TRAP_LOAD_TRAP_BLOCK(%g7, %g6)
	srlx		%g4, 22, %g6
80:	stx		%g5, [%g7 + TRAP_PER_CPU_TSB_HUGE_TEMP]

#endif

	ldx		[%g7 + TRAP_PER_CPU_PGD_PADDR], %g7

	/* At this point we have:
	 * %g1 --	TSB entry address
	 * %g3 --	FAULT_CODE_{D,I}TLB
	 * %g4 --	missing virtual address
	 * %g6 --	TAG TARGET (vaddr >> 22)
	 * %g7 --	page table physical address
	 *
	 * We know that both the base PAGE_SIZE TSB and the HPAGE_SIZE
	 * TSB both lack a matching entry.
	 */
tsb_miss_page_table_walk_sun4v_fastpath:
	USER_PGTABLE_WALK_TL1(%g4, %g7, %g5, %g2, tsb_do_fault)

	/* Valid PTE is now in %g5.  */

#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
	sethi		%uhi(_PAGE_PMD_HUGE), %g7
	sllx		%g7, 32, %g7

	andcc		%g5, %g7, %g0
	be,pt		%xcc, 60f
	 nop

	/* It is a huge page, use huge page TSB entry address we
	 * calculated above.  If the huge page TSB has not been
	 * allocated, setup a trap stack and call hugetlb_setup()
	 * to do so, then return from the trap to replay the TLB
	 * miss.
	 *
	 * This is necessary to handle the case of transparent huge
	 * pages where we don't really have a non-atomic context
	 * in which to allocate the hugepage TSB hash table.  When
	 * the 'mm' faults in the hugepage for the first time, we
	 * thus handle it here.  This also makes sure that we can
	 * allocate the TSB hash table on the correct NUMA node.
	 */
	TRAP_LOAD_TRAP_BLOCK(%g7, %g2)
	ldx		[%g7 + TRAP_PER_CPU_TSB_HUGE_TEMP], %g1
	cmp		%g1, -1
	bne,pt		%xcc, 60f
	 nop

661:	rdpr		%pstate, %g5
	wrpr		%g5, PSTATE_AG | PSTATE_MG, %pstate
	.section	.sun4v_2insn_patch, "ax"
	.word		661b
	SET_GL(1)
	nop
	.previous

	rdpr	%tl, %g7
	cmp	%g7, 1
	bne,pn	%xcc, winfix_trampoline
	 mov	%g3, %g4
	ba,pt	%xcc, etrap
	 rd	%pc, %g7
	call	hugetlb_setup
	 add	%sp, PTREGS_OFF, %o0
	ba,pt	%xcc, rtrap
	 nop

60:
#endif

	/* At this point we have:
	 * %g1 --	TSB entry address
	 * %g3 --	FAULT_CODE_{D,I}TLB
	 * %g5 --	valid PTE
	 * %g6 --	TAG TARGET (vaddr >> 22)
	 */
tsb_reload:
	TSB_LOCK_TAG(%g1, %g2, %g7)
	TSB_WRITE(%g1, %g5, %g6)

	/* Finally, load TLB and return from trap.  */
tsb_tlb_reload:
	cmp		%g3, FAULT_CODE_DTLB
	bne,pn		%xcc, tsb_itlb_load
	 nop

tsb_dtlb_load:

661:	stxa		%g5, [%g0] ASI_DTLB_DATA_IN
	retry
	.section	.sun4v_2insn_patch, "ax"
	.word		661b
	nop
	nop
	.previous

	/* For sun4v the ASI_DTLB_DATA_IN store and the retry
	 * instruction get nop'd out and we get here to branch
	 * to the sun4v tlb load code.  The registers are setup
	 * as follows:
	 *
	 * %g4: vaddr
	 * %g5: PTE
	 * %g6:	TAG
	 *
	 * The sun4v TLB load wants the PTE in %g3 so we fix that
	 * up here.
	 */
	ba,pt		%xcc, sun4v_dtlb_load
	 mov		%g5, %g3

tsb_itlb_load:
	/* Executable bit must be set.  */
661:	sethi		%hi(_PAGE_EXEC_4U), %g4
	andcc		%g5, %g4, %g0
	.section	.sun4v_2insn_patch, "ax"
	.word		661b
	andcc		%g5, _PAGE_EXEC_4V, %g0
	nop
	.previous

	be,pn		%xcc, tsb_do_fault
	 nop

661:	stxa		%g5, [%g0] ASI_ITLB_DATA_IN
	retry
	.section	.sun4v_2insn_patch, "ax"
	.word		661b
	nop
	nop
	.previous

	/* For sun4v the ASI_ITLB_DATA_IN store and the retry
	 * instruction get nop'd out and we get here to branch
	 * to the sun4v tlb load code.  The registers are setup
	 * as follows:
	 *
	 * %g4: vaddr
	 * %g5: PTE
	 * %g6:	TAG
	 *
	 * The sun4v TLB load wants the PTE in %g3 so we fix that
	 * up here.
	 */
	ba,pt		%xcc, sun4v_itlb_load
	 mov		%g5, %g3

	/* No valid entry in the page tables, do full fault
	 * processing.
	 */

	.globl		tsb_do_fault
tsb_do_fault:
	cmp		%g3, FAULT_CODE_DTLB

661:	rdpr		%pstate, %g5
	wrpr		%g5, PSTATE_AG | PSTATE_MG, %pstate
	.section	.sun4v_2insn_patch, "ax"
	.word		661b
	SET_GL(1)
	ldxa		[%g0] ASI_SCRATCHPAD, %g4
	.previous

	bne,pn		%xcc, tsb_do_itlb_fault
	 nop

tsb_do_dtlb_fault:
	rdpr	%tl, %g3
	cmp	%g3, 1

661:	mov	TLB_TAG_ACCESS, %g4
	ldxa	[%g4] ASI_DMMU, %g5
	.section .sun4v_2insn_patch, "ax"
	.word	661b
	ldx	[%g4 + HV_FAULT_D_ADDR_OFFSET], %g5
	nop
	.previous

	/* Clear context ID bits.  */
	srlx		%g5, PAGE_SHIFT, %g5
	sllx		%g5, PAGE_SHIFT, %g5

	be,pt	%xcc, sparc64_realfault_common
	 mov	FAULT_CODE_DTLB, %g4
	ba,pt	%xcc, winfix_trampoline
	 nop

tsb_do_itlb_fault:
	rdpr	%tpc, %g5
	ba,pt	%xcc, sparc64_realfault_common
	 mov	FAULT_CODE_ITLB, %g4

	.globl	sparc64_realfault_common
sparc64_realfault_common:
	/* fault code in %g4, fault address in %g5, etrap will
	 * preserve these two values in %l4 and %l5 respectively
	 */
	ba,pt	%xcc, etrap			! Save trap state
1:	 rd	%pc, %g7			! ...
	stb	%l4, [%g6 + TI_FAULT_CODE]	! Save fault code
	stx	%l5, [%g6 + TI_FAULT_ADDR]	! Save fault address
	call	do_sparc64_fault		! Call fault handler
	 add	%sp, PTREGS_OFF, %o0		! Compute pt_regs arg
	ba,pt	%xcc, rtrap			! Restore cpu state
	 nop					! Delay slot (fill me)

winfix_trampoline:
	rdpr	%tpc, %g3			! Prepare winfixup TNPC
	or	%g3, 0x7c, %g3			! Compute branch offset
	wrpr	%g3, %tnpc			! Write it into TNPC
	done					! Trap return

	/* Insert an entry into the TSB.
	 *
	 * %o0: TSB entry pointer (virt or phys address)
	 * %o1: tag
	 * %o2:	pte
	 */
	.align	32
	.globl	__tsb_insert
__tsb_insert:
	rdpr	%pstate, %o5
	wrpr	%o5, PSTATE_IE, %pstate
	TSB_LOCK_TAG(%o0, %g2, %g3)
	TSB_WRITE(%o0, %o2, %o1)
	wrpr	%o5, %pstate
	retl
	 nop
	.size	__tsb_insert, .-__tsb_insert

	/* Flush the given TSB entry if it has the matching
	 * tag.
	 *
	 * %o0: TSB entry pointer (virt or phys address)
	 * %o1:	tag
	 */
	.align	32
	.globl	tsb_flush
	.type	tsb_flush,#function
tsb_flush:
	sethi	%hi(TSB_TAG_LOCK_HIGH), %g2
1:	TSB_LOAD_TAG(%o0, %g1)
	srlx	%g1, 32, %o3
	andcc	%o3, %g2, %g0
	bne,pn	%icc, 1b
	 nop
	cmp	%g1, %o1
	mov	1, %o3
	bne,pt	%xcc, 2f
	 sllx	%o3, TSB_TAG_INVALID_BIT, %o3
	TSB_CAS_TAG(%o0, %g1, %o3)
	cmp	%g1, %o3
	bne,pn	%xcc, 1b
	 nop
2:	retl
	 nop
	.size	tsb_flush, .-tsb_flush

	/* Reload MMU related context switch state at
	 * schedule() time.
	 *
	 * %o0: page table physical address
	 * %o1:	TSB base config pointer
	 * %o2:	TSB huge config pointer, or NULL if none
	 * %o3:	Hypervisor TSB descriptor physical address
	 * %o4: Secondary context to load, if non-zero
	 *
	 * We have to run this whole thing with interrupts
	 * disabled so that the current cpu doesn't change
	 * due to preemption.
	 */
	.align	32
	.globl	__tsb_context_switch
	.type	__tsb_context_switch,#function
__tsb_context_switch:
	rdpr	%pstate, %g1
	wrpr	%g1, PSTATE_IE, %pstate

	brz,pn	%o4, 1f
	 mov	SECONDARY_CONTEXT, %o5

661:	stxa	%o4, [%o5] ASI_DMMU
	.section .sun4v_1insn_patch, "ax"
	.word	661b
	stxa	%o4, [%o5] ASI_MMU
	.previous
	flush	%g6

1:
	TRAP_LOAD_TRAP_BLOCK(%g2, %g3)

	stx	%o0, [%g2 + TRAP_PER_CPU_PGD_PADDR]

	ldx	[%o1 + TSB_CONFIG_REG_VAL], %o0
	brz,pt	%o2, 1f
	 mov	-1, %g3

	ldx	[%o2 + TSB_CONFIG_REG_VAL], %g3

1:	stx	%g3, [%g2 + TRAP_PER_CPU_TSB_HUGE]

	sethi	%hi(tlb_type), %g2
	lduw	[%g2 + %lo(tlb_type)], %g2
	cmp	%g2, 3
	bne,pt	%icc, 50f
	 nop

	/* Hypervisor TSB switch. */
	mov	SCRATCHPAD_UTSBREG1, %o5
	stxa	%o0, [%o5] ASI_SCRATCHPAD
	mov	SCRATCHPAD_UTSBREG2, %o5
	stxa	%g3, [%o5] ASI_SCRATCHPAD

	mov	2, %o0
	cmp	%g3, -1
	move	%xcc, 1, %o0

	mov	HV_FAST_MMU_TSB_CTXNON0, %o5
	mov	%o3, %o1
	ta	HV_FAST_TRAP

	/* Finish up.  */
	ba,pt	%xcc, 9f
	 nop

	/* SUN4U TSB switch.  */
50:	mov	TSB_REG, %o5
	stxa	%o0, [%o5] ASI_DMMU
	membar	#Sync
	stxa	%o0, [%o5] ASI_IMMU
	membar	#Sync

2:	ldx	[%o1 + TSB_CONFIG_MAP_VADDR], %o4
	brz	%o4, 9f
	 ldx	[%o1 + TSB_CONFIG_MAP_PTE], %o5

	sethi	%hi(sparc64_highest_unlocked_tlb_ent), %g2
	mov	TLB_TAG_ACCESS, %g3
	lduw	[%g2 + %lo(sparc64_highest_unlocked_tlb_ent)], %g2
	stxa	%o4, [%g3] ASI_DMMU
	membar	#Sync
	sllx	%g2, 3, %g2
	stxa	%o5, [%g2] ASI_DTLB_DATA_ACCESS
	membar	#Sync

	brz,pt	%o2, 9f
	 nop

	ldx	[%o2 + TSB_CONFIG_MAP_VADDR], %o4
	ldx	[%o2 + TSB_CONFIG_MAP_PTE], %o5
	mov	TLB_TAG_ACCESS, %g3
	stxa	%o4, [%g3] ASI_DMMU
	membar	#Sync
	sub	%g2, (1 << 3), %g2
	stxa	%o5, [%g2] ASI_DTLB_DATA_ACCESS
	membar	#Sync

9:
	wrpr	%g1, %pstate

	retl
	 nop
	.size	__tsb_context_switch, .-__tsb_context_switch

#define TSB_PASS_BITS	((1 << TSB_TAG_LOCK_BIT) | \
			 (1 << TSB_TAG_INVALID_BIT))

	.align	32
	.globl	copy_tsb
	.type	copy_tsb,#function
copy_tsb:		/* %o0=old_tsb_base, %o1=old_tsb_size
			 * %o2=new_tsb_base, %o3=new_tsb_size
			 * %o4=page_size_shift
			 */
	sethi		%uhi(TSB_PASS_BITS), %g7
	srlx		%o3, 4, %o3
	add		%o0, %o1, %o1	/* end of old tsb */
	sllx		%g7, 32, %g7
	sub		%o3, 1, %o3	/* %o3 == new tsb hash mask */

	mov		%o4, %g1	/* page_size_shift */

661:	prefetcha	[%o0] ASI_N, #one_read
	.section	.tsb_phys_patch, "ax"
	.word		661b
	prefetcha	[%o0] ASI_PHYS_USE_EC, #one_read
	.previous

90:	andcc		%o0, (64 - 1), %g0
	bne		1f
	 add		%o0, 64, %o5

661:	prefetcha	[%o5] ASI_N, #one_read
	.section	.tsb_phys_patch, "ax"
	.word		661b
	prefetcha	[%o5] ASI_PHYS_USE_EC, #one_read
	.previous

1:	TSB_LOAD_QUAD(%o0, %g2)		/* %g2/%g3 == TSB entry */
	andcc		%g2, %g7, %g0	/* LOCK or INVALID set? */
	bne,pn		%xcc, 80f	/* Skip it */
	 sllx		%g2, 22, %o4	/* TAG --> VADDR */

	/* This can definitely be computed faster... */
	srlx		%o0, 4, %o5	/* Build index */
	and		%o5, 511, %o5	/* Mask index */
	sllx		%o5, %g1, %o5	/* Put into vaddr position */
	or		%o4, %o5, %o4	/* Full VADDR. */
	srlx		%o4, %g1, %o4	/* Shift down to create index */
	and		%o4, %o3, %o4	/* Mask with new_tsb_nents-1 */
	sllx		%o4, 4, %o4	/* Shift back up into tsb ent offset */
	TSB_STORE(%o2 + %o4, %g2)	/* Store TAG */
	add		%o4, 0x8, %o4	/* Advance to TTE */
	TSB_STORE(%o2 + %o4, %g3)	/* Store TTE */

80:	add		%o0, 16, %o0
	cmp		%o0, %o1
	bne,pt		%xcc, 90b
	 nop

	retl
	 nop
	.size		copy_tsb, .-copy_tsb

	/* Set the invalid bit in all TSB entries.  */
	.align		32
	.globl		tsb_init
	.type		tsb_init,#function
tsb_init:		/* %o0 = TSB vaddr, %o1 = size in bytes */
	prefetch	[%o0 + 0x000], #n_writes
	mov		1, %g1
	prefetch	[%o0 + 0x040], #n_writes
	sllx		%g1, TSB_TAG_INVALID_BIT, %g1
	prefetch	[%o0 + 0x080], #n_writes
1:	prefetch	[%o0 + 0x0c0], #n_writes
	stx		%g1, [%o0 + 0x00]
	stx		%g1, [%o0 + 0x10]
	stx		%g1, [%o0 + 0x20]
	stx		%g1, [%o0 + 0x30]
	prefetch	[%o0 + 0x100], #n_writes
	stx		%g1, [%o0 + 0x40]
	stx		%g1, [%o0 + 0x50]
	stx		%g1, [%o0 + 0x60]
	stx		%g1, [%o0 + 0x70]
	prefetch	[%o0 + 0x140], #n_writes
	stx		%g1, [%o0 + 0x80]
	stx		%g1, [%o0 + 0x90]
	stx		%g1, [%o0 + 0xa0]
	stx		%g1, [%o0 + 0xb0]
	prefetch	[%o0 + 0x180], #n_writes
	stx		%g1, [%o0 + 0xc0]
	stx		%g1, [%o0 + 0xd0]
	stx		%g1, [%o0 + 0xe0]
	stx		%g1, [%o0 + 0xf0]
	subcc		%o1, 0x100, %o1
	bne,pt		%xcc, 1b
	 add		%o0, 0x100, %o0
	retl
	 nop
	nop
	nop
	.size		tsb_init, .-tsb_init

	.globl		NGtsb_init
	.type		NGtsb_init,#function
NGtsb_init:
	rd		%asi, %g2
	mov		1, %g1
	wr		%g0, ASI_BLK_INIT_QUAD_LDD_P, %asi
	sllx		%g1, TSB_TAG_INVALID_BIT, %g1
1:	stxa		%g1, [%o0 + 0x00] %asi
	stxa		%g1, [%o0 + 0x10] %asi
	stxa		%g1, [%o0 + 0x20] %asi
	stxa		%g1, [%o0 + 0x30] %asi
	stxa		%g1, [%o0 + 0x40] %asi
	stxa		%g1, [%o0 + 0x50] %asi
	stxa		%g1, [%o0 + 0x60] %asi
	stxa		%g1, [%o0 + 0x70] %asi
	stxa		%g1, [%o0 + 0x80] %asi
	stxa		%g1, [%o0 + 0x90] %asi
	stxa		%g1, [%o0 + 0xa0] %asi
	stxa		%g1, [%o0 + 0xb0] %asi
	stxa		%g1, [%o0 + 0xc0] %asi
	stxa		%g1, [%o0 + 0xd0] %asi
	stxa		%g1, [%o0 + 0xe0] %asi
	stxa		%g1, [%o0 + 0xf0] %asi
	subcc		%o1, 0x100, %o1
	bne,pt		%xcc, 1b
	 add		%o0, 0x100, %o0
	membar		#Sync
	retl
	 wr		%g2, 0x0, %asi
	.size		NGtsb_init, .-NGtsb_init
Commit	Line	Data
74bf4312 DM	1	/* tsb.S: Sparc64 TSB table handling.
	2	*
	3	* Copyright (C) 2006 David S. Miller <davem@davemloft.net>
	4	*/
	5
dcc1e8dd	6
74bf4312	7	#include <asm/tsb.h>
618e9ed9	8	#include <asm/hypervisor.h>
dcc1e8dd DM	9	#include <asm/page.h>
	10	#include <asm/cpudata.h>
	11	#include <asm/mmu.h>
74bf4312 DM	12
	13	.text
	14	.align 32
	15
	16	/* Invoked from TLB miss handler, we are in the
	17	* MMU global registers and they are setup like
	18	* this:
	19	*
	20	* %g1: TSB entry pointer
	21	* %g2: available temporary
	22	* %g3: FAULT_CODE_{D,I}TLB
	23	* %g4: available temporary
	24	* %g5: available temporary
	25	* %g6: TAG TARGET
d257d5da DM	26	* %g7: available temporary, will be loaded by us with
d257d5da DM	27	* the physical address base of the linux page
74bf4312 DM	28	* tables for the current address space
74bf4312 DM	29	*/
74bf4312 DM	30	tsb_miss_dtlb:
74bf4312 DM	31	mov TLB_TAG_ACCESS, %g4
4f6deb8c DM	32	ldxa [%g4] ASI_DMMU, %g4
4f6deb8c DM	33	srlx %g4, PAGE_SHIFT, %g4
74bf4312	34	ba,pt %xcc, tsb_miss_page_table_walk
4f6deb8c	35	sllx %g4, PAGE_SHIFT, %g4
74bf4312	36
74bf4312 DM	37	tsb_miss_itlb:
74bf4312 DM	38	mov TLB_TAG_ACCESS, %g4
4f6deb8c DM	39	ldxa [%g4] ASI_IMMU, %g4
4f6deb8c DM	40	srlx %g4, PAGE_SHIFT, %g4
74bf4312	41	ba,pt %xcc, tsb_miss_page_table_walk
4f6deb8c	42	sllx %g4, PAGE_SHIFT, %g4
74bf4312	43
36a68e77	44	/* At this point we have:
dcc1e8dd	45	* %g1 -- PAGE_SIZE TSB entry address
7a1ac526 DM	46	* %g3 -- FAULT_CODE_{D,I}TLB
7a1ac526 DM	47	* %g4 -- missing virtual address
8b234274	48	* %g6 -- TAG TARGET (vaddr >> 22)
d257d5da	49	*/
74bf4312	50	tsb_miss_page_table_walk:
dcc1e8dd	51	TRAP_LOAD_TRAP_BLOCK(%g7, %g5)
56fb4df6	52
dcc1e8dd DM	53	/* Before committing to a full page table walk,
	54	* check the huge page TSB.
	55	*/
9e695d2e	56	#if defined(CONFIG_HUGETLB_PAGE) \|\| defined(CONFIG_TRANSPARENT_HUGEPAGE)
dcc1e8dd DM	57
	58	661: ldx [%g7 + TRAP_PER_CPU_TSB_HUGE], %g5
	59	nop
	60	.section .sun4v_2insn_patch, "ax"
	61	.word 661b
	62	mov SCRATCHPAD_UTSBREG2, %g5
	63	ldxa [%g5] ASI_SCRATCHPAD, %g5
	64	.previous
	65
	66	cmp %g5, -1
	67	be,pt %xcc, 80f
	68	nop
	69
	70	/* We need an aligned pair of registers containing 2 values
	71	* which can be easily rematerialized. %g6 and %g7 foot the
	72	* bill just nicely. We'll save %g6 away into %g2 for the
	73	* huge page TSB TAG comparison.
	74	*
	75	* Perform a huge page TSB lookup.
	76	*/
	77	mov %g6, %g2
	78	and %g5, 0x7, %g6
	79	mov 512, %g7
	80	andn %g5, 0x7, %g5
	81	sllx %g7, %g6, %g7
37b3a8ff	82	srlx %g4, REAL_HPAGE_SHIFT, %g6
dcc1e8dd DM	83	sub %g7, 1, %g7
	84	and %g6, %g7, %g6
	85	sllx %g6, 4, %g6
	86	add %g5, %g6, %g5
	87
	88	TSB_LOAD_QUAD(%g5, %g6)
	89	cmp %g6, %g2
	90	be,a,pt %xcc, tsb_tlb_reload
	91	mov %g7, %g5
	92
	93	/* No match, remember the huge page TSB entry address,
	94	* and restore %g6 and %g7.
	95	*/
	96	TRAP_LOAD_TRAP_BLOCK(%g7, %g6)
	97	srlx %g4, 22, %g6
	98	80: stx %g5, [%g7 + TRAP_PER_CPU_TSB_HUGE_TEMP]
	99
	100	#endif
	101
	102	ldx [%g7 + TRAP_PER_CPU_PGD_PADDR], %g7
74bf4312	103
7a1ac526 DM	104	/* At this point we have:
	105	* %g1 -- TSB entry address
	106	* %g3 -- FAULT_CODE_{D,I}TLB
dcc1e8dd	107	* %g4 -- missing virtual address
7a1ac526	108	* %g6 -- TAG TARGET (vaddr >> 22)
dcc1e8dd DM	109	* %g7 -- page table physical address
	110	*
	111	* We know that both the base PAGE_SIZE TSB and the HPAGE_SIZE
	112	* TSB both lack a matching entry.
7a1ac526	113	*/
dcc1e8dd DM	114	tsb_miss_page_table_walk_sun4v_fastpath:
dcc1e8dd DM	115	USER_PGTABLE_WALK_TL1(%g4, %g7, %g5, %g2, tsb_do_fault)
74bf4312	116
9e695d2e	117	/* Valid PTE is now in %g5. */
dcc1e8dd	118
9e695d2e	119	#if defined(CONFIG_HUGETLB_PAGE) \|\| defined(CONFIG_TRANSPARENT_HUGEPAGE)
c7d9f77d	120	sethi %uhi(_PAGE_PMD_HUGE), %g7
dcc1e8dd	121	sllx %g7, 32, %g7
dcc1e8dd	122
c7d9f77d NG	123	andcc %g5, %g7, %g0
c7d9f77d NG	124	be,pt %xcc, 60f
dcc1e8dd DM	125	nop
	126
	127	/* It is a huge page, use huge page TSB entry address we
0fbebed6 DM	128	* calculated above. If the huge page TSB has not been
	129	* allocated, setup a trap stack and call hugetlb_setup()
	130	* to do so, then return from the trap to replay the TLB
	131	* miss.
	132	*
	133	* This is necessary to handle the case of transparent huge
	134	* pages where we don't really have a non-atomic context
	135	* in which to allocate the hugepage TSB hash table. When
	136	* the 'mm' faults in the hugepage for the first time, we
	137	* thus handle it here. This also makes sure that we can
	138	* allocate the TSB hash table on the correct NUMA node.
dcc1e8dd DM	139	*/
dcc1e8dd DM	140	TRAP_LOAD_TRAP_BLOCK(%g7, %g2)
0fbebed6 DM	141	ldx [%g7 + TRAP_PER_CPU_TSB_HUGE_TEMP], %g1
	142	cmp %g1, -1
	143	bne,pt %xcc, 60f
	144	nop
	145
	146	661: rdpr %pstate, %g5
	147	wrpr %g5, PSTATE_AG \| PSTATE_MG, %pstate
	148	.section .sun4v_2insn_patch, "ax"
	149	.word 661b
	150	SET_GL(1)
	151	nop
	152	.previous
	153
84bd6d8b DM	154	rdpr %tl, %g7
84bd6d8b DM	155	cmp %g7, 1
0fbebed6	156	bne,pn %xcc, winfix_trampoline
84bd6d8b	157	mov %g3, %g4
0fbebed6 DM	158	ba,pt %xcc, etrap
	159	rd %pc, %g7
	160	call hugetlb_setup
	161	add %sp, PTREGS_OFF, %o0
	162	ba,pt %xcc, rtrap
	163	nop
	164
dcc1e8dd DM	165	60:
dcc1e8dd DM	166	#endif
74bf4312	167
dcc1e8dd DM	168	/* At this point we have:
	169	* %g1 -- TSB entry address
	170	* %g3 -- FAULT_CODE_{D,I}TLB
	171	* %g5 -- valid PTE
	172	* %g6 -- TAG TARGET (vaddr >> 22)
	173	*/
	174	tsb_reload:
	175	TSB_LOCK_TAG(%g1, %g2, %g7)
74bf4312 DM	176	TSB_WRITE(%g1, %g5, %g6)
	177
	178	/* Finally, load TLB and return from trap. */
	179	tsb_tlb_reload:
	180	cmp %g3, FAULT_CODE_DTLB
	181	bne,pn %xcc, tsb_itlb_load
	182	nop
	183
	184	tsb_dtlb_load:
d257d5da DM	185
d257d5da DM	186	661: stxa %g5, [%g0] ASI_DTLB_DATA_IN
74bf4312	187	retry
df7d6aec	188	.section .sun4v_2insn_patch, "ax"
d257d5da DM	189	.word 661b
	190	nop
	191	nop
	192	.previous
	193
	194	/* For sun4v the ASI_DTLB_DATA_IN store and the retry
	195	* instruction get nop'd out and we get here to branch
	196	* to the sun4v tlb load code. The registers are setup
	197	* as follows:
	198	*
	199	* %g4: vaddr
	200	* %g5: PTE
	201	* %g6: TAG
	202	*
	203	* The sun4v TLB load wants the PTE in %g3 so we fix that
	204	* up here.
	205	*/
	206	ba,pt %xcc, sun4v_dtlb_load
	207	mov %g5, %g3
74bf4312 DM	208
74bf4312 DM	209	tsb_itlb_load:
45f791eb	210	/* Executable bit must be set. */
1f474646 DM	211	661: sethi %hi(_PAGE_EXEC_4U), %g4
	212	andcc %g5, %g4, %g0
	213	.section .sun4v_2insn_patch, "ax"
45f791eb DM	214	.word 661b
45f791eb DM	215	andcc %g5, _PAGE_EXEC_4V, %g0
1f474646	216	nop
45f791eb DM	217	.previous
	218
	219	be,pn %xcc, tsb_do_fault
	220	nop
d257d5da DM	221
d257d5da DM	222	661: stxa %g5, [%g0] ASI_ITLB_DATA_IN
74bf4312	223	retry
df7d6aec	224	.section .sun4v_2insn_patch, "ax"
d257d5da DM	225	.word 661b
	226	nop
	227	nop
	228	.previous
	229
	230	/* For sun4v the ASI_ITLB_DATA_IN store and the retry
	231	* instruction get nop'd out and we get here to branch
	232	* to the sun4v tlb load code. The registers are setup
	233	* as follows:
	234	*
	235	* %g4: vaddr
	236	* %g5: PTE
	237	* %g6: TAG
	238	*
	239	* The sun4v TLB load wants the PTE in %g3 so we fix that
	240	* up here.
	241	*/
	242	ba,pt %xcc, sun4v_itlb_load
	243	mov %g5, %g3
74bf4312 DM	244
	245	/* No valid entry in the page tables, do full fault
	246	* processing.
	247	*/
	248
	249	.globl tsb_do_fault
	250	tsb_do_fault:
	251	cmp %g3, FAULT_CODE_DTLB
45fec05f DM	252
	253	661: rdpr %pstate, %g5
	254	wrpr %g5, PSTATE_AG \| PSTATE_MG, %pstate
df7d6aec	255	.section .sun4v_2insn_patch, "ax"
45fec05f	256	.word 661b
6c8927c9	257	SET_GL(1)
8b234274	258	ldxa [%g0] ASI_SCRATCHPAD, %g4
45fec05f DM	259	.previous
45fec05f DM	260
74bf4312	261	bne,pn %xcc, tsb_do_itlb_fault
45fec05f	262	nop
74bf4312 DM	263
74bf4312 DM	264	tsb_do_dtlb_fault:
d257d5da DM	265	rdpr %tl, %g3
	266	cmp %g3, 1
	267
	268	661: mov TLB_TAG_ACCESS, %g4
74bf4312	269	ldxa [%g4] ASI_DMMU, %g5
df7d6aec	270	.section .sun4v_2insn_patch, "ax"
d257d5da	271	.word 661b
8b234274	272	ldx [%g4 + HV_FAULT_D_ADDR_OFFSET], %g5
d257d5da DM	273	nop
	274	.previous
	275
4f6deb8c DM	276	/* Clear context ID bits. */
	277	srlx %g5, PAGE_SHIFT, %g5
	278	sllx %g5, PAGE_SHIFT, %g5
	279
74bf4312 DM	280	be,pt %xcc, sparc64_realfault_common
	281	mov FAULT_CODE_DTLB, %g4
	282	ba,pt %xcc, winfix_trampoline
	283	nop
	284
	285	tsb_do_itlb_fault:
	286	rdpr %tpc, %g5
	287	ba,pt %xcc, sparc64_realfault_common
	288	mov FAULT_CODE_ITLB, %g4
	289
	290	.globl sparc64_realfault_common
	291	sparc64_realfault_common:
9bc657b2 DM	292	/* fault code in %g4, fault address in %g5, etrap will
	293	* preserve these two values in %l4 and %l5 respectively
	294	*/
74bf4312 DM	295	ba,pt %xcc, etrap ! Save trap state
74bf4312 DM	296	1: rd %pc, %g7 ! ...
9bc657b2 DM	297	stb %l4, [%g6 + TI_FAULT_CODE] ! Save fault code
9bc657b2 DM	298	stx %l5, [%g6 + TI_FAULT_ADDR] ! Save fault address
74bf4312 DM	299	call do_sparc64_fault ! Call fault handler
74bf4312 DM	300	add %sp, PTREGS_OFF, %o0 ! Compute pt_regs arg
7697daaa	301	ba,pt %xcc, rtrap ! Restore cpu state
74bf4312 DM	302	nop ! Delay slot (fill me)
74bf4312 DM	303
74bf4312 DM	304	winfix_trampoline:
	305	rdpr %tpc, %g3 ! Prepare winfixup TNPC
	306	or %g3, 0x7c, %g3 ! Compute branch offset
	307	wrpr %g3, %tnpc ! Write it into TNPC
	308	done ! Trap return
	309
b70c0fa1 DM	310	/* Insert an entry into the TSB.
b70c0fa1 DM	311	*
517af332	312	* %o0: TSB entry pointer (virt or phys address)
b70c0fa1 DM	313	* %o1: tag
	314	* %o2: pte
	315	*/
	316	.align 32
517af332 DM	317	.globl __tsb_insert
517af332 DM	318	__tsb_insert:
b70c0fa1 DM	319	rdpr %pstate, %o5
	320	wrpr %o5, PSTATE_IE, %pstate
	321	TSB_LOCK_TAG(%o0, %g2, %g3)
	322	TSB_WRITE(%o0, %o2, %o1)
	323	wrpr %o5, %pstate
	324	retl
	325	nop
7a1ac526	326	.size __tsb_insert, .-__tsb_insert
b70c0fa1	327
517af332 DM	328	/* Flush the given TSB entry if it has the matching
	329	* tag.
	330	*
	331	* %o0: TSB entry pointer (virt or phys address)
	332	* %o1: tag
	333	*/
	334	.align 32
	335	.globl tsb_flush
7a1ac526	336	.type tsb_flush,#function
517af332 DM	337	tsb_flush:
	338	sethi %hi(TSB_TAG_LOCK_HIGH), %g2
	339	1: TSB_LOAD_TAG(%o0, %g1)
	340	srlx %g1, 32, %o3
	341	andcc %o3, %g2, %g0
	342	bne,pn %icc, 1b
293666b7	343	nop
517af332	344	cmp %g1, %o1
8b234274	345	mov 1, %o3
517af332	346	bne,pt %xcc, 2f
8b234274	347	sllx %o3, TSB_TAG_INVALID_BIT, %o3
517af332 DM	348	TSB_CAS_TAG(%o0, %g1, %o3)
	349	cmp %g1, %o3
	350	bne,pn %xcc, 1b
	351	nop
	352	2: retl
293666b7	353	nop
7a1ac526	354	.size tsb_flush, .-tsb_flush
517af332	355
74bf4312 DM	356	/* Reload MMU related context switch state at
	357	* schedule() time.
	358	*
	359	* %o0: page table physical address
dcc1e8dd DM	360	* %o1: TSB base config pointer
	361	* %o2: TSB huge config pointer, or NULL if none
	362	* %o3: Hypervisor TSB descriptor physical address
fc290a11	363	* %o4: Secondary context to load, if non-zero
98c5584c DM	364	*
	365	* We have to run this whole thing with interrupts
	366	* disabled so that the current cpu doesn't change
	367	* due to preemption.
74bf4312	368	*/
56fb4df6	369	.align 32
98c5584c	370	.globl __tsb_context_switch
7a1ac526	371	.type __tsb_context_switch,#function
98c5584c	372	__tsb_context_switch:
dcc1e8dd DM	373	rdpr %pstate, %g1
	374	wrpr %g1, PSTATE_IE, %pstate
	375
fc290a11 RG	376	brz,pn %o4, 1f
	377	mov SECONDARY_CONTEXT, %o5
	378
	379	661: stxa %o4, [%o5] ASI_DMMU
	380	.section .sun4v_1insn_patch, "ax"
	381	.word 661b
	382	stxa %o4, [%o5] ASI_MMU
	383	.previous
	384	flush %g6
	385
	386	1:
dcc1e8dd	387	TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
74bf4312	388
98c5584c	389	stx %o0, [%g2 + TRAP_PER_CPU_PGD_PADDR]
74bf4312	390
dcc1e8dd DM	391	ldx [%o1 + TSB_CONFIG_REG_VAL], %o0
	392	brz,pt %o2, 1f
	393	mov -1, %g3
	394
	395	ldx [%o2 + TSB_CONFIG_REG_VAL], %g3
	396
	397	1: stx %g3, [%g2 + TRAP_PER_CPU_TSB_HUGE]
	398
	399	sethi %hi(tlb_type), %g2
	400	lduw [%g2 + %lo(tlb_type)], %g2
	401	cmp %g2, 3
	402	bne,pt %icc, 50f
618e9ed9 DM	403	nop
	404
	405	/* Hypervisor TSB switch. */
dcc1e8dd DM	406	mov SCRATCHPAD_UTSBREG1, %o5
	407	stxa %o0, [%o5] ASI_SCRATCHPAD
	408	mov SCRATCHPAD_UTSBREG2, %o5
	409	stxa %g3, [%o5] ASI_SCRATCHPAD
	410
	411	mov 2, %o0
	412	cmp %g3, -1
	413	move %xcc, 1, %o0
a7b31bac	414
164c220f	415	mov HV_FAST_MMU_TSB_CTXNON0, %o5
dcc1e8dd	416	mov %o3, %o1
618e9ed9 DM	417	ta HV_FAST_TRAP
618e9ed9 DM	418
dcc1e8dd	419	/* Finish up. */
618e9ed9	420	ba,pt %xcc, 9f
dcc1e8dd	421	nop
74bf4312	422
618e9ed9	423	/* SUN4U TSB switch. */
dcc1e8dd DM	424	50: mov TSB_REG, %o5
dcc1e8dd DM	425	stxa %o0, [%o5] ASI_DMMU
618e9ed9	426	membar #Sync
dcc1e8dd	427	stxa %o0, [%o5] ASI_IMMU
74bf4312 DM	428	membar #Sync
74bf4312 DM	429
dcc1e8dd DM	430	2: ldx [%o1 + TSB_CONFIG_MAP_VADDR], %o4
	431	brz %o4, 9f
	432	ldx [%o1 + TSB_CONFIG_MAP_PTE], %o5
74bf4312	433
618e9ed9	434	sethi %hi(sparc64_highest_unlocked_tlb_ent), %g2
dcc1e8dd	435	mov TLB_TAG_ACCESS, %g3
618e9ed9	436	lduw [%g2 + %lo(sparc64_highest_unlocked_tlb_ent)], %g2
dcc1e8dd	437	stxa %o4, [%g3] ASI_DMMU
6b6d0172 DM	438	membar #Sync
6b6d0172 DM	439	sllx %g2, 3, %g2
dcc1e8dd DM	440	stxa %o5, [%g2] ASI_DTLB_DATA_ACCESS
	441	membar #Sync
	442
	443	brz,pt %o2, 9f
	444	nop
	445
	446	ldx [%o2 + TSB_CONFIG_MAP_VADDR], %o4
	447	ldx [%o2 + TSB_CONFIG_MAP_PTE], %o5
	448	mov TLB_TAG_ACCESS, %g3
	449	stxa %o4, [%g3] ASI_DMMU
	450	membar #Sync
	451	sub %g2, (1 << 3), %g2
	452	stxa %o5, [%g2] ASI_DTLB_DATA_ACCESS
6b6d0172	453	membar #Sync
dcc1e8dd	454
74bf4312	455	9:
dcc1e8dd	456	wrpr %g1, %pstate
74bf4312 DM	457
74bf4312 DM	458	retl
98c5584c	459	nop
7a1ac526 DM	460	.size __tsb_context_switch, .-__tsb_context_switch
	461
	462	#define TSB_PASS_BITS ((1 << TSB_TAG_LOCK_BIT) \| \
	463	(1 << TSB_TAG_INVALID_BIT))
	464
	465	.align 32
	466	.globl copy_tsb
	467	.type copy_tsb,#function
	468	copy_tsb: /* %o0=old_tsb_base, %o1=old_tsb_size
	469	* %o2=new_tsb_base, %o3=new_tsb_size
654f4807	470	* %o4=page_size_shift
7a1ac526 DM	471	*/
	472	sethi %uhi(TSB_PASS_BITS), %g7
	473	srlx %o3, 4, %o3
654f4807	474	add %o0, %o1, %o1 /* end of old tsb */
7a1ac526 DM	475	sllx %g7, 32, %g7
	476	sub %o3, 1, %o3 /* %o3 == new tsb hash mask */
	477
654f4807 MK	478	mov %o4, %g1 /* page_size_shift */
654f4807 MK	479
7a1ac526 DM	480	661: prefetcha [%o0] ASI_N, #one_read
	481	.section .tsb_phys_patch, "ax"
	482	.word 661b
	483	prefetcha [%o0] ASI_PHYS_USE_EC, #one_read
	484	.previous
	485
	486	90: andcc %o0, (64 - 1), %g0
	487	bne 1f
	488	add %o0, 64, %o5
	489
	490	661: prefetcha [%o5] ASI_N, #one_read
	491	.section .tsb_phys_patch, "ax"
	492	.word 661b
	493	prefetcha [%o5] ASI_PHYS_USE_EC, #one_read
	494	.previous
	495
	496	1: TSB_LOAD_QUAD(%o0, %g2) /* %g2/%g3 == TSB entry */
	497	andcc %g2, %g7, %g0 /* LOCK or INVALID set? */
	498	bne,pn %xcc, 80f /* Skip it */
	499	sllx %g2, 22, %o4 /* TAG --> VADDR */
	500
	501	/* This can definitely be computed faster... */
	502	srlx %o0, 4, %o5 /* Build index */
	503	and %o5, 511, %o5 /* Mask index */
654f4807	504	sllx %o5, %g1, %o5 /* Put into vaddr position */
7a1ac526	505	or %o4, %o5, %o4 /* Full VADDR. */
654f4807	506	srlx %o4, %g1, %o4 /* Shift down to create index */
7a1ac526 DM	507	and %o4, %o3, %o4 /* Mask with new_tsb_nents-1 */
	508	sllx %o4, 4, %o4 /* Shift back up into tsb ent offset */
	509	TSB_STORE(%o2 + %o4, %g2) /* Store TAG */
	510	add %o4, 0x8, %o4 /* Advance to TTE */
	511	TSB_STORE(%o2 + %o4, %g3) /* Store TTE */
	512
	513	80: add %o0, 16, %o0
654f4807	514	cmp %o0, %o1
7a1ac526 DM	515	bne,pt %xcc, 90b
	516	nop
	517
	518	retl
293666b7	519	nop
7a1ac526	520	.size copy_tsb, .-copy_tsb
bb8646d8 DM	521
	522	/* Set the invalid bit in all TSB entries. */
	523	.align 32
	524	.globl tsb_init
	525	.type tsb_init,#function
	526	tsb_init: /* %o0 = TSB vaddr, %o1 = size in bytes */
	527	prefetch [%o0 + 0x000], #n_writes
	528	mov 1, %g1
	529	prefetch [%o0 + 0x040], #n_writes
	530	sllx %g1, TSB_TAG_INVALID_BIT, %g1
	531	prefetch [%o0 + 0x080], #n_writes
	532	1: prefetch [%o0 + 0x0c0], #n_writes
	533	stx %g1, [%o0 + 0x00]
	534	stx %g1, [%o0 + 0x10]
	535	stx %g1, [%o0 + 0x20]
	536	stx %g1, [%o0 + 0x30]
	537	prefetch [%o0 + 0x100], #n_writes
	538	stx %g1, [%o0 + 0x40]
	539	stx %g1, [%o0 + 0x50]
	540	stx %g1, [%o0 + 0x60]
	541	stx %g1, [%o0 + 0x70]
	542	prefetch [%o0 + 0x140], #n_writes
	543	stx %g1, [%o0 + 0x80]
	544	stx %g1, [%o0 + 0x90]
	545	stx %g1, [%o0 + 0xa0]
	546	stx %g1, [%o0 + 0xb0]
	547	prefetch [%o0 + 0x180], #n_writes
	548	stx %g1, [%o0 + 0xc0]
	549	stx %g1, [%o0 + 0xd0]
	550	stx %g1, [%o0 + 0xe0]
	551	stx %g1, [%o0 + 0xf0]
	552	subcc %o1, 0x100, %o1
	553	bne,pt %xcc, 1b
	554	add %o0, 0x100, %o0
	555	retl
	556	nop
	557	nop
	558	nop
	559	.size tsb_init, .-tsb_init
	560
	561	.globl NGtsb_init
	562	.type NGtsb_init,#function
	563	NGtsb_init:
	564	rd %asi, %g2
	565	mov 1, %g1
	566	wr %g0, ASI_BLK_INIT_QUAD_LDD_P, %asi
	567	sllx %g1, TSB_TAG_INVALID_BIT, %g1
	568	1: stxa %g1, [%o0 + 0x00] %asi
	569	stxa %g1, [%o0 + 0x10] %asi
	570	stxa %g1, [%o0 + 0x20] %asi
	571	stxa %g1, [%o0 + 0x30] %asi
	572	stxa %g1, [%o0 + 0x40] %asi
	573	stxa %g1, [%o0 + 0x50] %asi
	574	stxa %g1, [%o0 + 0x60] %asi
	575	stxa %g1, [%o0 + 0x70] %asi
	576	stxa %g1, [%o0 + 0x80] %asi
	577	stxa %g1, [%o0 + 0x90] %asi
	578	stxa %g1, [%o0 + 0xa0] %asi
	579	stxa %g1, [%o0 + 0xb0] %asi
	580	stxa %g1, [%o0 + 0xc0] %asi
	581	stxa %g1, [%o0 + 0xd0] %asi
	582	stxa %g1, [%o0 + 0xe0] %asi
	583	stxa %g1, [%o0 + 0xf0] %asi
	584	subcc %o1, 0x100, %o1
585	bne,pt %xcc, 1b
586	add %o0, 0x100, %o0
24d559ca	587	membar #Sync
bb8646d8 DM	588	retl
	589	wr %g2, 0x0, %asi
	590	.size NGtsb_init, .-NGtsb_init