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1da177e4 LT |
1 | /* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $ |
2 | * arch/sparc64/mm/init.c | |
3 | * | |
4 | * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu) | |
5 | * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz) | |
6 | */ | |
7 | ||
c4bce90e | 8 | #include <linux/module.h> |
1da177e4 LT |
9 | #include <linux/kernel.h> |
10 | #include <linux/sched.h> | |
11 | #include <linux/string.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/bootmem.h> | |
14 | #include <linux/mm.h> | |
15 | #include <linux/hugetlb.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/initrd.h> | |
18 | #include <linux/swap.h> | |
19 | #include <linux/pagemap.h> | |
c9cf5528 | 20 | #include <linux/poison.h> |
1da177e4 LT |
21 | #include <linux/fs.h> |
22 | #include <linux/seq_file.h> | |
05e14cb3 | 23 | #include <linux/kprobes.h> |
1ac4f5eb | 24 | #include <linux/cache.h> |
13edad7a | 25 | #include <linux/sort.h> |
1da177e4 LT |
26 | |
27 | #include <asm/head.h> | |
28 | #include <asm/system.h> | |
29 | #include <asm/page.h> | |
30 | #include <asm/pgalloc.h> | |
31 | #include <asm/pgtable.h> | |
32 | #include <asm/oplib.h> | |
33 | #include <asm/iommu.h> | |
34 | #include <asm/io.h> | |
35 | #include <asm/uaccess.h> | |
36 | #include <asm/mmu_context.h> | |
37 | #include <asm/tlbflush.h> | |
38 | #include <asm/dma.h> | |
39 | #include <asm/starfire.h> | |
40 | #include <asm/tlb.h> | |
41 | #include <asm/spitfire.h> | |
42 | #include <asm/sections.h> | |
517af332 | 43 | #include <asm/tsb.h> |
481295f9 | 44 | #include <asm/hypervisor.h> |
372b07bb | 45 | #include <asm/prom.h> |
1da177e4 LT |
46 | |
47 | extern void device_scan(void); | |
48 | ||
9cc3a1ac DM |
49 | #define MAX_PHYS_ADDRESS (1UL << 42UL) |
50 | #define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL) | |
51 | #define KPTE_BITMAP_BYTES \ | |
52 | ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8) | |
53 | ||
54 | unsigned long kern_linear_pte_xor[2] __read_mostly; | |
55 | ||
56 | /* A bitmap, one bit for every 256MB of physical memory. If the bit | |
57 | * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else | |
58 | * if set we should use a 256MB page (via kern_linear_pte_xor[1]). | |
59 | */ | |
60 | unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)]; | |
61 | ||
d1acb421 | 62 | #ifndef CONFIG_DEBUG_PAGEALLOC |
d7744a09 DM |
63 | /* A special kernel TSB for 4MB and 256MB linear mappings. */ |
64 | struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES]; | |
d1acb421 | 65 | #endif |
d7744a09 | 66 | |
13edad7a DM |
67 | #define MAX_BANKS 32 |
68 | ||
69 | static struct linux_prom64_registers pavail[MAX_BANKS] __initdata; | |
70 | static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata; | |
71 | static int pavail_ents __initdata; | |
72 | static int pavail_rescan_ents __initdata; | |
73 | ||
74 | static int cmp_p64(const void *a, const void *b) | |
75 | { | |
76 | const struct linux_prom64_registers *x = a, *y = b; | |
77 | ||
78 | if (x->phys_addr > y->phys_addr) | |
79 | return 1; | |
80 | if (x->phys_addr < y->phys_addr) | |
81 | return -1; | |
82 | return 0; | |
83 | } | |
84 | ||
85 | static void __init read_obp_memory(const char *property, | |
86 | struct linux_prom64_registers *regs, | |
87 | int *num_ents) | |
88 | { | |
89 | int node = prom_finddevice("/memory"); | |
90 | int prop_size = prom_getproplen(node, property); | |
91 | int ents, ret, i; | |
92 | ||
93 | ents = prop_size / sizeof(struct linux_prom64_registers); | |
94 | if (ents > MAX_BANKS) { | |
95 | prom_printf("The machine has more %s property entries than " | |
96 | "this kernel can support (%d).\n", | |
97 | property, MAX_BANKS); | |
98 | prom_halt(); | |
99 | } | |
100 | ||
101 | ret = prom_getproperty(node, property, (char *) regs, prop_size); | |
102 | if (ret == -1) { | |
103 | prom_printf("Couldn't get %s property from /memory.\n"); | |
104 | prom_halt(); | |
105 | } | |
106 | ||
13edad7a DM |
107 | /* Sanitize what we got from the firmware, by page aligning |
108 | * everything. | |
109 | */ | |
110 | for (i = 0; i < ents; i++) { | |
111 | unsigned long base, size; | |
112 | ||
113 | base = regs[i].phys_addr; | |
114 | size = regs[i].reg_size; | |
10147570 | 115 | |
13edad7a DM |
116 | size &= PAGE_MASK; |
117 | if (base & ~PAGE_MASK) { | |
118 | unsigned long new_base = PAGE_ALIGN(base); | |
119 | ||
120 | size -= new_base - base; | |
121 | if ((long) size < 0L) | |
122 | size = 0UL; | |
123 | base = new_base; | |
124 | } | |
0015d3d6 DM |
125 | if (size == 0UL) { |
126 | /* If it is empty, simply get rid of it. | |
127 | * This simplifies the logic of the other | |
128 | * functions that process these arrays. | |
129 | */ | |
130 | memmove(®s[i], ®s[i + 1], | |
131 | (ents - i - 1) * sizeof(regs[0])); | |
486ad10a | 132 | i--; |
0015d3d6 DM |
133 | ents--; |
134 | continue; | |
486ad10a | 135 | } |
0015d3d6 DM |
136 | regs[i].phys_addr = base; |
137 | regs[i].reg_size = size; | |
486ad10a DM |
138 | } |
139 | ||
140 | *num_ents = ents; | |
141 | ||
c9c10830 | 142 | sort(regs, ents, sizeof(struct linux_prom64_registers), |
13edad7a DM |
143 | cmp_p64, NULL); |
144 | } | |
1da177e4 | 145 | |
2bdb3cb2 | 146 | unsigned long *sparc64_valid_addr_bitmap __read_mostly; |
1da177e4 | 147 | |
d1112018 | 148 | /* Kernel physical address base and size in bytes. */ |
1ac4f5eb DM |
149 | unsigned long kern_base __read_mostly; |
150 | unsigned long kern_size __read_mostly; | |
1da177e4 | 151 | |
1da177e4 LT |
152 | /* get_new_mmu_context() uses "cache + 1". */ |
153 | DEFINE_SPINLOCK(ctx_alloc_lock); | |
154 | unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1; | |
155 | #define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6)) | |
156 | unsigned long mmu_context_bmap[CTX_BMAP_SLOTS]; | |
157 | ||
1da177e4 LT |
158 | /* Initial ramdisk setup */ |
159 | extern unsigned long sparc_ramdisk_image64; | |
160 | extern unsigned int sparc_ramdisk_image; | |
161 | extern unsigned int sparc_ramdisk_size; | |
162 | ||
1ac4f5eb | 163 | struct page *mem_map_zero __read_mostly; |
1da177e4 | 164 | |
0835ae0f DM |
165 | unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly; |
166 | ||
167 | unsigned long sparc64_kern_pri_context __read_mostly; | |
168 | unsigned long sparc64_kern_pri_nuc_bits __read_mostly; | |
169 | unsigned long sparc64_kern_sec_context __read_mostly; | |
170 | ||
1da177e4 LT |
171 | int bigkernel = 0; |
172 | ||
e18b890b | 173 | struct kmem_cache *pgtable_cache __read_mostly; |
1da177e4 | 174 | |
e18b890b | 175 | static void zero_ctor(void *addr, struct kmem_cache *cache, unsigned long flags) |
3c936465 DM |
176 | { |
177 | clear_page(addr); | |
178 | } | |
05e28f9d | 179 | |
9b4006dc DM |
180 | extern void tsb_cache_init(void); |
181 | ||
3c936465 | 182 | void pgtable_cache_init(void) |
1da177e4 | 183 | { |
3c936465 DM |
184 | pgtable_cache = kmem_cache_create("pgtable_cache", |
185 | PAGE_SIZE, PAGE_SIZE, | |
186 | SLAB_HWCACHE_ALIGN | | |
187 | SLAB_MUST_HWCACHE_ALIGN, | |
188 | zero_ctor, | |
189 | NULL); | |
190 | if (!pgtable_cache) { | |
9b4006dc | 191 | prom_printf("Could not create pgtable_cache\n"); |
3c936465 | 192 | prom_halt(); |
1da177e4 | 193 | } |
9b4006dc | 194 | tsb_cache_init(); |
1da177e4 LT |
195 | } |
196 | ||
197 | #ifdef CONFIG_DEBUG_DCFLUSH | |
198 | atomic_t dcpage_flushes = ATOMIC_INIT(0); | |
199 | #ifdef CONFIG_SMP | |
200 | atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0); | |
201 | #endif | |
202 | #endif | |
203 | ||
7a591cfe | 204 | inline void flush_dcache_page_impl(struct page *page) |
1da177e4 | 205 | { |
7a591cfe | 206 | BUG_ON(tlb_type == hypervisor); |
1da177e4 LT |
207 | #ifdef CONFIG_DEBUG_DCFLUSH |
208 | atomic_inc(&dcpage_flushes); | |
209 | #endif | |
210 | ||
211 | #ifdef DCACHE_ALIASING_POSSIBLE | |
212 | __flush_dcache_page(page_address(page), | |
213 | ((tlb_type == spitfire) && | |
214 | page_mapping(page) != NULL)); | |
215 | #else | |
216 | if (page_mapping(page) != NULL && | |
217 | tlb_type == spitfire) | |
218 | __flush_icache_page(__pa(page_address(page))); | |
219 | #endif | |
220 | } | |
221 | ||
222 | #define PG_dcache_dirty PG_arch_1 | |
17b0e199 DM |
223 | #define PG_dcache_cpu_shift 24UL |
224 | #define PG_dcache_cpu_mask (256UL - 1UL) | |
48b0e548 DM |
225 | |
226 | #if NR_CPUS > 256 | |
227 | #error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus | |
228 | #endif | |
1da177e4 LT |
229 | |
230 | #define dcache_dirty_cpu(page) \ | |
48b0e548 | 231 | (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask) |
1da177e4 LT |
232 | |
233 | static __inline__ void set_dcache_dirty(struct page *page, int this_cpu) | |
234 | { | |
235 | unsigned long mask = this_cpu; | |
48b0e548 DM |
236 | unsigned long non_cpu_bits; |
237 | ||
238 | non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift); | |
239 | mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty); | |
240 | ||
1da177e4 LT |
241 | __asm__ __volatile__("1:\n\t" |
242 | "ldx [%2], %%g7\n\t" | |
243 | "and %%g7, %1, %%g1\n\t" | |
244 | "or %%g1, %0, %%g1\n\t" | |
245 | "casx [%2], %%g7, %%g1\n\t" | |
246 | "cmp %%g7, %%g1\n\t" | |
b445e26c | 247 | "membar #StoreLoad | #StoreStore\n\t" |
1da177e4 | 248 | "bne,pn %%xcc, 1b\n\t" |
b445e26c | 249 | " nop" |
1da177e4 LT |
250 | : /* no outputs */ |
251 | : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags) | |
252 | : "g1", "g7"); | |
253 | } | |
254 | ||
255 | static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu) | |
256 | { | |
257 | unsigned long mask = (1UL << PG_dcache_dirty); | |
258 | ||
259 | __asm__ __volatile__("! test_and_clear_dcache_dirty\n" | |
260 | "1:\n\t" | |
261 | "ldx [%2], %%g7\n\t" | |
48b0e548 | 262 | "srlx %%g7, %4, %%g1\n\t" |
1da177e4 LT |
263 | "and %%g1, %3, %%g1\n\t" |
264 | "cmp %%g1, %0\n\t" | |
265 | "bne,pn %%icc, 2f\n\t" | |
266 | " andn %%g7, %1, %%g1\n\t" | |
267 | "casx [%2], %%g7, %%g1\n\t" | |
268 | "cmp %%g7, %%g1\n\t" | |
b445e26c | 269 | "membar #StoreLoad | #StoreStore\n\t" |
1da177e4 | 270 | "bne,pn %%xcc, 1b\n\t" |
b445e26c | 271 | " nop\n" |
1da177e4 LT |
272 | "2:" |
273 | : /* no outputs */ | |
274 | : "r" (cpu), "r" (mask), "r" (&page->flags), | |
48b0e548 DM |
275 | "i" (PG_dcache_cpu_mask), |
276 | "i" (PG_dcache_cpu_shift) | |
1da177e4 LT |
277 | : "g1", "g7"); |
278 | } | |
279 | ||
517af332 DM |
280 | static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte) |
281 | { | |
282 | unsigned long tsb_addr = (unsigned long) ent; | |
283 | ||
3b3ab2eb | 284 | if (tlb_type == cheetah_plus || tlb_type == hypervisor) |
517af332 DM |
285 | tsb_addr = __pa(tsb_addr); |
286 | ||
287 | __tsb_insert(tsb_addr, tag, pte); | |
288 | } | |
289 | ||
c4bce90e DM |
290 | unsigned long _PAGE_ALL_SZ_BITS __read_mostly; |
291 | unsigned long _PAGE_SZBITS __read_mostly; | |
292 | ||
1da177e4 LT |
293 | void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte) |
294 | { | |
bd40791e | 295 | struct mm_struct *mm; |
74ae9987 | 296 | struct tsb *tsb; |
7a1ac526 | 297 | unsigned long tag, flags; |
dcc1e8dd | 298 | unsigned long tsb_index, tsb_hash_shift; |
7a591cfe DM |
299 | |
300 | if (tlb_type != hypervisor) { | |
301 | unsigned long pfn = pte_pfn(pte); | |
302 | unsigned long pg_flags; | |
303 | struct page *page; | |
304 | ||
305 | if (pfn_valid(pfn) && | |
306 | (page = pfn_to_page(pfn), page_mapping(page)) && | |
307 | ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) { | |
308 | int cpu = ((pg_flags >> PG_dcache_cpu_shift) & | |
309 | PG_dcache_cpu_mask); | |
310 | int this_cpu = get_cpu(); | |
311 | ||
312 | /* This is just to optimize away some function calls | |
313 | * in the SMP case. | |
314 | */ | |
315 | if (cpu == this_cpu) | |
316 | flush_dcache_page_impl(page); | |
317 | else | |
318 | smp_flush_dcache_page_impl(page, cpu); | |
319 | ||
320 | clear_dcache_dirty_cpu(page, cpu); | |
321 | ||
322 | put_cpu(); | |
323 | } | |
1da177e4 | 324 | } |
bd40791e DM |
325 | |
326 | mm = vma->vm_mm; | |
7a1ac526 | 327 | |
dcc1e8dd DM |
328 | tsb_index = MM_TSB_BASE; |
329 | tsb_hash_shift = PAGE_SHIFT; | |
330 | ||
7a1ac526 DM |
331 | spin_lock_irqsave(&mm->context.lock, flags); |
332 | ||
dcc1e8dd DM |
333 | #ifdef CONFIG_HUGETLB_PAGE |
334 | if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) { | |
335 | if ((tlb_type == hypervisor && | |
336 | (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) || | |
337 | (tlb_type != hypervisor && | |
338 | (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) { | |
339 | tsb_index = MM_TSB_HUGE; | |
340 | tsb_hash_shift = HPAGE_SHIFT; | |
341 | } | |
342 | } | |
343 | #endif | |
344 | ||
345 | tsb = mm->context.tsb_block[tsb_index].tsb; | |
346 | tsb += ((address >> tsb_hash_shift) & | |
347 | (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL)); | |
74ae9987 DM |
348 | tag = (address >> 22UL); |
349 | tsb_insert(tsb, tag, pte_val(pte)); | |
7a1ac526 DM |
350 | |
351 | spin_unlock_irqrestore(&mm->context.lock, flags); | |
1da177e4 LT |
352 | } |
353 | ||
354 | void flush_dcache_page(struct page *page) | |
355 | { | |
a9546f59 DM |
356 | struct address_space *mapping; |
357 | int this_cpu; | |
1da177e4 | 358 | |
7a591cfe DM |
359 | if (tlb_type == hypervisor) |
360 | return; | |
361 | ||
a9546f59 DM |
362 | /* Do not bother with the expensive D-cache flush if it |
363 | * is merely the zero page. The 'bigcore' testcase in GDB | |
364 | * causes this case to run millions of times. | |
365 | */ | |
366 | if (page == ZERO_PAGE(0)) | |
367 | return; | |
368 | ||
369 | this_cpu = get_cpu(); | |
370 | ||
371 | mapping = page_mapping(page); | |
1da177e4 | 372 | if (mapping && !mapping_mapped(mapping)) { |
a9546f59 | 373 | int dirty = test_bit(PG_dcache_dirty, &page->flags); |
1da177e4 | 374 | if (dirty) { |
a9546f59 DM |
375 | int dirty_cpu = dcache_dirty_cpu(page); |
376 | ||
1da177e4 LT |
377 | if (dirty_cpu == this_cpu) |
378 | goto out; | |
379 | smp_flush_dcache_page_impl(page, dirty_cpu); | |
380 | } | |
381 | set_dcache_dirty(page, this_cpu); | |
382 | } else { | |
383 | /* We could delay the flush for the !page_mapping | |
384 | * case too. But that case is for exec env/arg | |
385 | * pages and those are %99 certainly going to get | |
386 | * faulted into the tlb (and thus flushed) anyways. | |
387 | */ | |
388 | flush_dcache_page_impl(page); | |
389 | } | |
390 | ||
391 | out: | |
392 | put_cpu(); | |
393 | } | |
394 | ||
05e14cb3 | 395 | void __kprobes flush_icache_range(unsigned long start, unsigned long end) |
1da177e4 | 396 | { |
a43fe0e7 | 397 | /* Cheetah and Hypervisor platform cpus have coherent I-cache. */ |
1da177e4 LT |
398 | if (tlb_type == spitfire) { |
399 | unsigned long kaddr; | |
400 | ||
a94aa253 DM |
401 | /* This code only runs on Spitfire cpus so this is |
402 | * why we can assume _PAGE_PADDR_4U. | |
403 | */ | |
404 | for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) { | |
405 | unsigned long paddr, mask = _PAGE_PADDR_4U; | |
406 | ||
407 | if (kaddr >= PAGE_OFFSET) | |
408 | paddr = kaddr & mask; | |
409 | else { | |
410 | pgd_t *pgdp = pgd_offset_k(kaddr); | |
411 | pud_t *pudp = pud_offset(pgdp, kaddr); | |
412 | pmd_t *pmdp = pmd_offset(pudp, kaddr); | |
413 | pte_t *ptep = pte_offset_kernel(pmdp, kaddr); | |
414 | ||
415 | paddr = pte_val(*ptep) & mask; | |
416 | } | |
417 | __flush_icache_page(paddr); | |
418 | } | |
1da177e4 LT |
419 | } |
420 | } | |
421 | ||
1da177e4 LT |
422 | void show_mem(void) |
423 | { | |
28256ca2 | 424 | printk(KERN_INFO "Mem-info:\n"); |
1da177e4 | 425 | show_free_areas(); |
28256ca2 | 426 | printk(KERN_INFO "Free swap: %6ldkB\n", |
1da177e4 | 427 | nr_swap_pages << (PAGE_SHIFT-10)); |
28256ca2 DM |
428 | printk(KERN_INFO "%ld pages of RAM\n", num_physpages); |
429 | printk(KERN_INFO "%lu free pages\n", nr_free_pages()); | |
1da177e4 LT |
430 | } |
431 | ||
432 | void mmu_info(struct seq_file *m) | |
433 | { | |
434 | if (tlb_type == cheetah) | |
435 | seq_printf(m, "MMU Type\t: Cheetah\n"); | |
436 | else if (tlb_type == cheetah_plus) | |
437 | seq_printf(m, "MMU Type\t: Cheetah+\n"); | |
438 | else if (tlb_type == spitfire) | |
439 | seq_printf(m, "MMU Type\t: Spitfire\n"); | |
a43fe0e7 DM |
440 | else if (tlb_type == hypervisor) |
441 | seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n"); | |
1da177e4 LT |
442 | else |
443 | seq_printf(m, "MMU Type\t: ???\n"); | |
444 | ||
445 | #ifdef CONFIG_DEBUG_DCFLUSH | |
446 | seq_printf(m, "DCPageFlushes\t: %d\n", | |
447 | atomic_read(&dcpage_flushes)); | |
448 | #ifdef CONFIG_SMP | |
449 | seq_printf(m, "DCPageFlushesXC\t: %d\n", | |
450 | atomic_read(&dcpage_flushes_xcall)); | |
451 | #endif /* CONFIG_SMP */ | |
452 | #endif /* CONFIG_DEBUG_DCFLUSH */ | |
453 | } | |
454 | ||
a94aa253 DM |
455 | struct linux_prom_translation { |
456 | unsigned long virt; | |
457 | unsigned long size; | |
458 | unsigned long data; | |
459 | }; | |
460 | ||
461 | /* Exported for kernel TLB miss handling in ktlb.S */ | |
462 | struct linux_prom_translation prom_trans[512] __read_mostly; | |
463 | unsigned int prom_trans_ents __read_mostly; | |
464 | ||
1da177e4 LT |
465 | /* Exported for SMP bootup purposes. */ |
466 | unsigned long kern_locked_tte_data; | |
467 | ||
c9c10830 DM |
468 | /* The obp translations are saved based on 8k pagesize, since obp can |
469 | * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS -> | |
74bf4312 | 470 | * HI_OBP_ADDRESS range are handled in ktlb.S. |
c9c10830 | 471 | */ |
5085b4a5 DM |
472 | static inline int in_obp_range(unsigned long vaddr) |
473 | { | |
474 | return (vaddr >= LOW_OBP_ADDRESS && | |
475 | vaddr < HI_OBP_ADDRESS); | |
476 | } | |
477 | ||
c9c10830 | 478 | static int cmp_ptrans(const void *a, const void *b) |
405599bd | 479 | { |
c9c10830 | 480 | const struct linux_prom_translation *x = a, *y = b; |
405599bd | 481 | |
c9c10830 DM |
482 | if (x->virt > y->virt) |
483 | return 1; | |
484 | if (x->virt < y->virt) | |
485 | return -1; | |
486 | return 0; | |
405599bd DM |
487 | } |
488 | ||
c9c10830 | 489 | /* Read OBP translations property into 'prom_trans[]'. */ |
9ad98c5b | 490 | static void __init read_obp_translations(void) |
405599bd | 491 | { |
c9c10830 | 492 | int n, node, ents, first, last, i; |
1da177e4 LT |
493 | |
494 | node = prom_finddevice("/virtual-memory"); | |
495 | n = prom_getproplen(node, "translations"); | |
405599bd | 496 | if (unlikely(n == 0 || n == -1)) { |
b206fc4c | 497 | prom_printf("prom_mappings: Couldn't get size.\n"); |
1da177e4 LT |
498 | prom_halt(); |
499 | } | |
405599bd DM |
500 | if (unlikely(n > sizeof(prom_trans))) { |
501 | prom_printf("prom_mappings: Size %Zd is too big.\n", n); | |
1da177e4 LT |
502 | prom_halt(); |
503 | } | |
405599bd | 504 | |
b206fc4c | 505 | if ((n = prom_getproperty(node, "translations", |
405599bd DM |
506 | (char *)&prom_trans[0], |
507 | sizeof(prom_trans))) == -1) { | |
b206fc4c | 508 | prom_printf("prom_mappings: Couldn't get property.\n"); |
1da177e4 LT |
509 | prom_halt(); |
510 | } | |
9ad98c5b | 511 | |
b206fc4c | 512 | n = n / sizeof(struct linux_prom_translation); |
9ad98c5b | 513 | |
c9c10830 DM |
514 | ents = n; |
515 | ||
516 | sort(prom_trans, ents, sizeof(struct linux_prom_translation), | |
517 | cmp_ptrans, NULL); | |
518 | ||
519 | /* Now kick out all the non-OBP entries. */ | |
520 | for (i = 0; i < ents; i++) { | |
521 | if (in_obp_range(prom_trans[i].virt)) | |
522 | break; | |
523 | } | |
524 | first = i; | |
525 | for (; i < ents; i++) { | |
526 | if (!in_obp_range(prom_trans[i].virt)) | |
527 | break; | |
528 | } | |
529 | last = i; | |
530 | ||
531 | for (i = 0; i < (last - first); i++) { | |
532 | struct linux_prom_translation *src = &prom_trans[i + first]; | |
533 | struct linux_prom_translation *dest = &prom_trans[i]; | |
534 | ||
535 | *dest = *src; | |
536 | } | |
537 | for (; i < ents; i++) { | |
538 | struct linux_prom_translation *dest = &prom_trans[i]; | |
539 | dest->virt = dest->size = dest->data = 0x0UL; | |
540 | } | |
541 | ||
542 | prom_trans_ents = last - first; | |
543 | ||
544 | if (tlb_type == spitfire) { | |
545 | /* Clear diag TTE bits. */ | |
546 | for (i = 0; i < prom_trans_ents; i++) | |
547 | prom_trans[i].data &= ~0x0003fe0000000000UL; | |
548 | } | |
405599bd | 549 | } |
1da177e4 | 550 | |
d82ace7d DM |
551 | static void __init hypervisor_tlb_lock(unsigned long vaddr, |
552 | unsigned long pte, | |
553 | unsigned long mmu) | |
554 | { | |
164c220f DM |
555 | register unsigned long func asm("%o5"); |
556 | register unsigned long arg0 asm("%o0"); | |
557 | register unsigned long arg1 asm("%o1"); | |
558 | register unsigned long arg2 asm("%o2"); | |
559 | register unsigned long arg3 asm("%o3"); | |
d82ace7d DM |
560 | |
561 | func = HV_FAST_MMU_MAP_PERM_ADDR; | |
562 | arg0 = vaddr; | |
563 | arg1 = 0; | |
564 | arg2 = pte; | |
565 | arg3 = mmu; | |
566 | __asm__ __volatile__("ta 0x80" | |
567 | : "=&r" (func), "=&r" (arg0), | |
568 | "=&r" (arg1), "=&r" (arg2), | |
569 | "=&r" (arg3) | |
570 | : "0" (func), "1" (arg0), "2" (arg1), | |
571 | "3" (arg2), "4" (arg3)); | |
12e126ad DM |
572 | if (arg0 != 0) { |
573 | prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: " | |
574 | "errors with %lx\n", vaddr, 0, pte, mmu, arg0); | |
575 | prom_halt(); | |
576 | } | |
d82ace7d DM |
577 | } |
578 | ||
c4bce90e DM |
579 | static unsigned long kern_large_tte(unsigned long paddr); |
580 | ||
898cf0ec | 581 | static void __init remap_kernel(void) |
405599bd DM |
582 | { |
583 | unsigned long phys_page, tte_vaddr, tte_data; | |
405599bd DM |
584 | int tlb_ent = sparc64_highest_locked_tlbent(); |
585 | ||
1da177e4 | 586 | tte_vaddr = (unsigned long) KERNBASE; |
bff06d55 | 587 | phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL; |
c4bce90e | 588 | tte_data = kern_large_tte(phys_page); |
1da177e4 LT |
589 | |
590 | kern_locked_tte_data = tte_data; | |
591 | ||
d82ace7d DM |
592 | /* Now lock us into the TLBs via Hypervisor or OBP. */ |
593 | if (tlb_type == hypervisor) { | |
594 | hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU); | |
595 | hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU); | |
596 | if (bigkernel) { | |
597 | tte_vaddr += 0x400000; | |
598 | tte_data += 0x400000; | |
599 | hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU); | |
600 | hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU); | |
601 | } | |
602 | } else { | |
603 | prom_dtlb_load(tlb_ent, tte_data, tte_vaddr); | |
604 | prom_itlb_load(tlb_ent, tte_data, tte_vaddr); | |
605 | if (bigkernel) { | |
606 | tlb_ent -= 1; | |
607 | prom_dtlb_load(tlb_ent, | |
608 | tte_data + 0x400000, | |
609 | tte_vaddr + 0x400000); | |
610 | prom_itlb_load(tlb_ent, | |
611 | tte_data + 0x400000, | |
612 | tte_vaddr + 0x400000); | |
613 | } | |
614 | sparc64_highest_unlocked_tlb_ent = tlb_ent - 1; | |
1da177e4 | 615 | } |
0835ae0f DM |
616 | if (tlb_type == cheetah_plus) { |
617 | sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 | | |
618 | CTX_CHEETAH_PLUS_NUC); | |
619 | sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC; | |
620 | sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0; | |
621 | } | |
405599bd | 622 | } |
1da177e4 | 623 | |
405599bd | 624 | |
c9c10830 | 625 | static void __init inherit_prom_mappings(void) |
9ad98c5b DM |
626 | { |
627 | read_obp_translations(); | |
405599bd DM |
628 | |
629 | /* Now fixup OBP's idea about where we really are mapped. */ | |
630 | prom_printf("Remapping the kernel... "); | |
631 | remap_kernel(); | |
1da177e4 | 632 | prom_printf("done.\n"); |
1da177e4 LT |
633 | } |
634 | ||
1da177e4 LT |
635 | void prom_world(int enter) |
636 | { | |
1da177e4 LT |
637 | if (!enter) |
638 | set_fs((mm_segment_t) { get_thread_current_ds() }); | |
639 | ||
3487d1d4 | 640 | __asm__ __volatile__("flushw"); |
1da177e4 LT |
641 | } |
642 | ||
643 | #ifdef DCACHE_ALIASING_POSSIBLE | |
644 | void __flush_dcache_range(unsigned long start, unsigned long end) | |
645 | { | |
646 | unsigned long va; | |
647 | ||
648 | if (tlb_type == spitfire) { | |
649 | int n = 0; | |
650 | ||
651 | for (va = start; va < end; va += 32) { | |
652 | spitfire_put_dcache_tag(va & 0x3fe0, 0x0); | |
653 | if (++n >= 512) | |
654 | break; | |
655 | } | |
a43fe0e7 | 656 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
1da177e4 LT |
657 | start = __pa(start); |
658 | end = __pa(end); | |
659 | for (va = start; va < end; va += 32) | |
660 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | |
661 | "membar #Sync" | |
662 | : /* no outputs */ | |
663 | : "r" (va), | |
664 | "i" (ASI_DCACHE_INVALIDATE)); | |
665 | } | |
666 | } | |
667 | #endif /* DCACHE_ALIASING_POSSIBLE */ | |
668 | ||
1da177e4 LT |
669 | /* Caller does TLB context flushing on local CPU if necessary. |
670 | * The caller also ensures that CTX_VALID(mm->context) is false. | |
671 | * | |
672 | * We must be careful about boundary cases so that we never | |
673 | * let the user have CTX 0 (nucleus) or we ever use a CTX | |
674 | * version of zero (and thus NO_CONTEXT would not be caught | |
675 | * by version mis-match tests in mmu_context.h). | |
a0663a79 DM |
676 | * |
677 | * Always invoked with interrupts disabled. | |
1da177e4 LT |
678 | */ |
679 | void get_new_mmu_context(struct mm_struct *mm) | |
680 | { | |
681 | unsigned long ctx, new_ctx; | |
682 | unsigned long orig_pgsz_bits; | |
a77754b4 | 683 | unsigned long flags; |
a0663a79 | 684 | int new_version; |
1da177e4 | 685 | |
a77754b4 | 686 | spin_lock_irqsave(&ctx_alloc_lock, flags); |
1da177e4 LT |
687 | orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK); |
688 | ctx = (tlb_context_cache + 1) & CTX_NR_MASK; | |
689 | new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx); | |
a0663a79 | 690 | new_version = 0; |
1da177e4 LT |
691 | if (new_ctx >= (1 << CTX_NR_BITS)) { |
692 | new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1); | |
693 | if (new_ctx >= ctx) { | |
694 | int i; | |
695 | new_ctx = (tlb_context_cache & CTX_VERSION_MASK) + | |
696 | CTX_FIRST_VERSION; | |
697 | if (new_ctx == 1) | |
698 | new_ctx = CTX_FIRST_VERSION; | |
699 | ||
700 | /* Don't call memset, for 16 entries that's just | |
701 | * plain silly... | |
702 | */ | |
703 | mmu_context_bmap[0] = 3; | |
704 | mmu_context_bmap[1] = 0; | |
705 | mmu_context_bmap[2] = 0; | |
706 | mmu_context_bmap[3] = 0; | |
707 | for (i = 4; i < CTX_BMAP_SLOTS; i += 4) { | |
708 | mmu_context_bmap[i + 0] = 0; | |
709 | mmu_context_bmap[i + 1] = 0; | |
710 | mmu_context_bmap[i + 2] = 0; | |
711 | mmu_context_bmap[i + 3] = 0; | |
712 | } | |
a0663a79 | 713 | new_version = 1; |
1da177e4 LT |
714 | goto out; |
715 | } | |
716 | } | |
717 | mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63)); | |
718 | new_ctx |= (tlb_context_cache & CTX_VERSION_MASK); | |
719 | out: | |
720 | tlb_context_cache = new_ctx; | |
721 | mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits; | |
a77754b4 | 722 | spin_unlock_irqrestore(&ctx_alloc_lock, flags); |
a0663a79 DM |
723 | |
724 | if (unlikely(new_version)) | |
725 | smp_new_mmu_context_version(); | |
1da177e4 LT |
726 | } |
727 | ||
1da177e4 LT |
728 | void sparc_ultra_dump_itlb(void) |
729 | { | |
730 | int slot; | |
731 | ||
732 | if (tlb_type == spitfire) { | |
733 | printk ("Contents of itlb: "); | |
734 | for (slot = 0; slot < 14; slot++) printk (" "); | |
735 | printk ("%2x:%016lx,%016lx\n", | |
736 | 0, | |
737 | spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0)); | |
738 | for (slot = 1; slot < 64; slot+=3) { | |
739 | printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n", | |
740 | slot, | |
741 | spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot), | |
742 | slot+1, | |
743 | spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1), | |
744 | slot+2, | |
745 | spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2)); | |
746 | } | |
747 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { | |
748 | printk ("Contents of itlb0:\n"); | |
749 | for (slot = 0; slot < 16; slot+=2) { | |
750 | printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n", | |
751 | slot, | |
752 | cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot), | |
753 | slot+1, | |
754 | cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1)); | |
755 | } | |
756 | printk ("Contents of itlb2:\n"); | |
757 | for (slot = 0; slot < 128; slot+=2) { | |
758 | printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n", | |
759 | slot, | |
760 | cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot), | |
761 | slot+1, | |
762 | cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1)); | |
763 | } | |
764 | } | |
765 | } | |
766 | ||
767 | void sparc_ultra_dump_dtlb(void) | |
768 | { | |
769 | int slot; | |
770 | ||
771 | if (tlb_type == spitfire) { | |
772 | printk ("Contents of dtlb: "); | |
773 | for (slot = 0; slot < 14; slot++) printk (" "); | |
774 | printk ("%2x:%016lx,%016lx\n", 0, | |
775 | spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0)); | |
776 | for (slot = 1; slot < 64; slot+=3) { | |
777 | printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n", | |
778 | slot, | |
779 | spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot), | |
780 | slot+1, | |
781 | spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1), | |
782 | slot+2, | |
783 | spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2)); | |
784 | } | |
785 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { | |
786 | printk ("Contents of dtlb0:\n"); | |
787 | for (slot = 0; slot < 16; slot+=2) { | |
788 | printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n", | |
789 | slot, | |
790 | cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot), | |
791 | slot+1, | |
792 | cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1)); | |
793 | } | |
794 | printk ("Contents of dtlb2:\n"); | |
795 | for (slot = 0; slot < 512; slot+=2) { | |
796 | printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n", | |
797 | slot, | |
798 | cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2), | |
799 | slot+1, | |
800 | cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2)); | |
801 | } | |
802 | if (tlb_type == cheetah_plus) { | |
803 | printk ("Contents of dtlb3:\n"); | |
804 | for (slot = 0; slot < 512; slot+=2) { | |
805 | printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n", | |
806 | slot, | |
807 | cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3), | |
808 | slot+1, | |
809 | cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3)); | |
810 | } | |
811 | } | |
812 | } | |
813 | } | |
814 | ||
815 | extern unsigned long cmdline_memory_size; | |
816 | ||
d1112018 DM |
817 | /* Find a free area for the bootmem map, avoiding the kernel image |
818 | * and the initial ramdisk. | |
819 | */ | |
820 | static unsigned long __init choose_bootmap_pfn(unsigned long start_pfn, | |
821 | unsigned long end_pfn) | |
1da177e4 | 822 | { |
d1112018 DM |
823 | unsigned long avoid_start, avoid_end, bootmap_size; |
824 | int i; | |
825 | ||
826 | bootmap_size = ((end_pfn - start_pfn) + 7) / 8; | |
827 | bootmap_size = ALIGN(bootmap_size, sizeof(long)); | |
828 | ||
829 | avoid_start = avoid_end = 0; | |
830 | #ifdef CONFIG_BLK_DEV_INITRD | |
831 | avoid_start = initrd_start; | |
832 | avoid_end = PAGE_ALIGN(initrd_end); | |
833 | #endif | |
834 | ||
835 | #ifdef CONFIG_DEBUG_BOOTMEM | |
836 | prom_printf("choose_bootmap_pfn: kern[%lx:%lx] avoid[%lx:%lx]\n", | |
837 | kern_base, PAGE_ALIGN(kern_base + kern_size), | |
838 | avoid_start, avoid_end); | |
839 | #endif | |
840 | for (i = 0; i < pavail_ents; i++) { | |
841 | unsigned long start, end; | |
842 | ||
843 | start = pavail[i].phys_addr; | |
844 | end = start + pavail[i].reg_size; | |
845 | ||
846 | while (start < end) { | |
847 | if (start >= kern_base && | |
848 | start < PAGE_ALIGN(kern_base + kern_size)) { | |
849 | start = PAGE_ALIGN(kern_base + kern_size); | |
850 | continue; | |
851 | } | |
852 | if (start >= avoid_start && start < avoid_end) { | |
853 | start = avoid_end; | |
854 | continue; | |
855 | } | |
856 | ||
857 | if ((end - start) < bootmap_size) | |
858 | break; | |
859 | ||
860 | if (start < kern_base && | |
861 | (start + bootmap_size) > kern_base) { | |
862 | start = PAGE_ALIGN(kern_base + kern_size); | |
863 | continue; | |
864 | } | |
865 | ||
866 | if (start < avoid_start && | |
867 | (start + bootmap_size) > avoid_start) { | |
868 | start = avoid_end; | |
869 | continue; | |
870 | } | |
871 | ||
872 | /* OK, it doesn't overlap anything, use it. */ | |
873 | #ifdef CONFIG_DEBUG_BOOTMEM | |
874 | prom_printf("choose_bootmap_pfn: Using %lx [%lx]\n", | |
875 | start >> PAGE_SHIFT, start); | |
876 | #endif | |
877 | return start >> PAGE_SHIFT; | |
878 | } | |
879 | } | |
880 | ||
881 | prom_printf("Cannot find free area for bootmap, aborting.\n"); | |
882 | prom_halt(); | |
883 | } | |
884 | ||
6fc5bae7 DM |
885 | static void __init trim_pavail(unsigned long *cur_size_p, |
886 | unsigned long *end_of_phys_p) | |
887 | { | |
888 | unsigned long to_trim = *cur_size_p - cmdline_memory_size; | |
889 | unsigned long avoid_start, avoid_end; | |
890 | int i; | |
891 | ||
892 | to_trim = PAGE_ALIGN(to_trim); | |
893 | ||
894 | avoid_start = avoid_end = 0; | |
895 | #ifdef CONFIG_BLK_DEV_INITRD | |
896 | avoid_start = initrd_start; | |
897 | avoid_end = PAGE_ALIGN(initrd_end); | |
898 | #endif | |
899 | ||
900 | /* Trim some pavail[] entries in order to satisfy the | |
901 | * requested "mem=xxx" kernel command line specification. | |
902 | * | |
903 | * We must not trim off the kernel image area nor the | |
904 | * initial ramdisk range (if any). Also, we must not trim | |
905 | * any pavail[] entry down to zero in order to preserve | |
906 | * the invariant that all pavail[] entries have a non-zero | |
907 | * size which is assumed by all of the code in here. | |
908 | */ | |
909 | for (i = 0; i < pavail_ents; i++) { | |
910 | unsigned long start, end, kern_end; | |
911 | unsigned long trim_low, trim_high, n; | |
912 | ||
913 | kern_end = PAGE_ALIGN(kern_base + kern_size); | |
914 | ||
915 | trim_low = start = pavail[i].phys_addr; | |
916 | trim_high = end = start + pavail[i].reg_size; | |
917 | ||
918 | if (kern_base >= start && | |
919 | kern_base < end) { | |
920 | trim_low = kern_base; | |
921 | if (kern_end >= end) | |
922 | continue; | |
923 | } | |
924 | if (kern_end >= start && | |
925 | kern_end < end) { | |
926 | trim_high = kern_end; | |
927 | } | |
928 | if (avoid_start && | |
929 | avoid_start >= start && | |
930 | avoid_start < end) { | |
931 | if (trim_low > avoid_start) | |
932 | trim_low = avoid_start; | |
933 | if (avoid_end >= end) | |
934 | continue; | |
935 | } | |
936 | if (avoid_end && | |
937 | avoid_end >= start && | |
938 | avoid_end < end) { | |
939 | if (trim_high < avoid_end) | |
940 | trim_high = avoid_end; | |
941 | } | |
942 | ||
943 | if (trim_high <= trim_low) | |
944 | continue; | |
945 | ||
946 | if (trim_low == start && trim_high == end) { | |
947 | /* Whole chunk is available for trimming. | |
948 | * Trim all except one page, in order to keep | |
949 | * entry non-empty. | |
950 | */ | |
951 | n = (end - start) - PAGE_SIZE; | |
952 | if (n > to_trim) | |
953 | n = to_trim; | |
954 | ||
955 | if (n) { | |
956 | pavail[i].phys_addr += n; | |
957 | pavail[i].reg_size -= n; | |
958 | to_trim -= n; | |
959 | } | |
960 | } else { | |
961 | n = (trim_low - start); | |
962 | if (n > to_trim) | |
963 | n = to_trim; | |
964 | ||
965 | if (n) { | |
966 | pavail[i].phys_addr += n; | |
967 | pavail[i].reg_size -= n; | |
968 | to_trim -= n; | |
969 | } | |
970 | if (to_trim) { | |
971 | n = end - trim_high; | |
972 | if (n > to_trim) | |
973 | n = to_trim; | |
974 | if (n) { | |
975 | pavail[i].reg_size -= n; | |
976 | to_trim -= n; | |
977 | } | |
978 | } | |
979 | } | |
980 | ||
981 | if (!to_trim) | |
982 | break; | |
983 | } | |
984 | ||
985 | /* Recalculate. */ | |
986 | *cur_size_p = 0UL; | |
987 | for (i = 0; i < pavail_ents; i++) { | |
988 | *end_of_phys_p = pavail[i].phys_addr + | |
989 | pavail[i].reg_size; | |
990 | *cur_size_p += pavail[i].reg_size; | |
991 | } | |
992 | } | |
993 | ||
d1112018 DM |
994 | static unsigned long __init bootmem_init(unsigned long *pages_avail, |
995 | unsigned long phys_base) | |
996 | { | |
997 | unsigned long bootmap_size, end_pfn; | |
1da177e4 LT |
998 | unsigned long end_of_phys_memory = 0UL; |
999 | unsigned long bootmap_pfn, bytes_avail, size; | |
1000 | int i; | |
1001 | ||
1002 | #ifdef CONFIG_DEBUG_BOOTMEM | |
13edad7a | 1003 | prom_printf("bootmem_init: Scan pavail, "); |
1da177e4 LT |
1004 | #endif |
1005 | ||
1006 | bytes_avail = 0UL; | |
13edad7a DM |
1007 | for (i = 0; i < pavail_ents; i++) { |
1008 | end_of_phys_memory = pavail[i].phys_addr + | |
1009 | pavail[i].reg_size; | |
1010 | bytes_avail += pavail[i].reg_size; | |
1da177e4 LT |
1011 | } |
1012 | ||
6fc5bae7 DM |
1013 | /* Determine the location of the initial ramdisk before trying |
1014 | * to honor the "mem=xxx" command line argument. We must know | |
1015 | * where the kernel image and the ramdisk image are so that we | |
1016 | * do not trim those two areas from the physical memory map. | |
1017 | */ | |
1da177e4 LT |
1018 | |
1019 | #ifdef CONFIG_BLK_DEV_INITRD | |
1020 | /* Now have to check initial ramdisk, so that bootmap does not overwrite it */ | |
1021 | if (sparc_ramdisk_image || sparc_ramdisk_image64) { | |
1022 | unsigned long ramdisk_image = sparc_ramdisk_image ? | |
1023 | sparc_ramdisk_image : sparc_ramdisk_image64; | |
715a0ecc | 1024 | ramdisk_image -= KERNBASE; |
1da177e4 LT |
1025 | initrd_start = ramdisk_image + phys_base; |
1026 | initrd_end = initrd_start + sparc_ramdisk_size; | |
1027 | if (initrd_end > end_of_phys_memory) { | |
1028 | printk(KERN_CRIT "initrd extends beyond end of memory " | |
1029 | "(0x%016lx > 0x%016lx)\ndisabling initrd\n", | |
1030 | initrd_end, end_of_phys_memory); | |
1031 | initrd_start = 0; | |
d1112018 | 1032 | initrd_end = 0; |
1da177e4 LT |
1033 | } |
1034 | } | |
1035 | #endif | |
6fc5bae7 DM |
1036 | |
1037 | if (cmdline_memory_size && | |
1038 | bytes_avail > cmdline_memory_size) | |
1039 | trim_pavail(&bytes_avail, | |
1040 | &end_of_phys_memory); | |
1041 | ||
1042 | *pages_avail = bytes_avail >> PAGE_SHIFT; | |
1043 | ||
1044 | end_pfn = end_of_phys_memory >> PAGE_SHIFT; | |
1045 | ||
1da177e4 LT |
1046 | /* Initialize the boot-time allocator. */ |
1047 | max_pfn = max_low_pfn = end_pfn; | |
d1112018 DM |
1048 | min_low_pfn = (phys_base >> PAGE_SHIFT); |
1049 | ||
1050 | bootmap_pfn = choose_bootmap_pfn(min_low_pfn, end_pfn); | |
1da177e4 LT |
1051 | |
1052 | #ifdef CONFIG_DEBUG_BOOTMEM | |
1053 | prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n", | |
1054 | min_low_pfn, bootmap_pfn, max_low_pfn); | |
1055 | #endif | |
d1112018 | 1056 | bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, |
17b0e199 | 1057 | min_low_pfn, end_pfn); |
1da177e4 | 1058 | |
1da177e4 LT |
1059 | /* Now register the available physical memory with the |
1060 | * allocator. | |
1061 | */ | |
13edad7a | 1062 | for (i = 0; i < pavail_ents; i++) { |
1da177e4 | 1063 | #ifdef CONFIG_DEBUG_BOOTMEM |
13edad7a DM |
1064 | prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n", |
1065 | i, pavail[i].phys_addr, pavail[i].reg_size); | |
1da177e4 | 1066 | #endif |
13edad7a | 1067 | free_bootmem(pavail[i].phys_addr, pavail[i].reg_size); |
1da177e4 LT |
1068 | } |
1069 | ||
1070 | #ifdef CONFIG_BLK_DEV_INITRD | |
1071 | if (initrd_start) { | |
1072 | size = initrd_end - initrd_start; | |
1073 | ||
1074 | /* Resert the initrd image area. */ | |
1075 | #ifdef CONFIG_DEBUG_BOOTMEM | |
1076 | prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n", | |
1077 | initrd_start, initrd_end); | |
1078 | #endif | |
1079 | reserve_bootmem(initrd_start, size); | |
1080 | *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1081 | ||
1082 | initrd_start += PAGE_OFFSET; | |
1083 | initrd_end += PAGE_OFFSET; | |
1084 | } | |
1085 | #endif | |
1086 | /* Reserve the kernel text/data/bss. */ | |
1087 | #ifdef CONFIG_DEBUG_BOOTMEM | |
1088 | prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size); | |
1089 | #endif | |
1090 | reserve_bootmem(kern_base, kern_size); | |
1091 | *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT; | |
1092 | ||
1093 | /* Reserve the bootmem map. We do not account for it | |
1094 | * in pages_avail because we will release that memory | |
1095 | * in free_all_bootmem. | |
1096 | */ | |
1097 | size = bootmap_size; | |
1098 | #ifdef CONFIG_DEBUG_BOOTMEM | |
1099 | prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n", | |
1100 | (bootmap_pfn << PAGE_SHIFT), size); | |
1101 | #endif | |
1102 | reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size); | |
1103 | *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1104 | ||
d1112018 DM |
1105 | for (i = 0; i < pavail_ents; i++) { |
1106 | unsigned long start_pfn, end_pfn; | |
1107 | ||
1108 | start_pfn = pavail[i].phys_addr >> PAGE_SHIFT; | |
1109 | end_pfn = (start_pfn + (pavail[i].reg_size >> PAGE_SHIFT)); | |
1110 | #ifdef CONFIG_DEBUG_BOOTMEM | |
1111 | prom_printf("memory_present(0, %lx, %lx)\n", | |
1112 | start_pfn, end_pfn); | |
1113 | #endif | |
1114 | memory_present(0, start_pfn, end_pfn); | |
1115 | } | |
1116 | ||
1117 | sparse_init(); | |
1118 | ||
1da177e4 LT |
1119 | return end_pfn; |
1120 | } | |
1121 | ||
9cc3a1ac DM |
1122 | static struct linux_prom64_registers pall[MAX_BANKS] __initdata; |
1123 | static int pall_ents __initdata; | |
1124 | ||
56425306 DM |
1125 | #ifdef CONFIG_DEBUG_PAGEALLOC |
1126 | static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot) | |
1127 | { | |
1128 | unsigned long vstart = PAGE_OFFSET + pstart; | |
1129 | unsigned long vend = PAGE_OFFSET + pend; | |
1130 | unsigned long alloc_bytes = 0UL; | |
1131 | ||
1132 | if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) { | |
13edad7a | 1133 | prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n", |
56425306 DM |
1134 | vstart, vend); |
1135 | prom_halt(); | |
1136 | } | |
1137 | ||
1138 | while (vstart < vend) { | |
1139 | unsigned long this_end, paddr = __pa(vstart); | |
1140 | pgd_t *pgd = pgd_offset_k(vstart); | |
1141 | pud_t *pud; | |
1142 | pmd_t *pmd; | |
1143 | pte_t *pte; | |
1144 | ||
1145 | pud = pud_offset(pgd, vstart); | |
1146 | if (pud_none(*pud)) { | |
1147 | pmd_t *new; | |
1148 | ||
1149 | new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); | |
1150 | alloc_bytes += PAGE_SIZE; | |
1151 | pud_populate(&init_mm, pud, new); | |
1152 | } | |
1153 | ||
1154 | pmd = pmd_offset(pud, vstart); | |
1155 | if (!pmd_present(*pmd)) { | |
1156 | pte_t *new; | |
1157 | ||
1158 | new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); | |
1159 | alloc_bytes += PAGE_SIZE; | |
1160 | pmd_populate_kernel(&init_mm, pmd, new); | |
1161 | } | |
1162 | ||
1163 | pte = pte_offset_kernel(pmd, vstart); | |
1164 | this_end = (vstart + PMD_SIZE) & PMD_MASK; | |
1165 | if (this_end > vend) | |
1166 | this_end = vend; | |
1167 | ||
1168 | while (vstart < this_end) { | |
1169 | pte_val(*pte) = (paddr | pgprot_val(prot)); | |
1170 | ||
1171 | vstart += PAGE_SIZE; | |
1172 | paddr += PAGE_SIZE; | |
1173 | pte++; | |
1174 | } | |
1175 | } | |
1176 | ||
1177 | return alloc_bytes; | |
1178 | } | |
1179 | ||
56425306 | 1180 | extern unsigned int kvmap_linear_patch[1]; |
9cc3a1ac DM |
1181 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
1182 | ||
1183 | static void __init mark_kpte_bitmap(unsigned long start, unsigned long end) | |
1184 | { | |
1185 | const unsigned long shift_256MB = 28; | |
1186 | const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL); | |
1187 | const unsigned long size_256MB = (1UL << shift_256MB); | |
1188 | ||
1189 | while (start < end) { | |
1190 | long remains; | |
1191 | ||
f7c00338 DM |
1192 | remains = end - start; |
1193 | if (remains < size_256MB) | |
1194 | break; | |
1195 | ||
9cc3a1ac DM |
1196 | if (start & mask_256MB) { |
1197 | start = (start + size_256MB) & ~mask_256MB; | |
1198 | continue; | |
1199 | } | |
1200 | ||
9cc3a1ac DM |
1201 | while (remains >= size_256MB) { |
1202 | unsigned long index = start >> shift_256MB; | |
1203 | ||
1204 | __set_bit(index, kpte_linear_bitmap); | |
1205 | ||
1206 | start += size_256MB; | |
1207 | remains -= size_256MB; | |
1208 | } | |
1209 | } | |
1210 | } | |
56425306 DM |
1211 | |
1212 | static void __init kernel_physical_mapping_init(void) | |
1213 | { | |
9cc3a1ac DM |
1214 | unsigned long i; |
1215 | #ifdef CONFIG_DEBUG_PAGEALLOC | |
1216 | unsigned long mem_alloced = 0UL; | |
1217 | #endif | |
56425306 | 1218 | |
13edad7a DM |
1219 | read_obp_memory("reg", &pall[0], &pall_ents); |
1220 | ||
1221 | for (i = 0; i < pall_ents; i++) { | |
56425306 DM |
1222 | unsigned long phys_start, phys_end; |
1223 | ||
13edad7a DM |
1224 | phys_start = pall[i].phys_addr; |
1225 | phys_end = phys_start + pall[i].reg_size; | |
9cc3a1ac DM |
1226 | |
1227 | mark_kpte_bitmap(phys_start, phys_end); | |
1228 | ||
1229 | #ifdef CONFIG_DEBUG_PAGEALLOC | |
56425306 DM |
1230 | mem_alloced += kernel_map_range(phys_start, phys_end, |
1231 | PAGE_KERNEL); | |
9cc3a1ac | 1232 | #endif |
56425306 DM |
1233 | } |
1234 | ||
9cc3a1ac | 1235 | #ifdef CONFIG_DEBUG_PAGEALLOC |
56425306 DM |
1236 | printk("Allocated %ld bytes for kernel page tables.\n", |
1237 | mem_alloced); | |
1238 | ||
1239 | kvmap_linear_patch[0] = 0x01000000; /* nop */ | |
1240 | flushi(&kvmap_linear_patch[0]); | |
1241 | ||
1242 | __flush_tlb_all(); | |
9cc3a1ac | 1243 | #endif |
56425306 DM |
1244 | } |
1245 | ||
9cc3a1ac | 1246 | #ifdef CONFIG_DEBUG_PAGEALLOC |
56425306 DM |
1247 | void kernel_map_pages(struct page *page, int numpages, int enable) |
1248 | { | |
1249 | unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT; | |
1250 | unsigned long phys_end = phys_start + (numpages * PAGE_SIZE); | |
1251 | ||
1252 | kernel_map_range(phys_start, phys_end, | |
1253 | (enable ? PAGE_KERNEL : __pgprot(0))); | |
1254 | ||
74bf4312 DM |
1255 | flush_tsb_kernel_range(PAGE_OFFSET + phys_start, |
1256 | PAGE_OFFSET + phys_end); | |
1257 | ||
56425306 DM |
1258 | /* we should perform an IPI and flush all tlbs, |
1259 | * but that can deadlock->flush only current cpu. | |
1260 | */ | |
1261 | __flush_tlb_kernel_range(PAGE_OFFSET + phys_start, | |
1262 | PAGE_OFFSET + phys_end); | |
1263 | } | |
1264 | #endif | |
1265 | ||
10147570 DM |
1266 | unsigned long __init find_ecache_flush_span(unsigned long size) |
1267 | { | |
0836a0eb DM |
1268 | int i; |
1269 | ||
13edad7a DM |
1270 | for (i = 0; i < pavail_ents; i++) { |
1271 | if (pavail[i].reg_size >= size) | |
1272 | return pavail[i].phys_addr; | |
0836a0eb DM |
1273 | } |
1274 | ||
13edad7a | 1275 | return ~0UL; |
0836a0eb DM |
1276 | } |
1277 | ||
517af332 DM |
1278 | static void __init tsb_phys_patch(void) |
1279 | { | |
d257d5da | 1280 | struct tsb_ldquad_phys_patch_entry *pquad; |
517af332 DM |
1281 | struct tsb_phys_patch_entry *p; |
1282 | ||
d257d5da DM |
1283 | pquad = &__tsb_ldquad_phys_patch; |
1284 | while (pquad < &__tsb_ldquad_phys_patch_end) { | |
1285 | unsigned long addr = pquad->addr; | |
1286 | ||
1287 | if (tlb_type == hypervisor) | |
1288 | *(unsigned int *) addr = pquad->sun4v_insn; | |
1289 | else | |
1290 | *(unsigned int *) addr = pquad->sun4u_insn; | |
1291 | wmb(); | |
1292 | __asm__ __volatile__("flush %0" | |
1293 | : /* no outputs */ | |
1294 | : "r" (addr)); | |
1295 | ||
1296 | pquad++; | |
1297 | } | |
1298 | ||
517af332 DM |
1299 | p = &__tsb_phys_patch; |
1300 | while (p < &__tsb_phys_patch_end) { | |
1301 | unsigned long addr = p->addr; | |
1302 | ||
1303 | *(unsigned int *) addr = p->insn; | |
1304 | wmb(); | |
1305 | __asm__ __volatile__("flush %0" | |
1306 | : /* no outputs */ | |
1307 | : "r" (addr)); | |
1308 | ||
1309 | p++; | |
1310 | } | |
1311 | } | |
1312 | ||
490384e7 | 1313 | /* Don't mark as init, we give this to the Hypervisor. */ |
d1acb421 DM |
1314 | #ifndef CONFIG_DEBUG_PAGEALLOC |
1315 | #define NUM_KTSB_DESCR 2 | |
1316 | #else | |
1317 | #define NUM_KTSB_DESCR 1 | |
1318 | #endif | |
1319 | static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR]; | |
490384e7 DM |
1320 | extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES]; |
1321 | ||
1322 | static void __init sun4v_ktsb_init(void) | |
1323 | { | |
1324 | unsigned long ktsb_pa; | |
1325 | ||
d7744a09 | 1326 | /* First KTSB for PAGE_SIZE mappings. */ |
490384e7 DM |
1327 | ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE); |
1328 | ||
1329 | switch (PAGE_SIZE) { | |
1330 | case 8 * 1024: | |
1331 | default: | |
1332 | ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K; | |
1333 | ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K; | |
1334 | break; | |
1335 | ||
1336 | case 64 * 1024: | |
1337 | ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K; | |
1338 | ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K; | |
1339 | break; | |
1340 | ||
1341 | case 512 * 1024: | |
1342 | ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K; | |
1343 | ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K; | |
1344 | break; | |
1345 | ||
1346 | case 4 * 1024 * 1024: | |
1347 | ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB; | |
1348 | ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB; | |
1349 | break; | |
1350 | }; | |
1351 | ||
3f19a84e | 1352 | ktsb_descr[0].assoc = 1; |
490384e7 DM |
1353 | ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES; |
1354 | ktsb_descr[0].ctx_idx = 0; | |
1355 | ktsb_descr[0].tsb_base = ktsb_pa; | |
1356 | ktsb_descr[0].resv = 0; | |
1357 | ||
d1acb421 | 1358 | #ifndef CONFIG_DEBUG_PAGEALLOC |
d7744a09 DM |
1359 | /* Second KTSB for 4MB/256MB mappings. */ |
1360 | ktsb_pa = (kern_base + | |
1361 | ((unsigned long)&swapper_4m_tsb[0] - KERNBASE)); | |
1362 | ||
1363 | ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB; | |
1364 | ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB | | |
1365 | HV_PGSZ_MASK_256MB); | |
1366 | ktsb_descr[1].assoc = 1; | |
1367 | ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES; | |
1368 | ktsb_descr[1].ctx_idx = 0; | |
1369 | ktsb_descr[1].tsb_base = ktsb_pa; | |
1370 | ktsb_descr[1].resv = 0; | |
d1acb421 | 1371 | #endif |
490384e7 DM |
1372 | } |
1373 | ||
1374 | void __cpuinit sun4v_ktsb_register(void) | |
1375 | { | |
1376 | register unsigned long func asm("%o5"); | |
1377 | register unsigned long arg0 asm("%o0"); | |
1378 | register unsigned long arg1 asm("%o1"); | |
1379 | unsigned long pa; | |
1380 | ||
1381 | pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE); | |
1382 | ||
1383 | func = HV_FAST_MMU_TSB_CTX0; | |
d1acb421 | 1384 | arg0 = NUM_KTSB_DESCR; |
490384e7 DM |
1385 | arg1 = pa; |
1386 | __asm__ __volatile__("ta %6" | |
1387 | : "=&r" (func), "=&r" (arg0), "=&r" (arg1) | |
1388 | : "0" (func), "1" (arg0), "2" (arg1), | |
1389 | "i" (HV_FAST_TRAP)); | |
1390 | } | |
1391 | ||
1da177e4 LT |
1392 | /* paging_init() sets up the page tables */ |
1393 | ||
1394 | extern void cheetah_ecache_flush_init(void); | |
d257d5da | 1395 | extern void sun4v_patch_tlb_handlers(void); |
1da177e4 LT |
1396 | |
1397 | static unsigned long last_valid_pfn; | |
56425306 | 1398 | pgd_t swapper_pg_dir[2048]; |
1da177e4 | 1399 | |
c4bce90e DM |
1400 | static void sun4u_pgprot_init(void); |
1401 | static void sun4v_pgprot_init(void); | |
1402 | ||
1da177e4 LT |
1403 | void __init paging_init(void) |
1404 | { | |
d1112018 | 1405 | unsigned long end_pfn, pages_avail, shift, phys_base; |
0836a0eb DM |
1406 | unsigned long real_end, i; |
1407 | ||
481295f9 DM |
1408 | kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL; |
1409 | kern_size = (unsigned long)&_end - (unsigned long)KERNBASE; | |
1410 | ||
d7744a09 | 1411 | /* Invalidate both kernel TSBs. */ |
8b234274 | 1412 | memset(swapper_tsb, 0x40, sizeof(swapper_tsb)); |
d1acb421 | 1413 | #ifndef CONFIG_DEBUG_PAGEALLOC |
d7744a09 | 1414 | memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb)); |
d1acb421 | 1415 | #endif |
8b234274 | 1416 | |
c4bce90e DM |
1417 | if (tlb_type == hypervisor) |
1418 | sun4v_pgprot_init(); | |
1419 | else | |
1420 | sun4u_pgprot_init(); | |
1421 | ||
d257d5da DM |
1422 | if (tlb_type == cheetah_plus || |
1423 | tlb_type == hypervisor) | |
517af332 DM |
1424 | tsb_phys_patch(); |
1425 | ||
490384e7 | 1426 | if (tlb_type == hypervisor) { |
d257d5da | 1427 | sun4v_patch_tlb_handlers(); |
490384e7 DM |
1428 | sun4v_ktsb_init(); |
1429 | } | |
d257d5da | 1430 | |
13edad7a DM |
1431 | /* Find available physical memory... */ |
1432 | read_obp_memory("available", &pavail[0], &pavail_ents); | |
0836a0eb DM |
1433 | |
1434 | phys_base = 0xffffffffffffffffUL; | |
13edad7a DM |
1435 | for (i = 0; i < pavail_ents; i++) |
1436 | phys_base = min(phys_base, pavail[i].phys_addr); | |
0836a0eb | 1437 | |
1da177e4 LT |
1438 | set_bit(0, mmu_context_bmap); |
1439 | ||
2bdb3cb2 DM |
1440 | shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE); |
1441 | ||
1da177e4 LT |
1442 | real_end = (unsigned long)_end; |
1443 | if ((real_end > ((unsigned long)KERNBASE + 0x400000))) | |
1444 | bigkernel = 1; | |
2bdb3cb2 DM |
1445 | if ((real_end > ((unsigned long)KERNBASE + 0x800000))) { |
1446 | prom_printf("paging_init: Kernel > 8MB, too large.\n"); | |
1447 | prom_halt(); | |
1da177e4 | 1448 | } |
2bdb3cb2 DM |
1449 | |
1450 | /* Set kernel pgd to upper alias so physical page computations | |
1da177e4 LT |
1451 | * work. |
1452 | */ | |
1453 | init_mm.pgd += ((shift) / (sizeof(pgd_t))); | |
1454 | ||
56425306 | 1455 | memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir)); |
1da177e4 LT |
1456 | |
1457 | /* Now can init the kernel/bad page tables. */ | |
1458 | pud_set(pud_offset(&swapper_pg_dir[0], 0), | |
56425306 | 1459 | swapper_low_pmd_dir + (shift / sizeof(pgd_t))); |
1da177e4 | 1460 | |
c9c10830 | 1461 | inherit_prom_mappings(); |
5085b4a5 | 1462 | |
a8b900d8 DM |
1463 | /* Ok, we can use our TLB miss and window trap handlers safely. */ |
1464 | setup_tba(); | |
1da177e4 | 1465 | |
c9c10830 | 1466 | __flush_tlb_all(); |
9ad98c5b | 1467 | |
490384e7 DM |
1468 | if (tlb_type == hypervisor) |
1469 | sun4v_ktsb_register(); | |
1470 | ||
2bdb3cb2 DM |
1471 | /* Setup bootmem... */ |
1472 | pages_avail = 0; | |
d1112018 DM |
1473 | last_valid_pfn = end_pfn = bootmem_init(&pages_avail, phys_base); |
1474 | ||
17b0e199 | 1475 | max_mapnr = last_valid_pfn; |
2bdb3cb2 | 1476 | |
56425306 | 1477 | kernel_physical_mapping_init(); |
56425306 | 1478 | |
372b07bb DM |
1479 | prom_build_devicetree(); |
1480 | ||
1da177e4 LT |
1481 | { |
1482 | unsigned long zones_size[MAX_NR_ZONES]; | |
1483 | unsigned long zholes_size[MAX_NR_ZONES]; | |
1da177e4 LT |
1484 | int znum; |
1485 | ||
1486 | for (znum = 0; znum < MAX_NR_ZONES; znum++) | |
1487 | zones_size[znum] = zholes_size[znum] = 0; | |
1488 | ||
1b51d3a0 DM |
1489 | zones_size[ZONE_NORMAL] = end_pfn; |
1490 | zholes_size[ZONE_NORMAL] = end_pfn - pages_avail; | |
1da177e4 LT |
1491 | |
1492 | free_area_init_node(0, &contig_page_data, zones_size, | |
17b0e199 DM |
1493 | __pa(PAGE_OFFSET) >> PAGE_SHIFT, |
1494 | zholes_size); | |
1da177e4 LT |
1495 | } |
1496 | ||
1497 | device_scan(); | |
1498 | } | |
1499 | ||
1da177e4 LT |
1500 | static void __init taint_real_pages(void) |
1501 | { | |
1da177e4 LT |
1502 | int i; |
1503 | ||
13edad7a | 1504 | read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents); |
1da177e4 | 1505 | |
13edad7a | 1506 | /* Find changes discovered in the physmem available rescan and |
1da177e4 LT |
1507 | * reserve the lost portions in the bootmem maps. |
1508 | */ | |
13edad7a | 1509 | for (i = 0; i < pavail_ents; i++) { |
1da177e4 LT |
1510 | unsigned long old_start, old_end; |
1511 | ||
13edad7a | 1512 | old_start = pavail[i].phys_addr; |
1da177e4 | 1513 | old_end = old_start + |
13edad7a | 1514 | pavail[i].reg_size; |
1da177e4 LT |
1515 | while (old_start < old_end) { |
1516 | int n; | |
1517 | ||
c2a5a46b | 1518 | for (n = 0; n < pavail_rescan_ents; n++) { |
1da177e4 LT |
1519 | unsigned long new_start, new_end; |
1520 | ||
13edad7a DM |
1521 | new_start = pavail_rescan[n].phys_addr; |
1522 | new_end = new_start + | |
1523 | pavail_rescan[n].reg_size; | |
1da177e4 LT |
1524 | |
1525 | if (new_start <= old_start && | |
1526 | new_end >= (old_start + PAGE_SIZE)) { | |
13edad7a DM |
1527 | set_bit(old_start >> 22, |
1528 | sparc64_valid_addr_bitmap); | |
1da177e4 LT |
1529 | goto do_next_page; |
1530 | } | |
1531 | } | |
1532 | reserve_bootmem(old_start, PAGE_SIZE); | |
1533 | ||
1534 | do_next_page: | |
1535 | old_start += PAGE_SIZE; | |
1536 | } | |
1537 | } | |
1538 | } | |
1539 | ||
c2a5a46b DM |
1540 | int __init page_in_phys_avail(unsigned long paddr) |
1541 | { | |
1542 | int i; | |
1543 | ||
1544 | paddr &= PAGE_MASK; | |
1545 | ||
1546 | for (i = 0; i < pavail_rescan_ents; i++) { | |
1547 | unsigned long start, end; | |
1548 | ||
1549 | start = pavail_rescan[i].phys_addr; | |
1550 | end = start + pavail_rescan[i].reg_size; | |
1551 | ||
1552 | if (paddr >= start && paddr < end) | |
1553 | return 1; | |
1554 | } | |
1555 | if (paddr >= kern_base && paddr < (kern_base + kern_size)) | |
1556 | return 1; | |
1557 | #ifdef CONFIG_BLK_DEV_INITRD | |
1558 | if (paddr >= __pa(initrd_start) && | |
1559 | paddr < __pa(PAGE_ALIGN(initrd_end))) | |
1560 | return 1; | |
1561 | #endif | |
1562 | ||
1563 | return 0; | |
1564 | } | |
1565 | ||
1da177e4 LT |
1566 | void __init mem_init(void) |
1567 | { | |
1568 | unsigned long codepages, datapages, initpages; | |
1569 | unsigned long addr, last; | |
1570 | int i; | |
1571 | ||
1572 | i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6); | |
1573 | i += 1; | |
2bdb3cb2 | 1574 | sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3); |
1da177e4 LT |
1575 | if (sparc64_valid_addr_bitmap == NULL) { |
1576 | prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n"); | |
1577 | prom_halt(); | |
1578 | } | |
1579 | memset(sparc64_valid_addr_bitmap, 0, i << 3); | |
1580 | ||
1581 | addr = PAGE_OFFSET + kern_base; | |
1582 | last = PAGE_ALIGN(kern_size) + addr; | |
1583 | while (addr < last) { | |
1584 | set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap); | |
1585 | addr += PAGE_SIZE; | |
1586 | } | |
1587 | ||
1588 | taint_real_pages(); | |
1589 | ||
1da177e4 LT |
1590 | high_memory = __va(last_valid_pfn << PAGE_SHIFT); |
1591 | ||
1592 | #ifdef CONFIG_DEBUG_BOOTMEM | |
1593 | prom_printf("mem_init: Calling free_all_bootmem().\n"); | |
1594 | #endif | |
1595 | totalram_pages = num_physpages = free_all_bootmem() - 1; | |
1596 | ||
1597 | /* | |
1598 | * Set up the zero page, mark it reserved, so that page count | |
1599 | * is not manipulated when freeing the page from user ptes. | |
1600 | */ | |
1601 | mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0); | |
1602 | if (mem_map_zero == NULL) { | |
1603 | prom_printf("paging_init: Cannot alloc zero page.\n"); | |
1604 | prom_halt(); | |
1605 | } | |
1606 | SetPageReserved(mem_map_zero); | |
1607 | ||
1608 | codepages = (((unsigned long) _etext) - ((unsigned long) _start)); | |
1609 | codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT; | |
1610 | datapages = (((unsigned long) _edata) - ((unsigned long) _etext)); | |
1611 | datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT; | |
1612 | initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin)); | |
1613 | initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT; | |
1614 | ||
96177299 | 1615 | printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n", |
1da177e4 LT |
1616 | nr_free_pages() << (PAGE_SHIFT-10), |
1617 | codepages << (PAGE_SHIFT-10), | |
1618 | datapages << (PAGE_SHIFT-10), | |
1619 | initpages << (PAGE_SHIFT-10), | |
1620 | PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT)); | |
1621 | ||
1622 | if (tlb_type == cheetah || tlb_type == cheetah_plus) | |
1623 | cheetah_ecache_flush_init(); | |
1624 | } | |
1625 | ||
898cf0ec | 1626 | void free_initmem(void) |
1da177e4 LT |
1627 | { |
1628 | unsigned long addr, initend; | |
1629 | ||
1630 | /* | |
1631 | * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes. | |
1632 | */ | |
1633 | addr = PAGE_ALIGN((unsigned long)(__init_begin)); | |
1634 | initend = (unsigned long)(__init_end) & PAGE_MASK; | |
1635 | for (; addr < initend; addr += PAGE_SIZE) { | |
1636 | unsigned long page; | |
1637 | struct page *p; | |
1638 | ||
1639 | page = (addr + | |
1640 | ((unsigned long) __va(kern_base)) - | |
1641 | ((unsigned long) KERNBASE)); | |
c9cf5528 | 1642 | memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE); |
1da177e4 LT |
1643 | p = virt_to_page(page); |
1644 | ||
1645 | ClearPageReserved(p); | |
7835e98b | 1646 | init_page_count(p); |
1da177e4 LT |
1647 | __free_page(p); |
1648 | num_physpages++; | |
1649 | totalram_pages++; | |
1650 | } | |
1651 | } | |
1652 | ||
1653 | #ifdef CONFIG_BLK_DEV_INITRD | |
1654 | void free_initrd_mem(unsigned long start, unsigned long end) | |
1655 | { | |
1656 | if (start < end) | |
1657 | printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10); | |
1658 | for (; start < end; start += PAGE_SIZE) { | |
1659 | struct page *p = virt_to_page(start); | |
1660 | ||
1661 | ClearPageReserved(p); | |
7835e98b | 1662 | init_page_count(p); |
1da177e4 LT |
1663 | __free_page(p); |
1664 | num_physpages++; | |
1665 | totalram_pages++; | |
1666 | } | |
1667 | } | |
1668 | #endif | |
c4bce90e | 1669 | |
c4bce90e DM |
1670 | #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U) |
1671 | #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V) | |
1672 | #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U) | |
1673 | #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V) | |
1674 | #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R) | |
1675 | #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R) | |
1676 | ||
1677 | pgprot_t PAGE_KERNEL __read_mostly; | |
1678 | EXPORT_SYMBOL(PAGE_KERNEL); | |
1679 | ||
1680 | pgprot_t PAGE_KERNEL_LOCKED __read_mostly; | |
1681 | pgprot_t PAGE_COPY __read_mostly; | |
0f15952a DM |
1682 | |
1683 | pgprot_t PAGE_SHARED __read_mostly; | |
1684 | EXPORT_SYMBOL(PAGE_SHARED); | |
1685 | ||
c4bce90e DM |
1686 | pgprot_t PAGE_EXEC __read_mostly; |
1687 | unsigned long pg_iobits __read_mostly; | |
1688 | ||
1689 | unsigned long _PAGE_IE __read_mostly; | |
987c74fc | 1690 | EXPORT_SYMBOL(_PAGE_IE); |
b2bef442 | 1691 | |
c4bce90e | 1692 | unsigned long _PAGE_E __read_mostly; |
b2bef442 DM |
1693 | EXPORT_SYMBOL(_PAGE_E); |
1694 | ||
c4bce90e | 1695 | unsigned long _PAGE_CACHE __read_mostly; |
b2bef442 | 1696 | EXPORT_SYMBOL(_PAGE_CACHE); |
c4bce90e DM |
1697 | |
1698 | static void prot_init_common(unsigned long page_none, | |
1699 | unsigned long page_shared, | |
1700 | unsigned long page_copy, | |
1701 | unsigned long page_readonly, | |
1702 | unsigned long page_exec_bit) | |
1703 | { | |
1704 | PAGE_COPY = __pgprot(page_copy); | |
0f15952a | 1705 | PAGE_SHARED = __pgprot(page_shared); |
c4bce90e DM |
1706 | |
1707 | protection_map[0x0] = __pgprot(page_none); | |
1708 | protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit); | |
1709 | protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit); | |
1710 | protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit); | |
1711 | protection_map[0x4] = __pgprot(page_readonly); | |
1712 | protection_map[0x5] = __pgprot(page_readonly); | |
1713 | protection_map[0x6] = __pgprot(page_copy); | |
1714 | protection_map[0x7] = __pgprot(page_copy); | |
1715 | protection_map[0x8] = __pgprot(page_none); | |
1716 | protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit); | |
1717 | protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit); | |
1718 | protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit); | |
1719 | protection_map[0xc] = __pgprot(page_readonly); | |
1720 | protection_map[0xd] = __pgprot(page_readonly); | |
1721 | protection_map[0xe] = __pgprot(page_shared); | |
1722 | protection_map[0xf] = __pgprot(page_shared); | |
1723 | } | |
1724 | ||
1725 | static void __init sun4u_pgprot_init(void) | |
1726 | { | |
1727 | unsigned long page_none, page_shared, page_copy, page_readonly; | |
1728 | unsigned long page_exec_bit; | |
1729 | ||
1730 | PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | | |
1731 | _PAGE_CACHE_4U | _PAGE_P_4U | | |
1732 | __ACCESS_BITS_4U | __DIRTY_BITS_4U | | |
1733 | _PAGE_EXEC_4U); | |
1734 | PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | | |
1735 | _PAGE_CACHE_4U | _PAGE_P_4U | | |
1736 | __ACCESS_BITS_4U | __DIRTY_BITS_4U | | |
1737 | _PAGE_EXEC_4U | _PAGE_L_4U); | |
1738 | PAGE_EXEC = __pgprot(_PAGE_EXEC_4U); | |
1739 | ||
1740 | _PAGE_IE = _PAGE_IE_4U; | |
1741 | _PAGE_E = _PAGE_E_4U; | |
1742 | _PAGE_CACHE = _PAGE_CACHE_4U; | |
1743 | ||
1744 | pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U | | |
1745 | __ACCESS_BITS_4U | _PAGE_E_4U); | |
1746 | ||
d1acb421 DM |
1747 | #ifdef CONFIG_DEBUG_PAGEALLOC |
1748 | kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^ | |
1749 | 0xfffff80000000000; | |
1750 | #else | |
9cc3a1ac | 1751 | kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^ |
c4bce90e | 1752 | 0xfffff80000000000; |
d1acb421 | 1753 | #endif |
9cc3a1ac DM |
1754 | kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U | |
1755 | _PAGE_P_4U | _PAGE_W_4U); | |
1756 | ||
1757 | /* XXX Should use 256MB on Panther. XXX */ | |
1758 | kern_linear_pte_xor[1] = kern_linear_pte_xor[0]; | |
c4bce90e DM |
1759 | |
1760 | _PAGE_SZBITS = _PAGE_SZBITS_4U; | |
1761 | _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U | | |
1762 | _PAGE_SZ64K_4U | _PAGE_SZ8K_4U | | |
1763 | _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U); | |
1764 | ||
1765 | ||
1766 | page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U; | |
1767 | page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | | |
1768 | __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U); | |
1769 | page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | | |
1770 | __ACCESS_BITS_4U | _PAGE_EXEC_4U); | |
1771 | page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | | |
1772 | __ACCESS_BITS_4U | _PAGE_EXEC_4U); | |
1773 | ||
1774 | page_exec_bit = _PAGE_EXEC_4U; | |
1775 | ||
1776 | prot_init_common(page_none, page_shared, page_copy, page_readonly, | |
1777 | page_exec_bit); | |
1778 | } | |
1779 | ||
1780 | static void __init sun4v_pgprot_init(void) | |
1781 | { | |
1782 | unsigned long page_none, page_shared, page_copy, page_readonly; | |
1783 | unsigned long page_exec_bit; | |
1784 | ||
1785 | PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID | | |
1786 | _PAGE_CACHE_4V | _PAGE_P_4V | | |
1787 | __ACCESS_BITS_4V | __DIRTY_BITS_4V | | |
1788 | _PAGE_EXEC_4V); | |
1789 | PAGE_KERNEL_LOCKED = PAGE_KERNEL; | |
1790 | PAGE_EXEC = __pgprot(_PAGE_EXEC_4V); | |
1791 | ||
1792 | _PAGE_IE = _PAGE_IE_4V; | |
1793 | _PAGE_E = _PAGE_E_4V; | |
1794 | _PAGE_CACHE = _PAGE_CACHE_4V; | |
1795 | ||
d1acb421 DM |
1796 | #ifdef CONFIG_DEBUG_PAGEALLOC |
1797 | kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^ | |
1798 | 0xfffff80000000000; | |
1799 | #else | |
9cc3a1ac DM |
1800 | kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^ |
1801 | 0xfffff80000000000; | |
d1acb421 | 1802 | #endif |
9cc3a1ac DM |
1803 | kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V | |
1804 | _PAGE_P_4V | _PAGE_W_4V); | |
1805 | ||
d1acb421 DM |
1806 | #ifdef CONFIG_DEBUG_PAGEALLOC |
1807 | kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^ | |
1808 | 0xfffff80000000000; | |
1809 | #else | |
9cc3a1ac | 1810 | kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^ |
c4bce90e | 1811 | 0xfffff80000000000; |
d1acb421 | 1812 | #endif |
9cc3a1ac DM |
1813 | kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V | |
1814 | _PAGE_P_4V | _PAGE_W_4V); | |
c4bce90e DM |
1815 | |
1816 | pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V | | |
1817 | __ACCESS_BITS_4V | _PAGE_E_4V); | |
1818 | ||
1819 | _PAGE_SZBITS = _PAGE_SZBITS_4V; | |
1820 | _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V | | |
1821 | _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V | | |
1822 | _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V | | |
1823 | _PAGE_SZ64K_4V | _PAGE_SZ8K_4V); | |
1824 | ||
1825 | page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V; | |
1826 | page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V | | |
1827 | __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V); | |
1828 | page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V | | |
1829 | __ACCESS_BITS_4V | _PAGE_EXEC_4V); | |
1830 | page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V | | |
1831 | __ACCESS_BITS_4V | _PAGE_EXEC_4V); | |
1832 | ||
1833 | page_exec_bit = _PAGE_EXEC_4V; | |
1834 | ||
1835 | prot_init_common(page_none, page_shared, page_copy, page_readonly, | |
1836 | page_exec_bit); | |
1837 | } | |
1838 | ||
1839 | unsigned long pte_sz_bits(unsigned long sz) | |
1840 | { | |
1841 | if (tlb_type == hypervisor) { | |
1842 | switch (sz) { | |
1843 | case 8 * 1024: | |
1844 | default: | |
1845 | return _PAGE_SZ8K_4V; | |
1846 | case 64 * 1024: | |
1847 | return _PAGE_SZ64K_4V; | |
1848 | case 512 * 1024: | |
1849 | return _PAGE_SZ512K_4V; | |
1850 | case 4 * 1024 * 1024: | |
1851 | return _PAGE_SZ4MB_4V; | |
1852 | }; | |
1853 | } else { | |
1854 | switch (sz) { | |
1855 | case 8 * 1024: | |
1856 | default: | |
1857 | return _PAGE_SZ8K_4U; | |
1858 | case 64 * 1024: | |
1859 | return _PAGE_SZ64K_4U; | |
1860 | case 512 * 1024: | |
1861 | return _PAGE_SZ512K_4U; | |
1862 | case 4 * 1024 * 1024: | |
1863 | return _PAGE_SZ4MB_4U; | |
1864 | }; | |
1865 | } | |
1866 | } | |
1867 | ||
1868 | pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size) | |
1869 | { | |
1870 | pte_t pte; | |
cf627156 DM |
1871 | |
1872 | pte_val(pte) = page | pgprot_val(pgprot_noncached(prot)); | |
c4bce90e DM |
1873 | pte_val(pte) |= (((unsigned long)space) << 32); |
1874 | pte_val(pte) |= pte_sz_bits(page_size); | |
c4bce90e | 1875 | |
cf627156 | 1876 | return pte; |
c4bce90e DM |
1877 | } |
1878 | ||
1879 | static unsigned long kern_large_tte(unsigned long paddr) | |
1880 | { | |
1881 | unsigned long val; | |
1882 | ||
1883 | val = (_PAGE_VALID | _PAGE_SZ4MB_4U | | |
1884 | _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U | | |
1885 | _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U); | |
1886 | if (tlb_type == hypervisor) | |
1887 | val = (_PAGE_VALID | _PAGE_SZ4MB_4V | | |
1888 | _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V | | |
1889 | _PAGE_EXEC_4V | _PAGE_W_4V); | |
1890 | ||
1891 | return val | paddr; | |
1892 | } | |
1893 | ||
c4bce90e DM |
1894 | /* If not locked, zap it. */ |
1895 | void __flush_tlb_all(void) | |
1896 | { | |
1897 | unsigned long pstate; | |
1898 | int i; | |
1899 | ||
1900 | __asm__ __volatile__("flushw\n\t" | |
1901 | "rdpr %%pstate, %0\n\t" | |
1902 | "wrpr %0, %1, %%pstate" | |
1903 | : "=r" (pstate) | |
1904 | : "i" (PSTATE_IE)); | |
1905 | if (tlb_type == spitfire) { | |
1906 | for (i = 0; i < 64; i++) { | |
1907 | /* Spitfire Errata #32 workaround */ | |
1908 | /* NOTE: Always runs on spitfire, so no | |
1909 | * cheetah+ page size encodings. | |
1910 | */ | |
1911 | __asm__ __volatile__("stxa %0, [%1] %2\n\t" | |
1912 | "flush %%g6" | |
1913 | : /* No outputs */ | |
1914 | : "r" (0), | |
1915 | "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); | |
1916 | ||
1917 | if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) { | |
1918 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | |
1919 | "membar #Sync" | |
1920 | : /* no outputs */ | |
1921 | : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU)); | |
1922 | spitfire_put_dtlb_data(i, 0x0UL); | |
1923 | } | |
1924 | ||
1925 | /* Spitfire Errata #32 workaround */ | |
1926 | /* NOTE: Always runs on spitfire, so no | |
1927 | * cheetah+ page size encodings. | |
1928 | */ | |
1929 | __asm__ __volatile__("stxa %0, [%1] %2\n\t" | |
1930 | "flush %%g6" | |
1931 | : /* No outputs */ | |
1932 | : "r" (0), | |
1933 | "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); | |
1934 | ||
1935 | if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) { | |
1936 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | |
1937 | "membar #Sync" | |
1938 | : /* no outputs */ | |
1939 | : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU)); | |
1940 | spitfire_put_itlb_data(i, 0x0UL); | |
1941 | } | |
1942 | } | |
1943 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { | |
1944 | cheetah_flush_dtlb_all(); | |
1945 | cheetah_flush_itlb_all(); | |
1946 | } | |
1947 | __asm__ __volatile__("wrpr %0, 0, %%pstate" | |
1948 | : : "r" (pstate)); | |
1949 | } | |
88d70794 DM |
1950 | |
1951 | #ifdef CONFIG_MEMORY_HOTPLUG | |
1952 | ||
1953 | void online_page(struct page *page) | |
1954 | { | |
1955 | ClearPageReserved(page); | |
fcab1e51 NP |
1956 | init_page_count(page); |
1957 | __free_page(page); | |
88d70794 DM |
1958 | totalram_pages++; |
1959 | num_physpages++; | |
1960 | } | |
1961 | ||
1962 | int remove_memory(u64 start, u64 size) | |
1963 | { | |
1964 | return -EINVAL; | |
1965 | } | |
1966 | ||
1967 | #endif /* CONFIG_MEMORY_HOTPLUG */ |