[mirror_ubuntu-bionic-kernel.git] / arch / x86 / include / asm / desc.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_DESC_H
#define _ASM_X86_DESC_H

#include <asm/desc_defs.h>
#include <asm/ldt.h>
#include <asm/mmu.h>
#include <asm/fixmap.h>
#include <asm/irq_vectors.h>
#include <asm/cpu_entry_area.h>

#include <linux/smp.h>
#include <linux/percpu.h>

static inline void fill_ldt(struct desc_struct *desc, const struct user_desc *info)
{
	desc->limit0		= info->limit & 0x0ffff;

	desc->base0		= (info->base_addr & 0x0000ffff);
	desc->base1		= (info->base_addr & 0x00ff0000) >> 16;

	desc->type		= (info->read_exec_only ^ 1) << 1;
	desc->type	       |= info->contents << 2;
	/* Set the ACCESS bit so it can be mapped RO */
	desc->type	       |= 1;

	desc->s			= 1;
	desc->dpl		= 0x3;
	desc->p			= info->seg_not_present ^ 1;
	desc->limit1		= (info->limit & 0xf0000) >> 16;
	desc->avl		= info->useable;
	desc->d			= info->seg_32bit;
	desc->g			= info->limit_in_pages;

	desc->base2		= (info->base_addr & 0xff000000) >> 24;
	/*
	 * Don't allow setting of the lm bit. It would confuse
	 * user_64bit_mode and would get overridden by sysret anyway.
	 */
	desc->l			= 0;
}

extern struct desc_ptr idt_descr;
extern gate_desc idt_table[];
extern const struct desc_ptr debug_idt_descr;
extern gate_desc debug_idt_table[];

struct gdt_page {
	struct desc_struct gdt[GDT_ENTRIES];
} __attribute__((aligned(PAGE_SIZE)));

DECLARE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page);

/* Provide the original GDT */
static inline struct desc_struct *get_cpu_gdt_rw(unsigned int cpu)
{
	return per_cpu(gdt_page, cpu).gdt;
}

/* Provide the current original GDT */
static inline struct desc_struct *get_current_gdt_rw(void)
{
	return this_cpu_ptr(&gdt_page)->gdt;
}

/* Provide the fixmap address of the remapped GDT */
static inline struct desc_struct *get_cpu_gdt_ro(int cpu)
{
	return (struct desc_struct *)&get_cpu_entry_area(cpu)->gdt;
}

/* Provide the current read-only GDT */
static inline struct desc_struct *get_current_gdt_ro(void)
{
	return get_cpu_gdt_ro(smp_processor_id());
}

/* Provide the physical address of the GDT page. */
static inline phys_addr_t get_cpu_gdt_paddr(unsigned int cpu)
{
	return per_cpu_ptr_to_phys(get_cpu_gdt_rw(cpu));
}

static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func,
			     unsigned dpl, unsigned ist, unsigned seg)
{
	gate->offset_low	= (u16) func;
	gate->bits.p		= 1;
	gate->bits.dpl		= dpl;
	gate->bits.zero		= 0;
	gate->bits.type		= type;
	gate->offset_middle	= (u16) (func >> 16);
#ifdef CONFIG_X86_64
	gate->segment		= __KERNEL_CS;
	gate->bits.ist		= ist;
	gate->reserved		= 0;
	gate->offset_high	= (u32) (func >> 32);
#else
	gate->segment		= seg;
	gate->bits.ist		= 0;
#endif
}

static inline int desc_empty(const void *ptr)
{
	const u32 *desc = ptr;

	return !(desc[0] | desc[1]);
}

#ifdef CONFIG_PARAVIRT
#include <asm/paravirt.h>
#else
#define load_TR_desc()				native_load_tr_desc()
#define load_gdt(dtr)				native_load_gdt(dtr)
#define load_idt(dtr)				native_load_idt(dtr)
#define load_tr(tr)				asm volatile("ltr %0"::"m" (tr))
#define load_ldt(ldt)				asm volatile("lldt %0"::"m" (ldt))

#define store_gdt(dtr)				native_store_gdt(dtr)
#define store_tr(tr)				(tr = native_store_tr())

#define load_TLS(t, cpu)			native_load_tls(t, cpu)
#define set_ldt					native_set_ldt

#define write_ldt_entry(dt, entry, desc)	native_write_ldt_entry(dt, entry, desc)
#define write_gdt_entry(dt, entry, desc, type)	native_write_gdt_entry(dt, entry, desc, type)
#define write_idt_entry(dt, entry, g)		native_write_idt_entry(dt, entry, g)

static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
{
}

static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
{
}
#endif	/* CONFIG_PARAVIRT */

#define store_ldt(ldt) asm("sldt %0" : "=m"(ldt))

static inline void native_write_idt_entry(gate_desc *idt, int entry, const gate_desc *gate)
{
	memcpy(&idt[entry], gate, sizeof(*gate));
}

static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry, const void *desc)
{
	memcpy(&ldt[entry], desc, 8);
}

static inline void
native_write_gdt_entry(struct desc_struct *gdt, int entry, const void *desc, int type)
{
	unsigned int size;

	switch (type) {
	case DESC_TSS:	size = sizeof(tss_desc);	break;
	case DESC_LDT:	size = sizeof(ldt_desc);	break;
	default:	size = sizeof(*gdt);		break;
	}

	memcpy(&gdt[entry], desc, size);
}

static inline void set_tssldt_descriptor(void *d, unsigned long addr,
					 unsigned type, unsigned size)
{
	struct ldttss_desc *desc = d;

	memset(desc, 0, sizeof(*desc));

	desc->limit0		= (u16) size;
	desc->base0		= (u16) addr;
	desc->base1		= (addr >> 16) & 0xFF;
	desc->type		= type;
	desc->p			= 1;
	desc->limit1		= (size >> 16) & 0xF;
	desc->base2		= (addr >> 24) & 0xFF;
#ifdef CONFIG_X86_64
	desc->base3		= (u32) (addr >> 32);
#endif
}

static inline void __set_tss_desc(unsigned cpu, unsigned int entry, struct x86_hw_tss *addr)
{
	struct desc_struct *d = get_cpu_gdt_rw(cpu);
	tss_desc tss;

	set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS,
			      __KERNEL_TSS_LIMIT);
	write_gdt_entry(d, entry, &tss, DESC_TSS);
}

#define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)

static inline void native_set_ldt(const void *addr, unsigned int entries)
{
	if (likely(entries == 0))
		asm volatile("lldt %w0"::"q" (0));
	else {
		unsigned cpu = smp_processor_id();
		ldt_desc ldt;

		set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT,
				      entries * LDT_ENTRY_SIZE - 1);
		write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_LDT,
				&ldt, DESC_LDT);
		asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8));
	}
}

static inline void native_load_gdt(const struct desc_ptr *dtr)
{
	asm volatile("lgdt %0"::"m" (*dtr));
}

static inline void native_load_idt(const struct desc_ptr *dtr)
{
	asm volatile("lidt %0"::"m" (*dtr));
}

static inline void native_store_gdt(struct desc_ptr *dtr)
{
	asm volatile("sgdt %0":"=m" (*dtr));
}

static inline void store_idt(struct desc_ptr *dtr)
{
	asm volatile("sidt %0":"=m" (*dtr));
}

/*
 * The LTR instruction marks the TSS GDT entry as busy. On 64-bit, the GDT is
 * a read-only remapping. To prevent a page fault, the GDT is switched to the
 * original writeable version when needed.
 */
#ifdef CONFIG_X86_64
static inline void native_load_tr_desc(void)
{
	struct desc_ptr gdt;
	int cpu = raw_smp_processor_id();
	bool restore = 0;
	struct desc_struct *fixmap_gdt;

	native_store_gdt(&gdt);
	fixmap_gdt = get_cpu_gdt_ro(cpu);

	/*
	 * If the current GDT is the read-only fixmap, swap to the original
	 * writeable version. Swap back at the end.
	 */
	if (gdt.address == (unsigned long)fixmap_gdt) {
		load_direct_gdt(cpu);
		restore = 1;
	}
	asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
	if (restore)
		load_fixmap_gdt(cpu);
}
#else
static inline void native_load_tr_desc(void)
{
	asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
}
#endif

static inline unsigned long native_store_tr(void)
{
	unsigned long tr;

	asm volatile("str %0":"=r" (tr));

	return tr;
}

static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
{
	struct desc_struct *gdt = get_cpu_gdt_rw(cpu);
	unsigned int i;

	for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
		gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
}

DECLARE_PER_CPU(bool, __tss_limit_invalid);

static inline void force_reload_TR(void)
{
	struct desc_struct *d = get_current_gdt_rw();
	tss_desc tss;

	memcpy(&tss, &d[GDT_ENTRY_TSS], sizeof(tss_desc));

	/*
	 * LTR requires an available TSS, and the TSS is currently
	 * busy.  Make it be available so that LTR will work.
	 */
	tss.type = DESC_TSS;
	write_gdt_entry(d, GDT_ENTRY_TSS, &tss, DESC_TSS);

	load_TR_desc();
	this_cpu_write(__tss_limit_invalid, false);
}

/*
 * Call this if you need the TSS limit to be correct, which should be the case
 * if and only if you have TIF_IO_BITMAP set or you're switching to a task
 * with TIF_IO_BITMAP set.
 */
static inline void refresh_tss_limit(void)
{
	DEBUG_LOCKS_WARN_ON(preemptible());

	if (unlikely(this_cpu_read(__tss_limit_invalid)))
		force_reload_TR();
}

/*
 * If you do something evil that corrupts the cached TSS limit (I'm looking
 * at you, VMX exits), call this function.
 *
 * The optimization here is that the TSS limit only matters for Linux if the
 * IO bitmap is in use.  If the TSS limit gets forced to its minimum value,
 * everything works except that IO bitmap will be ignored and all CPL 3 IO
 * instructions will #GP, which is exactly what we want for normal tasks.
 */
static inline void invalidate_tss_limit(void)
{
	DEBUG_LOCKS_WARN_ON(preemptible());

	if (unlikely(test_thread_flag(TIF_IO_BITMAP)))
		force_reload_TR();
	else
		this_cpu_write(__tss_limit_invalid, true);
}

/* This intentionally ignores lm, since 32-bit apps don't have that field. */
#define LDT_empty(info)					\
	((info)->base_addr		== 0	&&	\
	 (info)->limit			== 0	&&	\
	 (info)->contents		== 0	&&	\
	 (info)->read_exec_only		== 1	&&	\
	 (info)->seg_32bit		== 0	&&	\
	 (info)->limit_in_pages		== 0	&&	\
	 (info)->seg_not_present	== 1	&&	\
	 (info)->useable		== 0)

/* Lots of programs expect an all-zero user_desc to mean "no segment at all". */
static inline bool LDT_zero(const struct user_desc *info)
{
	return (info->base_addr		== 0 &&
		info->limit		== 0 &&
		info->contents		== 0 &&
		info->read_exec_only	== 0 &&
		info->seg_32bit		== 0 &&
		info->limit_in_pages	== 0 &&
		info->seg_not_present	== 0 &&
		info->useable		== 0);
}

static inline void clear_LDT(void)
{
	set_ldt(NULL, 0);
}

static inline unsigned long get_desc_base(const struct desc_struct *desc)
{
	return (unsigned)(desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24));
}

static inline void set_desc_base(struct desc_struct *desc, unsigned long base)
{
	desc->base0 = base & 0xffff;
	desc->base1 = (base >> 16) & 0xff;
	desc->base2 = (base >> 24) & 0xff;
}

static inline unsigned long get_desc_limit(const struct desc_struct *desc)
{
	return desc->limit0 | (desc->limit1 << 16);
}

static inline void set_desc_limit(struct desc_struct *desc, unsigned long limit)
{
	desc->limit0 = limit & 0xffff;
	desc->limit1 = (limit >> 16) & 0xf;
}

void update_intr_gate(unsigned int n, const void *addr);
void alloc_intr_gate(unsigned int n, const void *addr);

extern unsigned long system_vectors[];

#ifdef CONFIG_X86_64
DECLARE_PER_CPU(u32, debug_idt_ctr);
static inline bool is_debug_idt_enabled(void)
{
	if (this_cpu_read(debug_idt_ctr))
		return true;

	return false;
}

static inline void load_debug_idt(void)
{
	load_idt((const struct desc_ptr *)&debug_idt_descr);
}
#else
static inline bool is_debug_idt_enabled(void)
{
	return false;
}

static inline void load_debug_idt(void)
{
}
#endif

/*
 * The load_current_idt() must be called with interrupts disabled
 * to avoid races. That way the IDT will always be set back to the expected
 * descriptor. It's also called when a CPU is being initialized, and
 * that doesn't need to disable interrupts, as nothing should be
 * bothering the CPU then.
 */
static inline void load_current_idt(void)
{
	if (is_debug_idt_enabled())
		load_debug_idt();
	else
		load_idt((const struct desc_ptr *)&idt_descr);
}

extern void idt_setup_early_handler(void);
extern void idt_setup_early_traps(void);
extern void idt_setup_traps(void);
extern void idt_setup_apic_and_irq_gates(void);

#ifdef CONFIG_X86_64
extern void idt_setup_early_pf(void);
extern void idt_setup_ist_traps(void);
extern void idt_setup_debugidt_traps(void);
#else
static inline void idt_setup_early_pf(void) { }
static inline void idt_setup_ist_traps(void) { }
static inline void idt_setup_debugidt_traps(void) { }
#endif

extern void idt_invalidate(void *addr);

#endif /* _ASM_X86_DESC_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
1965aae3 PA	2	#ifndef _ASM_X86_DESC_H
1965aae3 PA	3	#define _ASM_X86_DESC_H
80fbb69a	4
80fbb69a GOC	5	#include <asm/desc_defs.h>
80fbb69a GOC	6	#include <asm/ldt.h>
881c2975	7	#include <asm/mmu.h>
69218e47	8	#include <asm/fixmap.h>
05161b9c	9	#include <asm/irq_vectors.h>
92a0f81d	10	#include <asm/cpu_entry_area.h>
9a3865b1	11
54cd0eac	12	#include <linux/smp.h>
c6ae41e7	13	#include <linux/percpu.h>
80fbb69a	14
9a3865b1 IM	15	static inline void fill_ldt(struct desc_struct desc, const struct user_desc info)
	16	{
	17	desc->limit0 = info->limit & 0x0ffff;
	18
	19	desc->base0 = (info->base_addr & 0x0000ffff);
	20	desc->base1 = (info->base_addr & 0x00ff0000) >> 16;
	21
	22	desc->type = (info->read_exec_only ^ 1) << 1;
	23	desc->type \|= info->contents << 2;
9f5cb6b3 TG	24	/* Set the ACCESS bit so it can be mapped RO */
9f5cb6b3 TG	25	desc->type \|= 1;
9a3865b1 IM	26
	27	desc->s = 1;
	28	desc->dpl = 0x3;
	29	desc->p = info->seg_not_present ^ 1;
38e9e81f	30	desc->limit1 = (info->limit & 0xf0000) >> 16;
9a3865b1 IM	31	desc->avl = info->useable;
	32	desc->d = info->seg_32bit;
	33	desc->g = info->limit_in_pages;
	34
	35	desc->base2 = (info->base_addr & 0xff000000) >> 24;
64f53a04	36	/*
318f5a2a AL	37	* Don't allow setting of the lm bit. It would confuse
318f5a2a AL	38	* user_64bit_mode and would get overridden by sysret anyway.
64f53a04	39	*/
9a3865b1	40	desc->l = 0;
80fbb69a GOC	41	}
80fbb69a GOC	42
881c2975 GOC	43	extern struct desc_ptr idt_descr;
881c2975 GOC	44	extern gate_desc idt_table[];
404f6aac	45	extern const struct desc_ptr debug_idt_descr;
629f4f9d	46	extern gate_desc debug_idt_table[];
80fbb69a	47
a939098a GC	48	struct gdt_page {
	49	struct desc_struct gdt[GDT_ENTRIES];
	50	} __attribute__((aligned(PAGE_SIZE)));
9a3865b1	51
9b8de747	52	DECLARE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page);
a939098a	53
69218e47 TG	54	/* Provide the original GDT */
69218e47 TG	55	static inline struct desc_struct *get_cpu_gdt_rw(unsigned int cpu)
a939098a GC	56	{
	57	return per_cpu(gdt_page, cpu).gdt;
	58	}
	59
69218e47 TG	60	/* Provide the current original GDT */
	61	static inline struct desc_struct *get_current_gdt_rw(void)
	62	{
	63	return this_cpu_ptr(&gdt_page)->gdt;
	64	}
	65
69218e47 TG	66	/* Provide the fixmap address of the remapped GDT */
	67	static inline struct desc_struct *get_cpu_gdt_ro(int cpu)
	68	{
ef8813ab	69	return (struct desc_struct *)&get_cpu_entry_area(cpu)->gdt;
69218e47 TG	70	}
69218e47 TG	71
69218e47 TG	72	/* Provide the current read-only GDT */
	73	static inline struct desc_struct *get_current_gdt_ro(void)
	74	{
	75	return get_cpu_gdt_ro(smp_processor_id());
	76	}
	77
aa4ea675 AL	78	/* Provide the physical address of the GDT page. */
	79	static inline phys_addr_t get_cpu_gdt_paddr(unsigned int cpu)
	80	{
	81	return per_cpu_ptr_to_phys(get_cpu_gdt_rw(cpu));
	82	}
	83
507f90c9 GOC	84	static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func,
	85	unsigned dpl, unsigned ist, unsigned seg)
	86	{
64b163fa TG	87	gate->offset_low = (u16) func;
	88	gate->bits.p = 1;
	89	gate->bits.dpl = dpl;
	90	gate->bits.zero = 0;
	91	gate->bits.type = type;
	92	gate->offset_middle = (u16) (func >> 16);
	93	#ifdef CONFIG_X86_64
9a3865b1	94	gate->segment = __KERNEL_CS;
64b163fa TG	95	gate->bits.ist = ist;
	96	gate->reserved = 0;
	97	gate->offset_high = (u32) (func >> 32);
54cd0eac	98	#else
64b163fa TG	99	gate->segment = seg;
64b163fa TG	100	gate->bits.ist = 0;
54cd0eac	101	#endif
64b163fa	102	}
54cd0eac	103
746ff60f GOC	104	static inline int desc_empty(const void *ptr)
	105	{
	106	const u32 *desc = ptr;
9a3865b1	107
746ff60f GOC	108	return !(desc[0] \| desc[1]);
	109	}
	110
54cd0eac GOC	111	#ifdef CONFIG_PARAVIRT
	112	#include <asm/paravirt.h>
	113	#else
9a3865b1 IM	114	#define load_TR_desc() native_load_tr_desc()
	115	#define load_gdt(dtr) native_load_gdt(dtr)
	116	#define load_idt(dtr) native_load_idt(dtr)
	117	#define load_tr(tr) asm volatile("ltr %0"::"m" (tr))
	118	#define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt))
	119
	120	#define store_gdt(dtr) native_store_gdt(dtr)
9a3865b1 IM	121	#define store_tr(tr) (tr = native_store_tr())
	122
	123	#define load_TLS(t, cpu) native_load_tls(t, cpu)
	124	#define set_ldt native_set_ldt
	125
	126	#define write_ldt_entry(dt, entry, desc) native_write_ldt_entry(dt, entry, desc)
	127	#define write_gdt_entry(dt, entry, desc, type) native_write_gdt_entry(dt, entry, desc, type)
	128	#define write_idt_entry(dt, entry, g) native_write_idt_entry(dt, entry, g)
38ffbe66 JF	129
	130	static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
	131	{
	132	}
	133
	134	static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
	135	{
	136	}
	137	#endif /* CONFIG_PARAVIRT */
54cd0eac	138
8229d754 JSR	139	#define store_ldt(ldt) asm("sldt %0" : "=m"(ldt))
8229d754 JSR	140
9a3865b1	141	static inline void native_write_idt_entry(gate_desc idt, int entry, const gate_desc gate)
54cd0eac GOC	142	{
	143	memcpy(&idt[entry], gate, sizeof(*gate));
	144	}
	145
9a3865b1	146	static inline void native_write_ldt_entry(struct desc_struct ldt, int entry, const void desc)
54cd0eac GOC	147	{
	148	memcpy(&ldt[entry], desc, 8);
	149	}
	150
9a3865b1 IM	151	static inline void
9a3865b1 IM	152	native_write_gdt_entry(struct desc_struct gdt, int entry, const void desc, int type)
54cd0eac GOC	153	{
54cd0eac GOC	154	unsigned int size;
9a3865b1	155
54cd0eac	156	switch (type) {
9a3865b1 IM	157	case DESC_TSS: size = sizeof(tss_desc); break;
	158	case DESC_LDT: size = sizeof(ldt_desc); break;
	159	default: size = sizeof(*gdt); break;
54cd0eac	160	}
9a3865b1	161
54cd0eac GOC	162	memcpy(&gdt[entry], desc, size);
	163	}
	164
64b163fa TG	165	static inline void set_tssldt_descriptor(void *d, unsigned long addr,
64b163fa TG	166	unsigned type, unsigned size)
c81c6ca4	167	{
87cc0376	168	struct ldttss_desc *desc = d;
9a3865b1	169
f6e0eba1	170	memset(desc, 0, sizeof(*desc));
9a3865b1	171
87cc0376	172	desc->limit0 = (u16) size;
64b163fa TG	173	desc->base0 = (u16) addr;
64b163fa TG	174	desc->base1 = (addr >> 16) & 0xFF;
9a3865b1 IM	175	desc->type = type;
	176	desc->p = 1;
	177	desc->limit1 = (size >> 16) & 0xF;
64b163fa	178	desc->base2 = (addr >> 24) & 0xFF;
87cc0376	179	#ifdef CONFIG_X86_64
64b163fa	180	desc->base3 = (u32) (addr >> 32);
c81c6ca4 GOC	181	#endif
	182	}
	183
7fb983b4	184	static inline void __set_tss_desc(unsigned cpu, unsigned int entry, struct x86_hw_tss *addr)
c81c6ca4	185	{
69218e47	186	struct desc_struct *d = get_cpu_gdt_rw(cpu);
c81c6ca4 GOC	187	tss_desc tss;
c81c6ca4 GOC	188
f6e0eba1	189	set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS,
4f53ab14	190	__KERNEL_TSS_LIMIT);
c81c6ca4 GOC	191	write_gdt_entry(d, entry, &tss, DESC_TSS);
	192	}
	193
	194	#define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)
	195
54cd0eac GOC	196	static inline void native_set_ldt(const void *addr, unsigned int entries)
	197	{
	198	if (likely(entries == 0))
c1773a16	199	asm volatile("lldt %w0"::"q" (0));
54cd0eac GOC	200	else {
	201	unsigned cpu = smp_processor_id();
	202	ldt_desc ldt;
	203
5ac37f87 MK	204	set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT,
5ac37f87 MK	205	entries * LDT_ENTRY_SIZE - 1);
69218e47	206	write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_LDT,
54cd0eac	207	&ldt, DESC_LDT);
c1773a16	208	asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8));
54cd0eac GOC	209	}
	210	}
	211
45fc8757 TG	212	static inline void native_load_gdt(const struct desc_ptr *dtr)
	213	{
	214	asm volatile("lgdt %0"::"m" (*dtr));
	215	}
	216
	217	static inline void native_load_idt(const struct desc_ptr *dtr)
	218	{
	219	asm volatile("lidt %0"::"m" (*dtr));
	220	}
	221
	222	static inline void native_store_gdt(struct desc_ptr *dtr)
	223	{
	224	asm volatile("sgdt %0":"=m" (*dtr));
	225	}
	226
87930019	227	static inline void store_idt(struct desc_ptr *dtr)
45fc8757 TG	228	{
	229	asm volatile("sidt %0":"=m" (*dtr));
	230	}
	231
	232	/*
	233	* The LTR instruction marks the TSS GDT entry as busy. On 64-bit, the GDT is
	234	* a read-only remapping. To prevent a page fault, the GDT is switched to the
	235	* original writeable version when needed.
	236	*/
	237	#ifdef CONFIG_X86_64
54cd0eac GOC	238	static inline void native_load_tr_desc(void)
54cd0eac GOC	239	{
45fc8757 TG	240	struct desc_ptr gdt;
	241	int cpu = raw_smp_processor_id();
	242	bool restore = 0;
	243	struct desc_struct *fixmap_gdt;
	244
	245	native_store_gdt(&gdt);
	246	fixmap_gdt = get_cpu_gdt_ro(cpu);
	247
	248	/*
	249	* If the current GDT is the read-only fixmap, swap to the original
	250	* writeable version. Swap back at the end.
	251	*/
	252	if (gdt.address == (unsigned long)fixmap_gdt) {
	253	load_direct_gdt(cpu);
	254	restore = 1;
	255	}
54cd0eac	256	asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
45fc8757 TG	257	if (restore)
	258	load_fixmap_gdt(cpu);
	259	}
	260	#else
	261	static inline void native_load_tr_desc(void)
	262	{
	263	asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
	264	}
	265	#endif
	266
	267	static inline unsigned long native_store_tr(void)
	268	{
	269	unsigned long tr;
	270
	271	asm volatile("str %0":"=r" (tr));
	272
	273	return tr;
	274	}
	275
	276	static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
	277	{
	278	struct desc_struct *gdt = get_cpu_gdt_rw(cpu);
	279	unsigned int i;
	280
	281	for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
	282	gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
54cd0eac GOC	283	}
54cd0eac GOC	284
b7ceaec1 AL	285	DECLARE_PER_CPU(bool, __tss_limit_invalid);
b7ceaec1 AL	286
b7ffc44d AL	287	static inline void force_reload_TR(void)
b7ffc44d AL	288	{
69218e47	289	struct desc_struct *d = get_current_gdt_rw();
b7ffc44d AL	290	tss_desc tss;
	291
	292	memcpy(&tss, &d[GDT_ENTRY_TSS], sizeof(tss_desc));
	293
	294	/*
	295	* LTR requires an available TSS, and the TSS is currently
	296	* busy. Make it be available so that LTR will work.
	297	*/
	298	tss.type = DESC_TSS;
	299	write_gdt_entry(d, GDT_ENTRY_TSS, &tss, DESC_TSS);
	300
	301	load_TR_desc();
b7ceaec1	302	this_cpu_write(__tss_limit_invalid, false);
b7ffc44d AL	303	}
b7ffc44d AL	304
b7ceaec1 AL	305	/*
	306	* Call this if you need the TSS limit to be correct, which should be the case
	307	* if and only if you have TIF_IO_BITMAP set or you're switching to a task
	308	* with TIF_IO_BITMAP set.
	309	*/
	310	static inline void refresh_tss_limit(void)
b7ffc44d AL	311	{
	312	DEBUG_LOCKS_WARN_ON(preemptible());
	313
b7ceaec1	314	if (unlikely(this_cpu_read(__tss_limit_invalid)))
b7ffc44d	315	force_reload_TR();
b7ffc44d AL	316	}
	317
	318	/*
	319	* If you do something evil that corrupts the cached TSS limit (I'm looking
	320	* at you, VMX exits), call this function.
	321	*
	322	* The optimization here is that the TSS limit only matters for Linux if the
	323	* IO bitmap is in use. If the TSS limit gets forced to its minimum value,
	324	* everything works except that IO bitmap will be ignored and all CPL 3 IO
	325	* instructions will #GP, which is exactly what we want for normal tasks.
	326	*/
	327	static inline void invalidate_tss_limit(void)
	328	{
	329	DEBUG_LOCKS_WARN_ON(preemptible());
	330
	331	if (unlikely(test_thread_flag(TIF_IO_BITMAP)))
	332	force_reload_TR();
	333	else
b7ceaec1	334	this_cpu_write(__tss_limit_invalid, true);
b7ffc44d AL	335	}
b7ffc44d AL	336
e30ab185 AL	337	/* This intentionally ignores lm, since 32-bit apps don't have that field. */
e30ab185 AL	338	#define LDT_empty(info) \
c1773a16 JP	339	((info)->base_addr == 0 && \
	340	(info)->limit == 0 && \
	341	(info)->contents == 0 && \
	342	(info)->read_exec_only == 1 && \
	343	(info)->seg_32bit == 0 && \
	344	(info)->limit_in_pages == 0 && \
	345	(info)->seg_not_present == 1 && \
	346	(info)->useable == 0)
881c2975	347
3669ef9f AL	348	/* Lots of programs expect an all-zero user_desc to mean "no segment at all". */
	349	static inline bool LDT_zero(const struct user_desc *info)
	350	{
	351	return (info->base_addr == 0 &&
	352	info->limit == 0 &&
	353	info->contents == 0 &&
	354	info->read_exec_only == 0 &&
	355	info->seg_32bit == 0 &&
	356	info->limit_in_pages == 0 &&
	357	info->seg_not_present == 0 &&
	358	info->useable == 0);
	359	}
	360
881c2975 GOC	361	static inline void clear_LDT(void)
	362	{
	363	set_ldt(NULL, 0);
	364	}
	365
1bd5718c	366	static inline unsigned long get_desc_base(const struct desc_struct *desc)
cc697852	367	{
2c75910f	368	return (unsigned)(desc->base0 \| ((desc->base1) << 16) \| ((desc->base2) << 24));
cc697852	369	}
1bd5718c	370
57594742 AM	371	static inline void set_desc_base(struct desc_struct *desc, unsigned long base)
	372	{
	373	desc->base0 = base & 0xffff;
	374	desc->base1 = (base >> 16) & 0xff;
	375	desc->base2 = (base >> 24) & 0xff;
	376	}
	377
1bd5718c RM	378	static inline unsigned long get_desc_limit(const struct desc_struct *desc)
1bd5718c RM	379	{
38e9e81f	380	return desc->limit0 \| (desc->limit1 << 16);
1bd5718c RM	381	}
1bd5718c RM	382
57594742 AM	383	static inline void set_desc_limit(struct desc_struct *desc, unsigned long limit)
	384	{
	385	desc->limit0 = limit & 0xffff;
38e9e81f	386	desc->limit1 = (limit >> 16) & 0xf;
57594742 AM	387	}
57594742 AM	388
facaa3e3	389	void update_intr_gate(unsigned int n, const void *addr);
db18da78	390	void alloc_intr_gate(unsigned int n, const void *addr);
507f90c9	391
7854f822	392	extern unsigned long system_vectors[];
305b92a2	393
629f4f9d SA	394	#ifdef CONFIG_X86_64
	395	DECLARE_PER_CPU(u32, debug_idt_ctr);
	396	static inline bool is_debug_idt_enabled(void)
	397	{
	398	if (this_cpu_read(debug_idt_ctr))
	399	return true;
	400
	401	return false;
	402	}
	403
	404	static inline void load_debug_idt(void)
	405	{
	406	load_idt((const struct desc_ptr *)&debug_idt_descr);
	407	}
	408	#else
	409	static inline bool is_debug_idt_enabled(void)
	410	{
	411	return false;
	412	}
	413
	414	static inline void load_debug_idt(void)
	415	{
	416	}
	417	#endif
	418
	419	/*
2b4bc789	420	* The load_current_idt() must be called with interrupts disabled
629f4f9d	421	* to avoid races. That way the IDT will always be set back to the expected
2b4bc789 SRRH	422	* descriptor. It's also called when a CPU is being initialized, and
	423	* that doesn't need to disable interrupts, as nothing should be
	424	* bothering the CPU then.
629f4f9d SA	425	*/
	426	static inline void load_current_idt(void)
	427	{
629f4f9d SA	428	if (is_debug_idt_enabled())
	429	load_debug_idt();
	430	else
	431	load_idt((const struct desc_ptr *)&idt_descr);
629f4f9d	432	}
e802a51e	433
588787fd TG	434	extern void idt_setup_early_handler(void);
588787fd TG	435	extern void idt_setup_early_traps(void);
b70543a0	436	extern void idt_setup_traps(void);
636a7598	437	extern void idt_setup_apic_and_irq_gates(void);
588787fd TG	438
	439	#ifdef CONFIG_X86_64
	440	extern void idt_setup_early_pf(void);
90f6225f	441	extern void idt_setup_ist_traps(void);
0a30908b	442	extern void idt_setup_debugidt_traps(void);
588787fd TG	443	#else
588787fd TG	444	static inline void idt_setup_early_pf(void) { }
90f6225f	445	static inline void idt_setup_ist_traps(void) { }
0a30908b	446	static inline void idt_setup_debugidt_traps(void) { }
588787fd TG	447	#endif
588787fd TG	448
e802a51e TG	449	extern void idt_invalidate(void *addr);
e802a51e TG	450
1965aae3	451	#endif /* _ASM_X86_DESC_H */