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1361b83a LT |
1 | /* |
2 | * Copyright (C) 1994 Linus Torvalds | |
3 | * | |
4 | * Pentium III FXSR, SSE support | |
5 | * General FPU state handling cleanups | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | * x86-64 work by Andi Kleen 2002 | |
8 | */ | |
9 | ||
78f7f1e5 IM |
10 | #ifndef _ASM_X86_FPU_INTERNAL_H |
11 | #define _ASM_X86_FPU_INTERNAL_H | |
1361b83a | 12 | |
050902c0 | 13 | #include <linux/compat.h> |
952f07ec | 14 | #include <linux/sched.h> |
1361b83a | 15 | #include <linux/slab.h> |
f89e32e0 | 16 | |
1361b83a | 17 | #include <asm/user.h> |
df6b35f4 | 18 | #include <asm/fpu/api.h> |
669ebabb | 19 | #include <asm/fpu/xstate.h> |
1361b83a | 20 | |
6ffc152e IM |
21 | /* |
22 | * High level FPU state handling functions: | |
23 | */ | |
0c306bcf | 24 | extern void fpu__activate_curr(struct fpu *fpu); |
05602812 | 25 | extern void fpu__activate_fpstate_read(struct fpu *fpu); |
6a81d7eb | 26 | extern void fpu__activate_fpstate_write(struct fpu *fpu); |
6ffc152e | 27 | extern void fpu__save(struct fpu *fpu); |
e1884d69 | 28 | extern void fpu__restore(struct fpu *fpu); |
82c0e45e | 29 | extern int fpu__restore_sig(void __user *buf, int ia32_frame); |
6ffc152e IM |
30 | extern void fpu__drop(struct fpu *fpu); |
31 | extern int fpu__copy(struct fpu *dst_fpu, struct fpu *src_fpu); | |
04c8e01d | 32 | extern void fpu__clear(struct fpu *fpu); |
b1b64dc3 IM |
33 | extern int fpu__exception_code(struct fpu *fpu, int trap_nr); |
34 | extern int dump_fpu(struct pt_regs *ptregs, struct user_i387_struct *fpstate); | |
6ffc152e | 35 | |
b1b64dc3 IM |
36 | /* |
37 | * Boot time FPU initialization functions: | |
38 | */ | |
39 | extern void fpu__init_cpu(void); | |
40 | extern void fpu__init_system_xstate(void); | |
41 | extern void fpu__init_cpu_xstate(void); | |
42 | extern void fpu__init_system(struct cpuinfo_x86 *c); | |
952f07ec IM |
43 | extern void fpu__init_check_bugs(void); |
44 | extern void fpu__resume_cpu(void); | |
45 | ||
e97131a8 IM |
46 | /* |
47 | * Debugging facility: | |
48 | */ | |
49 | #ifdef CONFIG_X86_DEBUG_FPU | |
50 | # define WARN_ON_FPU(x) WARN_ON_ONCE(x) | |
51 | #else | |
83242c51 | 52 | # define WARN_ON_FPU(x) ({ (void)(x); 0; }) |
e97131a8 IM |
53 | #endif |
54 | ||
1c927eea | 55 | /* |
b1b64dc3 | 56 | * FPU related CPU feature flag helper routines: |
1c927eea | 57 | */ |
5d2bd700 SS |
58 | static __always_inline __pure bool use_eager_fpu(void) |
59 | { | |
c6b40691 | 60 | return static_cpu_has_safe(X86_FEATURE_EAGER_FPU); |
5d2bd700 SS |
61 | } |
62 | ||
1361b83a LT |
63 | static __always_inline __pure bool use_xsaveopt(void) |
64 | { | |
c6b40691 | 65 | return static_cpu_has_safe(X86_FEATURE_XSAVEOPT); |
1361b83a LT |
66 | } |
67 | ||
68 | static __always_inline __pure bool use_xsave(void) | |
69 | { | |
c6b40691 | 70 | return static_cpu_has_safe(X86_FEATURE_XSAVE); |
1361b83a LT |
71 | } |
72 | ||
73 | static __always_inline __pure bool use_fxsr(void) | |
74 | { | |
c6b40691 | 75 | return static_cpu_has_safe(X86_FEATURE_FXSR); |
1361b83a LT |
76 | } |
77 | ||
b1b64dc3 IM |
78 | /* |
79 | * fpstate handling functions: | |
80 | */ | |
81 | ||
82 | extern union fpregs_state init_fpstate; | |
83 | ||
84 | extern void fpstate_init(union fpregs_state *state); | |
85 | #ifdef CONFIG_MATH_EMULATION | |
86 | extern void fpstate_init_soft(struct swregs_state *soft); | |
87 | #else | |
88 | static inline void fpstate_init_soft(struct swregs_state *soft) {} | |
89 | #endif | |
90 | static inline void fpstate_init_fxstate(struct fxregs_state *fx) | |
91 | { | |
92 | fx->cwd = 0x37f; | |
93 | fx->mxcsr = MXCSR_DEFAULT; | |
94 | } | |
36e49e7f | 95 | extern void fpstate_sanitize_xstate(struct fpu *fpu); |
1361b83a | 96 | |
49b8c695 PA |
97 | #define user_insn(insn, output, input...) \ |
98 | ({ \ | |
99 | int err; \ | |
100 | asm volatile(ASM_STAC "\n" \ | |
101 | "1:" #insn "\n\t" \ | |
102 | "2: " ASM_CLAC "\n" \ | |
103 | ".section .fixup,\"ax\"\n" \ | |
104 | "3: movl $-1,%[err]\n" \ | |
105 | " jmp 2b\n" \ | |
106 | ".previous\n" \ | |
107 | _ASM_EXTABLE(1b, 3b) \ | |
108 | : [err] "=r" (err), output \ | |
109 | : "0"(0), input); \ | |
110 | err; \ | |
111 | }) | |
112 | ||
0ca5bd0d SS |
113 | #define check_insn(insn, output, input...) \ |
114 | ({ \ | |
115 | int err; \ | |
116 | asm volatile("1:" #insn "\n\t" \ | |
117 | "2:\n" \ | |
118 | ".section .fixup,\"ax\"\n" \ | |
119 | "3: movl $-1,%[err]\n" \ | |
120 | " jmp 2b\n" \ | |
121 | ".previous\n" \ | |
122 | _ASM_EXTABLE(1b, 3b) \ | |
123 | : [err] "=r" (err), output \ | |
124 | : "0"(0), input); \ | |
125 | err; \ | |
126 | }) | |
127 | ||
c47ada30 | 128 | static inline int copy_fregs_to_user(struct fregs_state __user *fx) |
1361b83a | 129 | { |
49b8c695 | 130 | return user_insn(fnsave %[fx]; fwait, [fx] "=m" (*fx), "m" (*fx)); |
1361b83a LT |
131 | } |
132 | ||
c47ada30 | 133 | static inline int copy_fxregs_to_user(struct fxregs_state __user *fx) |
1361b83a | 134 | { |
0ca5bd0d | 135 | if (config_enabled(CONFIG_X86_32)) |
49b8c695 | 136 | return user_insn(fxsave %[fx], [fx] "=m" (*fx), "m" (*fx)); |
0ca5bd0d | 137 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) |
49b8c695 | 138 | return user_insn(fxsaveq %[fx], [fx] "=m" (*fx), "m" (*fx)); |
1361b83a | 139 | |
c6813144 | 140 | /* See comment in copy_fxregs_to_kernel() below. */ |
49b8c695 | 141 | return user_insn(rex64/fxsave (%[fx]), "=m" (*fx), [fx] "R" (fx)); |
1361b83a LT |
142 | } |
143 | ||
9ccc27a5 | 144 | static inline void copy_kernel_to_fxregs(struct fxregs_state *fx) |
1361b83a | 145 | { |
43b287b3 IM |
146 | int err; |
147 | ||
148 | if (config_enabled(CONFIG_X86_32)) { | |
149 | err = check_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
150 | } else { | |
151 | if (config_enabled(CONFIG_AS_FXSAVEQ)) { | |
152 | err = check_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
153 | } else { | |
154 | /* See comment in copy_fxregs_to_kernel() below. */ | |
155 | err = check_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx), "m" (*fx)); | |
156 | } | |
157 | } | |
158 | /* Copying from a kernel buffer to FPU registers should never fail: */ | |
159 | WARN_ON_FPU(err); | |
1361b83a LT |
160 | } |
161 | ||
c47ada30 | 162 | static inline int copy_user_to_fxregs(struct fxregs_state __user *fx) |
e139e955 PA |
163 | { |
164 | if (config_enabled(CONFIG_X86_32)) | |
165 | return user_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
166 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) | |
167 | return user_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
168 | ||
c6813144 | 169 | /* See comment in copy_fxregs_to_kernel() below. */ |
e139e955 PA |
170 | return user_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx), |
171 | "m" (*fx)); | |
172 | } | |
173 | ||
9ccc27a5 | 174 | static inline void copy_kernel_to_fregs(struct fregs_state *fx) |
1361b83a | 175 | { |
43b287b3 IM |
176 | int err = check_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx)); |
177 | ||
178 | WARN_ON_FPU(err); | |
e139e955 PA |
179 | } |
180 | ||
c47ada30 | 181 | static inline int copy_user_to_fregs(struct fregs_state __user *fx) |
e139e955 PA |
182 | { |
183 | return user_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
1361b83a LT |
184 | } |
185 | ||
c6813144 | 186 | static inline void copy_fxregs_to_kernel(struct fpu *fpu) |
1361b83a | 187 | { |
0ca5bd0d | 188 | if (config_enabled(CONFIG_X86_32)) |
7366ed77 | 189 | asm volatile( "fxsave %[fx]" : [fx] "=m" (fpu->state.fxsave)); |
0ca5bd0d | 190 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) |
7366ed77 | 191 | asm volatile("fxsaveq %[fx]" : [fx] "=m" (fpu->state.fxsave)); |
0ca5bd0d SS |
192 | else { |
193 | /* Using "rex64; fxsave %0" is broken because, if the memory | |
194 | * operand uses any extended registers for addressing, a second | |
195 | * REX prefix will be generated (to the assembler, rex64 | |
196 | * followed by semicolon is a separate instruction), and hence | |
197 | * the 64-bitness is lost. | |
198 | * | |
199 | * Using "fxsaveq %0" would be the ideal choice, but is only | |
200 | * supported starting with gas 2.16. | |
201 | * | |
202 | * Using, as a workaround, the properly prefixed form below | |
203 | * isn't accepted by any binutils version so far released, | |
204 | * complaining that the same type of prefix is used twice if | |
205 | * an extended register is needed for addressing (fix submitted | |
206 | * to mainline 2005-11-21). | |
207 | * | |
7366ed77 | 208 | * asm volatile("rex64/fxsave %0" : "=m" (fpu->state.fxsave)); |
0ca5bd0d SS |
209 | * |
210 | * This, however, we can work around by forcing the compiler to | |
211 | * select an addressing mode that doesn't require extended | |
212 | * registers. | |
213 | */ | |
214 | asm volatile( "rex64/fxsave (%[fx])" | |
7366ed77 IM |
215 | : "=m" (fpu->state.fxsave) |
216 | : [fx] "R" (&fpu->state.fxsave)); | |
0ca5bd0d | 217 | } |
1361b83a LT |
218 | } |
219 | ||
fd169b05 IM |
220 | /* These macros all use (%edi)/(%rdi) as the single memory argument. */ |
221 | #define XSAVE ".byte " REX_PREFIX "0x0f,0xae,0x27" | |
222 | #define XSAVEOPT ".byte " REX_PREFIX "0x0f,0xae,0x37" | |
223 | #define XSAVES ".byte " REX_PREFIX "0x0f,0xc7,0x2f" | |
224 | #define XRSTOR ".byte " REX_PREFIX "0x0f,0xae,0x2f" | |
225 | #define XRSTORS ".byte " REX_PREFIX "0x0f,0xc7,0x1f" | |
226 | ||
b74a0cf1 BP |
227 | #define XSTATE_OP(op, st, lmask, hmask, err) \ |
228 | asm volatile("1:" op "\n\t" \ | |
229 | "xor %[err], %[err]\n" \ | |
230 | "2:\n\t" \ | |
231 | ".pushsection .fixup,\"ax\"\n\t" \ | |
232 | "3: movl $-2,%[err]\n\t" \ | |
233 | "jmp 2b\n\t" \ | |
234 | ".popsection\n\t" \ | |
235 | _ASM_EXTABLE(1b, 3b) \ | |
236 | : [err] "=r" (err) \ | |
237 | : "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \ | |
238 | : "memory") | |
239 | ||
b7106fa0 BP |
240 | /* |
241 | * If XSAVES is enabled, it replaces XSAVEOPT because it supports a compact | |
242 | * format and supervisor states in addition to modified optimization in | |
243 | * XSAVEOPT. | |
244 | * | |
245 | * Otherwise, if XSAVEOPT is enabled, XSAVEOPT replaces XSAVE because XSAVEOPT | |
246 | * supports modified optimization which is not supported by XSAVE. | |
247 | * | |
248 | * We use XSAVE as a fallback. | |
249 | * | |
250 | * The 661 label is defined in the ALTERNATIVE* macros as the address of the | |
251 | * original instruction which gets replaced. We need to use it here as the | |
252 | * address of the instruction where we might get an exception at. | |
253 | */ | |
254 | #define XSTATE_XSAVE(st, lmask, hmask, err) \ | |
255 | asm volatile(ALTERNATIVE_2(XSAVE, \ | |
256 | XSAVEOPT, X86_FEATURE_XSAVEOPT, \ | |
257 | XSAVES, X86_FEATURE_XSAVES) \ | |
258 | "\n" \ | |
259 | "xor %[err], %[err]\n" \ | |
260 | "3:\n" \ | |
261 | ".pushsection .fixup,\"ax\"\n" \ | |
262 | "4: movl $-2, %[err]\n" \ | |
263 | "jmp 3b\n" \ | |
264 | ".popsection\n" \ | |
265 | _ASM_EXTABLE(661b, 4b) \ | |
266 | : [err] "=r" (err) \ | |
267 | : "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \ | |
268 | : "memory") | |
269 | ||
270 | /* | |
271 | * Use XRSTORS to restore context if it is enabled. XRSTORS supports compact | |
272 | * XSAVE area format. | |
273 | */ | |
274 | #define XSTATE_XRESTORE(st, lmask, hmask, err) \ | |
275 | asm volatile(ALTERNATIVE(XRSTOR, \ | |
276 | XRSTORS, X86_FEATURE_XSAVES) \ | |
277 | "\n" \ | |
278 | "xor %[err], %[err]\n" \ | |
279 | "3:\n" \ | |
280 | ".pushsection .fixup,\"ax\"\n" \ | |
281 | "4: movl $-2, %[err]\n" \ | |
282 | "jmp 3b\n" \ | |
283 | ".popsection\n" \ | |
284 | _ASM_EXTABLE(661b, 4b) \ | |
285 | : [err] "=r" (err) \ | |
286 | : "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \ | |
287 | : "memory") | |
b74a0cf1 | 288 | |
fd169b05 IM |
289 | /* |
290 | * This function is called only during boot time when x86 caps are not set | |
291 | * up and alternative can not be used yet. | |
292 | */ | |
8c05f05e | 293 | static inline void copy_xregs_to_kernel_booting(struct xregs_state *xstate) |
fd169b05 IM |
294 | { |
295 | u64 mask = -1; | |
296 | u32 lmask = mask; | |
297 | u32 hmask = mask >> 32; | |
b74a0cf1 | 298 | int err; |
fd169b05 IM |
299 | |
300 | WARN_ON(system_state != SYSTEM_BOOTING); | |
301 | ||
b74a0cf1 BP |
302 | if (static_cpu_has_safe(X86_FEATURE_XSAVES)) |
303 | XSTATE_OP(XSAVES, xstate, lmask, hmask, err); | |
fd169b05 | 304 | else |
b74a0cf1 | 305 | XSTATE_OP(XSAVE, xstate, lmask, hmask, err); |
8c05f05e IM |
306 | |
307 | /* We should never fault when copying to a kernel buffer: */ | |
308 | WARN_ON_FPU(err); | |
fd169b05 IM |
309 | } |
310 | ||
311 | /* | |
312 | * This function is called only during boot time when x86 caps are not set | |
313 | * up and alternative can not be used yet. | |
314 | */ | |
d65fcd60 | 315 | static inline void copy_kernel_to_xregs_booting(struct xregs_state *xstate) |
fd169b05 | 316 | { |
d65fcd60 | 317 | u64 mask = -1; |
fd169b05 IM |
318 | u32 lmask = mask; |
319 | u32 hmask = mask >> 32; | |
b74a0cf1 | 320 | int err; |
fd169b05 IM |
321 | |
322 | WARN_ON(system_state != SYSTEM_BOOTING); | |
323 | ||
b74a0cf1 BP |
324 | if (static_cpu_has_safe(X86_FEATURE_XSAVES)) |
325 | XSTATE_OP(XRSTORS, xstate, lmask, hmask, err); | |
fd169b05 | 326 | else |
b74a0cf1 | 327 | XSTATE_OP(XRSTOR, xstate, lmask, hmask, err); |
8c05f05e IM |
328 | |
329 | /* We should never fault when copying from a kernel buffer: */ | |
330 | WARN_ON_FPU(err); | |
fd169b05 IM |
331 | } |
332 | ||
333 | /* | |
334 | * Save processor xstate to xsave area. | |
335 | */ | |
8c05f05e | 336 | static inline void copy_xregs_to_kernel(struct xregs_state *xstate) |
fd169b05 IM |
337 | { |
338 | u64 mask = -1; | |
339 | u32 lmask = mask; | |
340 | u32 hmask = mask >> 32; | |
b7106fa0 | 341 | int err; |
fd169b05 IM |
342 | |
343 | WARN_ON(!alternatives_patched); | |
344 | ||
b7106fa0 | 345 | XSTATE_XSAVE(xstate, lmask, hmask, err); |
fd169b05 | 346 | |
8c05f05e IM |
347 | /* We should never fault when copying to a kernel buffer: */ |
348 | WARN_ON_FPU(err); | |
fd169b05 IM |
349 | } |
350 | ||
351 | /* | |
352 | * Restore processor xstate from xsave area. | |
353 | */ | |
8c05f05e | 354 | static inline void copy_kernel_to_xregs(struct xregs_state *xstate, u64 mask) |
fd169b05 | 355 | { |
fd169b05 IM |
356 | u32 lmask = mask; |
357 | u32 hmask = mask >> 32; | |
b7106fa0 | 358 | int err; |
fd169b05 | 359 | |
b7106fa0 | 360 | XSTATE_XRESTORE(xstate, lmask, hmask, err); |
fd169b05 | 361 | |
8c05f05e IM |
362 | /* We should never fault when copying from a kernel buffer: */ |
363 | WARN_ON_FPU(err); | |
fd169b05 IM |
364 | } |
365 | ||
366 | /* | |
367 | * Save xstate to user space xsave area. | |
368 | * | |
369 | * We don't use modified optimization because xrstor/xrstors might track | |
370 | * a different application. | |
371 | * | |
372 | * We don't use compacted format xsave area for | |
373 | * backward compatibility for old applications which don't understand | |
374 | * compacted format of xsave area. | |
375 | */ | |
376 | static inline int copy_xregs_to_user(struct xregs_state __user *buf) | |
377 | { | |
378 | int err; | |
379 | ||
380 | /* | |
381 | * Clear the xsave header first, so that reserved fields are | |
382 | * initialized to zero. | |
383 | */ | |
384 | err = __clear_user(&buf->header, sizeof(buf->header)); | |
385 | if (unlikely(err)) | |
386 | return -EFAULT; | |
387 | ||
b74a0cf1 BP |
388 | stac(); |
389 | XSTATE_OP(XSAVE, buf, -1, -1, err); | |
390 | clac(); | |
391 | ||
fd169b05 IM |
392 | return err; |
393 | } | |
394 | ||
395 | /* | |
396 | * Restore xstate from user space xsave area. | |
397 | */ | |
398 | static inline int copy_user_to_xregs(struct xregs_state __user *buf, u64 mask) | |
399 | { | |
fd169b05 IM |
400 | struct xregs_state *xstate = ((__force struct xregs_state *)buf); |
401 | u32 lmask = mask; | |
402 | u32 hmask = mask >> 32; | |
b74a0cf1 BP |
403 | int err; |
404 | ||
405 | stac(); | |
406 | XSTATE_OP(XRSTOR, xstate, lmask, hmask, err); | |
407 | clac(); | |
fd169b05 | 408 | |
fd169b05 IM |
409 | return err; |
410 | } | |
411 | ||
1361b83a LT |
412 | /* |
413 | * These must be called with preempt disabled. Returns | |
4f836347 IM |
414 | * 'true' if the FPU state is still intact and we can |
415 | * keep registers active. | |
416 | * | |
417 | * The legacy FNSAVE instruction cleared all FPU state | |
418 | * unconditionally, so registers are essentially destroyed. | |
419 | * Modern FPU state can be kept in registers, if there are | |
1bc6b056 | 420 | * no pending FP exceptions. |
1361b83a | 421 | */ |
4f836347 | 422 | static inline int copy_fpregs_to_fpstate(struct fpu *fpu) |
1361b83a | 423 | { |
1bc6b056 | 424 | if (likely(use_xsave())) { |
c6813144 | 425 | copy_xregs_to_kernel(&fpu->state.xsave); |
1bc6b056 IM |
426 | return 1; |
427 | } | |
1361b83a | 428 | |
1bc6b056 | 429 | if (likely(use_fxsr())) { |
c6813144 | 430 | copy_fxregs_to_kernel(fpu); |
1bc6b056 | 431 | return 1; |
1361b83a LT |
432 | } |
433 | ||
434 | /* | |
1bc6b056 IM |
435 | * Legacy FPU register saving, FNSAVE always clears FPU registers, |
436 | * so we have to mark them inactive: | |
1361b83a | 437 | */ |
87dafd41 | 438 | asm volatile("fnsave %[fp]; fwait" : [fp] "=m" (fpu->state.fsave)); |
4f836347 | 439 | |
4f836347 | 440 | return 0; |
1361b83a LT |
441 | } |
442 | ||
003e2e8b | 443 | static inline void __copy_kernel_to_fpregs(union fpregs_state *fpstate) |
1361b83a | 444 | { |
8c05f05e | 445 | if (use_xsave()) { |
003e2e8b | 446 | copy_kernel_to_xregs(&fpstate->xsave, -1); |
8c05f05e IM |
447 | } else { |
448 | if (use_fxsr()) | |
003e2e8b | 449 | copy_kernel_to_fxregs(&fpstate->fxsave); |
8c05f05e | 450 | else |
003e2e8b | 451 | copy_kernel_to_fregs(&fpstate->fsave); |
8c05f05e | 452 | } |
1361b83a LT |
453 | } |
454 | ||
003e2e8b | 455 | static inline void copy_kernel_to_fpregs(union fpregs_state *fpstate) |
1361b83a | 456 | { |
6ca7a8a1 BP |
457 | /* |
458 | * AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception is | |
459 | * pending. Clear the x87 state here by setting it to fixed values. | |
460 | * "m" is a random variable that should be in L1. | |
461 | */ | |
9b13a93d | 462 | if (unlikely(static_cpu_has_bug_safe(X86_BUG_FXSAVE_LEAK))) { |
26bef131 LT |
463 | asm volatile( |
464 | "fnclex\n\t" | |
465 | "emms\n\t" | |
466 | "fildl %P[addr]" /* set F?P to defined value */ | |
003e2e8b | 467 | : : [addr] "m" (fpstate)); |
26bef131 | 468 | } |
1361b83a | 469 | |
003e2e8b | 470 | __copy_kernel_to_fpregs(fpstate); |
1361b83a LT |
471 | } |
472 | ||
87dafd41 | 473 | extern int copy_fpstate_to_sigframe(void __user *buf, void __user *fp, int size); |
b1b64dc3 IM |
474 | |
475 | /* | |
476 | * FPU context switch related helper methods: | |
477 | */ | |
478 | ||
479 | DECLARE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx); | |
480 | ||
481 | /* | |
482 | * Must be run with preemption disabled: this clears the fpu_fpregs_owner_ctx, | |
483 | * on this CPU. | |
484 | * | |
485 | * This will disable any lazy FPU state restore of the current FPU state, | |
486 | * but if the current thread owns the FPU, it will still be saved by. | |
487 | */ | |
488 | static inline void __cpu_disable_lazy_restore(unsigned int cpu) | |
489 | { | |
490 | per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; | |
491 | } | |
492 | ||
493 | static inline int fpu_want_lazy_restore(struct fpu *fpu, unsigned int cpu) | |
494 | { | |
495 | return fpu == this_cpu_read_stable(fpu_fpregs_owner_ctx) && cpu == fpu->last_cpu; | |
496 | } | |
497 | ||
498 | ||
32b49b3c IM |
499 | /* |
500 | * Wrap lazy FPU TS handling in a 'hw fpregs activation/deactivation' | |
501 | * idiom, which is then paired with the sw-flag (fpregs_active) later on: | |
502 | */ | |
503 | ||
504 | static inline void __fpregs_activate_hw(void) | |
505 | { | |
506 | if (!use_eager_fpu()) | |
507 | clts(); | |
508 | } | |
509 | ||
510 | static inline void __fpregs_deactivate_hw(void) | |
511 | { | |
512 | if (!use_eager_fpu()) | |
513 | stts(); | |
514 | } | |
515 | ||
516 | /* Must be paired with an 'stts' (fpregs_deactivate_hw()) after! */ | |
723c58e4 | 517 | static inline void __fpregs_deactivate(struct fpu *fpu) |
1361b83a | 518 | { |
e97131a8 IM |
519 | WARN_ON_FPU(!fpu->fpregs_active); |
520 | ||
d5cea9b0 | 521 | fpu->fpregs_active = 0; |
36b544dc | 522 | this_cpu_write(fpu_fpregs_owner_ctx, NULL); |
1361b83a LT |
523 | } |
524 | ||
32b49b3c | 525 | /* Must be paired with a 'clts' (fpregs_activate_hw()) before! */ |
dfaea4e6 | 526 | static inline void __fpregs_activate(struct fpu *fpu) |
1361b83a | 527 | { |
e97131a8 IM |
528 | WARN_ON_FPU(fpu->fpregs_active); |
529 | ||
d5cea9b0 | 530 | fpu->fpregs_active = 1; |
c0311f63 | 531 | this_cpu_write(fpu_fpregs_owner_ctx, fpu); |
1361b83a LT |
532 | } |
533 | ||
952f07ec IM |
534 | /* |
535 | * The question "does this thread have fpu access?" | |
536 | * is slightly racy, since preemption could come in | |
537 | * and revoke it immediately after the test. | |
538 | * | |
539 | * However, even in that very unlikely scenario, | |
540 | * we can just assume we have FPU access - typically | |
541 | * to save the FP state - we'll just take a #NM | |
542 | * fault and get the FPU access back. | |
543 | */ | |
3c6dffa9 | 544 | static inline int fpregs_active(void) |
952f07ec IM |
545 | { |
546 | return current->thread.fpu.fpregs_active; | |
547 | } | |
548 | ||
1361b83a LT |
549 | /* |
550 | * Encapsulate the CR0.TS handling together with the | |
551 | * software flag. | |
552 | * | |
553 | * These generally need preemption protection to work, | |
554 | * do try to avoid using these on their own. | |
555 | */ | |
66af8e27 | 556 | static inline void fpregs_activate(struct fpu *fpu) |
1361b83a | 557 | { |
32b49b3c | 558 | __fpregs_activate_hw(); |
66af8e27 | 559 | __fpregs_activate(fpu); |
1361b83a LT |
560 | } |
561 | ||
66af8e27 | 562 | static inline void fpregs_deactivate(struct fpu *fpu) |
1361b83a | 563 | { |
66af8e27 | 564 | __fpregs_deactivate(fpu); |
32b49b3c | 565 | __fpregs_deactivate_hw(); |
1361b83a LT |
566 | } |
567 | ||
568 | /* | |
569 | * FPU state switching for scheduling. | |
570 | * | |
571 | * This is a two-stage process: | |
572 | * | |
573 | * - switch_fpu_prepare() saves the old state and | |
574 | * sets the new state of the CR0.TS bit. This is | |
575 | * done within the context of the old process. | |
576 | * | |
577 | * - switch_fpu_finish() restores the new state as | |
578 | * necessary. | |
579 | */ | |
580 | typedef struct { int preload; } fpu_switch_t; | |
581 | ||
cb8818b6 IM |
582 | static inline fpu_switch_t |
583 | switch_fpu_prepare(struct fpu *old_fpu, struct fpu *new_fpu, int cpu) | |
1361b83a LT |
584 | { |
585 | fpu_switch_t fpu; | |
586 | ||
304bceda SS |
587 | /* |
588 | * If the task has used the math, pre-load the FPU on xsave processors | |
589 | * or if the past 5 consecutive context-switches used math. | |
590 | */ | |
c5bedc68 | 591 | fpu.preload = new_fpu->fpstate_active && |
cb8818b6 | 592 | (use_eager_fpu() || new_fpu->counter > 5); |
1361ef29 | 593 | |
d5cea9b0 | 594 | if (old_fpu->fpregs_active) { |
4f836347 | 595 | if (!copy_fpregs_to_fpstate(old_fpu)) |
cb8818b6 | 596 | old_fpu->last_cpu = -1; |
1361ef29 | 597 | else |
cb8818b6 | 598 | old_fpu->last_cpu = cpu; |
1361ef29 | 599 | |
36b544dc | 600 | /* But leave fpu_fpregs_owner_ctx! */ |
d5cea9b0 | 601 | old_fpu->fpregs_active = 0; |
1361b83a LT |
602 | |
603 | /* Don't change CR0.TS if we just switch! */ | |
604 | if (fpu.preload) { | |
cb8818b6 | 605 | new_fpu->counter++; |
dfaea4e6 | 606 | __fpregs_activate(new_fpu); |
7366ed77 | 607 | prefetch(&new_fpu->state); |
32b49b3c IM |
608 | } else { |
609 | __fpregs_deactivate_hw(); | |
610 | } | |
1361b83a | 611 | } else { |
cb8818b6 IM |
612 | old_fpu->counter = 0; |
613 | old_fpu->last_cpu = -1; | |
1361b83a | 614 | if (fpu.preload) { |
cb8818b6 | 615 | new_fpu->counter++; |
66ddc2cb | 616 | if (fpu_want_lazy_restore(new_fpu, cpu)) |
1361b83a LT |
617 | fpu.preload = 0; |
618 | else | |
7366ed77 | 619 | prefetch(&new_fpu->state); |
232f62cd | 620 | fpregs_activate(new_fpu); |
1361b83a LT |
621 | } |
622 | } | |
623 | return fpu; | |
624 | } | |
625 | ||
b1b64dc3 IM |
626 | /* |
627 | * Misc helper functions: | |
628 | */ | |
629 | ||
1361b83a LT |
630 | /* |
631 | * By the time this gets called, we've already cleared CR0.TS and | |
632 | * given the process the FPU if we are going to preload the FPU | |
633 | * state - all we need to do is to conditionally restore the register | |
634 | * state itself. | |
635 | */ | |
384a23f9 | 636 | static inline void switch_fpu_finish(struct fpu *new_fpu, fpu_switch_t fpu_switch) |
1361b83a | 637 | { |
9ccc27a5 | 638 | if (fpu_switch.preload) |
003e2e8b | 639 | copy_kernel_to_fpregs(&new_fpu->state); |
1361b83a LT |
640 | } |
641 | ||
1361b83a | 642 | /* |
fb14b4ea | 643 | * Needs to be preemption-safe. |
1361b83a | 644 | * |
377ffbcc | 645 | * NOTE! user_fpu_begin() must be used only immediately before restoring |
fb14b4ea ON |
646 | * the save state. It does not do any saving/restoring on its own. In |
647 | * lazy FPU mode, it is just an optimization to avoid a #NM exception, | |
648 | * the task can lose the FPU right after preempt_enable(). | |
1361b83a | 649 | */ |
1361b83a LT |
650 | static inline void user_fpu_begin(void) |
651 | { | |
4540d3fa IM |
652 | struct fpu *fpu = ¤t->thread.fpu; |
653 | ||
1361b83a | 654 | preempt_disable(); |
3c6dffa9 | 655 | if (!fpregs_active()) |
232f62cd | 656 | fpregs_activate(fpu); |
1361b83a LT |
657 | preempt_enable(); |
658 | } | |
659 | ||
b1b64dc3 IM |
660 | /* |
661 | * MXCSR and XCR definitions: | |
662 | */ | |
663 | ||
664 | extern unsigned int mxcsr_feature_mask; | |
665 | ||
666 | #define XCR_XFEATURE_ENABLED_MASK 0x00000000 | |
667 | ||
668 | static inline u64 xgetbv(u32 index) | |
669 | { | |
670 | u32 eax, edx; | |
671 | ||
672 | asm volatile(".byte 0x0f,0x01,0xd0" /* xgetbv */ | |
673 | : "=a" (eax), "=d" (edx) | |
674 | : "c" (index)); | |
675 | return eax + ((u64)edx << 32); | |
676 | } | |
677 | ||
678 | static inline void xsetbv(u32 index, u64 value) | |
679 | { | |
680 | u32 eax = value; | |
681 | u32 edx = value >> 32; | |
682 | ||
683 | asm volatile(".byte 0x0f,0x01,0xd1" /* xsetbv */ | |
684 | : : "a" (eax), "d" (edx), "c" (index)); | |
685 | } | |
686 | ||
78f7f1e5 | 687 | #endif /* _ASM_X86_FPU_INTERNAL_H */ |