[mirror_ubuntu-artful-kernel.git] / arch / x86 / include / asm / mce.h

#ifndef _ASM_X86_MCE_H
#define _ASM_X86_MCE_H

#include <uapi/asm/mce.h>

/*
 * Machine Check support for x86
 */

/* MCG_CAP register defines */
#define MCG_BANKCNT_MASK	0xff         /* Number of Banks */
#define MCG_CTL_P		(1ULL<<8)    /* MCG_CTL register available */
#define MCG_EXT_P		(1ULL<<9)    /* Extended registers available */
#define MCG_CMCI_P		(1ULL<<10)   /* CMCI supported */
#define MCG_EXT_CNT_MASK	0xff0000     /* Number of Extended registers */
#define MCG_EXT_CNT_SHIFT	16
#define MCG_EXT_CNT(c)		(((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
#define MCG_SER_P		(1ULL<<24)   /* MCA recovery/new status bits */
#define MCG_ELOG_P		(1ULL<<26)   /* Extended error log supported */

/* MCG_STATUS register defines */
#define MCG_STATUS_RIPV  (1ULL<<0)   /* restart ip valid */
#define MCG_STATUS_EIPV  (1ULL<<1)   /* ip points to correct instruction */
#define MCG_STATUS_MCIP  (1ULL<<2)   /* machine check in progress */

/* MCi_STATUS register defines */
#define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
#define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
#define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
#define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
#define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
#define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
#define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
#define MCI_STATUS_S	 (1ULL<<56)  /* Signaled machine check */
#define MCI_STATUS_AR	 (1ULL<<55)  /* Action required */

/* AMD-specific bits */
#define MCI_STATUS_DEFERRED	(1ULL<<44)  /* declare an uncorrected error */
#define MCI_STATUS_POISON	(1ULL<<43)  /* access poisonous data */

/*
 * Note that the full MCACOD field of IA32_MCi_STATUS MSR is
 * bits 15:0.  But bit 12 is the 'F' bit, defined for corrected
 * errors to indicate that errors are being filtered by hardware.
 * We should mask out bit 12 when looking for specific signatures
 * of uncorrected errors - so the F bit is deliberately skipped
 * in this #define.
 */
#define MCACOD		  0xefff     /* MCA Error Code */

/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
#define MCACOD_SCRUB	0x00C0	/* 0xC0-0xCF Memory Scrubbing */
#define MCACOD_SCRUBMSK	0xeff0	/* Skip bit 12 ('F' bit) */
#define MCACOD_L3WB	0x017A	/* L3 Explicit Writeback */
#define MCACOD_DATA	0x0134	/* Data Load */
#define MCACOD_INSTR	0x0150	/* Instruction Fetch */

/* MCi_MISC register defines */
#define MCI_MISC_ADDR_LSB(m)	((m) & 0x3f)
#define MCI_MISC_ADDR_MODE(m)	(((m) >> 6) & 7)
#define  MCI_MISC_ADDR_SEGOFF	0	/* segment offset */
#define  MCI_MISC_ADDR_LINEAR	1	/* linear address */
#define  MCI_MISC_ADDR_PHYS	2	/* physical address */
#define  MCI_MISC_ADDR_MEM	3	/* memory address */
#define  MCI_MISC_ADDR_GENERIC	7	/* generic */

/* CTL2 register defines */
#define MCI_CTL2_CMCI_EN		(1ULL << 30)
#define MCI_CTL2_CMCI_THRESHOLD_MASK	0x7fffULL

#define MCJ_CTX_MASK		3
#define MCJ_CTX(flags)		((flags) & MCJ_CTX_MASK)
#define MCJ_CTX_RANDOM		0    /* inject context: random */
#define MCJ_CTX_PROCESS		0x1  /* inject context: process */
#define MCJ_CTX_IRQ		0x2  /* inject context: IRQ */
#define MCJ_NMI_BROADCAST	0x4  /* do NMI broadcasting */
#define MCJ_EXCEPTION		0x8  /* raise as exception */
#define MCJ_IRQ_BROADCAST	0x10 /* do IRQ broadcasting */

#define MCE_OVERFLOW 0		/* bit 0 in flags means overflow */

/* Software defined banks */
#define MCE_EXTENDED_BANK	128
#define MCE_THERMAL_BANK	(MCE_EXTENDED_BANK + 0)

#define MCE_LOG_LEN 32
#define MCE_LOG_SIGNATURE	"MACHINECHECK"

/*
 * This structure contains all data related to the MCE log.  Also
 * carries a signature to make it easier to find from external
 * debugging tools.  Each entry is only valid when its finished flag
 * is set.
 */
struct mce_log {
	char signature[12]; /* "MACHINECHECK" */
	unsigned len;	    /* = MCE_LOG_LEN */
	unsigned next;
	unsigned flags;
	unsigned recordlen;	/* length of struct mce */
	struct mce entry[MCE_LOG_LEN];
};

struct mca_config {
	bool dont_log_ce;
	bool cmci_disabled;
	bool ignore_ce;
	bool disabled;
	bool ser;
	bool bios_cmci_threshold;
	u8 banks;
	s8 bootlog;
	int tolerant;
	int monarch_timeout;
	int panic_timeout;
	u32 rip_msr;
};

extern struct mca_config mca_cfg;
extern void mce_register_decode_chain(struct notifier_block *nb);
extern void mce_unregister_decode_chain(struct notifier_block *nb);

#include <linux/percpu.h>
#include <linux/atomic.h>

extern int mce_p5_enabled;

#ifdef CONFIG_X86_MCE
int mcheck_init(void);
void mcheck_cpu_init(struct cpuinfo_x86 *c);
#else
static inline int mcheck_init(void) { return 0; }
static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
#endif

#ifdef CONFIG_X86_ANCIENT_MCE
void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
void winchip_mcheck_init(struct cpuinfo_x86 *c);
static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
#else
static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
static inline void enable_p5_mce(void) {}
#endif

void mce_setup(struct mce *m);
void mce_log(struct mce *m);
DECLARE_PER_CPU(struct device *, mce_device);

/*
 * Maximum banks number.
 * This is the limit of the current register layout on
 * Intel CPUs.
 */
#define MAX_NR_BANKS 32

#ifdef CONFIG_X86_MCE_INTEL
void mce_intel_feature_init(struct cpuinfo_x86 *c);
void cmci_clear(void);
void cmci_reenable(void);
void cmci_rediscover(void);
void cmci_recheck(void);
#else
static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
static inline void cmci_clear(void) {}
static inline void cmci_reenable(void) {}
static inline void cmci_rediscover(void) {}
static inline void cmci_recheck(void) {}
#endif

#ifdef CONFIG_X86_MCE_AMD
void mce_amd_feature_init(struct cpuinfo_x86 *c);
#else
static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
#endif

int mce_available(struct cpuinfo_x86 *c);

DECLARE_PER_CPU(unsigned, mce_exception_count);
DECLARE_PER_CPU(unsigned, mce_poll_count);

typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);

enum mcp_flags {
	MCP_TIMESTAMP	= BIT(0),	/* log time stamp */
	MCP_UC		= BIT(1),	/* log uncorrected errors */
	MCP_DONTLOG	= BIT(2),	/* only clear, don't log */
};
bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b);

int mce_notify_irq(void);

DECLARE_PER_CPU(struct mce, injectm);

extern void register_mce_write_callback(ssize_t (*)(struct file *filp,
				    const char __user *ubuf,
				    size_t usize, loff_t *off));

/* Disable CMCI/polling for MCA bank claimed by firmware */
extern void mce_disable_bank(int bank);

/*
 * Exception handler
 */

/* Call the installed machine check handler for this CPU setup. */
extern void (*machine_check_vector)(struct pt_regs *, long error_code);
void do_machine_check(struct pt_regs *, long);

/*
 * Threshold handler
 */

extern void (*mce_threshold_vector)(void);
extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);

/*
 * Thermal handler
 */

void intel_init_thermal(struct cpuinfo_x86 *c);

void mce_log_therm_throt_event(__u64 status);

/* Interrupt Handler for core thermal thresholds */
extern int (*platform_thermal_notify)(__u64 msr_val);

/* Interrupt Handler for package thermal thresholds */
extern int (*platform_thermal_package_notify)(__u64 msr_val);

/* Callback support of rate control, return true, if
 * callback has rate control */
extern bool (*platform_thermal_package_rate_control)(void);

#ifdef CONFIG_X86_THERMAL_VECTOR
extern void mcheck_intel_therm_init(void);
#else
static inline void mcheck_intel_therm_init(void) { }
#endif

/*
 * Used by APEI to report memory error via /dev/mcelog
 */

struct cper_sec_mem_err;
extern void apei_mce_report_mem_error(int corrected,
				      struct cper_sec_mem_err *mem_err);

#endif /* _ASM_X86_MCE_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_MCE_H
1965aae3 PA	2	#define _ASM_X86_MCE_H
e2f43029	3
af170c50	4	#include <uapi/asm/mce.h>
e2f43029	5
f51bde6f BP	6	/*
	7	* Machine Check support for x86
	8	*/
	9
	10	/* MCG_CAP register defines */
	11	#define MCG_BANKCNT_MASK 0xff /* Number of Banks */
	12	#define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */
	13	#define MCG_EXT_P (1ULL<<9) /* Extended registers available */
	14	#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
	15	#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
	16	#define MCG_EXT_CNT_SHIFT 16
	17	#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
	18	#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
4b3db708	19	#define MCG_ELOG_P (1ULL<<26) /* Extended error log supported */
f51bde6f BP	20
	21	/* MCG_STATUS register defines */
	22	#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
	23	#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
	24	#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
	25
	26	/* MCi_STATUS register defines */
	27	#define MCI_STATUS_VAL (1ULL<<63) /* valid error */
	28	#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
	29	#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
	30	#define MCI_STATUS_EN (1ULL<<60) /* error enabled */
	31	#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
	32	#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
	33	#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
	34	#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
	35	#define MCI_STATUS_AR (1ULL<<55) /* Action required */
0ca06c08	36
e3480271 CY	37	/* AMD-specific bits */
	38	#define MCI_STATUS_DEFERRED (1ULL<<44) /* declare an uncorrected error */
	39	#define MCI_STATUS_POISON (1ULL<<43) /* access poisonous data */
	40
0ca06c08 TL	41	/*
	42	* Note that the full MCACOD field of IA32_MCi_STATUS MSR is
	43	* bits 15:0. But bit 12 is the 'F' bit, defined for corrected
	44	* errors to indicate that errors are being filtered by hardware.
	45	* We should mask out bit 12 when looking for specific signatures
	46	* of uncorrected errors - so the F bit is deliberately skipped
	47	* in this #define.
	48	*/
	49	#define MCACOD 0xefff /* MCA Error Code */
f51bde6f BP	50
	51	/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
	52	#define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */
0ca06c08	53	#define MCACOD_SCRUBMSK 0xeff0 /* Skip bit 12 ('F' bit) */
f51bde6f BP	54	#define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */
	55	#define MCACOD_DATA 0x0134 /* Data Load */
	56	#define MCACOD_INSTR 0x0150 /* Instruction Fetch */
	57
	58	/* MCi_MISC register defines */
	59	#define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
	60	#define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7)
	61	#define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */
	62	#define MCI_MISC_ADDR_LINEAR 1 /* linear address */
	63	#define MCI_MISC_ADDR_PHYS 2 /* physical address */
	64	#define MCI_MISC_ADDR_MEM 3 /* memory address */
	65	#define MCI_MISC_ADDR_GENERIC 7 /* generic */
	66
	67	/* CTL2 register defines */
	68	#define MCI_CTL2_CMCI_EN (1ULL << 30)
	69	#define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
	70
	71	#define MCJ_CTX_MASK 3
	72	#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
	73	#define MCJ_CTX_RANDOM 0 /* inject context: random */
	74	#define MCJ_CTX_PROCESS 0x1 /* inject context: process */
	75	#define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */
	76	#define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */
	77	#define MCJ_EXCEPTION 0x8 /* raise as exception */
a9093684	78	#define MCJ_IRQ_BROADCAST 0x10 /* do IRQ broadcasting */
f51bde6f BP	79
	80	#define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
	81
	82	/* Software defined banks */
	83	#define MCE_EXTENDED_BANK 128
	84	#define MCE_THERMAL_BANK (MCE_EXTENDED_BANK + 0)
f51bde6f BP	85
	86	#define MCE_LOG_LEN 32
	87	#define MCE_LOG_SIGNATURE "MACHINECHECK"
	88
	89	/*
	90	* This structure contains all data related to the MCE log. Also
	91	* carries a signature to make it easier to find from external
	92	* debugging tools. Each entry is only valid when its finished flag
	93	* is set.
	94	*/
	95	struct mce_log {
	96	char signature[12]; /* "MACHINECHECK" */
	97	unsigned len; /* = MCE_LOG_LEN */
	98	unsigned next;
	99	unsigned flags;
	100	unsigned recordlen; /* length of struct mce */
	101	struct mce entry[MCE_LOG_LEN];
	102	};
d203f0b8 BP	103
	104	struct mca_config {
	105	bool dont_log_ce;
7af19e4a BP	106	bool cmci_disabled;
7af19e4a BP	107	bool ignore_ce;
1462594b BP	108	bool disabled;
	109	bool ser;
	110	bool bios_cmci_threshold;
d203f0b8	111	u8 banks;
84c2559d	112	s8 bootlog;
d203f0b8	113	int tolerant;
84c2559d	114	int monarch_timeout;
7af19e4a	115	int panic_timeout;
84c2559d	116	u32 rip_msr;
d203f0b8 BP	117	};
d203f0b8 BP	118
7af19e4a	119	extern struct mca_config mca_cfg;
3653ada5 BP	120	extern void mce_register_decode_chain(struct notifier_block *nb);
3653ada5 BP	121	extern void mce_unregister_decode_chain(struct notifier_block *nb);
df39a2e4	122
9e55e44e	123	#include <linux/percpu.h>
60063497	124	#include <linux/atomic.h>
9e55e44e	125
c6978369	126	extern int mce_p5_enabled;
e2f43029	127
58995d2d	128	#ifdef CONFIG_X86_MCE
a2202aa2	129	int mcheck_init(void);
5e09954a	130	void mcheck_cpu_init(struct cpuinfo_x86 *c);
58995d2d	131	#else
a2202aa2	132	static inline int mcheck_init(void) { return 0; }
5e09954a	133	static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
58995d2d HS	134	#endif
58995d2d HS	135
9e55e44e HS	136	#ifdef CONFIG_X86_ANCIENT_MCE
	137	void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
	138	void winchip_mcheck_init(struct cpuinfo_x86 *c);
c6978369	139	static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
9e55e44e HS	140	#else
	141	static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
	142	static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
c6978369	143	static inline void enable_p5_mce(void) {}
9e55e44e HS	144	#endif
9e55e44e HS	145
b5f2fa4e	146	void mce_setup(struct mce *m);
e2f43029	147	void mce_log(struct mce *m);
d6126ef5	148	DECLARE_PER_CPU(struct device *, mce_device);
e2f43029	149
41fdff32	150	/*
3ccdccfa AK	151	* Maximum banks number.
	152	* This is the limit of the current register layout on
	153	* Intel CPUs.
41fdff32	154	*/
3ccdccfa	155	#define MAX_NR_BANKS 32
41fdff32	156
e2f43029 TG	157	#ifdef CONFIG_X86_MCE_INTEL
e2f43029 TG	158	void mce_intel_feature_init(struct cpuinfo_x86 *c);
88ccbedd AK	159	void cmci_clear(void);
88ccbedd AK	160	void cmci_reenable(void);
7a0c819d	161	void cmci_rediscover(void);
88ccbedd	162	void cmci_recheck(void);
e2f43029 TG	163	#else
e2f43029 TG	164	static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
88ccbedd AK	165	static inline void cmci_clear(void) {}
88ccbedd AK	166	static inline void cmci_reenable(void) {}
7a0c819d	167	static inline void cmci_rediscover(void) {}
88ccbedd	168	static inline void cmci_recheck(void) {}
e2f43029 TG	169	#endif
	170
	171	#ifdef CONFIG_X86_MCE_AMD
	172	void mce_amd_feature_init(struct cpuinfo_x86 *c);
	173	#else
	174	static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
	175	#endif
	176
38736072	177	int mce_available(struct cpuinfo_x86 *c);
88ccbedd	178
01ca79f1	179	DECLARE_PER_CPU(unsigned, mce_exception_count);
ca84f696	180	DECLARE_PER_CPU(unsigned, mce_poll_count);
01ca79f1	181
ee031c31 AK	182	typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
	183	DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
	184
b79109c3	185	enum mcp_flags {
3f2f0680 BP	186	MCP_TIMESTAMP = BIT(0), /* log time stamp */
	187	MCP_UC = BIT(1), /* log uncorrected errors */
	188	MCP_DONTLOG = BIT(2), /* only clear, don't log */
b79109c3	189	};
3f2f0680	190	bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
b79109c3	191
9ff36ee9	192	int mce_notify_irq(void);
e2f43029	193
ea149b36	194	DECLARE_PER_CPU(struct mce, injectm);
66f5ddf3 TL	195
	196	extern void register_mce_write_callback(ssize_t ()(struct file filp,
	197	const char __user *ubuf,
	198	size_t usize, loff_t *off));
ea149b36	199
c3d1fb56 NR	200	/* Disable CMCI/polling for MCA bank claimed by firmware */
	201	extern void mce_disable_bank(int bank);
	202
58995d2d HS	203	/*
	204	* Exception handler
	205	*/
	206
	207	/* Call the installed machine check handler for this CPU setup. */
	208	extern void (machine_check_vector)(struct pt_regs , long error_code);
	209	void do_machine_check(struct pt_regs *, long);
	210
	211	/*
	212	* Threshold handler
	213	*/
e2f43029	214
b2762686	215	extern void (*mce_threshold_vector)(void);
58995d2d	216	extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
b2762686	217
e8ce2c5e HS	218	/*
	219	* Thermal handler
	220	*/
	221
e8ce2c5e HS	222	void intel_init_thermal(struct cpuinfo_x86 *c);
e8ce2c5e HS	223
e8ce2c5e	224	void mce_log_therm_throt_event(__u64 status);
a2202aa2	225
9e76a97e D	226	/* Interrupt Handler for core thermal thresholds */
	227	extern int (*platform_thermal_notify)(__u64 msr_val);
	228
25cdce17 SP	229	/* Interrupt Handler for package thermal thresholds */
	230	extern int (*platform_thermal_package_notify)(__u64 msr_val);
	231
	232	/* Callback support of rate control, return true, if
	233	* callback has rate control */
	234	extern bool (*platform_thermal_package_rate_control)(void);
	235
a2202aa2 YW	236	#ifdef CONFIG_X86_THERMAL_VECTOR
	237	extern void mcheck_intel_therm_init(void);
	238	#else
	239	static inline void mcheck_intel_therm_init(void) { }
	240	#endif
	241
d334a491 HY	242	/*
	243	* Used by APEI to report memory error via /dev/mcelog
	244	*/
	245
	246	struct cper_sec_mem_err;
	247	extern void apei_mce_report_mem_error(int corrected,
	248	struct cper_sec_mem_err *mem_err);
	249
1965aae3	250	#endif /* _ASM_X86_MCE_H */