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x86/microcode: Attempt late loading only when new microcode is present
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b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
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2#ifndef _ASM_X86_MICROCODE_H
3#define _ASM_X86_MICROCODE_H
d45de409 4
99f925ce 5#include <asm/cpu.h>
760d765b 6#include <linux/earlycpio.h>
5f9c01aa 7#include <linux/initrd.h>
760d765b 8
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9#define native_rdmsr(msr, val1, val2) \
10do { \
0c12d18a 11 u64 __val = __rdmsr((msr)); \
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12 (void)((val1) = (u32)__val); \
13 (void)((val2) = (u32)(__val >> 32)); \
14} while (0)
15
16#define native_wrmsr(msr, low, high) \
0c12d18a 17 __wrmsr(msr, low, high)
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18
19#define native_wrmsrl(msr, val) \
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20 __wrmsr((msr), (u32)((u64)(val)), \
21 (u32)((u64)(val) >> 32))
e1b43e3f 22
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23struct ucode_patch {
24 struct list_head plist;
25 void *data; /* Intel uses only this one */
26 u32 patch_id;
27 u16 equiv_cpu;
28};
29
30extern struct list_head microcode_cache;
31
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32struct cpu_signature {
33 unsigned int sig;
34 unsigned int pf;
35 unsigned int rev;
36};
8d86f390 37
a0a29b62 38struct device;
d45de409 39
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40enum ucode_state {
41 UCODE_OK = 0,
3b6e17f3 42 UCODE_NEW,
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43 UCODE_UPDATED,
44 UCODE_NFOUND,
45 UCODE_ERROR,
46};
871b72dd 47
26bf7a48 48struct microcode_ops {
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49 enum ucode_state (*request_microcode_user) (int cpu,
50 const void __user *buf, size_t size);
a0a29b62 51
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52 enum ucode_state (*request_microcode_fw) (int cpu, struct device *,
53 bool refresh_fw);
a0a29b62 54
a0a29b62 55 void (*microcode_fini_cpu) (int cpu);
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56
57 /*
58 * The generic 'microcode_core' part guarantees that
59 * the callbacks below run on a target cpu when they
60 * are being called.
61 * See also the "Synchronization" section in microcode_core.c.
62 */
96d0dd3c 63 enum ucode_state (*apply_microcode) (int cpu);
871b72dd 64 int (*collect_cpu_info) (int cpu, struct cpu_signature *csig);
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65};
66
d45de409 67struct ucode_cpu_info {
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68 struct cpu_signature cpu_sig;
69 int valid;
70 void *mc;
c3b71bce 71};
d45de409 72extern struct ucode_cpu_info ucode_cpu_info[];
06b8534c 73struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa);
d45de409 74
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75#ifdef CONFIG_MICROCODE_INTEL
76extern struct microcode_ops * __init init_intel_microcode(void);
77#else
78static inline struct microcode_ops * __init init_intel_microcode(void)
79{
80 return NULL;
81}
82#endif /* CONFIG_MICROCODE_INTEL */
83
84#ifdef CONFIG_MICROCODE_AMD
85extern struct microcode_ops * __init init_amd_microcode(void);
f72c1a57 86extern void __exit exit_amd_microcode(void);
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87#else
88static inline struct microcode_ops * __init init_amd_microcode(void)
89{
90 return NULL;
91}
f72c1a57 92static inline void __exit exit_amd_microcode(void) {}
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93#endif
94
a8ebf6d1 95#define MAX_UCODE_COUNT 128
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96
97#define QCHAR(a, b, c, d) ((a) + ((b) << 8) + ((c) << 16) + ((d) << 24))
98#define CPUID_INTEL1 QCHAR('G', 'e', 'n', 'u')
99#define CPUID_INTEL2 QCHAR('i', 'n', 'e', 'I')
100#define CPUID_INTEL3 QCHAR('n', 't', 'e', 'l')
101#define CPUID_AMD1 QCHAR('A', 'u', 't', 'h')
102#define CPUID_AMD2 QCHAR('e', 'n', 't', 'i')
103#define CPUID_AMD3 QCHAR('c', 'A', 'M', 'D')
104
105#define CPUID_IS(a, b, c, ebx, ecx, edx) \
106 (!((ebx ^ (a))|(edx ^ (b))|(ecx ^ (c))))
107
108/*
109 * In early loading microcode phase on BSP, boot_cpu_data is not set up yet.
99f925ce 110 * x86_cpuid_vendor() gets vendor id for BSP.
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111 *
112 * In 32 bit AP case, accessing boot_cpu_data needs linear address. To simplify
99f925ce 113 * coding, we still use x86_cpuid_vendor() to get vendor id for AP.
58ce8d6d 114 *
99f925ce 115 * x86_cpuid_vendor() gets vendor information directly from CPUID.
58ce8d6d 116 */
99f925ce 117static inline int x86_cpuid_vendor(void)
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118{
119 u32 eax = 0x00000000;
120 u32 ebx, ecx = 0, edx;
121
122 native_cpuid(&eax, &ebx, &ecx, &edx);
123
124 if (CPUID_IS(CPUID_INTEL1, CPUID_INTEL2, CPUID_INTEL3, ebx, ecx, edx))
125 return X86_VENDOR_INTEL;
126
127 if (CPUID_IS(CPUID_AMD1, CPUID_AMD2, CPUID_AMD3, ebx, ecx, edx))
128 return X86_VENDOR_AMD;
129
130 return X86_VENDOR_UNKNOWN;
131}
132
99f925ce 133static inline unsigned int x86_cpuid_family(void)
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134{
135 u32 eax = 0x00000001;
136 u32 ebx, ecx = 0, edx;
137
138 native_cpuid(&eax, &ebx, &ecx, &edx);
139
99f925ce 140 return x86_family(eax);
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141}
142
fe055896 143#ifdef CONFIG_MICROCODE
f5bdfefb 144int __init microcode_init(void);
a8ebf6d1 145extern void __init load_ucode_bsp(void);
148f9bb8 146extern void load_ucode_ap(void);
fbae4ba8 147void reload_early_microcode(void);
760d765b 148extern bool get_builtin_firmware(struct cpio_data *cd, const char *name);
24c25032 149extern bool initrd_gone;
a8ebf6d1 150#else
f5bdfefb 151static inline int __init microcode_init(void) { return 0; };
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152static inline void __init load_ucode_bsp(void) { }
153static inline void load_ucode_ap(void) { }
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154static inline void reload_early_microcode(void) { }
155static inline bool
156get_builtin_firmware(struct cpio_data *cd, const char *name) { return false; }
a8ebf6d1 157#endif
5f9c01aa 158
1965aae3 159#endif /* _ASM_X86_MICROCODE_H */