[mirror_ubuntu-bionic-kernel.git] / arch / x86 / include / asm / mpspec_def.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_MPSPEC_DEF_H
#define _ASM_X86_MPSPEC_DEF_H

/*
 * Structure definitions for SMP machines following the
 * Intel Multiprocessing Specification 1.1 and 1.4.
 */

/*
 * This tag identifies where the SMP configuration
 * information is.
 */

#define SMP_MAGIC_IDENT	(('_'<<24) | ('P'<<16) | ('M'<<8) | '_')

#ifdef CONFIG_X86_32
# define MAX_MPC_ENTRY 1024
#endif

/* Intel MP Floating Pointer Structure */
struct mpf_intel {
	char signature[4];		/* "_MP_"			*/
	unsigned int physptr;		/* Configuration table address	*/
	unsigned char length;		/* Our length (paragraphs)	*/
	unsigned char specification;	/* Specification version	*/
	unsigned char checksum;		/* Checksum (makes sum 0)	*/
	unsigned char feature1;		/* Standard or configuration ?	*/
	unsigned char feature2;		/* Bit7 set for IMCR|PIC	*/
	unsigned char feature3;		/* Unused (0)			*/
	unsigned char feature4;		/* Unused (0)			*/
	unsigned char feature5;		/* Unused (0)			*/
};

#define MPC_SIGNATURE "PCMP"

struct mpc_table {
	char signature[4];
	unsigned short length;		/* Size of table */
	char spec;			/* 0x01 */
	char checksum;
	char oem[8];
	char productid[12];
	unsigned int oemptr;		/* 0 if not present */
	unsigned short oemsize;		/* 0 if not present */
	unsigned short oemcount;
	unsigned int lapic;		/* APIC address */
	unsigned int reserved;
};

/* Followed by entries */

#define	MP_PROCESSOR		0
#define	MP_BUS			1
#define	MP_IOAPIC		2
#define	MP_INTSRC		3
#define	MP_LINTSRC		4
/* Used by IBM NUMA-Q to describe node locality */
#define	MP_TRANSLATION		192

#define CPU_ENABLED		1	/* Processor is available */
#define CPU_BOOTPROCESSOR	2	/* Processor is the BP */

#define CPU_STEPPING_MASK	0x000F
#define CPU_MODEL_MASK		0x00F0
#define CPU_FAMILY_MASK		0x0F00

struct mpc_cpu {
	unsigned char type;
	unsigned char apicid;		/* Local APIC number */
	unsigned char apicver;		/* Its versions */
	unsigned char cpuflag;
	unsigned int cpufeature;
	unsigned int featureflag;	/* CPUID feature value */
	unsigned int reserved[2];
};

struct mpc_bus {
	unsigned char type;
	unsigned char busid;
	unsigned char bustype[6];
};

/* List of Bus Type string values, Intel MP Spec. */
#define BUSTYPE_EISA	"EISA"
#define BUSTYPE_ISA	"ISA"
#define BUSTYPE_INTERN	"INTERN"	/* Internal BUS */
#define BUSTYPE_MCA	"MCA"		/* Obsolete */
#define BUSTYPE_VL	"VL"		/* Local bus */
#define BUSTYPE_PCI	"PCI"
#define BUSTYPE_PCMCIA	"PCMCIA"
#define BUSTYPE_CBUS	"CBUS"
#define BUSTYPE_CBUSII	"CBUSII"
#define BUSTYPE_FUTURE	"FUTURE"
#define BUSTYPE_MBI	"MBI"
#define BUSTYPE_MBII	"MBII"
#define BUSTYPE_MPI	"MPI"
#define BUSTYPE_MPSA	"MPSA"
#define BUSTYPE_NUBUS	"NUBUS"
#define BUSTYPE_TC	"TC"
#define BUSTYPE_VME	"VME"
#define BUSTYPE_XPRESS	"XPRESS"

#define MPC_APIC_USABLE		0x01

struct mpc_ioapic {
	unsigned char type;
	unsigned char apicid;
	unsigned char apicver;
	unsigned char flags;
	unsigned int apicaddr;
};

struct mpc_intsrc {
	unsigned char type;
	unsigned char irqtype;
	unsigned short irqflag;
	unsigned char srcbus;
	unsigned char srcbusirq;
	unsigned char dstapic;
	unsigned char dstirq;
};

enum mp_irq_source_types {
	mp_INT = 0,
	mp_NMI = 1,
	mp_SMI = 2,
	mp_ExtINT = 3
};

#define MP_IRQDIR_DEFAULT	0
#define MP_IRQDIR_HIGH		1
#define MP_IRQDIR_LOW		3

#define MP_APIC_ALL	0xFF

struct mpc_lintsrc {
	unsigned char type;
	unsigned char irqtype;
	unsigned short irqflag;
	unsigned char srcbusid;
	unsigned char srcbusirq;
	unsigned char destapic;
	unsigned char destapiclint;
};

#define MPC_OEM_SIGNATURE "_OEM"

struct mpc_oemtable {
	char signature[4];
	unsigned short length;		/* Size of table */
	char  rev;			/* 0x01 */
	char  checksum;
	char  mpc[8];
};

/*
 *	Default configurations
 *
 *	1	2 CPU ISA 82489DX
 *	2	2 CPU EISA 82489DX neither IRQ 0 timer nor IRQ 13 DMA chaining
 *	3	2 CPU EISA 82489DX
 *	4	2 CPU MCA 82489DX
 *	5	2 CPU ISA+PCI
 *	6	2 CPU EISA+PCI
 *	7	2 CPU MCA+PCI
 */

enum mp_bustype {
	MP_BUS_ISA = 1,
	MP_BUS_EISA,
	MP_BUS_PCI,
};
#endif /* _ASM_X86_MPSPEC_DEF_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
1965aae3 PA	2	#ifndef _ASM_X86_MPSPEC_DEF_H
1965aae3 PA	3	#define _ASM_X86_MPSPEC_DEF_H
1da177e4 LT	4
	5	/*
	6	* Structure definitions for SMP machines following the
	7	* Intel Multiprocessing Specification 1.1 and 1.4.
	8	*/
	9
	10	/*
	11	* This tag identifies where the SMP configuration
64883ab0	12	* information is.
1da177e4	13	*/
64883ab0	14
8f08403e	15	#define SMP_MAGIC_IDENT (('_'<<24) \| ('P'<<16) \| ('M'<<8) \| '_')
1da177e4	16
64883ab0 TG	17	#ifdef CONFIG_X86_32
64883ab0 TG	18	# define MAX_MPC_ENTRY 1024
64883ab0	19	#endif
1da177e4	20
41401db6 JSR	21	/* Intel MP Floating Pointer Structure */
41401db6 JSR	22	struct mpf_intel {
1eb1b3b6 JSR	23	char signature[4]; /* "_MP_" */
	24	unsigned int physptr; /* Configuration table address */
	25	unsigned char length; /* Our length (paragraphs) */
	26	unsigned char specification; /* Specification version */
	27	unsigned char checksum; /* Checksum (makes sum 0) */
	28	unsigned char feature1; /* Standard or configuration ? */
	29	unsigned char feature2; /* Bit7 set for IMCR\|PIC */
	30	unsigned char feature3; /* Unused (0) */
	31	unsigned char feature4; /* Unused (0) */
	32	unsigned char feature5; /* Unused (0) */
1da177e4 LT	33	};
1da177e4 LT	34
64883ab0 TG	35	#define MPC_SIGNATURE "PCMP"
64883ab0 TG	36
f29521e4	37	struct mpc_table {
6c65da50 JSR	38	char signature[4];
	39	unsigned short length; /* Size of table */
	40	char spec; /* 0x01 */
	41	char checksum;
	42	char oem[8];
	43	char productid[12];
	44	unsigned int oemptr; /* 0 if not present */
	45	unsigned short oemsize; /* 0 if not present */
	46	unsigned short oemcount;
	47	unsigned int lapic; /* APIC address */
64883ab0	48	unsigned int reserved;
1da177e4 LT	49	};
	50
	51	/* Followed by entries */
	52
64883ab0 TG	53	#define MP_PROCESSOR 0
	54	#define MP_BUS 1
	55	#define MP_IOAPIC 2
	56	#define MP_INTSRC 3
	57	#define MP_LINTSRC 4
	58	/* Used by IBM NUMA-Q to describe node locality */
	59	#define MP_TRANSLATION 192
	60
	61	#define CPU_ENABLED 1 /* Processor is available */
	62	#define CPU_BOOTPROCESSOR 2 /* Processor is the BP */
	63
	64	#define CPU_STEPPING_MASK 0x000F
	65	#define CPU_MODEL_MASK 0x00F0
	66	#define CPU_FAMILY_MASK 0x0F00
1da177e4	67
f4f21b71	68	struct mpc_cpu {
c4563826 JSR	69	unsigned char type;
	70	unsigned char apicid; /* Local APIC number */
	71	unsigned char apicver; /* Its versions */
	72	unsigned char cpuflag;
	73	unsigned int cpufeature;
	74	unsigned int featureflag; /* CPUID feature value */
	75	unsigned int reserved[2];
1da177e4 LT	76	};
1da177e4 LT	77
00fb8606	78	struct mpc_bus {
d4c715fa JSR	79	unsigned char type;
	80	unsigned char busid;
	81	unsigned char bustype[6];
1da177e4 LT	82	};
	83
	84	/* List of Bus Type string values, Intel MP Spec. */
	85	#define BUSTYPE_EISA "EISA"
	86	#define BUSTYPE_ISA "ISA"
	87	#define BUSTYPE_INTERN "INTERN" /* Internal BUS */
bb8187d3	88	#define BUSTYPE_MCA "MCA" /* Obsolete */
1da177e4 LT	89	#define BUSTYPE_VL "VL" /* Local bus */
	90	#define BUSTYPE_PCI "PCI"
	91	#define BUSTYPE_PCMCIA "PCMCIA"
	92	#define BUSTYPE_CBUS "CBUS"
	93	#define BUSTYPE_CBUSII "CBUSII"
	94	#define BUSTYPE_FUTURE "FUTURE"
	95	#define BUSTYPE_MBI "MBI"
	96	#define BUSTYPE_MBII "MBII"
	97	#define BUSTYPE_MPI "MPI"
	98	#define BUSTYPE_MPSA "MPSA"
	99	#define BUSTYPE_NUBUS "NUBUS"
	100	#define BUSTYPE_TC "TC"
	101	#define BUSTYPE_VME "VME"
	102	#define BUSTYPE_XPRESS "XPRESS"
1da177e4	103
64883ab0 TG	104	#define MPC_APIC_USABLE 0x01
64883ab0 TG	105
2b85b5fb	106	struct mpc_ioapic {
5df82c7d JSR	107	unsigned char type;
	108	unsigned char apicid;
	109	unsigned char apicver;
	110	unsigned char flags;
	111	unsigned int apicaddr;
1da177e4 LT	112	};
1da177e4 LT	113
540d4e72	114	struct mpc_intsrc {
e253b396 JSR	115	unsigned char type;
	116	unsigned char irqtype;
	117	unsigned short irqflag;
	118	unsigned char srcbus;
	119	unsigned char srcbusirq;
	120	unsigned char dstapic;
	121	unsigned char dstirq;
1da177e4 LT	122	};
	123
	124	enum mp_irq_source_types {
	125	mp_INT = 0,
	126	mp_NMI = 1,
	127	mp_SMI = 2,
	128	mp_ExtINT = 3
	129	};
	130
	131	#define MP_IRQDIR_DEFAULT 0
	132	#define MP_IRQDIR_HIGH 1
	133	#define MP_IRQDIR_LOW 3
	134
64883ab0	135	#define MP_APIC_ALL 0xFF
1da177e4	136
8fb2952b	137	struct mpc_lintsrc {
b5ced7cd JSR	138	unsigned char type;
	139	unsigned char irqtype;
	140	unsigned short irqflag;
	141	unsigned char srcbusid;
	142	unsigned char srcbusirq;
	143	unsigned char destapic;
	144	unsigned char destapiclint;
1da177e4 LT	145	};
1da177e4 LT	146
64883ab0 TG	147	#define MPC_OEM_SIGNATURE "_OEM"
64883ab0 TG	148
b0e239ff	149	struct mpc_oemtable {
a1d0272a JSR	150	char signature[4];
	151	unsigned short length; /* Size of table */
	152	char rev; /* 0x01 */
	153	char checksum;
	154	char mpc[8];
1da177e4 LT	155	};
1da177e4 LT	156
1da177e4 LT	157	/*
	158	* Default configurations
	159	*
	160	* 1 2 CPU ISA 82489DX
	161	* 2 2 CPU EISA 82489DX neither IRQ 0 timer nor IRQ 13 DMA chaining
	162	* 3 2 CPU EISA 82489DX
	163	* 4 2 CPU MCA 82489DX
	164	* 5 2 CPU ISA+PCI
	165	* 6 2 CPU EISA+PCI
	166	* 7 2 CPU MCA+PCI
	167	*/
	168
	169	enum mp_bustype {
	170	MP_BUS_ISA = 1,
	171	MP_BUS_EISA,
	172	MP_BUS_PCI,
1da177e4	173	};
1965aae3	174	#endif /* _ASM_X86_MPSPEC_DEF_H */