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1965aae3 PA |
1 | #ifndef _ASM_X86_PARAVIRT_H |
2 | #define _ASM_X86_PARAVIRT_H | |
d3561b7f RR |
3 | /* Various instructions on x86 need to be replaced for |
4 | * para-virtualization: those hooks are defined here. */ | |
b239fb25 JF |
5 | |
6 | #ifdef CONFIG_PARAVIRT | |
54321d94 | 7 | #include <asm/pgtable_types.h> |
658be9d3 | 8 | #include <asm/asm.h> |
d3561b7f | 9 | |
ac5672f8 | 10 | #include <asm/paravirt_types.h> |
ecb93d1c | 11 | |
d3561b7f | 12 | #ifndef __ASSEMBLY__ |
187f1882 | 13 | #include <linux/bug.h> |
3dc494e8 | 14 | #include <linux/types.h> |
d4c10477 | 15 | #include <linux/cpumask.h> |
1a45b7aa | 16 | |
f8822f42 JF |
17 | static inline int paravirt_enabled(void) |
18 | { | |
93b1eab3 | 19 | return pv_info.paravirt_enabled; |
f8822f42 | 20 | } |
d3561b7f | 21 | |
faca6227 | 22 | static inline void load_sp0(struct tss_struct *tss, |
d3561b7f RR |
23 | struct thread_struct *thread) |
24 | { | |
faca6227 | 25 | PVOP_VCALL2(pv_cpu_ops.load_sp0, tss, thread); |
d3561b7f RR |
26 | } |
27 | ||
d3561b7f RR |
28 | /* The paravirtualized CPUID instruction. */ |
29 | static inline void __cpuid(unsigned int *eax, unsigned int *ebx, | |
30 | unsigned int *ecx, unsigned int *edx) | |
31 | { | |
93b1eab3 | 32 | PVOP_VCALL4(pv_cpu_ops.cpuid, eax, ebx, ecx, edx); |
d3561b7f RR |
33 | } |
34 | ||
35 | /* | |
36 | * These special macros can be used to get or set a debugging register | |
37 | */ | |
f8822f42 JF |
38 | static inline unsigned long paravirt_get_debugreg(int reg) |
39 | { | |
93b1eab3 | 40 | return PVOP_CALL1(unsigned long, pv_cpu_ops.get_debugreg, reg); |
f8822f42 JF |
41 | } |
42 | #define get_debugreg(var, reg) var = paravirt_get_debugreg(reg) | |
43 | static inline void set_debugreg(unsigned long val, int reg) | |
44 | { | |
93b1eab3 | 45 | PVOP_VCALL2(pv_cpu_ops.set_debugreg, reg, val); |
f8822f42 | 46 | } |
d3561b7f | 47 | |
f8822f42 JF |
48 | static inline void clts(void) |
49 | { | |
93b1eab3 | 50 | PVOP_VCALL0(pv_cpu_ops.clts); |
f8822f42 | 51 | } |
d3561b7f | 52 | |
f8822f42 JF |
53 | static inline unsigned long read_cr0(void) |
54 | { | |
93b1eab3 | 55 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr0); |
f8822f42 | 56 | } |
d3561b7f | 57 | |
f8822f42 JF |
58 | static inline void write_cr0(unsigned long x) |
59 | { | |
93b1eab3 | 60 | PVOP_VCALL1(pv_cpu_ops.write_cr0, x); |
f8822f42 JF |
61 | } |
62 | ||
63 | static inline unsigned long read_cr2(void) | |
64 | { | |
93b1eab3 | 65 | return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr2); |
f8822f42 JF |
66 | } |
67 | ||
68 | static inline void write_cr2(unsigned long x) | |
69 | { | |
93b1eab3 | 70 | PVOP_VCALL1(pv_mmu_ops.write_cr2, x); |
f8822f42 JF |
71 | } |
72 | ||
73 | static inline unsigned long read_cr3(void) | |
74 | { | |
93b1eab3 | 75 | return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr3); |
f8822f42 | 76 | } |
d3561b7f | 77 | |
f8822f42 JF |
78 | static inline void write_cr3(unsigned long x) |
79 | { | |
93b1eab3 | 80 | PVOP_VCALL1(pv_mmu_ops.write_cr3, x); |
f8822f42 | 81 | } |
d3561b7f | 82 | |
1e02ce4c | 83 | static inline unsigned long __read_cr4(void) |
f8822f42 | 84 | { |
93b1eab3 | 85 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4); |
f8822f42 | 86 | } |
1e02ce4c | 87 | static inline unsigned long __read_cr4_safe(void) |
f8822f42 | 88 | { |
93b1eab3 | 89 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4_safe); |
f8822f42 | 90 | } |
d3561b7f | 91 | |
1e02ce4c | 92 | static inline void __write_cr4(unsigned long x) |
f8822f42 | 93 | { |
93b1eab3 | 94 | PVOP_VCALL1(pv_cpu_ops.write_cr4, x); |
f8822f42 | 95 | } |
3dc494e8 | 96 | |
94ea03cd | 97 | #ifdef CONFIG_X86_64 |
4c9890c2 GOC |
98 | static inline unsigned long read_cr8(void) |
99 | { | |
100 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr8); | |
101 | } | |
102 | ||
103 | static inline void write_cr8(unsigned long x) | |
104 | { | |
105 | PVOP_VCALL1(pv_cpu_ops.write_cr8, x); | |
106 | } | |
94ea03cd | 107 | #endif |
4c9890c2 | 108 | |
df9ee292 | 109 | static inline void arch_safe_halt(void) |
d3561b7f | 110 | { |
93b1eab3 | 111 | PVOP_VCALL0(pv_irq_ops.safe_halt); |
d3561b7f RR |
112 | } |
113 | ||
114 | static inline void halt(void) | |
115 | { | |
c8217b83 | 116 | PVOP_VCALL0(pv_irq_ops.halt); |
f8822f42 JF |
117 | } |
118 | ||
119 | static inline void wbinvd(void) | |
120 | { | |
93b1eab3 | 121 | PVOP_VCALL0(pv_cpu_ops.wbinvd); |
d3561b7f | 122 | } |
d3561b7f | 123 | |
93b1eab3 | 124 | #define get_kernel_rpl() (pv_info.kernel_rpl) |
d3561b7f | 125 | |
f8822f42 JF |
126 | static inline u64 paravirt_read_msr(unsigned msr, int *err) |
127 | { | |
93b1eab3 | 128 | return PVOP_CALL2(u64, pv_cpu_ops.read_msr, msr, err); |
f8822f42 | 129 | } |
132ec92f | 130 | |
f8822f42 JF |
131 | static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high) |
132 | { | |
93b1eab3 | 133 | return PVOP_CALL3(int, pv_cpu_ops.write_msr, msr, low, high); |
f8822f42 JF |
134 | } |
135 | ||
90a0a06a | 136 | /* These should all do BUG_ON(_err), but our headers are too tangled. */ |
49cd740b JP |
137 | #define rdmsr(msr, val1, val2) \ |
138 | do { \ | |
f8822f42 JF |
139 | int _err; \ |
140 | u64 _l = paravirt_read_msr(msr, &_err); \ | |
141 | val1 = (u32)_l; \ | |
142 | val2 = _l >> 32; \ | |
49cd740b | 143 | } while (0) |
d3561b7f | 144 | |
49cd740b JP |
145 | #define wrmsr(msr, val1, val2) \ |
146 | do { \ | |
f8822f42 | 147 | paravirt_write_msr(msr, val1, val2); \ |
49cd740b | 148 | } while (0) |
d3561b7f | 149 | |
49cd740b JP |
150 | #define rdmsrl(msr, val) \ |
151 | do { \ | |
f8822f42 JF |
152 | int _err; \ |
153 | val = paravirt_read_msr(msr, &_err); \ | |
49cd740b | 154 | } while (0) |
d3561b7f | 155 | |
47edb651 AL |
156 | static inline void wrmsrl(unsigned msr, u64 val) |
157 | { | |
158 | wrmsr(msr, (u32)val, (u32)(val>>32)); | |
159 | } | |
160 | ||
49cd740b | 161 | #define wrmsr_safe(msr, a, b) paravirt_write_msr(msr, a, b) |
d3561b7f RR |
162 | |
163 | /* rdmsr with exception handling */ | |
49cd740b JP |
164 | #define rdmsr_safe(msr, a, b) \ |
165 | ({ \ | |
f8822f42 JF |
166 | int _err; \ |
167 | u64 _l = paravirt_read_msr(msr, &_err); \ | |
168 | (*a) = (u32)_l; \ | |
169 | (*b) = _l >> 32; \ | |
49cd740b JP |
170 | _err; \ |
171 | }) | |
d3561b7f | 172 | |
1de87bd4 AK |
173 | static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) |
174 | { | |
175 | int err; | |
176 | ||
177 | *p = paravirt_read_msr(msr, &err); | |
178 | return err; | |
179 | } | |
177fed1e | 180 | |
688340ea JF |
181 | static inline unsigned long long paravirt_sched_clock(void) |
182 | { | |
93b1eab3 | 183 | return PVOP_CALL0(unsigned long long, pv_time_ops.sched_clock); |
688340ea | 184 | } |
6cb9a835 | 185 | |
c5905afb IM |
186 | struct static_key; |
187 | extern struct static_key paravirt_steal_enabled; | |
188 | extern struct static_key paravirt_steal_rq_enabled; | |
3c404b57 GC |
189 | |
190 | static inline u64 paravirt_steal_clock(int cpu) | |
191 | { | |
192 | return PVOP_CALL1(u64, pv_time_ops.steal_clock, cpu); | |
193 | } | |
194 | ||
f8822f42 JF |
195 | static inline unsigned long long paravirt_read_pmc(int counter) |
196 | { | |
93b1eab3 | 197 | return PVOP_CALL1(u64, pv_cpu_ops.read_pmc, counter); |
f8822f42 | 198 | } |
d3561b7f | 199 | |
49cd740b JP |
200 | #define rdpmc(counter, low, high) \ |
201 | do { \ | |
f8822f42 JF |
202 | u64 _l = paravirt_read_pmc(counter); \ |
203 | low = (u32)_l; \ | |
204 | high = _l >> 32; \ | |
49cd740b | 205 | } while (0) |
3dc494e8 | 206 | |
1ff4d58a AK |
207 | #define rdpmcl(counter, val) ((val) = paravirt_read_pmc(counter)) |
208 | ||
38ffbe66 JF |
209 | static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries) |
210 | { | |
211 | PVOP_VCALL2(pv_cpu_ops.alloc_ldt, ldt, entries); | |
212 | } | |
213 | ||
214 | static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries) | |
215 | { | |
216 | PVOP_VCALL2(pv_cpu_ops.free_ldt, ldt, entries); | |
217 | } | |
218 | ||
f8822f42 JF |
219 | static inline void load_TR_desc(void) |
220 | { | |
93b1eab3 | 221 | PVOP_VCALL0(pv_cpu_ops.load_tr_desc); |
f8822f42 | 222 | } |
6b68f01b | 223 | static inline void load_gdt(const struct desc_ptr *dtr) |
f8822f42 | 224 | { |
93b1eab3 | 225 | PVOP_VCALL1(pv_cpu_ops.load_gdt, dtr); |
f8822f42 | 226 | } |
6b68f01b | 227 | static inline void load_idt(const struct desc_ptr *dtr) |
f8822f42 | 228 | { |
93b1eab3 | 229 | PVOP_VCALL1(pv_cpu_ops.load_idt, dtr); |
f8822f42 JF |
230 | } |
231 | static inline void set_ldt(const void *addr, unsigned entries) | |
232 | { | |
93b1eab3 | 233 | PVOP_VCALL2(pv_cpu_ops.set_ldt, addr, entries); |
f8822f42 | 234 | } |
6b68f01b | 235 | static inline void store_idt(struct desc_ptr *dtr) |
f8822f42 | 236 | { |
93b1eab3 | 237 | PVOP_VCALL1(pv_cpu_ops.store_idt, dtr); |
f8822f42 JF |
238 | } |
239 | static inline unsigned long paravirt_store_tr(void) | |
240 | { | |
93b1eab3 | 241 | return PVOP_CALL0(unsigned long, pv_cpu_ops.store_tr); |
f8822f42 JF |
242 | } |
243 | #define store_tr(tr) ((tr) = paravirt_store_tr()) | |
244 | static inline void load_TLS(struct thread_struct *t, unsigned cpu) | |
245 | { | |
93b1eab3 | 246 | PVOP_VCALL2(pv_cpu_ops.load_tls, t, cpu); |
f8822f42 | 247 | } |
75b8bb3e | 248 | |
9f9d489a JF |
249 | #ifdef CONFIG_X86_64 |
250 | static inline void load_gs_index(unsigned int gs) | |
251 | { | |
252 | PVOP_VCALL1(pv_cpu_ops.load_gs_index, gs); | |
253 | } | |
254 | #endif | |
255 | ||
75b8bb3e GOC |
256 | static inline void write_ldt_entry(struct desc_struct *dt, int entry, |
257 | const void *desc) | |
f8822f42 | 258 | { |
75b8bb3e | 259 | PVOP_VCALL3(pv_cpu_ops.write_ldt_entry, dt, entry, desc); |
f8822f42 | 260 | } |
014b15be GOC |
261 | |
262 | static inline void write_gdt_entry(struct desc_struct *dt, int entry, | |
263 | void *desc, int type) | |
f8822f42 | 264 | { |
014b15be | 265 | PVOP_VCALL4(pv_cpu_ops.write_gdt_entry, dt, entry, desc, type); |
f8822f42 | 266 | } |
014b15be | 267 | |
8d947344 | 268 | static inline void write_idt_entry(gate_desc *dt, int entry, const gate_desc *g) |
f8822f42 | 269 | { |
8d947344 | 270 | PVOP_VCALL3(pv_cpu_ops.write_idt_entry, dt, entry, g); |
f8822f42 JF |
271 | } |
272 | static inline void set_iopl_mask(unsigned mask) | |
273 | { | |
93b1eab3 | 274 | PVOP_VCALL1(pv_cpu_ops.set_iopl_mask, mask); |
f8822f42 | 275 | } |
3dc494e8 | 276 | |
d3561b7f | 277 | /* The paravirtualized I/O functions */ |
49cd740b JP |
278 | static inline void slow_down_io(void) |
279 | { | |
93b1eab3 | 280 | pv_cpu_ops.io_delay(); |
d3561b7f | 281 | #ifdef REALLY_SLOW_IO |
93b1eab3 JF |
282 | pv_cpu_ops.io_delay(); |
283 | pv_cpu_ops.io_delay(); | |
284 | pv_cpu_ops.io_delay(); | |
d3561b7f RR |
285 | #endif |
286 | } | |
287 | ||
ae5da273 ZA |
288 | #ifdef CONFIG_SMP |
289 | static inline void startup_ipi_hook(int phys_apicid, unsigned long start_eip, | |
290 | unsigned long start_esp) | |
291 | { | |
93b1eab3 JF |
292 | PVOP_VCALL3(pv_apic_ops.startup_ipi_hook, |
293 | phys_apicid, start_eip, start_esp); | |
ae5da273 ZA |
294 | } |
295 | #endif | |
13623d79 | 296 | |
d6dd61c8 JF |
297 | static inline void paravirt_activate_mm(struct mm_struct *prev, |
298 | struct mm_struct *next) | |
299 | { | |
93b1eab3 | 300 | PVOP_VCALL2(pv_mmu_ops.activate_mm, prev, next); |
d6dd61c8 JF |
301 | } |
302 | ||
a1ea1c03 DH |
303 | static inline void paravirt_arch_dup_mmap(struct mm_struct *oldmm, |
304 | struct mm_struct *mm) | |
d6dd61c8 | 305 | { |
93b1eab3 | 306 | PVOP_VCALL2(pv_mmu_ops.dup_mmap, oldmm, mm); |
d6dd61c8 JF |
307 | } |
308 | ||
a1ea1c03 | 309 | static inline void paravirt_arch_exit_mmap(struct mm_struct *mm) |
d6dd61c8 | 310 | { |
93b1eab3 | 311 | PVOP_VCALL1(pv_mmu_ops.exit_mmap, mm); |
d6dd61c8 JF |
312 | } |
313 | ||
f8822f42 JF |
314 | static inline void __flush_tlb(void) |
315 | { | |
93b1eab3 | 316 | PVOP_VCALL0(pv_mmu_ops.flush_tlb_user); |
f8822f42 JF |
317 | } |
318 | static inline void __flush_tlb_global(void) | |
319 | { | |
93b1eab3 | 320 | PVOP_VCALL0(pv_mmu_ops.flush_tlb_kernel); |
f8822f42 JF |
321 | } |
322 | static inline void __flush_tlb_single(unsigned long addr) | |
323 | { | |
93b1eab3 | 324 | PVOP_VCALL1(pv_mmu_ops.flush_tlb_single, addr); |
f8822f42 | 325 | } |
da181a8b | 326 | |
4595f962 RR |
327 | static inline void flush_tlb_others(const struct cpumask *cpumask, |
328 | struct mm_struct *mm, | |
e7b52ffd AS |
329 | unsigned long start, |
330 | unsigned long end) | |
d4c10477 | 331 | { |
e7b52ffd | 332 | PVOP_VCALL4(pv_mmu_ops.flush_tlb_others, cpumask, mm, start, end); |
d4c10477 JF |
333 | } |
334 | ||
eba0045f JF |
335 | static inline int paravirt_pgd_alloc(struct mm_struct *mm) |
336 | { | |
337 | return PVOP_CALL1(int, pv_mmu_ops.pgd_alloc, mm); | |
338 | } | |
339 | ||
340 | static inline void paravirt_pgd_free(struct mm_struct *mm, pgd_t *pgd) | |
341 | { | |
342 | PVOP_VCALL2(pv_mmu_ops.pgd_free, mm, pgd); | |
343 | } | |
344 | ||
f8639939 | 345 | static inline void paravirt_alloc_pte(struct mm_struct *mm, unsigned long pfn) |
f8822f42 | 346 | { |
6944a9c8 | 347 | PVOP_VCALL2(pv_mmu_ops.alloc_pte, mm, pfn); |
f8822f42 | 348 | } |
f8639939 | 349 | static inline void paravirt_release_pte(unsigned long pfn) |
f8822f42 | 350 | { |
6944a9c8 | 351 | PVOP_VCALL1(pv_mmu_ops.release_pte, pfn); |
f8822f42 | 352 | } |
c119ecce | 353 | |
f8639939 | 354 | static inline void paravirt_alloc_pmd(struct mm_struct *mm, unsigned long pfn) |
f8822f42 | 355 | { |
6944a9c8 | 356 | PVOP_VCALL2(pv_mmu_ops.alloc_pmd, mm, pfn); |
f8822f42 | 357 | } |
c119ecce | 358 | |
f8639939 | 359 | static inline void paravirt_release_pmd(unsigned long pfn) |
da181a8b | 360 | { |
6944a9c8 | 361 | PVOP_VCALL1(pv_mmu_ops.release_pmd, pfn); |
da181a8b RR |
362 | } |
363 | ||
f8639939 | 364 | static inline void paravirt_alloc_pud(struct mm_struct *mm, unsigned long pfn) |
2761fa09 JF |
365 | { |
366 | PVOP_VCALL2(pv_mmu_ops.alloc_pud, mm, pfn); | |
367 | } | |
f8639939 | 368 | static inline void paravirt_release_pud(unsigned long pfn) |
2761fa09 JF |
369 | { |
370 | PVOP_VCALL1(pv_mmu_ops.release_pud, pfn); | |
371 | } | |
372 | ||
f8822f42 JF |
373 | static inline void pte_update(struct mm_struct *mm, unsigned long addr, |
374 | pte_t *ptep) | |
da181a8b | 375 | { |
93b1eab3 | 376 | PVOP_VCALL3(pv_mmu_ops.pte_update, mm, addr, ptep); |
da181a8b | 377 | } |
331127f7 AA |
378 | static inline void pmd_update(struct mm_struct *mm, unsigned long addr, |
379 | pmd_t *pmdp) | |
380 | { | |
381 | PVOP_VCALL3(pv_mmu_ops.pmd_update, mm, addr, pmdp); | |
382 | } | |
da181a8b | 383 | |
f8822f42 JF |
384 | static inline void pte_update_defer(struct mm_struct *mm, unsigned long addr, |
385 | pte_t *ptep) | |
da181a8b | 386 | { |
93b1eab3 | 387 | PVOP_VCALL3(pv_mmu_ops.pte_update_defer, mm, addr, ptep); |
da181a8b RR |
388 | } |
389 | ||
331127f7 AA |
390 | static inline void pmd_update_defer(struct mm_struct *mm, unsigned long addr, |
391 | pmd_t *pmdp) | |
392 | { | |
393 | PVOP_VCALL3(pv_mmu_ops.pmd_update_defer, mm, addr, pmdp); | |
394 | } | |
395 | ||
773221f4 | 396 | static inline pte_t __pte(pteval_t val) |
da181a8b | 397 | { |
773221f4 JF |
398 | pteval_t ret; |
399 | ||
400 | if (sizeof(pteval_t) > sizeof(long)) | |
da5de7c2 JF |
401 | ret = PVOP_CALLEE2(pteval_t, |
402 | pv_mmu_ops.make_pte, | |
403 | val, (u64)val >> 32); | |
773221f4 | 404 | else |
da5de7c2 JF |
405 | ret = PVOP_CALLEE1(pteval_t, |
406 | pv_mmu_ops.make_pte, | |
407 | val); | |
773221f4 | 408 | |
c8e5393a | 409 | return (pte_t) { .pte = ret }; |
da181a8b RR |
410 | } |
411 | ||
773221f4 JF |
412 | static inline pteval_t pte_val(pte_t pte) |
413 | { | |
414 | pteval_t ret; | |
415 | ||
416 | if (sizeof(pteval_t) > sizeof(long)) | |
da5de7c2 JF |
417 | ret = PVOP_CALLEE2(pteval_t, pv_mmu_ops.pte_val, |
418 | pte.pte, (u64)pte.pte >> 32); | |
773221f4 | 419 | else |
da5de7c2 JF |
420 | ret = PVOP_CALLEE1(pteval_t, pv_mmu_ops.pte_val, |
421 | pte.pte); | |
773221f4 JF |
422 | |
423 | return ret; | |
424 | } | |
425 | ||
ef38503e | 426 | static inline pgd_t __pgd(pgdval_t val) |
da181a8b | 427 | { |
ef38503e JF |
428 | pgdval_t ret; |
429 | ||
430 | if (sizeof(pgdval_t) > sizeof(long)) | |
da5de7c2 JF |
431 | ret = PVOP_CALLEE2(pgdval_t, pv_mmu_ops.make_pgd, |
432 | val, (u64)val >> 32); | |
ef38503e | 433 | else |
da5de7c2 JF |
434 | ret = PVOP_CALLEE1(pgdval_t, pv_mmu_ops.make_pgd, |
435 | val); | |
ef38503e JF |
436 | |
437 | return (pgd_t) { ret }; | |
438 | } | |
439 | ||
440 | static inline pgdval_t pgd_val(pgd_t pgd) | |
441 | { | |
442 | pgdval_t ret; | |
443 | ||
444 | if (sizeof(pgdval_t) > sizeof(long)) | |
da5de7c2 JF |
445 | ret = PVOP_CALLEE2(pgdval_t, pv_mmu_ops.pgd_val, |
446 | pgd.pgd, (u64)pgd.pgd >> 32); | |
ef38503e | 447 | else |
da5de7c2 JF |
448 | ret = PVOP_CALLEE1(pgdval_t, pv_mmu_ops.pgd_val, |
449 | pgd.pgd); | |
ef38503e JF |
450 | |
451 | return ret; | |
f8822f42 JF |
452 | } |
453 | ||
08b882c6 JF |
454 | #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION |
455 | static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, unsigned long addr, | |
456 | pte_t *ptep) | |
457 | { | |
458 | pteval_t ret; | |
459 | ||
460 | ret = PVOP_CALL3(pteval_t, pv_mmu_ops.ptep_modify_prot_start, | |
461 | mm, addr, ptep); | |
462 | ||
463 | return (pte_t) { .pte = ret }; | |
464 | } | |
465 | ||
466 | static inline void ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr, | |
467 | pte_t *ptep, pte_t pte) | |
468 | { | |
469 | if (sizeof(pteval_t) > sizeof(long)) | |
470 | /* 5 arg words */ | |
471 | pv_mmu_ops.ptep_modify_prot_commit(mm, addr, ptep, pte); | |
472 | else | |
473 | PVOP_VCALL4(pv_mmu_ops.ptep_modify_prot_commit, | |
474 | mm, addr, ptep, pte.pte); | |
475 | } | |
476 | ||
4eed80cd JF |
477 | static inline void set_pte(pte_t *ptep, pte_t pte) |
478 | { | |
479 | if (sizeof(pteval_t) > sizeof(long)) | |
480 | PVOP_VCALL3(pv_mmu_ops.set_pte, ptep, | |
481 | pte.pte, (u64)pte.pte >> 32); | |
482 | else | |
483 | PVOP_VCALL2(pv_mmu_ops.set_pte, ptep, | |
484 | pte.pte); | |
485 | } | |
486 | ||
487 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, | |
488 | pte_t *ptep, pte_t pte) | |
489 | { | |
490 | if (sizeof(pteval_t) > sizeof(long)) | |
491 | /* 5 arg words */ | |
492 | pv_mmu_ops.set_pte_at(mm, addr, ptep, pte); | |
493 | else | |
494 | PVOP_VCALL4(pv_mmu_ops.set_pte_at, mm, addr, ptep, pte.pte); | |
495 | } | |
496 | ||
331127f7 AA |
497 | static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, |
498 | pmd_t *pmdp, pmd_t pmd) | |
499 | { | |
331127f7 AA |
500 | if (sizeof(pmdval_t) > sizeof(long)) |
501 | /* 5 arg words */ | |
502 | pv_mmu_ops.set_pmd_at(mm, addr, pmdp, pmd); | |
503 | else | |
cacf061c AA |
504 | PVOP_VCALL4(pv_mmu_ops.set_pmd_at, mm, addr, pmdp, |
505 | native_pmd_val(pmd)); | |
331127f7 | 506 | } |
331127f7 | 507 | |
60b3f626 JF |
508 | static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) |
509 | { | |
510 | pmdval_t val = native_pmd_val(pmd); | |
511 | ||
512 | if (sizeof(pmdval_t) > sizeof(long)) | |
513 | PVOP_VCALL3(pv_mmu_ops.set_pmd, pmdp, val, (u64)val >> 32); | |
514 | else | |
515 | PVOP_VCALL2(pv_mmu_ops.set_pmd, pmdp, val); | |
516 | } | |
517 | ||
98233368 | 518 | #if CONFIG_PGTABLE_LEVELS >= 3 |
1fe91514 GOC |
519 | static inline pmd_t __pmd(pmdval_t val) |
520 | { | |
521 | pmdval_t ret; | |
522 | ||
523 | if (sizeof(pmdval_t) > sizeof(long)) | |
da5de7c2 JF |
524 | ret = PVOP_CALLEE2(pmdval_t, pv_mmu_ops.make_pmd, |
525 | val, (u64)val >> 32); | |
1fe91514 | 526 | else |
da5de7c2 JF |
527 | ret = PVOP_CALLEE1(pmdval_t, pv_mmu_ops.make_pmd, |
528 | val); | |
1fe91514 GOC |
529 | |
530 | return (pmd_t) { ret }; | |
531 | } | |
532 | ||
533 | static inline pmdval_t pmd_val(pmd_t pmd) | |
534 | { | |
535 | pmdval_t ret; | |
536 | ||
537 | if (sizeof(pmdval_t) > sizeof(long)) | |
da5de7c2 JF |
538 | ret = PVOP_CALLEE2(pmdval_t, pv_mmu_ops.pmd_val, |
539 | pmd.pmd, (u64)pmd.pmd >> 32); | |
1fe91514 | 540 | else |
da5de7c2 JF |
541 | ret = PVOP_CALLEE1(pmdval_t, pv_mmu_ops.pmd_val, |
542 | pmd.pmd); | |
1fe91514 GOC |
543 | |
544 | return ret; | |
545 | } | |
546 | ||
547 | static inline void set_pud(pud_t *pudp, pud_t pud) | |
548 | { | |
549 | pudval_t val = native_pud_val(pud); | |
550 | ||
551 | if (sizeof(pudval_t) > sizeof(long)) | |
552 | PVOP_VCALL3(pv_mmu_ops.set_pud, pudp, | |
553 | val, (u64)val >> 32); | |
554 | else | |
555 | PVOP_VCALL2(pv_mmu_ops.set_pud, pudp, | |
556 | val); | |
557 | } | |
98233368 | 558 | #if CONFIG_PGTABLE_LEVELS == 4 |
9042219c EH |
559 | static inline pud_t __pud(pudval_t val) |
560 | { | |
561 | pudval_t ret; | |
562 | ||
563 | if (sizeof(pudval_t) > sizeof(long)) | |
da5de7c2 JF |
564 | ret = PVOP_CALLEE2(pudval_t, pv_mmu_ops.make_pud, |
565 | val, (u64)val >> 32); | |
9042219c | 566 | else |
da5de7c2 JF |
567 | ret = PVOP_CALLEE1(pudval_t, pv_mmu_ops.make_pud, |
568 | val); | |
9042219c EH |
569 | |
570 | return (pud_t) { ret }; | |
571 | } | |
572 | ||
573 | static inline pudval_t pud_val(pud_t pud) | |
574 | { | |
575 | pudval_t ret; | |
576 | ||
577 | if (sizeof(pudval_t) > sizeof(long)) | |
4767afbf JF |
578 | ret = PVOP_CALLEE2(pudval_t, pv_mmu_ops.pud_val, |
579 | pud.pud, (u64)pud.pud >> 32); | |
9042219c | 580 | else |
4767afbf JF |
581 | ret = PVOP_CALLEE1(pudval_t, pv_mmu_ops.pud_val, |
582 | pud.pud); | |
9042219c EH |
583 | |
584 | return ret; | |
585 | } | |
586 | ||
587 | static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) | |
588 | { | |
589 | pgdval_t val = native_pgd_val(pgd); | |
590 | ||
591 | if (sizeof(pgdval_t) > sizeof(long)) | |
592 | PVOP_VCALL3(pv_mmu_ops.set_pgd, pgdp, | |
593 | val, (u64)val >> 32); | |
594 | else | |
595 | PVOP_VCALL2(pv_mmu_ops.set_pgd, pgdp, | |
596 | val); | |
597 | } | |
598 | ||
599 | static inline void pgd_clear(pgd_t *pgdp) | |
600 | { | |
601 | set_pgd(pgdp, __pgd(0)); | |
602 | } | |
603 | ||
604 | static inline void pud_clear(pud_t *pudp) | |
605 | { | |
606 | set_pud(pudp, __pud(0)); | |
607 | } | |
608 | ||
98233368 | 609 | #endif /* CONFIG_PGTABLE_LEVELS == 4 */ |
9042219c | 610 | |
98233368 | 611 | #endif /* CONFIG_PGTABLE_LEVELS >= 3 */ |
1fe91514 | 612 | |
4eed80cd JF |
613 | #ifdef CONFIG_X86_PAE |
614 | /* Special-case pte-setting operations for PAE, which can't update a | |
615 | 64-bit pte atomically */ | |
616 | static inline void set_pte_atomic(pte_t *ptep, pte_t pte) | |
617 | { | |
618 | PVOP_VCALL3(pv_mmu_ops.set_pte_atomic, ptep, | |
619 | pte.pte, pte.pte >> 32); | |
620 | } | |
621 | ||
4eed80cd JF |
622 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, |
623 | pte_t *ptep) | |
624 | { | |
625 | PVOP_VCALL3(pv_mmu_ops.pte_clear, mm, addr, ptep); | |
626 | } | |
60b3f626 JF |
627 | |
628 | static inline void pmd_clear(pmd_t *pmdp) | |
629 | { | |
630 | PVOP_VCALL1(pv_mmu_ops.pmd_clear, pmdp); | |
631 | } | |
4eed80cd JF |
632 | #else /* !CONFIG_X86_PAE */ |
633 | static inline void set_pte_atomic(pte_t *ptep, pte_t pte) | |
634 | { | |
635 | set_pte(ptep, pte); | |
636 | } | |
637 | ||
4eed80cd JF |
638 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, |
639 | pte_t *ptep) | |
640 | { | |
641 | set_pte_at(mm, addr, ptep, __pte(0)); | |
642 | } | |
60b3f626 JF |
643 | |
644 | static inline void pmd_clear(pmd_t *pmdp) | |
645 | { | |
646 | set_pmd(pmdp, __pmd(0)); | |
647 | } | |
4eed80cd JF |
648 | #endif /* CONFIG_X86_PAE */ |
649 | ||
7fd7d83d | 650 | #define __HAVE_ARCH_START_CONTEXT_SWITCH |
224101ed | 651 | static inline void arch_start_context_switch(struct task_struct *prev) |
f8822f42 | 652 | { |
224101ed | 653 | PVOP_VCALL1(pv_cpu_ops.start_context_switch, prev); |
f8822f42 JF |
654 | } |
655 | ||
224101ed | 656 | static inline void arch_end_context_switch(struct task_struct *next) |
f8822f42 | 657 | { |
224101ed | 658 | PVOP_VCALL1(pv_cpu_ops.end_context_switch, next); |
f8822f42 JF |
659 | } |
660 | ||
9226d125 | 661 | #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE |
f8822f42 JF |
662 | static inline void arch_enter_lazy_mmu_mode(void) |
663 | { | |
8965c1c0 | 664 | PVOP_VCALL0(pv_mmu_ops.lazy_mode.enter); |
f8822f42 JF |
665 | } |
666 | ||
667 | static inline void arch_leave_lazy_mmu_mode(void) | |
668 | { | |
8965c1c0 | 669 | PVOP_VCALL0(pv_mmu_ops.lazy_mode.leave); |
f8822f42 JF |
670 | } |
671 | ||
511ba86e BO |
672 | static inline void arch_flush_lazy_mmu_mode(void) |
673 | { | |
674 | PVOP_VCALL0(pv_mmu_ops.lazy_mode.flush); | |
675 | } | |
9226d125 | 676 | |
aeaaa59c | 677 | static inline void __set_fixmap(unsigned /* enum fixed_addresses */ idx, |
3b3809ac | 678 | phys_addr_t phys, pgprot_t flags) |
aeaaa59c JF |
679 | { |
680 | pv_mmu_ops.set_fixmap(idx, phys, flags); | |
681 | } | |
682 | ||
b4ecc126 | 683 | #if defined(CONFIG_SMP) && defined(CONFIG_PARAVIRT_SPINLOCKS) |
4bb689ee | 684 | |
62c7a1e9 | 685 | #ifdef CONFIG_QUEUED_SPINLOCKS |
f233f7f1 PZI |
686 | |
687 | static __always_inline void pv_queued_spin_lock_slowpath(struct qspinlock *lock, | |
688 | u32 val) | |
689 | { | |
690 | PVOP_VCALL2(pv_lock_ops.queued_spin_lock_slowpath, lock, val); | |
691 | } | |
692 | ||
693 | static __always_inline void pv_queued_spin_unlock(struct qspinlock *lock) | |
694 | { | |
695 | PVOP_VCALLEE1(pv_lock_ops.queued_spin_unlock, lock); | |
696 | } | |
697 | ||
698 | static __always_inline void pv_wait(u8 *ptr, u8 val) | |
699 | { | |
700 | PVOP_VCALL2(pv_lock_ops.wait, ptr, val); | |
701 | } | |
702 | ||
703 | static __always_inline void pv_kick(int cpu) | |
704 | { | |
705 | PVOP_VCALL1(pv_lock_ops.kick, cpu); | |
706 | } | |
707 | ||
62c7a1e9 | 708 | #else /* !CONFIG_QUEUED_SPINLOCKS */ |
f233f7f1 | 709 | |
545ac138 JF |
710 | static __always_inline void __ticket_lock_spinning(struct arch_spinlock *lock, |
711 | __ticket_t ticket) | |
74d4affd | 712 | { |
354714dd | 713 | PVOP_VCALLEE2(pv_lock_ops.lock_spinning, lock, ticket); |
74d4affd JF |
714 | } |
715 | ||
96f853ea | 716 | static __always_inline void __ticket_unlock_kick(struct arch_spinlock *lock, |
545ac138 | 717 | __ticket_t ticket) |
74d4affd | 718 | { |
545ac138 | 719 | PVOP_VCALL2(pv_lock_ops.unlock_kick, lock, ticket); |
74d4affd JF |
720 | } |
721 | ||
62c7a1e9 | 722 | #endif /* CONFIG_QUEUED_SPINLOCKS */ |
f233f7f1 PZI |
723 | |
724 | #endif /* SMP && PARAVIRT_SPINLOCKS */ | |
4bb689ee | 725 | |
2e47d3e6 | 726 | #ifdef CONFIG_X86_32 |
ecb93d1c JF |
727 | #define PV_SAVE_REGS "pushl %ecx; pushl %edx;" |
728 | #define PV_RESTORE_REGS "popl %edx; popl %ecx;" | |
729 | ||
730 | /* save and restore all caller-save registers, except return value */ | |
e584f559 JF |
731 | #define PV_SAVE_ALL_CALLER_REGS "pushl %ecx;" |
732 | #define PV_RESTORE_ALL_CALLER_REGS "popl %ecx;" | |
ecb93d1c | 733 | |
2e47d3e6 GOC |
734 | #define PV_FLAGS_ARG "0" |
735 | #define PV_EXTRA_CLOBBERS | |
736 | #define PV_VEXTRA_CLOBBERS | |
737 | #else | |
ecb93d1c JF |
738 | /* save and restore all caller-save registers, except return value */ |
739 | #define PV_SAVE_ALL_CALLER_REGS \ | |
740 | "push %rcx;" \ | |
741 | "push %rdx;" \ | |
742 | "push %rsi;" \ | |
743 | "push %rdi;" \ | |
744 | "push %r8;" \ | |
745 | "push %r9;" \ | |
746 | "push %r10;" \ | |
747 | "push %r11;" | |
748 | #define PV_RESTORE_ALL_CALLER_REGS \ | |
749 | "pop %r11;" \ | |
750 | "pop %r10;" \ | |
751 | "pop %r9;" \ | |
752 | "pop %r8;" \ | |
753 | "pop %rdi;" \ | |
754 | "pop %rsi;" \ | |
755 | "pop %rdx;" \ | |
756 | "pop %rcx;" | |
757 | ||
2e47d3e6 GOC |
758 | /* We save some registers, but all of them, that's too much. We clobber all |
759 | * caller saved registers but the argument parameter */ | |
760 | #define PV_SAVE_REGS "pushq %%rdi;" | |
761 | #define PV_RESTORE_REGS "popq %%rdi;" | |
c24481e9 JF |
762 | #define PV_EXTRA_CLOBBERS EXTRA_CLOBBERS, "rcx" , "rdx", "rsi" |
763 | #define PV_VEXTRA_CLOBBERS EXTRA_CLOBBERS, "rdi", "rcx" , "rdx", "rsi" | |
2e47d3e6 GOC |
764 | #define PV_FLAGS_ARG "D" |
765 | #endif | |
766 | ||
ecb93d1c JF |
767 | /* |
768 | * Generate a thunk around a function which saves all caller-save | |
769 | * registers except for the return value. This allows C functions to | |
770 | * be called from assembler code where fewer than normal registers are | |
771 | * available. It may also help code generation around calls from C | |
772 | * code if the common case doesn't use many registers. | |
773 | * | |
774 | * When a callee is wrapped in a thunk, the caller can assume that all | |
775 | * arg regs and all scratch registers are preserved across the | |
776 | * call. The return value in rax/eax will not be saved, even for void | |
777 | * functions. | |
778 | */ | |
779 | #define PV_CALLEE_SAVE_REGS_THUNK(func) \ | |
780 | extern typeof(func) __raw_callee_save_##func; \ | |
ecb93d1c JF |
781 | \ |
782 | asm(".pushsection .text;" \ | |
a2e7f0e3 | 783 | ".globl __raw_callee_save_" #func " ; " \ |
ecb93d1c JF |
784 | "__raw_callee_save_" #func ": " \ |
785 | PV_SAVE_ALL_CALLER_REGS \ | |
786 | "call " #func ";" \ | |
787 | PV_RESTORE_ALL_CALLER_REGS \ | |
788 | "ret;" \ | |
789 | ".popsection") | |
790 | ||
791 | /* Get a reference to a callee-save function */ | |
792 | #define PV_CALLEE_SAVE(func) \ | |
793 | ((struct paravirt_callee_save) { __raw_callee_save_##func }) | |
794 | ||
795 | /* Promise that "func" already uses the right calling convention */ | |
796 | #define __PV_IS_CALLEE_SAVE(func) \ | |
797 | ((struct paravirt_callee_save) { func }) | |
798 | ||
b5908548 | 799 | static inline notrace unsigned long arch_local_save_flags(void) |
139ec7c4 | 800 | { |
71999d98 | 801 | return PVOP_CALLEE0(unsigned long, pv_irq_ops.save_fl); |
139ec7c4 RR |
802 | } |
803 | ||
b5908548 | 804 | static inline notrace void arch_local_irq_restore(unsigned long f) |
139ec7c4 | 805 | { |
71999d98 | 806 | PVOP_VCALLEE1(pv_irq_ops.restore_fl, f); |
139ec7c4 RR |
807 | } |
808 | ||
b5908548 | 809 | static inline notrace void arch_local_irq_disable(void) |
139ec7c4 | 810 | { |
71999d98 | 811 | PVOP_VCALLEE0(pv_irq_ops.irq_disable); |
139ec7c4 RR |
812 | } |
813 | ||
b5908548 | 814 | static inline notrace void arch_local_irq_enable(void) |
139ec7c4 | 815 | { |
71999d98 | 816 | PVOP_VCALLEE0(pv_irq_ops.irq_enable); |
139ec7c4 RR |
817 | } |
818 | ||
b5908548 | 819 | static inline notrace unsigned long arch_local_irq_save(void) |
139ec7c4 RR |
820 | { |
821 | unsigned long f; | |
822 | ||
df9ee292 DH |
823 | f = arch_local_save_flags(); |
824 | arch_local_irq_disable(); | |
139ec7c4 RR |
825 | return f; |
826 | } | |
827 | ||
74d4affd | 828 | |
294688c0 | 829 | /* Make sure as little as possible of this mess escapes. */ |
d5822035 | 830 | #undef PARAVIRT_CALL |
1a45b7aa JF |
831 | #undef __PVOP_CALL |
832 | #undef __PVOP_VCALL | |
f8822f42 JF |
833 | #undef PVOP_VCALL0 |
834 | #undef PVOP_CALL0 | |
835 | #undef PVOP_VCALL1 | |
836 | #undef PVOP_CALL1 | |
837 | #undef PVOP_VCALL2 | |
838 | #undef PVOP_CALL2 | |
839 | #undef PVOP_VCALL3 | |
840 | #undef PVOP_CALL3 | |
841 | #undef PVOP_VCALL4 | |
842 | #undef PVOP_CALL4 | |
139ec7c4 | 843 | |
6f30c1ac TG |
844 | extern void default_banner(void); |
845 | ||
d3561b7f RR |
846 | #else /* __ASSEMBLY__ */ |
847 | ||
658be9d3 | 848 | #define _PVSITE(ptype, clobbers, ops, word, algn) \ |
139ec7c4 RR |
849 | 771:; \ |
850 | ops; \ | |
851 | 772:; \ | |
852 | .pushsection .parainstructions,"a"; \ | |
658be9d3 GOC |
853 | .align algn; \ |
854 | word 771b; \ | |
139ec7c4 RR |
855 | .byte ptype; \ |
856 | .byte 772b-771b; \ | |
857 | .short clobbers; \ | |
858 | .popsection | |
859 | ||
658be9d3 | 860 | |
9104a18d | 861 | #define COND_PUSH(set, mask, reg) \ |
ecb93d1c | 862 | .if ((~(set)) & mask); push %reg; .endif |
9104a18d | 863 | #define COND_POP(set, mask, reg) \ |
ecb93d1c | 864 | .if ((~(set)) & mask); pop %reg; .endif |
9104a18d | 865 | |
658be9d3 | 866 | #ifdef CONFIG_X86_64 |
9104a18d JF |
867 | |
868 | #define PV_SAVE_REGS(set) \ | |
869 | COND_PUSH(set, CLBR_RAX, rax); \ | |
870 | COND_PUSH(set, CLBR_RCX, rcx); \ | |
871 | COND_PUSH(set, CLBR_RDX, rdx); \ | |
872 | COND_PUSH(set, CLBR_RSI, rsi); \ | |
873 | COND_PUSH(set, CLBR_RDI, rdi); \ | |
874 | COND_PUSH(set, CLBR_R8, r8); \ | |
875 | COND_PUSH(set, CLBR_R9, r9); \ | |
876 | COND_PUSH(set, CLBR_R10, r10); \ | |
877 | COND_PUSH(set, CLBR_R11, r11) | |
878 | #define PV_RESTORE_REGS(set) \ | |
879 | COND_POP(set, CLBR_R11, r11); \ | |
880 | COND_POP(set, CLBR_R10, r10); \ | |
881 | COND_POP(set, CLBR_R9, r9); \ | |
882 | COND_POP(set, CLBR_R8, r8); \ | |
883 | COND_POP(set, CLBR_RDI, rdi); \ | |
884 | COND_POP(set, CLBR_RSI, rsi); \ | |
885 | COND_POP(set, CLBR_RDX, rdx); \ | |
886 | COND_POP(set, CLBR_RCX, rcx); \ | |
887 | COND_POP(set, CLBR_RAX, rax) | |
888 | ||
6057fc82 | 889 | #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 8) |
658be9d3 | 890 | #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .quad, 8) |
491eccb7 | 891 | #define PARA_INDIRECT(addr) *addr(%rip) |
658be9d3 | 892 | #else |
9104a18d JF |
893 | #define PV_SAVE_REGS(set) \ |
894 | COND_PUSH(set, CLBR_EAX, eax); \ | |
895 | COND_PUSH(set, CLBR_EDI, edi); \ | |
896 | COND_PUSH(set, CLBR_ECX, ecx); \ | |
897 | COND_PUSH(set, CLBR_EDX, edx) | |
898 | #define PV_RESTORE_REGS(set) \ | |
899 | COND_POP(set, CLBR_EDX, edx); \ | |
900 | COND_POP(set, CLBR_ECX, ecx); \ | |
901 | COND_POP(set, CLBR_EDI, edi); \ | |
902 | COND_POP(set, CLBR_EAX, eax) | |
903 | ||
6057fc82 | 904 | #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 4) |
658be9d3 | 905 | #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .long, 4) |
491eccb7 | 906 | #define PARA_INDIRECT(addr) *%cs:addr |
658be9d3 GOC |
907 | #endif |
908 | ||
93b1eab3 JF |
909 | #define INTERRUPT_RETURN \ |
910 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_iret), CLBR_NONE, \ | |
491eccb7 | 911 | jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_iret)) |
d5822035 JF |
912 | |
913 | #define DISABLE_INTERRUPTS(clobbers) \ | |
93b1eab3 | 914 | PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_disable), clobbers, \ |
ecb93d1c | 915 | PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \ |
491eccb7 | 916 | call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_disable); \ |
ecb93d1c | 917 | PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);) |
d5822035 JF |
918 | |
919 | #define ENABLE_INTERRUPTS(clobbers) \ | |
93b1eab3 | 920 | PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_enable), clobbers, \ |
ecb93d1c | 921 | PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \ |
491eccb7 | 922 | call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_enable); \ |
ecb93d1c | 923 | PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);) |
d5822035 | 924 | |
2be29982 JF |
925 | #define USERGS_SYSRET32 \ |
926 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_usergs_sysret32), \ | |
6abcd98f | 927 | CLBR_NONE, \ |
2be29982 | 928 | jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_usergs_sysret32)) |
2e47d3e6 | 929 | |
6057fc82 | 930 | #ifdef CONFIG_X86_32 |
491eccb7 JF |
931 | #define GET_CR0_INTO_EAX \ |
932 | push %ecx; push %edx; \ | |
933 | call PARA_INDIRECT(pv_cpu_ops+PV_CPU_read_cr0); \ | |
42c24fa2 | 934 | pop %edx; pop %ecx |
2be29982 JF |
935 | |
936 | #define ENABLE_INTERRUPTS_SYSEXIT \ | |
937 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_irq_enable_sysexit), \ | |
938 | CLBR_NONE, \ | |
939 | jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_irq_enable_sysexit)) | |
940 | ||
941 | ||
942 | #else /* !CONFIG_X86_32 */ | |
a00394f8 JF |
943 | |
944 | /* | |
945 | * If swapgs is used while the userspace stack is still current, | |
946 | * there's no way to call a pvop. The PV replacement *must* be | |
947 | * inlined, or the swapgs instruction must be trapped and emulated. | |
948 | */ | |
949 | #define SWAPGS_UNSAFE_STACK \ | |
950 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \ | |
951 | swapgs) | |
952 | ||
9104a18d JF |
953 | /* |
954 | * Note: swapgs is very special, and in practise is either going to be | |
955 | * implemented with a single "swapgs" instruction or something very | |
956 | * special. Either way, we don't need to save any registers for | |
957 | * it. | |
958 | */ | |
e801f864 GOC |
959 | #define SWAPGS \ |
960 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \ | |
9104a18d | 961 | call PARA_INDIRECT(pv_cpu_ops+PV_CPU_swapgs) \ |
e801f864 GOC |
962 | ) |
963 | ||
ffc4bc9c PA |
964 | #define GET_CR2_INTO_RAX \ |
965 | call PARA_INDIRECT(pv_mmu_ops+PV_MMU_read_cr2) | |
4a8c4c4e | 966 | |
fab58420 JF |
967 | #define PARAVIRT_ADJUST_EXCEPTION_FRAME \ |
968 | PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_adjust_exception_frame), \ | |
969 | CLBR_NONE, \ | |
970 | call PARA_INDIRECT(pv_irq_ops+PV_IRQ_adjust_exception_frame)) | |
971 | ||
2be29982 JF |
972 | #define USERGS_SYSRET64 \ |
973 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_usergs_sysret64), \ | |
d75cd22f | 974 | CLBR_NONE, \ |
2be29982 | 975 | jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_usergs_sysret64)) |
2be29982 | 976 | #endif /* CONFIG_X86_32 */ |
139ec7c4 | 977 | |
d3561b7f | 978 | #endif /* __ASSEMBLY__ */ |
6f30c1ac TG |
979 | #else /* CONFIG_PARAVIRT */ |
980 | # define default_banner x86_init_noop | |
a1ea1c03 DH |
981 | #ifndef __ASSEMBLY__ |
982 | static inline void paravirt_arch_dup_mmap(struct mm_struct *oldmm, | |
983 | struct mm_struct *mm) | |
984 | { | |
985 | } | |
986 | ||
987 | static inline void paravirt_arch_exit_mmap(struct mm_struct *mm) | |
988 | { | |
989 | } | |
990 | #endif /* __ASSEMBLY__ */ | |
6f30c1ac | 991 | #endif /* !CONFIG_PARAVIRT */ |
1965aae3 | 992 | #endif /* _ASM_X86_PARAVIRT_H */ |