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b6c02715 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
23 | #include <linux/scatterlist.h> | |
24 | #include <linux/iommu-helper.h> | |
25 | #include <asm/proto.h> | |
46a7fa27 | 26 | #include <asm/iommu.h> |
1d9b16d1 | 27 | #include <asm/gart.h> |
b6c02715 | 28 | #include <asm/amd_iommu_types.h> |
c6da992e | 29 | #include <asm/amd_iommu.h> |
b6c02715 JR |
30 | |
31 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
32 | ||
136f78a1 JR |
33 | #define EXIT_LOOP_COUNT 10000000 |
34 | ||
b6c02715 JR |
35 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
36 | ||
bd60b735 JR |
37 | /* A list of preallocated protection domains */ |
38 | static LIST_HEAD(iommu_pd_list); | |
39 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
40 | ||
431b2a20 JR |
41 | /* |
42 | * general struct to manage commands send to an IOMMU | |
43 | */ | |
d6449536 | 44 | struct iommu_cmd { |
b6c02715 JR |
45 | u32 data[4]; |
46 | }; | |
47 | ||
bd0e5211 JR |
48 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
49 | struct unity_map_entry *e); | |
50 | ||
431b2a20 | 51 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ |
4da70b9e JR |
52 | static int iommu_has_npcache(struct amd_iommu *iommu) |
53 | { | |
ae9b9403 | 54 | return iommu->cap & (1UL << IOMMU_CAP_NPCACHE); |
4da70b9e JR |
55 | } |
56 | ||
a80dc3e0 JR |
57 | /**************************************************************************** |
58 | * | |
59 | * Interrupt handling functions | |
60 | * | |
61 | ****************************************************************************/ | |
62 | ||
90008ee4 JR |
63 | static void iommu_print_event(void *__evt) |
64 | { | |
65 | u32 *event = __evt; | |
66 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
67 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
68 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
69 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
70 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
71 | ||
72 | printk(KERN_ERR "AMD IOMMU: Event logged ["); | |
73 | ||
74 | switch (type) { | |
75 | case EVENT_TYPE_ILL_DEV: | |
76 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
77 | "address=0x%016llx flags=0x%04x]\n", | |
78 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
79 | address, flags); | |
80 | break; | |
81 | case EVENT_TYPE_IO_FAULT: | |
82 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
83 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
84 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
85 | domid, address, flags); | |
86 | break; | |
87 | case EVENT_TYPE_DEV_TAB_ERR: | |
88 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
89 | "address=0x%016llx flags=0x%04x]\n", | |
90 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
91 | address, flags); | |
92 | break; | |
93 | case EVENT_TYPE_PAGE_TAB_ERR: | |
94 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
95 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
96 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
97 | domid, address, flags); | |
98 | break; | |
99 | case EVENT_TYPE_ILL_CMD: | |
100 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
101 | break; | |
102 | case EVENT_TYPE_CMD_HARD_ERR: | |
103 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
104 | "flags=0x%04x]\n", address, flags); | |
105 | break; | |
106 | case EVENT_TYPE_IOTLB_INV_TO: | |
107 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
108 | "address=0x%016llx]\n", | |
109 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
110 | address); | |
111 | break; | |
112 | case EVENT_TYPE_INV_DEV_REQ: | |
113 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
114 | "address=0x%016llx flags=0x%04x]\n", | |
115 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
116 | address, flags); | |
117 | break; | |
118 | default: | |
119 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
120 | } | |
121 | } | |
122 | ||
123 | static void iommu_poll_events(struct amd_iommu *iommu) | |
124 | { | |
125 | u32 head, tail; | |
126 | unsigned long flags; | |
127 | ||
128 | spin_lock_irqsave(&iommu->lock, flags); | |
129 | ||
130 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
131 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
132 | ||
133 | while (head != tail) { | |
134 | iommu_print_event(iommu->evt_buf + head); | |
135 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; | |
136 | } | |
137 | ||
138 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
139 | ||
140 | spin_unlock_irqrestore(&iommu->lock, flags); | |
141 | } | |
142 | ||
a80dc3e0 JR |
143 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
144 | { | |
90008ee4 JR |
145 | struct amd_iommu *iommu; |
146 | ||
147 | list_for_each_entry(iommu, &amd_iommu_list, list) | |
148 | iommu_poll_events(iommu); | |
149 | ||
150 | return IRQ_HANDLED; | |
a80dc3e0 JR |
151 | } |
152 | ||
431b2a20 JR |
153 | /**************************************************************************** |
154 | * | |
155 | * IOMMU command queuing functions | |
156 | * | |
157 | ****************************************************************************/ | |
158 | ||
159 | /* | |
160 | * Writes the command to the IOMMUs command buffer and informs the | |
161 | * hardware about the new command. Must be called with iommu->lock held. | |
162 | */ | |
d6449536 | 163 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
164 | { |
165 | u32 tail, head; | |
166 | u8 *target; | |
167 | ||
168 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 169 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
170 | memcpy_toio(target, cmd, sizeof(*cmd)); |
171 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
172 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
173 | if (tail == head) | |
174 | return -ENOMEM; | |
175 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
176 | ||
177 | return 0; | |
178 | } | |
179 | ||
431b2a20 JR |
180 | /* |
181 | * General queuing function for commands. Takes iommu->lock and calls | |
182 | * __iommu_queue_command(). | |
183 | */ | |
d6449536 | 184 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
185 | { |
186 | unsigned long flags; | |
187 | int ret; | |
188 | ||
189 | spin_lock_irqsave(&iommu->lock, flags); | |
190 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb JR |
191 | if (!ret) |
192 | iommu->need_sync = 1; | |
a19ae1ec JR |
193 | spin_unlock_irqrestore(&iommu->lock, flags); |
194 | ||
195 | return ret; | |
196 | } | |
197 | ||
431b2a20 JR |
198 | /* |
199 | * This function is called whenever we need to ensure that the IOMMU has | |
200 | * completed execution of all commands we sent. It sends a | |
201 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
202 | * us about that by writing a value to a physical address we pass with | |
203 | * the command. | |
204 | */ | |
a19ae1ec JR |
205 | static int iommu_completion_wait(struct amd_iommu *iommu) |
206 | { | |
7e4f88da | 207 | int ret = 0, ready = 0; |
519c31ba | 208 | unsigned status = 0; |
d6449536 | 209 | struct iommu_cmd cmd; |
7e4f88da | 210 | unsigned long flags, i = 0; |
a19ae1ec JR |
211 | |
212 | memset(&cmd, 0, sizeof(cmd)); | |
519c31ba | 213 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; |
a19ae1ec JR |
214 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); |
215 | ||
7e4f88da JR |
216 | spin_lock_irqsave(&iommu->lock, flags); |
217 | ||
09ee17eb JR |
218 | if (!iommu->need_sync) |
219 | goto out; | |
220 | ||
221 | iommu->need_sync = 0; | |
222 | ||
7e4f88da | 223 | ret = __iommu_queue_command(iommu, &cmd); |
a19ae1ec JR |
224 | |
225 | if (ret) | |
7e4f88da | 226 | goto out; |
a19ae1ec | 227 | |
136f78a1 JR |
228 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
229 | ++i; | |
519c31ba JR |
230 | /* wait for the bit to become one */ |
231 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
232 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
136f78a1 JR |
233 | } |
234 | ||
519c31ba JR |
235 | /* set bit back to zero */ |
236 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
237 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
238 | ||
84df8175 JR |
239 | if (unlikely(i == EXIT_LOOP_COUNT)) |
240 | panic("AMD IOMMU: Completion wait loop failed\n"); | |
241 | ||
7e4f88da JR |
242 | out: |
243 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec JR |
244 | |
245 | return 0; | |
246 | } | |
247 | ||
431b2a20 JR |
248 | /* |
249 | * Command send function for invalidating a device table entry | |
250 | */ | |
a19ae1ec JR |
251 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
252 | { | |
d6449536 | 253 | struct iommu_cmd cmd; |
ee2fa743 | 254 | int ret; |
a19ae1ec JR |
255 | |
256 | BUG_ON(iommu == NULL); | |
257 | ||
258 | memset(&cmd, 0, sizeof(cmd)); | |
259 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
260 | cmd.data[0] = devid; | |
261 | ||
ee2fa743 JR |
262 | ret = iommu_queue_command(iommu, &cmd); |
263 | ||
ee2fa743 | 264 | return ret; |
a19ae1ec JR |
265 | } |
266 | ||
431b2a20 JR |
267 | /* |
268 | * Generic command send function for invalidaing TLB entries | |
269 | */ | |
a19ae1ec JR |
270 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
271 | u64 address, u16 domid, int pde, int s) | |
272 | { | |
d6449536 | 273 | struct iommu_cmd cmd; |
ee2fa743 | 274 | int ret; |
a19ae1ec JR |
275 | |
276 | memset(&cmd, 0, sizeof(cmd)); | |
277 | address &= PAGE_MASK; | |
278 | CMD_SET_TYPE(&cmd, CMD_INV_IOMMU_PAGES); | |
279 | cmd.data[1] |= domid; | |
8a456695 | 280 | cmd.data[2] = lower_32_bits(address); |
8ea80d78 | 281 | cmd.data[3] = upper_32_bits(address); |
431b2a20 | 282 | if (s) /* size bit - we flush more than one 4kb page */ |
a19ae1ec | 283 | cmd.data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; |
431b2a20 | 284 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ |
a19ae1ec JR |
285 | cmd.data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
286 | ||
ee2fa743 JR |
287 | ret = iommu_queue_command(iommu, &cmd); |
288 | ||
ee2fa743 | 289 | return ret; |
a19ae1ec JR |
290 | } |
291 | ||
431b2a20 JR |
292 | /* |
293 | * TLB invalidation function which is called from the mapping functions. | |
294 | * It invalidates a single PTE if the range to flush is within a single | |
295 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
296 | */ | |
a19ae1ec JR |
297 | static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid, |
298 | u64 address, size_t size) | |
299 | { | |
999ba417 | 300 | int s = 0; |
e3c449f5 | 301 | unsigned pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
302 | |
303 | address &= PAGE_MASK; | |
304 | ||
999ba417 JR |
305 | if (pages > 1) { |
306 | /* | |
307 | * If we have to flush more than one page, flush all | |
308 | * TLB entries for this domain | |
309 | */ | |
310 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
311 | s = 1; | |
a19ae1ec JR |
312 | } |
313 | ||
999ba417 JR |
314 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s); |
315 | ||
a19ae1ec JR |
316 | return 0; |
317 | } | |
b6c02715 | 318 | |
1c655773 JR |
319 | /* Flush the whole IO/TLB for a given protection domain */ |
320 | static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid) | |
321 | { | |
322 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
323 | ||
324 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1); | |
325 | } | |
326 | ||
431b2a20 JR |
327 | /**************************************************************************** |
328 | * | |
329 | * The functions below are used the create the page table mappings for | |
330 | * unity mapped regions. | |
331 | * | |
332 | ****************************************************************************/ | |
333 | ||
334 | /* | |
335 | * Generic mapping functions. It maps a physical address into a DMA | |
336 | * address space. It allocates the page table pages if necessary. | |
337 | * In the future it can be extended to a generic mapping function | |
338 | * supporting all features of AMD IOMMU page tables like level skipping | |
339 | * and full 64 bit address spaces. | |
340 | */ | |
38e817fe JR |
341 | static int iommu_map_page(struct protection_domain *dom, |
342 | unsigned long bus_addr, | |
343 | unsigned long phys_addr, | |
344 | int prot) | |
bd0e5211 JR |
345 | { |
346 | u64 __pte, *pte, *page; | |
347 | ||
348 | bus_addr = PAGE_ALIGN(bus_addr); | |
bb9d4ff8 | 349 | phys_addr = PAGE_ALIGN(phys_addr); |
bd0e5211 JR |
350 | |
351 | /* only support 512GB address spaces for now */ | |
352 | if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK)) | |
353 | return -EINVAL; | |
354 | ||
355 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
356 | ||
357 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
358 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
359 | if (!page) | |
360 | return -ENOMEM; | |
361 | *pte = IOMMU_L2_PDE(virt_to_phys(page)); | |
362 | } | |
363 | ||
364 | pte = IOMMU_PTE_PAGE(*pte); | |
365 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
366 | ||
367 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
368 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
369 | if (!page) | |
370 | return -ENOMEM; | |
371 | *pte = IOMMU_L1_PDE(virt_to_phys(page)); | |
372 | } | |
373 | ||
374 | pte = IOMMU_PTE_PAGE(*pte); | |
375 | pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)]; | |
376 | ||
377 | if (IOMMU_PTE_PRESENT(*pte)) | |
378 | return -EBUSY; | |
379 | ||
380 | __pte = phys_addr | IOMMU_PTE_P; | |
381 | if (prot & IOMMU_PROT_IR) | |
382 | __pte |= IOMMU_PTE_IR; | |
383 | if (prot & IOMMU_PROT_IW) | |
384 | __pte |= IOMMU_PTE_IW; | |
385 | ||
386 | *pte = __pte; | |
387 | ||
388 | return 0; | |
389 | } | |
390 | ||
431b2a20 JR |
391 | /* |
392 | * This function checks if a specific unity mapping entry is needed for | |
393 | * this specific IOMMU. | |
394 | */ | |
bd0e5211 JR |
395 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
396 | struct unity_map_entry *entry) | |
397 | { | |
398 | u16 bdf, i; | |
399 | ||
400 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
401 | bdf = amd_iommu_alias_table[i]; | |
402 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
403 | return 1; | |
404 | } | |
405 | ||
406 | return 0; | |
407 | } | |
408 | ||
431b2a20 JR |
409 | /* |
410 | * Init the unity mappings for a specific IOMMU in the system | |
411 | * | |
412 | * Basically iterates over all unity mapping entries and applies them to | |
413 | * the default domain DMA of that IOMMU if necessary. | |
414 | */ | |
bd0e5211 JR |
415 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
416 | { | |
417 | struct unity_map_entry *entry; | |
418 | int ret; | |
419 | ||
420 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
421 | if (!iommu_for_unity_map(iommu, entry)) | |
422 | continue; | |
423 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
424 | if (ret) | |
425 | return ret; | |
426 | } | |
427 | ||
428 | return 0; | |
429 | } | |
430 | ||
431b2a20 JR |
431 | /* |
432 | * This function actually applies the mapping to the page table of the | |
433 | * dma_ops domain. | |
434 | */ | |
bd0e5211 JR |
435 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
436 | struct unity_map_entry *e) | |
437 | { | |
438 | u64 addr; | |
439 | int ret; | |
440 | ||
441 | for (addr = e->address_start; addr < e->address_end; | |
442 | addr += PAGE_SIZE) { | |
38e817fe | 443 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot); |
bd0e5211 JR |
444 | if (ret) |
445 | return ret; | |
446 | /* | |
447 | * if unity mapping is in aperture range mark the page | |
448 | * as allocated in the aperture | |
449 | */ | |
450 | if (addr < dma_dom->aperture_size) | |
451 | __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap); | |
452 | } | |
453 | ||
454 | return 0; | |
455 | } | |
456 | ||
431b2a20 JR |
457 | /* |
458 | * Inits the unity mappings required for a specific device | |
459 | */ | |
bd0e5211 JR |
460 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
461 | u16 devid) | |
462 | { | |
463 | struct unity_map_entry *e; | |
464 | int ret; | |
465 | ||
466 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
467 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
468 | continue; | |
469 | ret = dma_ops_unity_map(dma_dom, e); | |
470 | if (ret) | |
471 | return ret; | |
472 | } | |
473 | ||
474 | return 0; | |
475 | } | |
476 | ||
431b2a20 JR |
477 | /**************************************************************************** |
478 | * | |
479 | * The next functions belong to the address allocator for the dma_ops | |
480 | * interface functions. They work like the allocators in the other IOMMU | |
481 | * drivers. Its basically a bitmap which marks the allocated pages in | |
482 | * the aperture. Maybe it could be enhanced in the future to a more | |
483 | * efficient allocator. | |
484 | * | |
485 | ****************************************************************************/ | |
d3086444 | 486 | |
431b2a20 JR |
487 | /* |
488 | * The address allocator core function. | |
489 | * | |
490 | * called with domain->lock held | |
491 | */ | |
d3086444 JR |
492 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
493 | struct dma_ops_domain *dom, | |
6d4f343f | 494 | unsigned int pages, |
832a90c3 JR |
495 | unsigned long align_mask, |
496 | u64 dma_mask) | |
d3086444 | 497 | { |
40becd8d | 498 | unsigned long limit; |
d3086444 | 499 | unsigned long address; |
d3086444 JR |
500 | unsigned long boundary_size; |
501 | ||
502 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, | |
503 | PAGE_SIZE) >> PAGE_SHIFT; | |
40becd8d FT |
504 | limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0, |
505 | dma_mask >> PAGE_SHIFT); | |
d3086444 | 506 | |
1c655773 | 507 | if (dom->next_bit >= limit) { |
d3086444 | 508 | dom->next_bit = 0; |
1c655773 JR |
509 | dom->need_flush = true; |
510 | } | |
d3086444 JR |
511 | |
512 | address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages, | |
6d4f343f | 513 | 0 , boundary_size, align_mask); |
1c655773 | 514 | if (address == -1) { |
d3086444 | 515 | address = iommu_area_alloc(dom->bitmap, limit, 0, pages, |
6d4f343f | 516 | 0, boundary_size, align_mask); |
1c655773 JR |
517 | dom->need_flush = true; |
518 | } | |
d3086444 JR |
519 | |
520 | if (likely(address != -1)) { | |
d3086444 JR |
521 | dom->next_bit = address + pages; |
522 | address <<= PAGE_SHIFT; | |
523 | } else | |
524 | address = bad_dma_address; | |
525 | ||
526 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
527 | ||
528 | return address; | |
529 | } | |
530 | ||
431b2a20 JR |
531 | /* |
532 | * The address free function. | |
533 | * | |
534 | * called with domain->lock held | |
535 | */ | |
d3086444 JR |
536 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
537 | unsigned long address, | |
538 | unsigned int pages) | |
539 | { | |
540 | address >>= PAGE_SHIFT; | |
541 | iommu_area_free(dom->bitmap, address, pages); | |
80be308d | 542 | |
8501c45c | 543 | if (address >= dom->next_bit) |
80be308d | 544 | dom->need_flush = true; |
d3086444 JR |
545 | } |
546 | ||
431b2a20 JR |
547 | /**************************************************************************** |
548 | * | |
549 | * The next functions belong to the domain allocation. A domain is | |
550 | * allocated for every IOMMU as the default domain. If device isolation | |
551 | * is enabled, every device get its own domain. The most important thing | |
552 | * about domains is the page table mapping the DMA address space they | |
553 | * contain. | |
554 | * | |
555 | ****************************************************************************/ | |
556 | ||
ec487d1a JR |
557 | static u16 domain_id_alloc(void) |
558 | { | |
559 | unsigned long flags; | |
560 | int id; | |
561 | ||
562 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
563 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
564 | BUG_ON(id == 0); | |
565 | if (id > 0 && id < MAX_DOMAIN_ID) | |
566 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
567 | else | |
568 | id = 0; | |
569 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
570 | ||
571 | return id; | |
572 | } | |
573 | ||
431b2a20 JR |
574 | /* |
575 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
576 | * ranges. | |
577 | */ | |
ec487d1a JR |
578 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
579 | unsigned long start_page, | |
580 | unsigned int pages) | |
581 | { | |
582 | unsigned int last_page = dom->aperture_size >> PAGE_SHIFT; | |
583 | ||
584 | if (start_page + pages > last_page) | |
585 | pages = last_page - start_page; | |
586 | ||
d26dbc5c | 587 | iommu_area_reserve(dom->bitmap, start_page, pages); |
ec487d1a JR |
588 | } |
589 | ||
86db2e5d | 590 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
591 | { |
592 | int i, j; | |
593 | u64 *p1, *p2, *p3; | |
594 | ||
86db2e5d | 595 | p1 = domain->pt_root; |
ec487d1a JR |
596 | |
597 | if (!p1) | |
598 | return; | |
599 | ||
600 | for (i = 0; i < 512; ++i) { | |
601 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
602 | continue; | |
603 | ||
604 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 605 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
606 | if (!IOMMU_PTE_PRESENT(p2[j])) |
607 | continue; | |
608 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
609 | free_page((unsigned long)p3); | |
610 | } | |
611 | ||
612 | free_page((unsigned long)p2); | |
613 | } | |
614 | ||
615 | free_page((unsigned long)p1); | |
86db2e5d JR |
616 | |
617 | domain->pt_root = NULL; | |
ec487d1a JR |
618 | } |
619 | ||
431b2a20 JR |
620 | /* |
621 | * Free a domain, only used if something went wrong in the | |
622 | * allocation path and we need to free an already allocated page table | |
623 | */ | |
ec487d1a JR |
624 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
625 | { | |
626 | if (!dom) | |
627 | return; | |
628 | ||
86db2e5d | 629 | free_pagetable(&dom->domain); |
ec487d1a JR |
630 | |
631 | kfree(dom->pte_pages); | |
632 | ||
633 | kfree(dom->bitmap); | |
634 | ||
635 | kfree(dom); | |
636 | } | |
637 | ||
431b2a20 JR |
638 | /* |
639 | * Allocates a new protection domain usable for the dma_ops functions. | |
640 | * It also intializes the page table and the address allocator data | |
641 | * structures required for the dma_ops interface | |
642 | */ | |
ec487d1a JR |
643 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu, |
644 | unsigned order) | |
645 | { | |
646 | struct dma_ops_domain *dma_dom; | |
647 | unsigned i, num_pte_pages; | |
648 | u64 *l2_pde; | |
649 | u64 address; | |
650 | ||
651 | /* | |
652 | * Currently the DMA aperture must be between 32 MB and 1GB in size | |
653 | */ | |
654 | if ((order < 25) || (order > 30)) | |
655 | return NULL; | |
656 | ||
657 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
658 | if (!dma_dom) | |
659 | return NULL; | |
660 | ||
661 | spin_lock_init(&dma_dom->domain.lock); | |
662 | ||
663 | dma_dom->domain.id = domain_id_alloc(); | |
664 | if (dma_dom->domain.id == 0) | |
665 | goto free_dma_dom; | |
666 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; | |
667 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
668 | dma_dom->domain.priv = dma_dom; | |
669 | if (!dma_dom->domain.pt_root) | |
670 | goto free_dma_dom; | |
671 | dma_dom->aperture_size = (1ULL << order); | |
672 | dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8), | |
673 | GFP_KERNEL); | |
674 | if (!dma_dom->bitmap) | |
675 | goto free_dma_dom; | |
676 | /* | |
677 | * mark the first page as allocated so we never return 0 as | |
678 | * a valid dma-address. So we can use 0 as error value | |
679 | */ | |
680 | dma_dom->bitmap[0] = 1; | |
681 | dma_dom->next_bit = 0; | |
682 | ||
1c655773 | 683 | dma_dom->need_flush = false; |
bd60b735 | 684 | dma_dom->target_dev = 0xffff; |
1c655773 | 685 | |
431b2a20 | 686 | /* Intialize the exclusion range if necessary */ |
ec487d1a JR |
687 | if (iommu->exclusion_start && |
688 | iommu->exclusion_start < dma_dom->aperture_size) { | |
689 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
e3c449f5 JR |
690 | int pages = iommu_num_pages(iommu->exclusion_start, |
691 | iommu->exclusion_length, | |
692 | PAGE_SIZE); | |
ec487d1a JR |
693 | dma_ops_reserve_addresses(dma_dom, startpage, pages); |
694 | } | |
695 | ||
431b2a20 JR |
696 | /* |
697 | * At the last step, build the page tables so we don't need to | |
698 | * allocate page table pages in the dma_ops mapping/unmapping | |
699 | * path. | |
700 | */ | |
ec487d1a JR |
701 | num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512); |
702 | dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *), | |
703 | GFP_KERNEL); | |
704 | if (!dma_dom->pte_pages) | |
705 | goto free_dma_dom; | |
706 | ||
707 | l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL); | |
708 | if (l2_pde == NULL) | |
709 | goto free_dma_dom; | |
710 | ||
711 | dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde)); | |
712 | ||
713 | for (i = 0; i < num_pte_pages; ++i) { | |
714 | dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL); | |
715 | if (!dma_dom->pte_pages[i]) | |
716 | goto free_dma_dom; | |
717 | address = virt_to_phys(dma_dom->pte_pages[i]); | |
718 | l2_pde[i] = IOMMU_L1_PDE(address); | |
719 | } | |
720 | ||
721 | return dma_dom; | |
722 | ||
723 | free_dma_dom: | |
724 | dma_ops_domain_free(dma_dom); | |
725 | ||
726 | return NULL; | |
727 | } | |
728 | ||
431b2a20 JR |
729 | /* |
730 | * Find out the protection domain structure for a given PCI device. This | |
731 | * will give us the pointer to the page table root for example. | |
732 | */ | |
b20ac0d4 JR |
733 | static struct protection_domain *domain_for_device(u16 devid) |
734 | { | |
735 | struct protection_domain *dom; | |
736 | unsigned long flags; | |
737 | ||
738 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
739 | dom = amd_iommu_pd_table[devid]; | |
740 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
741 | ||
742 | return dom; | |
743 | } | |
744 | ||
431b2a20 JR |
745 | /* |
746 | * If a device is not yet associated with a domain, this function does | |
747 | * assigns it visible for the hardware | |
748 | */ | |
b20ac0d4 JR |
749 | static void set_device_domain(struct amd_iommu *iommu, |
750 | struct protection_domain *domain, | |
751 | u16 devid) | |
752 | { | |
753 | unsigned long flags; | |
754 | ||
755 | u64 pte_root = virt_to_phys(domain->pt_root); | |
756 | ||
38ddf41b JR |
757 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
758 | << DEV_ENTRY_MODE_SHIFT; | |
759 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 JR |
760 | |
761 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
38ddf41b JR |
762 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); |
763 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | |
b20ac0d4 JR |
764 | amd_iommu_dev_table[devid].data[2] = domain->id; |
765 | ||
766 | amd_iommu_pd_table[devid] = domain; | |
767 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
768 | ||
769 | iommu_queue_inv_dev_entry(iommu, devid); | |
b20ac0d4 JR |
770 | } |
771 | ||
431b2a20 JR |
772 | /***************************************************************************** |
773 | * | |
774 | * The next functions belong to the dma_ops mapping/unmapping code. | |
775 | * | |
776 | *****************************************************************************/ | |
777 | ||
dbcc112e JR |
778 | /* |
779 | * This function checks if the driver got a valid device from the caller to | |
780 | * avoid dereferencing invalid pointers. | |
781 | */ | |
782 | static bool check_device(struct device *dev) | |
783 | { | |
784 | if (!dev || !dev->dma_mask) | |
785 | return false; | |
786 | ||
787 | return true; | |
788 | } | |
789 | ||
bd60b735 JR |
790 | /* |
791 | * In this function the list of preallocated protection domains is traversed to | |
792 | * find the domain for a specific device | |
793 | */ | |
794 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
795 | { | |
796 | struct dma_ops_domain *entry, *ret = NULL; | |
797 | unsigned long flags; | |
798 | ||
799 | if (list_empty(&iommu_pd_list)) | |
800 | return NULL; | |
801 | ||
802 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
803 | ||
804 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
805 | if (entry->target_dev == devid) { | |
806 | ret = entry; | |
807 | list_del(&ret->list); | |
808 | break; | |
809 | } | |
810 | } | |
811 | ||
812 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
813 | ||
814 | return ret; | |
815 | } | |
816 | ||
431b2a20 JR |
817 | /* |
818 | * In the dma_ops path we only have the struct device. This function | |
819 | * finds the corresponding IOMMU, the protection domain and the | |
820 | * requestor id for a given device. | |
821 | * If the device is not yet associated with a domain this is also done | |
822 | * in this function. | |
823 | */ | |
b20ac0d4 JR |
824 | static int get_device_resources(struct device *dev, |
825 | struct amd_iommu **iommu, | |
826 | struct protection_domain **domain, | |
827 | u16 *bdf) | |
828 | { | |
829 | struct dma_ops_domain *dma_dom; | |
830 | struct pci_dev *pcidev; | |
831 | u16 _bdf; | |
832 | ||
dbcc112e JR |
833 | *iommu = NULL; |
834 | *domain = NULL; | |
835 | *bdf = 0xffff; | |
836 | ||
837 | if (dev->bus != &pci_bus_type) | |
838 | return 0; | |
b20ac0d4 JR |
839 | |
840 | pcidev = to_pci_dev(dev); | |
d591b0a3 | 841 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); |
b20ac0d4 | 842 | |
431b2a20 | 843 | /* device not translated by any IOMMU in the system? */ |
dbcc112e | 844 | if (_bdf > amd_iommu_last_bdf) |
b20ac0d4 | 845 | return 0; |
b20ac0d4 JR |
846 | |
847 | *bdf = amd_iommu_alias_table[_bdf]; | |
848 | ||
849 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
850 | if (*iommu == NULL) | |
851 | return 0; | |
b20ac0d4 JR |
852 | *domain = domain_for_device(*bdf); |
853 | if (*domain == NULL) { | |
bd60b735 JR |
854 | dma_dom = find_protection_domain(*bdf); |
855 | if (!dma_dom) | |
856 | dma_dom = (*iommu)->default_dom; | |
b20ac0d4 JR |
857 | *domain = &dma_dom->domain; |
858 | set_device_domain(*iommu, *domain, *bdf); | |
859 | printk(KERN_INFO "AMD IOMMU: Using protection domain %d for " | |
860 | "device ", (*domain)->id); | |
861 | print_devid(_bdf, 1); | |
862 | } | |
863 | ||
f91ba190 JR |
864 | if (domain_for_device(_bdf) == NULL) |
865 | set_device_domain(*iommu, *domain, _bdf); | |
866 | ||
b20ac0d4 JR |
867 | return 1; |
868 | } | |
869 | ||
431b2a20 JR |
870 | /* |
871 | * This is the generic map function. It maps one 4kb page at paddr to | |
872 | * the given address in the DMA address space for the domain. | |
873 | */ | |
cb76c322 JR |
874 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, |
875 | struct dma_ops_domain *dom, | |
876 | unsigned long address, | |
877 | phys_addr_t paddr, | |
878 | int direction) | |
879 | { | |
880 | u64 *pte, __pte; | |
881 | ||
882 | WARN_ON(address > dom->aperture_size); | |
883 | ||
884 | paddr &= PAGE_MASK; | |
885 | ||
886 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
887 | pte += IOMMU_PTE_L0_INDEX(address); | |
888 | ||
889 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
890 | ||
891 | if (direction == DMA_TO_DEVICE) | |
892 | __pte |= IOMMU_PTE_IR; | |
893 | else if (direction == DMA_FROM_DEVICE) | |
894 | __pte |= IOMMU_PTE_IW; | |
895 | else if (direction == DMA_BIDIRECTIONAL) | |
896 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
897 | ||
898 | WARN_ON(*pte); | |
899 | ||
900 | *pte = __pte; | |
901 | ||
902 | return (dma_addr_t)address; | |
903 | } | |
904 | ||
431b2a20 JR |
905 | /* |
906 | * The generic unmapping function for on page in the DMA address space. | |
907 | */ | |
cb76c322 JR |
908 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, |
909 | struct dma_ops_domain *dom, | |
910 | unsigned long address) | |
911 | { | |
912 | u64 *pte; | |
913 | ||
914 | if (address >= dom->aperture_size) | |
915 | return; | |
916 | ||
8ad909c4 | 917 | WARN_ON(address & ~PAGE_MASK || address >= dom->aperture_size); |
cb76c322 JR |
918 | |
919 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
920 | pte += IOMMU_PTE_L0_INDEX(address); | |
921 | ||
922 | WARN_ON(!*pte); | |
923 | ||
924 | *pte = 0ULL; | |
925 | } | |
926 | ||
431b2a20 JR |
927 | /* |
928 | * This function contains common code for mapping of a physically | |
24f81160 JR |
929 | * contiguous memory region into DMA address space. It is used by all |
930 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
931 | * Must be called with the domain lock held. |
932 | */ | |
cb76c322 JR |
933 | static dma_addr_t __map_single(struct device *dev, |
934 | struct amd_iommu *iommu, | |
935 | struct dma_ops_domain *dma_dom, | |
936 | phys_addr_t paddr, | |
937 | size_t size, | |
6d4f343f | 938 | int dir, |
832a90c3 JR |
939 | bool align, |
940 | u64 dma_mask) | |
cb76c322 JR |
941 | { |
942 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
943 | dma_addr_t address, start; | |
944 | unsigned int pages; | |
6d4f343f | 945 | unsigned long align_mask = 0; |
cb76c322 JR |
946 | int i; |
947 | ||
e3c449f5 | 948 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
949 | paddr &= PAGE_MASK; |
950 | ||
6d4f343f JR |
951 | if (align) |
952 | align_mask = (1UL << get_order(size)) - 1; | |
953 | ||
832a90c3 JR |
954 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
955 | dma_mask); | |
cb76c322 JR |
956 | if (unlikely(address == bad_dma_address)) |
957 | goto out; | |
958 | ||
959 | start = address; | |
960 | for (i = 0; i < pages; ++i) { | |
961 | dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); | |
962 | paddr += PAGE_SIZE; | |
963 | start += PAGE_SIZE; | |
964 | } | |
965 | address += offset; | |
966 | ||
afa9fdc2 | 967 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
1c655773 JR |
968 | iommu_flush_tlb(iommu, dma_dom->domain.id); |
969 | dma_dom->need_flush = false; | |
970 | } else if (unlikely(iommu_has_npcache(iommu))) | |
270cab24 JR |
971 | iommu_flush_pages(iommu, dma_dom->domain.id, address, size); |
972 | ||
cb76c322 JR |
973 | out: |
974 | return address; | |
975 | } | |
976 | ||
431b2a20 JR |
977 | /* |
978 | * Does the reverse of the __map_single function. Must be called with | |
979 | * the domain lock held too | |
980 | */ | |
cb76c322 JR |
981 | static void __unmap_single(struct amd_iommu *iommu, |
982 | struct dma_ops_domain *dma_dom, | |
983 | dma_addr_t dma_addr, | |
984 | size_t size, | |
985 | int dir) | |
986 | { | |
987 | dma_addr_t i, start; | |
988 | unsigned int pages; | |
989 | ||
b8d9905d JR |
990 | if ((dma_addr == bad_dma_address) || |
991 | (dma_addr + size > dma_dom->aperture_size)) | |
cb76c322 JR |
992 | return; |
993 | ||
e3c449f5 | 994 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
995 | dma_addr &= PAGE_MASK; |
996 | start = dma_addr; | |
997 | ||
998 | for (i = 0; i < pages; ++i) { | |
999 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1000 | start += PAGE_SIZE; | |
1001 | } | |
1002 | ||
1003 | dma_ops_free_addresses(dma_dom, dma_addr, pages); | |
270cab24 | 1004 | |
80be308d | 1005 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
1c655773 | 1006 | iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size); |
80be308d JR |
1007 | dma_dom->need_flush = false; |
1008 | } | |
cb76c322 JR |
1009 | } |
1010 | ||
431b2a20 JR |
1011 | /* |
1012 | * The exported map_single function for dma_ops. | |
1013 | */ | |
4da70b9e JR |
1014 | static dma_addr_t map_single(struct device *dev, phys_addr_t paddr, |
1015 | size_t size, int dir) | |
1016 | { | |
1017 | unsigned long flags; | |
1018 | struct amd_iommu *iommu; | |
1019 | struct protection_domain *domain; | |
1020 | u16 devid; | |
1021 | dma_addr_t addr; | |
832a90c3 | 1022 | u64 dma_mask; |
4da70b9e | 1023 | |
dbcc112e JR |
1024 | if (!check_device(dev)) |
1025 | return bad_dma_address; | |
1026 | ||
832a90c3 | 1027 | dma_mask = *dev->dma_mask; |
4da70b9e JR |
1028 | |
1029 | get_device_resources(dev, &iommu, &domain, &devid); | |
1030 | ||
1031 | if (iommu == NULL || domain == NULL) | |
431b2a20 | 1032 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1033 | return (dma_addr_t)paddr; |
1034 | ||
1035 | spin_lock_irqsave(&domain->lock, flags); | |
832a90c3 JR |
1036 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false, |
1037 | dma_mask); | |
4da70b9e JR |
1038 | if (addr == bad_dma_address) |
1039 | goto out; | |
1040 | ||
09ee17eb | 1041 | iommu_completion_wait(iommu); |
4da70b9e JR |
1042 | |
1043 | out: | |
1044 | spin_unlock_irqrestore(&domain->lock, flags); | |
1045 | ||
1046 | return addr; | |
1047 | } | |
1048 | ||
431b2a20 JR |
1049 | /* |
1050 | * The exported unmap_single function for dma_ops. | |
1051 | */ | |
4da70b9e JR |
1052 | static void unmap_single(struct device *dev, dma_addr_t dma_addr, |
1053 | size_t size, int dir) | |
1054 | { | |
1055 | unsigned long flags; | |
1056 | struct amd_iommu *iommu; | |
1057 | struct protection_domain *domain; | |
1058 | u16 devid; | |
1059 | ||
dbcc112e JR |
1060 | if (!check_device(dev) || |
1061 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
431b2a20 | 1062 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1063 | return; |
1064 | ||
1065 | spin_lock_irqsave(&domain->lock, flags); | |
1066 | ||
1067 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
1068 | ||
09ee17eb | 1069 | iommu_completion_wait(iommu); |
4da70b9e JR |
1070 | |
1071 | spin_unlock_irqrestore(&domain->lock, flags); | |
1072 | } | |
1073 | ||
431b2a20 JR |
1074 | /* |
1075 | * This is a special map_sg function which is used if we should map a | |
1076 | * device which is not handled by an AMD IOMMU in the system. | |
1077 | */ | |
65b050ad JR |
1078 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1079 | int nelems, int dir) | |
1080 | { | |
1081 | struct scatterlist *s; | |
1082 | int i; | |
1083 | ||
1084 | for_each_sg(sglist, s, nelems, i) { | |
1085 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1086 | s->dma_length = s->length; | |
1087 | } | |
1088 | ||
1089 | return nelems; | |
1090 | } | |
1091 | ||
431b2a20 JR |
1092 | /* |
1093 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1094 | * lists). | |
1095 | */ | |
65b050ad JR |
1096 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
1097 | int nelems, int dir) | |
1098 | { | |
1099 | unsigned long flags; | |
1100 | struct amd_iommu *iommu; | |
1101 | struct protection_domain *domain; | |
1102 | u16 devid; | |
1103 | int i; | |
1104 | struct scatterlist *s; | |
1105 | phys_addr_t paddr; | |
1106 | int mapped_elems = 0; | |
832a90c3 | 1107 | u64 dma_mask; |
65b050ad | 1108 | |
dbcc112e JR |
1109 | if (!check_device(dev)) |
1110 | return 0; | |
1111 | ||
832a90c3 | 1112 | dma_mask = *dev->dma_mask; |
65b050ad JR |
1113 | |
1114 | get_device_resources(dev, &iommu, &domain, &devid); | |
1115 | ||
1116 | if (!iommu || !domain) | |
1117 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
1118 | ||
1119 | spin_lock_irqsave(&domain->lock, flags); | |
1120 | ||
1121 | for_each_sg(sglist, s, nelems, i) { | |
1122 | paddr = sg_phys(s); | |
1123 | ||
1124 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
832a90c3 JR |
1125 | paddr, s->length, dir, false, |
1126 | dma_mask); | |
65b050ad JR |
1127 | |
1128 | if (s->dma_address) { | |
1129 | s->dma_length = s->length; | |
1130 | mapped_elems++; | |
1131 | } else | |
1132 | goto unmap; | |
65b050ad JR |
1133 | } |
1134 | ||
09ee17eb | 1135 | iommu_completion_wait(iommu); |
65b050ad JR |
1136 | |
1137 | out: | |
1138 | spin_unlock_irqrestore(&domain->lock, flags); | |
1139 | ||
1140 | return mapped_elems; | |
1141 | unmap: | |
1142 | for_each_sg(sglist, s, mapped_elems, i) { | |
1143 | if (s->dma_address) | |
1144 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1145 | s->dma_length, dir); | |
1146 | s->dma_address = s->dma_length = 0; | |
1147 | } | |
1148 | ||
1149 | mapped_elems = 0; | |
1150 | ||
1151 | goto out; | |
1152 | } | |
1153 | ||
431b2a20 JR |
1154 | /* |
1155 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1156 | * lists). | |
1157 | */ | |
65b050ad JR |
1158 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
1159 | int nelems, int dir) | |
1160 | { | |
1161 | unsigned long flags; | |
1162 | struct amd_iommu *iommu; | |
1163 | struct protection_domain *domain; | |
1164 | struct scatterlist *s; | |
1165 | u16 devid; | |
1166 | int i; | |
1167 | ||
dbcc112e JR |
1168 | if (!check_device(dev) || |
1169 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
65b050ad JR |
1170 | return; |
1171 | ||
1172 | spin_lock_irqsave(&domain->lock, flags); | |
1173 | ||
1174 | for_each_sg(sglist, s, nelems, i) { | |
1175 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1176 | s->dma_length, dir); | |
65b050ad JR |
1177 | s->dma_address = s->dma_length = 0; |
1178 | } | |
1179 | ||
09ee17eb | 1180 | iommu_completion_wait(iommu); |
65b050ad JR |
1181 | |
1182 | spin_unlock_irqrestore(&domain->lock, flags); | |
1183 | } | |
1184 | ||
431b2a20 JR |
1185 | /* |
1186 | * The exported alloc_coherent function for dma_ops. | |
1187 | */ | |
5d8b53cf JR |
1188 | static void *alloc_coherent(struct device *dev, size_t size, |
1189 | dma_addr_t *dma_addr, gfp_t flag) | |
1190 | { | |
1191 | unsigned long flags; | |
1192 | void *virt_addr; | |
1193 | struct amd_iommu *iommu; | |
1194 | struct protection_domain *domain; | |
1195 | u16 devid; | |
1196 | phys_addr_t paddr; | |
832a90c3 | 1197 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 1198 | |
dbcc112e JR |
1199 | if (!check_device(dev)) |
1200 | return NULL; | |
5d8b53cf | 1201 | |
13d9fead FT |
1202 | if (!get_device_resources(dev, &iommu, &domain, &devid)) |
1203 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
5d8b53cf | 1204 | |
c97ac535 | 1205 | flag |= __GFP_ZERO; |
5d8b53cf JR |
1206 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
1207 | if (!virt_addr) | |
1208 | return 0; | |
1209 | ||
5d8b53cf JR |
1210 | paddr = virt_to_phys(virt_addr); |
1211 | ||
5d8b53cf JR |
1212 | if (!iommu || !domain) { |
1213 | *dma_addr = (dma_addr_t)paddr; | |
1214 | return virt_addr; | |
1215 | } | |
1216 | ||
832a90c3 JR |
1217 | if (!dma_mask) |
1218 | dma_mask = *dev->dma_mask; | |
1219 | ||
5d8b53cf JR |
1220 | spin_lock_irqsave(&domain->lock, flags); |
1221 | ||
1222 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
832a90c3 | 1223 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf JR |
1224 | |
1225 | if (*dma_addr == bad_dma_address) { | |
1226 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1227 | virt_addr = NULL; | |
1228 | goto out; | |
1229 | } | |
1230 | ||
09ee17eb | 1231 | iommu_completion_wait(iommu); |
5d8b53cf JR |
1232 | |
1233 | out: | |
1234 | spin_unlock_irqrestore(&domain->lock, flags); | |
1235 | ||
1236 | return virt_addr; | |
1237 | } | |
1238 | ||
431b2a20 JR |
1239 | /* |
1240 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 1241 | */ |
5d8b53cf JR |
1242 | static void free_coherent(struct device *dev, size_t size, |
1243 | void *virt_addr, dma_addr_t dma_addr) | |
1244 | { | |
1245 | unsigned long flags; | |
1246 | struct amd_iommu *iommu; | |
1247 | struct protection_domain *domain; | |
1248 | u16 devid; | |
1249 | ||
dbcc112e JR |
1250 | if (!check_device(dev)) |
1251 | return; | |
1252 | ||
5d8b53cf JR |
1253 | get_device_resources(dev, &iommu, &domain, &devid); |
1254 | ||
1255 | if (!iommu || !domain) | |
1256 | goto free_mem; | |
1257 | ||
1258 | spin_lock_irqsave(&domain->lock, flags); | |
1259 | ||
1260 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 1261 | |
09ee17eb | 1262 | iommu_completion_wait(iommu); |
5d8b53cf JR |
1263 | |
1264 | spin_unlock_irqrestore(&domain->lock, flags); | |
1265 | ||
1266 | free_mem: | |
1267 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1268 | } | |
1269 | ||
b39ba6ad JR |
1270 | /* |
1271 | * This function is called by the DMA layer to find out if we can handle a | |
1272 | * particular device. It is part of the dma_ops. | |
1273 | */ | |
1274 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
1275 | { | |
1276 | u16 bdf; | |
1277 | struct pci_dev *pcidev; | |
1278 | ||
1279 | /* No device or no PCI device */ | |
1280 | if (!dev || dev->bus != &pci_bus_type) | |
1281 | return 0; | |
1282 | ||
1283 | pcidev = to_pci_dev(dev); | |
1284 | ||
1285 | bdf = calc_devid(pcidev->bus->number, pcidev->devfn); | |
1286 | ||
1287 | /* Out of our scope? */ | |
1288 | if (bdf > amd_iommu_last_bdf) | |
1289 | return 0; | |
1290 | ||
1291 | return 1; | |
1292 | } | |
1293 | ||
c432f3df | 1294 | /* |
431b2a20 JR |
1295 | * The function for pre-allocating protection domains. |
1296 | * | |
c432f3df JR |
1297 | * If the driver core informs the DMA layer if a driver grabs a device |
1298 | * we don't need to preallocate the protection domains anymore. | |
1299 | * For now we have to. | |
1300 | */ | |
1301 | void prealloc_protection_domains(void) | |
1302 | { | |
1303 | struct pci_dev *dev = NULL; | |
1304 | struct dma_ops_domain *dma_dom; | |
1305 | struct amd_iommu *iommu; | |
1306 | int order = amd_iommu_aperture_order; | |
1307 | u16 devid; | |
1308 | ||
1309 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
1310 | devid = (dev->bus->number << 8) | dev->devfn; | |
3a61ec38 | 1311 | if (devid > amd_iommu_last_bdf) |
c432f3df JR |
1312 | continue; |
1313 | devid = amd_iommu_alias_table[devid]; | |
1314 | if (domain_for_device(devid)) | |
1315 | continue; | |
1316 | iommu = amd_iommu_rlookup_table[devid]; | |
1317 | if (!iommu) | |
1318 | continue; | |
1319 | dma_dom = dma_ops_domain_alloc(iommu, order); | |
1320 | if (!dma_dom) | |
1321 | continue; | |
1322 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
1323 | dma_dom->target_dev = devid; |
1324 | ||
1325 | list_add_tail(&dma_dom->list, &iommu_pd_list); | |
c432f3df JR |
1326 | } |
1327 | } | |
1328 | ||
6631ee9d JR |
1329 | static struct dma_mapping_ops amd_iommu_dma_ops = { |
1330 | .alloc_coherent = alloc_coherent, | |
1331 | .free_coherent = free_coherent, | |
1332 | .map_single = map_single, | |
1333 | .unmap_single = unmap_single, | |
1334 | .map_sg = map_sg, | |
1335 | .unmap_sg = unmap_sg, | |
b39ba6ad | 1336 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
1337 | }; |
1338 | ||
431b2a20 JR |
1339 | /* |
1340 | * The function which clues the AMD IOMMU driver into dma_ops. | |
1341 | */ | |
6631ee9d JR |
1342 | int __init amd_iommu_init_dma_ops(void) |
1343 | { | |
1344 | struct amd_iommu *iommu; | |
1345 | int order = amd_iommu_aperture_order; | |
1346 | int ret; | |
1347 | ||
431b2a20 JR |
1348 | /* |
1349 | * first allocate a default protection domain for every IOMMU we | |
1350 | * found in the system. Devices not assigned to any other | |
1351 | * protection domain will be assigned to the default one. | |
1352 | */ | |
6631ee9d JR |
1353 | list_for_each_entry(iommu, &amd_iommu_list, list) { |
1354 | iommu->default_dom = dma_ops_domain_alloc(iommu, order); | |
1355 | if (iommu->default_dom == NULL) | |
1356 | return -ENOMEM; | |
1357 | ret = iommu_init_unity_mappings(iommu); | |
1358 | if (ret) | |
1359 | goto free_domains; | |
1360 | } | |
1361 | ||
431b2a20 JR |
1362 | /* |
1363 | * If device isolation is enabled, pre-allocate the protection | |
1364 | * domains for each device. | |
1365 | */ | |
6631ee9d JR |
1366 | if (amd_iommu_isolate) |
1367 | prealloc_protection_domains(); | |
1368 | ||
1369 | iommu_detected = 1; | |
1370 | force_iommu = 1; | |
1371 | bad_dma_address = 0; | |
92af4e29 | 1372 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
1373 | gart_iommu_aperture_disabled = 1; |
1374 | gart_iommu_aperture = 0; | |
92af4e29 | 1375 | #endif |
6631ee9d | 1376 | |
431b2a20 | 1377 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
1378 | dma_ops = &amd_iommu_dma_ops; |
1379 | ||
1380 | return 0; | |
1381 | ||
1382 | free_domains: | |
1383 | ||
1384 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
1385 | if (iommu->default_dom) | |
1386 | dma_ops_domain_free(iommu->default_dom); | |
1387 | } | |
1388 | ||
1389 | return ret; | |
1390 | } |