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b6c02715 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
7f26508b | 23 | #include <linux/debugfs.h> |
b6c02715 JR |
24 | #include <linux/scatterlist.h> |
25 | #include <linux/iommu-helper.h> | |
c156e347 JR |
26 | #ifdef CONFIG_IOMMU_API |
27 | #include <linux/iommu.h> | |
28 | #endif | |
b6c02715 | 29 | #include <asm/proto.h> |
46a7fa27 | 30 | #include <asm/iommu.h> |
1d9b16d1 | 31 | #include <asm/gart.h> |
b6c02715 | 32 | #include <asm/amd_iommu_types.h> |
c6da992e | 33 | #include <asm/amd_iommu.h> |
b6c02715 JR |
34 | |
35 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
36 | ||
136f78a1 JR |
37 | #define EXIT_LOOP_COUNT 10000000 |
38 | ||
b6c02715 JR |
39 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
40 | ||
bd60b735 JR |
41 | /* A list of preallocated protection domains */ |
42 | static LIST_HEAD(iommu_pd_list); | |
43 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
44 | ||
26961efe JR |
45 | #ifdef CONFIG_IOMMU_API |
46 | static struct iommu_ops amd_iommu_ops; | |
47 | #endif | |
48 | ||
431b2a20 JR |
49 | /* |
50 | * general struct to manage commands send to an IOMMU | |
51 | */ | |
d6449536 | 52 | struct iommu_cmd { |
b6c02715 JR |
53 | u32 data[4]; |
54 | }; | |
55 | ||
bd0e5211 JR |
56 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
57 | struct unity_map_entry *e); | |
e275a2a0 JR |
58 | static struct dma_ops_domain *find_protection_domain(u16 devid); |
59 | ||
bd0e5211 | 60 | |
7f26508b JR |
61 | #ifdef CONFIG_AMD_IOMMU_STATS |
62 | ||
63 | /* | |
64 | * Initialization code for statistics collection | |
65 | */ | |
66 | ||
da49f6df JR |
67 | DECLARE_STATS_COUNTER(compl_wait); |
68 | ||
7f26508b JR |
69 | static struct dentry *stats_dir; |
70 | static struct dentry *de_isolate; | |
71 | static struct dentry *de_fflush; | |
72 | ||
73 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
74 | { | |
75 | if (stats_dir == NULL) | |
76 | return; | |
77 | ||
78 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
79 | &cnt->value); | |
80 | } | |
81 | ||
82 | static void amd_iommu_stats_init(void) | |
83 | { | |
84 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
85 | if (stats_dir == NULL) | |
86 | return; | |
87 | ||
88 | de_isolate = debugfs_create_bool("isolation", 0444, stats_dir, | |
89 | (u32 *)&amd_iommu_isolate); | |
90 | ||
91 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, | |
92 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
93 | |
94 | amd_iommu_stats_add(&compl_wait); | |
7f26508b JR |
95 | } |
96 | ||
97 | #endif | |
98 | ||
431b2a20 | 99 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ |
4da70b9e JR |
100 | static int iommu_has_npcache(struct amd_iommu *iommu) |
101 | { | |
ae9b9403 | 102 | return iommu->cap & (1UL << IOMMU_CAP_NPCACHE); |
4da70b9e JR |
103 | } |
104 | ||
a80dc3e0 JR |
105 | /**************************************************************************** |
106 | * | |
107 | * Interrupt handling functions | |
108 | * | |
109 | ****************************************************************************/ | |
110 | ||
90008ee4 JR |
111 | static void iommu_print_event(void *__evt) |
112 | { | |
113 | u32 *event = __evt; | |
114 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
115 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
116 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
117 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
118 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
119 | ||
120 | printk(KERN_ERR "AMD IOMMU: Event logged ["); | |
121 | ||
122 | switch (type) { | |
123 | case EVENT_TYPE_ILL_DEV: | |
124 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
125 | "address=0x%016llx flags=0x%04x]\n", | |
126 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
127 | address, flags); | |
128 | break; | |
129 | case EVENT_TYPE_IO_FAULT: | |
130 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
131 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
132 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
133 | domid, address, flags); | |
134 | break; | |
135 | case EVENT_TYPE_DEV_TAB_ERR: | |
136 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
137 | "address=0x%016llx flags=0x%04x]\n", | |
138 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
139 | address, flags); | |
140 | break; | |
141 | case EVENT_TYPE_PAGE_TAB_ERR: | |
142 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
143 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
144 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
145 | domid, address, flags); | |
146 | break; | |
147 | case EVENT_TYPE_ILL_CMD: | |
148 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
149 | break; | |
150 | case EVENT_TYPE_CMD_HARD_ERR: | |
151 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
152 | "flags=0x%04x]\n", address, flags); | |
153 | break; | |
154 | case EVENT_TYPE_IOTLB_INV_TO: | |
155 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
156 | "address=0x%016llx]\n", | |
157 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
158 | address); | |
159 | break; | |
160 | case EVENT_TYPE_INV_DEV_REQ: | |
161 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
162 | "address=0x%016llx flags=0x%04x]\n", | |
163 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
164 | address, flags); | |
165 | break; | |
166 | default: | |
167 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
168 | } | |
169 | } | |
170 | ||
171 | static void iommu_poll_events(struct amd_iommu *iommu) | |
172 | { | |
173 | u32 head, tail; | |
174 | unsigned long flags; | |
175 | ||
176 | spin_lock_irqsave(&iommu->lock, flags); | |
177 | ||
178 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
179 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
180 | ||
181 | while (head != tail) { | |
182 | iommu_print_event(iommu->evt_buf + head); | |
183 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; | |
184 | } | |
185 | ||
186 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
187 | ||
188 | spin_unlock_irqrestore(&iommu->lock, flags); | |
189 | } | |
190 | ||
a80dc3e0 JR |
191 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
192 | { | |
90008ee4 JR |
193 | struct amd_iommu *iommu; |
194 | ||
195 | list_for_each_entry(iommu, &amd_iommu_list, list) | |
196 | iommu_poll_events(iommu); | |
197 | ||
198 | return IRQ_HANDLED; | |
a80dc3e0 JR |
199 | } |
200 | ||
431b2a20 JR |
201 | /**************************************************************************** |
202 | * | |
203 | * IOMMU command queuing functions | |
204 | * | |
205 | ****************************************************************************/ | |
206 | ||
207 | /* | |
208 | * Writes the command to the IOMMUs command buffer and informs the | |
209 | * hardware about the new command. Must be called with iommu->lock held. | |
210 | */ | |
d6449536 | 211 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
212 | { |
213 | u32 tail, head; | |
214 | u8 *target; | |
215 | ||
216 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 217 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
218 | memcpy_toio(target, cmd, sizeof(*cmd)); |
219 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
220 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
221 | if (tail == head) | |
222 | return -ENOMEM; | |
223 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
224 | ||
225 | return 0; | |
226 | } | |
227 | ||
431b2a20 JR |
228 | /* |
229 | * General queuing function for commands. Takes iommu->lock and calls | |
230 | * __iommu_queue_command(). | |
231 | */ | |
d6449536 | 232 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
233 | { |
234 | unsigned long flags; | |
235 | int ret; | |
236 | ||
237 | spin_lock_irqsave(&iommu->lock, flags); | |
238 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb | 239 | if (!ret) |
0cfd7aa9 | 240 | iommu->need_sync = true; |
a19ae1ec JR |
241 | spin_unlock_irqrestore(&iommu->lock, flags); |
242 | ||
243 | return ret; | |
244 | } | |
245 | ||
8d201968 JR |
246 | /* |
247 | * This function waits until an IOMMU has completed a completion | |
248 | * wait command | |
249 | */ | |
250 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
251 | { | |
252 | int ready = 0; | |
253 | unsigned status = 0; | |
254 | unsigned long i = 0; | |
255 | ||
da49f6df JR |
256 | INC_STATS_COUNTER(compl_wait); |
257 | ||
8d201968 JR |
258 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
259 | ++i; | |
260 | /* wait for the bit to become one */ | |
261 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
262 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
263 | } | |
264 | ||
265 | /* set bit back to zero */ | |
266 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
267 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
268 | ||
269 | if (unlikely(i == EXIT_LOOP_COUNT)) | |
270 | panic("AMD IOMMU: Completion wait loop failed\n"); | |
271 | } | |
272 | ||
273 | /* | |
274 | * This function queues a completion wait command into the command | |
275 | * buffer of an IOMMU | |
276 | */ | |
277 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
278 | { | |
279 | struct iommu_cmd cmd; | |
280 | ||
281 | memset(&cmd, 0, sizeof(cmd)); | |
282 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; | |
283 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); | |
284 | ||
285 | return __iommu_queue_command(iommu, &cmd); | |
286 | } | |
287 | ||
431b2a20 JR |
288 | /* |
289 | * This function is called whenever we need to ensure that the IOMMU has | |
290 | * completed execution of all commands we sent. It sends a | |
291 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
292 | * us about that by writing a value to a physical address we pass with | |
293 | * the command. | |
294 | */ | |
a19ae1ec JR |
295 | static int iommu_completion_wait(struct amd_iommu *iommu) |
296 | { | |
8d201968 JR |
297 | int ret = 0; |
298 | unsigned long flags; | |
a19ae1ec | 299 | |
7e4f88da JR |
300 | spin_lock_irqsave(&iommu->lock, flags); |
301 | ||
09ee17eb JR |
302 | if (!iommu->need_sync) |
303 | goto out; | |
304 | ||
8d201968 | 305 | ret = __iommu_completion_wait(iommu); |
09ee17eb | 306 | |
0cfd7aa9 | 307 | iommu->need_sync = false; |
a19ae1ec JR |
308 | |
309 | if (ret) | |
7e4f88da | 310 | goto out; |
a19ae1ec | 311 | |
8d201968 | 312 | __iommu_wait_for_completion(iommu); |
84df8175 | 313 | |
7e4f88da JR |
314 | out: |
315 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec JR |
316 | |
317 | return 0; | |
318 | } | |
319 | ||
431b2a20 JR |
320 | /* |
321 | * Command send function for invalidating a device table entry | |
322 | */ | |
a19ae1ec JR |
323 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
324 | { | |
d6449536 | 325 | struct iommu_cmd cmd; |
ee2fa743 | 326 | int ret; |
a19ae1ec JR |
327 | |
328 | BUG_ON(iommu == NULL); | |
329 | ||
330 | memset(&cmd, 0, sizeof(cmd)); | |
331 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
332 | cmd.data[0] = devid; | |
333 | ||
ee2fa743 JR |
334 | ret = iommu_queue_command(iommu, &cmd); |
335 | ||
ee2fa743 | 336 | return ret; |
a19ae1ec JR |
337 | } |
338 | ||
237b6f33 JR |
339 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
340 | u16 domid, int pde, int s) | |
341 | { | |
342 | memset(cmd, 0, sizeof(*cmd)); | |
343 | address &= PAGE_MASK; | |
344 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
345 | cmd->data[1] |= domid; | |
346 | cmd->data[2] = lower_32_bits(address); | |
347 | cmd->data[3] = upper_32_bits(address); | |
348 | if (s) /* size bit - we flush more than one 4kb page */ | |
349 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
350 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
351 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
352 | } | |
353 | ||
431b2a20 JR |
354 | /* |
355 | * Generic command send function for invalidaing TLB entries | |
356 | */ | |
a19ae1ec JR |
357 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
358 | u64 address, u16 domid, int pde, int s) | |
359 | { | |
d6449536 | 360 | struct iommu_cmd cmd; |
ee2fa743 | 361 | int ret; |
a19ae1ec | 362 | |
237b6f33 | 363 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); |
a19ae1ec | 364 | |
ee2fa743 JR |
365 | ret = iommu_queue_command(iommu, &cmd); |
366 | ||
ee2fa743 | 367 | return ret; |
a19ae1ec JR |
368 | } |
369 | ||
431b2a20 JR |
370 | /* |
371 | * TLB invalidation function which is called from the mapping functions. | |
372 | * It invalidates a single PTE if the range to flush is within a single | |
373 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
374 | */ | |
a19ae1ec JR |
375 | static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid, |
376 | u64 address, size_t size) | |
377 | { | |
999ba417 | 378 | int s = 0; |
e3c449f5 | 379 | unsigned pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
380 | |
381 | address &= PAGE_MASK; | |
382 | ||
999ba417 JR |
383 | if (pages > 1) { |
384 | /* | |
385 | * If we have to flush more than one page, flush all | |
386 | * TLB entries for this domain | |
387 | */ | |
388 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
389 | s = 1; | |
a19ae1ec JR |
390 | } |
391 | ||
999ba417 JR |
392 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s); |
393 | ||
a19ae1ec JR |
394 | return 0; |
395 | } | |
b6c02715 | 396 | |
1c655773 JR |
397 | /* Flush the whole IO/TLB for a given protection domain */ |
398 | static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid) | |
399 | { | |
400 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
401 | ||
402 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1); | |
403 | } | |
404 | ||
43f49609 JR |
405 | #ifdef CONFIG_IOMMU_API |
406 | /* | |
407 | * This function is used to flush the IO/TLB for a given protection domain | |
408 | * on every IOMMU in the system | |
409 | */ | |
410 | static void iommu_flush_domain(u16 domid) | |
411 | { | |
412 | unsigned long flags; | |
413 | struct amd_iommu *iommu; | |
414 | struct iommu_cmd cmd; | |
415 | ||
416 | __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
417 | domid, 1, 1); | |
418 | ||
419 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
420 | spin_lock_irqsave(&iommu->lock, flags); | |
421 | __iommu_queue_command(iommu, &cmd); | |
422 | __iommu_completion_wait(iommu); | |
423 | __iommu_wait_for_completion(iommu); | |
424 | spin_unlock_irqrestore(&iommu->lock, flags); | |
425 | } | |
426 | } | |
427 | #endif | |
428 | ||
431b2a20 JR |
429 | /**************************************************************************** |
430 | * | |
431 | * The functions below are used the create the page table mappings for | |
432 | * unity mapped regions. | |
433 | * | |
434 | ****************************************************************************/ | |
435 | ||
436 | /* | |
437 | * Generic mapping functions. It maps a physical address into a DMA | |
438 | * address space. It allocates the page table pages if necessary. | |
439 | * In the future it can be extended to a generic mapping function | |
440 | * supporting all features of AMD IOMMU page tables like level skipping | |
441 | * and full 64 bit address spaces. | |
442 | */ | |
38e817fe JR |
443 | static int iommu_map_page(struct protection_domain *dom, |
444 | unsigned long bus_addr, | |
445 | unsigned long phys_addr, | |
446 | int prot) | |
bd0e5211 JR |
447 | { |
448 | u64 __pte, *pte, *page; | |
449 | ||
450 | bus_addr = PAGE_ALIGN(bus_addr); | |
bb9d4ff8 | 451 | phys_addr = PAGE_ALIGN(phys_addr); |
bd0e5211 JR |
452 | |
453 | /* only support 512GB address spaces for now */ | |
454 | if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK)) | |
455 | return -EINVAL; | |
456 | ||
457 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
458 | ||
459 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
460 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
461 | if (!page) | |
462 | return -ENOMEM; | |
463 | *pte = IOMMU_L2_PDE(virt_to_phys(page)); | |
464 | } | |
465 | ||
466 | pte = IOMMU_PTE_PAGE(*pte); | |
467 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
468 | ||
469 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
470 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
471 | if (!page) | |
472 | return -ENOMEM; | |
473 | *pte = IOMMU_L1_PDE(virt_to_phys(page)); | |
474 | } | |
475 | ||
476 | pte = IOMMU_PTE_PAGE(*pte); | |
477 | pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)]; | |
478 | ||
479 | if (IOMMU_PTE_PRESENT(*pte)) | |
480 | return -EBUSY; | |
481 | ||
482 | __pte = phys_addr | IOMMU_PTE_P; | |
483 | if (prot & IOMMU_PROT_IR) | |
484 | __pte |= IOMMU_PTE_IR; | |
485 | if (prot & IOMMU_PROT_IW) | |
486 | __pte |= IOMMU_PTE_IW; | |
487 | ||
488 | *pte = __pte; | |
489 | ||
490 | return 0; | |
491 | } | |
492 | ||
eb74ff6c JR |
493 | #ifdef CONFIG_IOMMU_API |
494 | static void iommu_unmap_page(struct protection_domain *dom, | |
495 | unsigned long bus_addr) | |
496 | { | |
497 | u64 *pte; | |
498 | ||
499 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
500 | ||
501 | if (!IOMMU_PTE_PRESENT(*pte)) | |
502 | return; | |
503 | ||
504 | pte = IOMMU_PTE_PAGE(*pte); | |
505 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
506 | ||
507 | if (!IOMMU_PTE_PRESENT(*pte)) | |
508 | return; | |
509 | ||
510 | pte = IOMMU_PTE_PAGE(*pte); | |
511 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
512 | ||
513 | *pte = 0; | |
514 | } | |
515 | #endif | |
516 | ||
431b2a20 JR |
517 | /* |
518 | * This function checks if a specific unity mapping entry is needed for | |
519 | * this specific IOMMU. | |
520 | */ | |
bd0e5211 JR |
521 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
522 | struct unity_map_entry *entry) | |
523 | { | |
524 | u16 bdf, i; | |
525 | ||
526 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
527 | bdf = amd_iommu_alias_table[i]; | |
528 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
529 | return 1; | |
530 | } | |
531 | ||
532 | return 0; | |
533 | } | |
534 | ||
431b2a20 JR |
535 | /* |
536 | * Init the unity mappings for a specific IOMMU in the system | |
537 | * | |
538 | * Basically iterates over all unity mapping entries and applies them to | |
539 | * the default domain DMA of that IOMMU if necessary. | |
540 | */ | |
bd0e5211 JR |
541 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
542 | { | |
543 | struct unity_map_entry *entry; | |
544 | int ret; | |
545 | ||
546 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
547 | if (!iommu_for_unity_map(iommu, entry)) | |
548 | continue; | |
549 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
550 | if (ret) | |
551 | return ret; | |
552 | } | |
553 | ||
554 | return 0; | |
555 | } | |
556 | ||
431b2a20 JR |
557 | /* |
558 | * This function actually applies the mapping to the page table of the | |
559 | * dma_ops domain. | |
560 | */ | |
bd0e5211 JR |
561 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
562 | struct unity_map_entry *e) | |
563 | { | |
564 | u64 addr; | |
565 | int ret; | |
566 | ||
567 | for (addr = e->address_start; addr < e->address_end; | |
568 | addr += PAGE_SIZE) { | |
38e817fe | 569 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot); |
bd0e5211 JR |
570 | if (ret) |
571 | return ret; | |
572 | /* | |
573 | * if unity mapping is in aperture range mark the page | |
574 | * as allocated in the aperture | |
575 | */ | |
576 | if (addr < dma_dom->aperture_size) | |
577 | __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap); | |
578 | } | |
579 | ||
580 | return 0; | |
581 | } | |
582 | ||
431b2a20 JR |
583 | /* |
584 | * Inits the unity mappings required for a specific device | |
585 | */ | |
bd0e5211 JR |
586 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
587 | u16 devid) | |
588 | { | |
589 | struct unity_map_entry *e; | |
590 | int ret; | |
591 | ||
592 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
593 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
594 | continue; | |
595 | ret = dma_ops_unity_map(dma_dom, e); | |
596 | if (ret) | |
597 | return ret; | |
598 | } | |
599 | ||
600 | return 0; | |
601 | } | |
602 | ||
431b2a20 JR |
603 | /**************************************************************************** |
604 | * | |
605 | * The next functions belong to the address allocator for the dma_ops | |
606 | * interface functions. They work like the allocators in the other IOMMU | |
607 | * drivers. Its basically a bitmap which marks the allocated pages in | |
608 | * the aperture. Maybe it could be enhanced in the future to a more | |
609 | * efficient allocator. | |
610 | * | |
611 | ****************************************************************************/ | |
d3086444 | 612 | |
431b2a20 JR |
613 | /* |
614 | * The address allocator core function. | |
615 | * | |
616 | * called with domain->lock held | |
617 | */ | |
d3086444 JR |
618 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
619 | struct dma_ops_domain *dom, | |
6d4f343f | 620 | unsigned int pages, |
832a90c3 JR |
621 | unsigned long align_mask, |
622 | u64 dma_mask) | |
d3086444 | 623 | { |
40becd8d | 624 | unsigned long limit; |
d3086444 | 625 | unsigned long address; |
d3086444 JR |
626 | unsigned long boundary_size; |
627 | ||
628 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, | |
629 | PAGE_SIZE) >> PAGE_SHIFT; | |
40becd8d FT |
630 | limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0, |
631 | dma_mask >> PAGE_SHIFT); | |
d3086444 | 632 | |
1c655773 | 633 | if (dom->next_bit >= limit) { |
d3086444 | 634 | dom->next_bit = 0; |
1c655773 JR |
635 | dom->need_flush = true; |
636 | } | |
d3086444 JR |
637 | |
638 | address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages, | |
6d4f343f | 639 | 0 , boundary_size, align_mask); |
1c655773 | 640 | if (address == -1) { |
d3086444 | 641 | address = iommu_area_alloc(dom->bitmap, limit, 0, pages, |
6d4f343f | 642 | 0, boundary_size, align_mask); |
1c655773 JR |
643 | dom->need_flush = true; |
644 | } | |
d3086444 JR |
645 | |
646 | if (likely(address != -1)) { | |
d3086444 JR |
647 | dom->next_bit = address + pages; |
648 | address <<= PAGE_SHIFT; | |
649 | } else | |
650 | address = bad_dma_address; | |
651 | ||
652 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
653 | ||
654 | return address; | |
655 | } | |
656 | ||
431b2a20 JR |
657 | /* |
658 | * The address free function. | |
659 | * | |
660 | * called with domain->lock held | |
661 | */ | |
d3086444 JR |
662 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
663 | unsigned long address, | |
664 | unsigned int pages) | |
665 | { | |
666 | address >>= PAGE_SHIFT; | |
667 | iommu_area_free(dom->bitmap, address, pages); | |
80be308d | 668 | |
8501c45c | 669 | if (address >= dom->next_bit) |
80be308d | 670 | dom->need_flush = true; |
d3086444 JR |
671 | } |
672 | ||
431b2a20 JR |
673 | /**************************************************************************** |
674 | * | |
675 | * The next functions belong to the domain allocation. A domain is | |
676 | * allocated for every IOMMU as the default domain. If device isolation | |
677 | * is enabled, every device get its own domain. The most important thing | |
678 | * about domains is the page table mapping the DMA address space they | |
679 | * contain. | |
680 | * | |
681 | ****************************************************************************/ | |
682 | ||
ec487d1a JR |
683 | static u16 domain_id_alloc(void) |
684 | { | |
685 | unsigned long flags; | |
686 | int id; | |
687 | ||
688 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
689 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
690 | BUG_ON(id == 0); | |
691 | if (id > 0 && id < MAX_DOMAIN_ID) | |
692 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
693 | else | |
694 | id = 0; | |
695 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
696 | ||
697 | return id; | |
698 | } | |
699 | ||
a2acfb75 JR |
700 | #ifdef CONFIG_IOMMU_API |
701 | static void domain_id_free(int id) | |
702 | { | |
703 | unsigned long flags; | |
704 | ||
705 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
706 | if (id > 0 && id < MAX_DOMAIN_ID) | |
707 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
708 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
709 | } | |
710 | #endif | |
711 | ||
431b2a20 JR |
712 | /* |
713 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
714 | * ranges. | |
715 | */ | |
ec487d1a JR |
716 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
717 | unsigned long start_page, | |
718 | unsigned int pages) | |
719 | { | |
720 | unsigned int last_page = dom->aperture_size >> PAGE_SHIFT; | |
721 | ||
722 | if (start_page + pages > last_page) | |
723 | pages = last_page - start_page; | |
724 | ||
d26dbc5c | 725 | iommu_area_reserve(dom->bitmap, start_page, pages); |
ec487d1a JR |
726 | } |
727 | ||
86db2e5d | 728 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
729 | { |
730 | int i, j; | |
731 | u64 *p1, *p2, *p3; | |
732 | ||
86db2e5d | 733 | p1 = domain->pt_root; |
ec487d1a JR |
734 | |
735 | if (!p1) | |
736 | return; | |
737 | ||
738 | for (i = 0; i < 512; ++i) { | |
739 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
740 | continue; | |
741 | ||
742 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 743 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
744 | if (!IOMMU_PTE_PRESENT(p2[j])) |
745 | continue; | |
746 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
747 | free_page((unsigned long)p3); | |
748 | } | |
749 | ||
750 | free_page((unsigned long)p2); | |
751 | } | |
752 | ||
753 | free_page((unsigned long)p1); | |
86db2e5d JR |
754 | |
755 | domain->pt_root = NULL; | |
ec487d1a JR |
756 | } |
757 | ||
431b2a20 JR |
758 | /* |
759 | * Free a domain, only used if something went wrong in the | |
760 | * allocation path and we need to free an already allocated page table | |
761 | */ | |
ec487d1a JR |
762 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
763 | { | |
764 | if (!dom) | |
765 | return; | |
766 | ||
86db2e5d | 767 | free_pagetable(&dom->domain); |
ec487d1a JR |
768 | |
769 | kfree(dom->pte_pages); | |
770 | ||
771 | kfree(dom->bitmap); | |
772 | ||
773 | kfree(dom); | |
774 | } | |
775 | ||
431b2a20 JR |
776 | /* |
777 | * Allocates a new protection domain usable for the dma_ops functions. | |
778 | * It also intializes the page table and the address allocator data | |
779 | * structures required for the dma_ops interface | |
780 | */ | |
ec487d1a JR |
781 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu, |
782 | unsigned order) | |
783 | { | |
784 | struct dma_ops_domain *dma_dom; | |
785 | unsigned i, num_pte_pages; | |
786 | u64 *l2_pde; | |
787 | u64 address; | |
788 | ||
789 | /* | |
790 | * Currently the DMA aperture must be between 32 MB and 1GB in size | |
791 | */ | |
792 | if ((order < 25) || (order > 30)) | |
793 | return NULL; | |
794 | ||
795 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
796 | if (!dma_dom) | |
797 | return NULL; | |
798 | ||
799 | spin_lock_init(&dma_dom->domain.lock); | |
800 | ||
801 | dma_dom->domain.id = domain_id_alloc(); | |
802 | if (dma_dom->domain.id == 0) | |
803 | goto free_dma_dom; | |
804 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; | |
805 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
9fdb19d6 | 806 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
807 | dma_dom->domain.priv = dma_dom; |
808 | if (!dma_dom->domain.pt_root) | |
809 | goto free_dma_dom; | |
810 | dma_dom->aperture_size = (1ULL << order); | |
811 | dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8), | |
812 | GFP_KERNEL); | |
813 | if (!dma_dom->bitmap) | |
814 | goto free_dma_dom; | |
815 | /* | |
816 | * mark the first page as allocated so we never return 0 as | |
817 | * a valid dma-address. So we can use 0 as error value | |
818 | */ | |
819 | dma_dom->bitmap[0] = 1; | |
820 | dma_dom->next_bit = 0; | |
821 | ||
1c655773 | 822 | dma_dom->need_flush = false; |
bd60b735 | 823 | dma_dom->target_dev = 0xffff; |
1c655773 | 824 | |
431b2a20 | 825 | /* Intialize the exclusion range if necessary */ |
ec487d1a JR |
826 | if (iommu->exclusion_start && |
827 | iommu->exclusion_start < dma_dom->aperture_size) { | |
828 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
e3c449f5 JR |
829 | int pages = iommu_num_pages(iommu->exclusion_start, |
830 | iommu->exclusion_length, | |
831 | PAGE_SIZE); | |
ec487d1a JR |
832 | dma_ops_reserve_addresses(dma_dom, startpage, pages); |
833 | } | |
834 | ||
431b2a20 JR |
835 | /* |
836 | * At the last step, build the page tables so we don't need to | |
837 | * allocate page table pages in the dma_ops mapping/unmapping | |
838 | * path. | |
839 | */ | |
ec487d1a JR |
840 | num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512); |
841 | dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *), | |
842 | GFP_KERNEL); | |
843 | if (!dma_dom->pte_pages) | |
844 | goto free_dma_dom; | |
845 | ||
846 | l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL); | |
847 | if (l2_pde == NULL) | |
848 | goto free_dma_dom; | |
849 | ||
850 | dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde)); | |
851 | ||
852 | for (i = 0; i < num_pte_pages; ++i) { | |
853 | dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL); | |
854 | if (!dma_dom->pte_pages[i]) | |
855 | goto free_dma_dom; | |
856 | address = virt_to_phys(dma_dom->pte_pages[i]); | |
857 | l2_pde[i] = IOMMU_L1_PDE(address); | |
858 | } | |
859 | ||
860 | return dma_dom; | |
861 | ||
862 | free_dma_dom: | |
863 | dma_ops_domain_free(dma_dom); | |
864 | ||
865 | return NULL; | |
866 | } | |
867 | ||
5b28df6f JR |
868 | /* |
869 | * little helper function to check whether a given protection domain is a | |
870 | * dma_ops domain | |
871 | */ | |
872 | static bool dma_ops_domain(struct protection_domain *domain) | |
873 | { | |
874 | return domain->flags & PD_DMA_OPS_MASK; | |
875 | } | |
876 | ||
431b2a20 JR |
877 | /* |
878 | * Find out the protection domain structure for a given PCI device. This | |
879 | * will give us the pointer to the page table root for example. | |
880 | */ | |
b20ac0d4 JR |
881 | static struct protection_domain *domain_for_device(u16 devid) |
882 | { | |
883 | struct protection_domain *dom; | |
884 | unsigned long flags; | |
885 | ||
886 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
887 | dom = amd_iommu_pd_table[devid]; | |
888 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
889 | ||
890 | return dom; | |
891 | } | |
892 | ||
431b2a20 JR |
893 | /* |
894 | * If a device is not yet associated with a domain, this function does | |
895 | * assigns it visible for the hardware | |
896 | */ | |
f1179dc0 JR |
897 | static void attach_device(struct amd_iommu *iommu, |
898 | struct protection_domain *domain, | |
899 | u16 devid) | |
b20ac0d4 JR |
900 | { |
901 | unsigned long flags; | |
b20ac0d4 JR |
902 | u64 pte_root = virt_to_phys(domain->pt_root); |
903 | ||
863c74eb JR |
904 | domain->dev_cnt += 1; |
905 | ||
38ddf41b JR |
906 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
907 | << DEV_ENTRY_MODE_SHIFT; | |
908 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 JR |
909 | |
910 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
38ddf41b JR |
911 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); |
912 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | |
b20ac0d4 JR |
913 | amd_iommu_dev_table[devid].data[2] = domain->id; |
914 | ||
915 | amd_iommu_pd_table[devid] = domain; | |
916 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
917 | ||
918 | iommu_queue_inv_dev_entry(iommu, devid); | |
b20ac0d4 JR |
919 | } |
920 | ||
355bf553 JR |
921 | /* |
922 | * Removes a device from a protection domain (unlocked) | |
923 | */ | |
924 | static void __detach_device(struct protection_domain *domain, u16 devid) | |
925 | { | |
926 | ||
927 | /* lock domain */ | |
928 | spin_lock(&domain->lock); | |
929 | ||
930 | /* remove domain from the lookup table */ | |
931 | amd_iommu_pd_table[devid] = NULL; | |
932 | ||
933 | /* remove entry from the device table seen by the hardware */ | |
934 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
935 | amd_iommu_dev_table[devid].data[1] = 0; | |
936 | amd_iommu_dev_table[devid].data[2] = 0; | |
937 | ||
938 | /* decrease reference counter */ | |
939 | domain->dev_cnt -= 1; | |
940 | ||
941 | /* ready */ | |
942 | spin_unlock(&domain->lock); | |
943 | } | |
944 | ||
945 | /* | |
946 | * Removes a device from a protection domain (with devtable_lock held) | |
947 | */ | |
948 | static void detach_device(struct protection_domain *domain, u16 devid) | |
949 | { | |
950 | unsigned long flags; | |
951 | ||
952 | /* lock device table */ | |
953 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
954 | __detach_device(domain, devid); | |
955 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
956 | } | |
e275a2a0 JR |
957 | |
958 | static int device_change_notifier(struct notifier_block *nb, | |
959 | unsigned long action, void *data) | |
960 | { | |
961 | struct device *dev = data; | |
962 | struct pci_dev *pdev = to_pci_dev(dev); | |
963 | u16 devid = calc_devid(pdev->bus->number, pdev->devfn); | |
964 | struct protection_domain *domain; | |
965 | struct dma_ops_domain *dma_domain; | |
966 | struct amd_iommu *iommu; | |
1ac4cbbc JR |
967 | int order = amd_iommu_aperture_order; |
968 | unsigned long flags; | |
e275a2a0 JR |
969 | |
970 | if (devid > amd_iommu_last_bdf) | |
971 | goto out; | |
972 | ||
973 | devid = amd_iommu_alias_table[devid]; | |
974 | ||
975 | iommu = amd_iommu_rlookup_table[devid]; | |
976 | if (iommu == NULL) | |
977 | goto out; | |
978 | ||
979 | domain = domain_for_device(devid); | |
980 | ||
981 | if (domain && !dma_ops_domain(domain)) | |
982 | WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound " | |
983 | "to a non-dma-ops domain\n", dev_name(dev)); | |
984 | ||
985 | switch (action) { | |
986 | case BUS_NOTIFY_BOUND_DRIVER: | |
987 | if (domain) | |
988 | goto out; | |
989 | dma_domain = find_protection_domain(devid); | |
990 | if (!dma_domain) | |
991 | dma_domain = iommu->default_dom; | |
992 | attach_device(iommu, &dma_domain->domain, devid); | |
993 | printk(KERN_INFO "AMD IOMMU: Using protection domain %d for " | |
994 | "device %s\n", dma_domain->domain.id, dev_name(dev)); | |
995 | break; | |
996 | case BUS_NOTIFY_UNBIND_DRIVER: | |
997 | if (!domain) | |
998 | goto out; | |
999 | detach_device(domain, devid); | |
1ac4cbbc JR |
1000 | break; |
1001 | case BUS_NOTIFY_ADD_DEVICE: | |
1002 | /* allocate a protection domain if a device is added */ | |
1003 | dma_domain = find_protection_domain(devid); | |
1004 | if (dma_domain) | |
1005 | goto out; | |
1006 | dma_domain = dma_ops_domain_alloc(iommu, order); | |
1007 | if (!dma_domain) | |
1008 | goto out; | |
1009 | dma_domain->target_dev = devid; | |
1010 | ||
1011 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1012 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1013 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1014 | ||
e275a2a0 JR |
1015 | break; |
1016 | default: | |
1017 | goto out; | |
1018 | } | |
1019 | ||
1020 | iommu_queue_inv_dev_entry(iommu, devid); | |
1021 | iommu_completion_wait(iommu); | |
1022 | ||
1023 | out: | |
1024 | return 0; | |
1025 | } | |
1026 | ||
1027 | struct notifier_block device_nb = { | |
1028 | .notifier_call = device_change_notifier, | |
1029 | }; | |
355bf553 | 1030 | |
431b2a20 JR |
1031 | /***************************************************************************** |
1032 | * | |
1033 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1034 | * | |
1035 | *****************************************************************************/ | |
1036 | ||
dbcc112e JR |
1037 | /* |
1038 | * This function checks if the driver got a valid device from the caller to | |
1039 | * avoid dereferencing invalid pointers. | |
1040 | */ | |
1041 | static bool check_device(struct device *dev) | |
1042 | { | |
1043 | if (!dev || !dev->dma_mask) | |
1044 | return false; | |
1045 | ||
1046 | return true; | |
1047 | } | |
1048 | ||
bd60b735 JR |
1049 | /* |
1050 | * In this function the list of preallocated protection domains is traversed to | |
1051 | * find the domain for a specific device | |
1052 | */ | |
1053 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
1054 | { | |
1055 | struct dma_ops_domain *entry, *ret = NULL; | |
1056 | unsigned long flags; | |
1057 | ||
1058 | if (list_empty(&iommu_pd_list)) | |
1059 | return NULL; | |
1060 | ||
1061 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1062 | ||
1063 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
1064 | if (entry->target_dev == devid) { | |
1065 | ret = entry; | |
bd60b735 JR |
1066 | break; |
1067 | } | |
1068 | } | |
1069 | ||
1070 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1071 | ||
1072 | return ret; | |
1073 | } | |
1074 | ||
431b2a20 JR |
1075 | /* |
1076 | * In the dma_ops path we only have the struct device. This function | |
1077 | * finds the corresponding IOMMU, the protection domain and the | |
1078 | * requestor id for a given device. | |
1079 | * If the device is not yet associated with a domain this is also done | |
1080 | * in this function. | |
1081 | */ | |
b20ac0d4 JR |
1082 | static int get_device_resources(struct device *dev, |
1083 | struct amd_iommu **iommu, | |
1084 | struct protection_domain **domain, | |
1085 | u16 *bdf) | |
1086 | { | |
1087 | struct dma_ops_domain *dma_dom; | |
1088 | struct pci_dev *pcidev; | |
1089 | u16 _bdf; | |
1090 | ||
dbcc112e JR |
1091 | *iommu = NULL; |
1092 | *domain = NULL; | |
1093 | *bdf = 0xffff; | |
1094 | ||
1095 | if (dev->bus != &pci_bus_type) | |
1096 | return 0; | |
b20ac0d4 JR |
1097 | |
1098 | pcidev = to_pci_dev(dev); | |
d591b0a3 | 1099 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); |
b20ac0d4 | 1100 | |
431b2a20 | 1101 | /* device not translated by any IOMMU in the system? */ |
dbcc112e | 1102 | if (_bdf > amd_iommu_last_bdf) |
b20ac0d4 | 1103 | return 0; |
b20ac0d4 JR |
1104 | |
1105 | *bdf = amd_iommu_alias_table[_bdf]; | |
1106 | ||
1107 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
1108 | if (*iommu == NULL) | |
1109 | return 0; | |
b20ac0d4 JR |
1110 | *domain = domain_for_device(*bdf); |
1111 | if (*domain == NULL) { | |
bd60b735 JR |
1112 | dma_dom = find_protection_domain(*bdf); |
1113 | if (!dma_dom) | |
1114 | dma_dom = (*iommu)->default_dom; | |
b20ac0d4 | 1115 | *domain = &dma_dom->domain; |
f1179dc0 | 1116 | attach_device(*iommu, *domain, *bdf); |
b20ac0d4 | 1117 | printk(KERN_INFO "AMD IOMMU: Using protection domain %d for " |
ab896722 | 1118 | "device %s\n", (*domain)->id, dev_name(dev)); |
b20ac0d4 JR |
1119 | } |
1120 | ||
f91ba190 | 1121 | if (domain_for_device(_bdf) == NULL) |
f1179dc0 | 1122 | attach_device(*iommu, *domain, _bdf); |
f91ba190 | 1123 | |
b20ac0d4 JR |
1124 | return 1; |
1125 | } | |
1126 | ||
431b2a20 JR |
1127 | /* |
1128 | * This is the generic map function. It maps one 4kb page at paddr to | |
1129 | * the given address in the DMA address space for the domain. | |
1130 | */ | |
cb76c322 JR |
1131 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, |
1132 | struct dma_ops_domain *dom, | |
1133 | unsigned long address, | |
1134 | phys_addr_t paddr, | |
1135 | int direction) | |
1136 | { | |
1137 | u64 *pte, __pte; | |
1138 | ||
1139 | WARN_ON(address > dom->aperture_size); | |
1140 | ||
1141 | paddr &= PAGE_MASK; | |
1142 | ||
1143 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
1144 | pte += IOMMU_PTE_L0_INDEX(address); | |
1145 | ||
1146 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1147 | ||
1148 | if (direction == DMA_TO_DEVICE) | |
1149 | __pte |= IOMMU_PTE_IR; | |
1150 | else if (direction == DMA_FROM_DEVICE) | |
1151 | __pte |= IOMMU_PTE_IW; | |
1152 | else if (direction == DMA_BIDIRECTIONAL) | |
1153 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1154 | ||
1155 | WARN_ON(*pte); | |
1156 | ||
1157 | *pte = __pte; | |
1158 | ||
1159 | return (dma_addr_t)address; | |
1160 | } | |
1161 | ||
431b2a20 JR |
1162 | /* |
1163 | * The generic unmapping function for on page in the DMA address space. | |
1164 | */ | |
cb76c322 JR |
1165 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, |
1166 | struct dma_ops_domain *dom, | |
1167 | unsigned long address) | |
1168 | { | |
1169 | u64 *pte; | |
1170 | ||
1171 | if (address >= dom->aperture_size) | |
1172 | return; | |
1173 | ||
8ad909c4 | 1174 | WARN_ON(address & ~PAGE_MASK || address >= dom->aperture_size); |
cb76c322 JR |
1175 | |
1176 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
1177 | pte += IOMMU_PTE_L0_INDEX(address); | |
1178 | ||
1179 | WARN_ON(!*pte); | |
1180 | ||
1181 | *pte = 0ULL; | |
1182 | } | |
1183 | ||
431b2a20 JR |
1184 | /* |
1185 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1186 | * contiguous memory region into DMA address space. It is used by all |
1187 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1188 | * Must be called with the domain lock held. |
1189 | */ | |
cb76c322 JR |
1190 | static dma_addr_t __map_single(struct device *dev, |
1191 | struct amd_iommu *iommu, | |
1192 | struct dma_ops_domain *dma_dom, | |
1193 | phys_addr_t paddr, | |
1194 | size_t size, | |
6d4f343f | 1195 | int dir, |
832a90c3 JR |
1196 | bool align, |
1197 | u64 dma_mask) | |
cb76c322 JR |
1198 | { |
1199 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
1200 | dma_addr_t address, start; | |
1201 | unsigned int pages; | |
6d4f343f | 1202 | unsigned long align_mask = 0; |
cb76c322 JR |
1203 | int i; |
1204 | ||
e3c449f5 | 1205 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1206 | paddr &= PAGE_MASK; |
1207 | ||
6d4f343f JR |
1208 | if (align) |
1209 | align_mask = (1UL << get_order(size)) - 1; | |
1210 | ||
832a90c3 JR |
1211 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1212 | dma_mask); | |
cb76c322 JR |
1213 | if (unlikely(address == bad_dma_address)) |
1214 | goto out; | |
1215 | ||
1216 | start = address; | |
1217 | for (i = 0; i < pages; ++i) { | |
1218 | dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); | |
1219 | paddr += PAGE_SIZE; | |
1220 | start += PAGE_SIZE; | |
1221 | } | |
1222 | address += offset; | |
1223 | ||
afa9fdc2 | 1224 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
1c655773 JR |
1225 | iommu_flush_tlb(iommu, dma_dom->domain.id); |
1226 | dma_dom->need_flush = false; | |
1227 | } else if (unlikely(iommu_has_npcache(iommu))) | |
270cab24 JR |
1228 | iommu_flush_pages(iommu, dma_dom->domain.id, address, size); |
1229 | ||
cb76c322 JR |
1230 | out: |
1231 | return address; | |
1232 | } | |
1233 | ||
431b2a20 JR |
1234 | /* |
1235 | * Does the reverse of the __map_single function. Must be called with | |
1236 | * the domain lock held too | |
1237 | */ | |
cb76c322 JR |
1238 | static void __unmap_single(struct amd_iommu *iommu, |
1239 | struct dma_ops_domain *dma_dom, | |
1240 | dma_addr_t dma_addr, | |
1241 | size_t size, | |
1242 | int dir) | |
1243 | { | |
1244 | dma_addr_t i, start; | |
1245 | unsigned int pages; | |
1246 | ||
b8d9905d JR |
1247 | if ((dma_addr == bad_dma_address) || |
1248 | (dma_addr + size > dma_dom->aperture_size)) | |
cb76c322 JR |
1249 | return; |
1250 | ||
e3c449f5 | 1251 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1252 | dma_addr &= PAGE_MASK; |
1253 | start = dma_addr; | |
1254 | ||
1255 | for (i = 0; i < pages; ++i) { | |
1256 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1257 | start += PAGE_SIZE; | |
1258 | } | |
1259 | ||
1260 | dma_ops_free_addresses(dma_dom, dma_addr, pages); | |
270cab24 | 1261 | |
80be308d | 1262 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
1c655773 | 1263 | iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size); |
80be308d JR |
1264 | dma_dom->need_flush = false; |
1265 | } | |
cb76c322 JR |
1266 | } |
1267 | ||
431b2a20 JR |
1268 | /* |
1269 | * The exported map_single function for dma_ops. | |
1270 | */ | |
4da70b9e JR |
1271 | static dma_addr_t map_single(struct device *dev, phys_addr_t paddr, |
1272 | size_t size, int dir) | |
1273 | { | |
1274 | unsigned long flags; | |
1275 | struct amd_iommu *iommu; | |
1276 | struct protection_domain *domain; | |
1277 | u16 devid; | |
1278 | dma_addr_t addr; | |
832a90c3 | 1279 | u64 dma_mask; |
4da70b9e | 1280 | |
dbcc112e JR |
1281 | if (!check_device(dev)) |
1282 | return bad_dma_address; | |
1283 | ||
832a90c3 | 1284 | dma_mask = *dev->dma_mask; |
4da70b9e JR |
1285 | |
1286 | get_device_resources(dev, &iommu, &domain, &devid); | |
1287 | ||
1288 | if (iommu == NULL || domain == NULL) | |
431b2a20 | 1289 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1290 | return (dma_addr_t)paddr; |
1291 | ||
5b28df6f JR |
1292 | if (!dma_ops_domain(domain)) |
1293 | return bad_dma_address; | |
1294 | ||
4da70b9e | 1295 | spin_lock_irqsave(&domain->lock, flags); |
832a90c3 JR |
1296 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false, |
1297 | dma_mask); | |
4da70b9e JR |
1298 | if (addr == bad_dma_address) |
1299 | goto out; | |
1300 | ||
09ee17eb | 1301 | iommu_completion_wait(iommu); |
4da70b9e JR |
1302 | |
1303 | out: | |
1304 | spin_unlock_irqrestore(&domain->lock, flags); | |
1305 | ||
1306 | return addr; | |
1307 | } | |
1308 | ||
431b2a20 JR |
1309 | /* |
1310 | * The exported unmap_single function for dma_ops. | |
1311 | */ | |
4da70b9e JR |
1312 | static void unmap_single(struct device *dev, dma_addr_t dma_addr, |
1313 | size_t size, int dir) | |
1314 | { | |
1315 | unsigned long flags; | |
1316 | struct amd_iommu *iommu; | |
1317 | struct protection_domain *domain; | |
1318 | u16 devid; | |
1319 | ||
dbcc112e JR |
1320 | if (!check_device(dev) || |
1321 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
431b2a20 | 1322 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1323 | return; |
1324 | ||
5b28df6f JR |
1325 | if (!dma_ops_domain(domain)) |
1326 | return; | |
1327 | ||
4da70b9e JR |
1328 | spin_lock_irqsave(&domain->lock, flags); |
1329 | ||
1330 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
1331 | ||
09ee17eb | 1332 | iommu_completion_wait(iommu); |
4da70b9e JR |
1333 | |
1334 | spin_unlock_irqrestore(&domain->lock, flags); | |
1335 | } | |
1336 | ||
431b2a20 JR |
1337 | /* |
1338 | * This is a special map_sg function which is used if we should map a | |
1339 | * device which is not handled by an AMD IOMMU in the system. | |
1340 | */ | |
65b050ad JR |
1341 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1342 | int nelems, int dir) | |
1343 | { | |
1344 | struct scatterlist *s; | |
1345 | int i; | |
1346 | ||
1347 | for_each_sg(sglist, s, nelems, i) { | |
1348 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1349 | s->dma_length = s->length; | |
1350 | } | |
1351 | ||
1352 | return nelems; | |
1353 | } | |
1354 | ||
431b2a20 JR |
1355 | /* |
1356 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1357 | * lists). | |
1358 | */ | |
65b050ad JR |
1359 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
1360 | int nelems, int dir) | |
1361 | { | |
1362 | unsigned long flags; | |
1363 | struct amd_iommu *iommu; | |
1364 | struct protection_domain *domain; | |
1365 | u16 devid; | |
1366 | int i; | |
1367 | struct scatterlist *s; | |
1368 | phys_addr_t paddr; | |
1369 | int mapped_elems = 0; | |
832a90c3 | 1370 | u64 dma_mask; |
65b050ad | 1371 | |
dbcc112e JR |
1372 | if (!check_device(dev)) |
1373 | return 0; | |
1374 | ||
832a90c3 | 1375 | dma_mask = *dev->dma_mask; |
65b050ad JR |
1376 | |
1377 | get_device_resources(dev, &iommu, &domain, &devid); | |
1378 | ||
1379 | if (!iommu || !domain) | |
1380 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
1381 | ||
5b28df6f JR |
1382 | if (!dma_ops_domain(domain)) |
1383 | return 0; | |
1384 | ||
65b050ad JR |
1385 | spin_lock_irqsave(&domain->lock, flags); |
1386 | ||
1387 | for_each_sg(sglist, s, nelems, i) { | |
1388 | paddr = sg_phys(s); | |
1389 | ||
1390 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
832a90c3 JR |
1391 | paddr, s->length, dir, false, |
1392 | dma_mask); | |
65b050ad JR |
1393 | |
1394 | if (s->dma_address) { | |
1395 | s->dma_length = s->length; | |
1396 | mapped_elems++; | |
1397 | } else | |
1398 | goto unmap; | |
65b050ad JR |
1399 | } |
1400 | ||
09ee17eb | 1401 | iommu_completion_wait(iommu); |
65b050ad JR |
1402 | |
1403 | out: | |
1404 | spin_unlock_irqrestore(&domain->lock, flags); | |
1405 | ||
1406 | return mapped_elems; | |
1407 | unmap: | |
1408 | for_each_sg(sglist, s, mapped_elems, i) { | |
1409 | if (s->dma_address) | |
1410 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1411 | s->dma_length, dir); | |
1412 | s->dma_address = s->dma_length = 0; | |
1413 | } | |
1414 | ||
1415 | mapped_elems = 0; | |
1416 | ||
1417 | goto out; | |
1418 | } | |
1419 | ||
431b2a20 JR |
1420 | /* |
1421 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1422 | * lists). | |
1423 | */ | |
65b050ad JR |
1424 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
1425 | int nelems, int dir) | |
1426 | { | |
1427 | unsigned long flags; | |
1428 | struct amd_iommu *iommu; | |
1429 | struct protection_domain *domain; | |
1430 | struct scatterlist *s; | |
1431 | u16 devid; | |
1432 | int i; | |
1433 | ||
dbcc112e JR |
1434 | if (!check_device(dev) || |
1435 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
65b050ad JR |
1436 | return; |
1437 | ||
5b28df6f JR |
1438 | if (!dma_ops_domain(domain)) |
1439 | return; | |
1440 | ||
65b050ad JR |
1441 | spin_lock_irqsave(&domain->lock, flags); |
1442 | ||
1443 | for_each_sg(sglist, s, nelems, i) { | |
1444 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1445 | s->dma_length, dir); | |
65b050ad JR |
1446 | s->dma_address = s->dma_length = 0; |
1447 | } | |
1448 | ||
09ee17eb | 1449 | iommu_completion_wait(iommu); |
65b050ad JR |
1450 | |
1451 | spin_unlock_irqrestore(&domain->lock, flags); | |
1452 | } | |
1453 | ||
431b2a20 JR |
1454 | /* |
1455 | * The exported alloc_coherent function for dma_ops. | |
1456 | */ | |
5d8b53cf JR |
1457 | static void *alloc_coherent(struct device *dev, size_t size, |
1458 | dma_addr_t *dma_addr, gfp_t flag) | |
1459 | { | |
1460 | unsigned long flags; | |
1461 | void *virt_addr; | |
1462 | struct amd_iommu *iommu; | |
1463 | struct protection_domain *domain; | |
1464 | u16 devid; | |
1465 | phys_addr_t paddr; | |
832a90c3 | 1466 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 1467 | |
dbcc112e JR |
1468 | if (!check_device(dev)) |
1469 | return NULL; | |
5d8b53cf | 1470 | |
13d9fead FT |
1471 | if (!get_device_resources(dev, &iommu, &domain, &devid)) |
1472 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
5d8b53cf | 1473 | |
c97ac535 | 1474 | flag |= __GFP_ZERO; |
5d8b53cf JR |
1475 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
1476 | if (!virt_addr) | |
1477 | return 0; | |
1478 | ||
5d8b53cf JR |
1479 | paddr = virt_to_phys(virt_addr); |
1480 | ||
5d8b53cf JR |
1481 | if (!iommu || !domain) { |
1482 | *dma_addr = (dma_addr_t)paddr; | |
1483 | return virt_addr; | |
1484 | } | |
1485 | ||
5b28df6f JR |
1486 | if (!dma_ops_domain(domain)) |
1487 | goto out_free; | |
1488 | ||
832a90c3 JR |
1489 | if (!dma_mask) |
1490 | dma_mask = *dev->dma_mask; | |
1491 | ||
5d8b53cf JR |
1492 | spin_lock_irqsave(&domain->lock, flags); |
1493 | ||
1494 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
832a90c3 | 1495 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 1496 | |
5b28df6f JR |
1497 | if (*dma_addr == bad_dma_address) |
1498 | goto out_free; | |
5d8b53cf | 1499 | |
09ee17eb | 1500 | iommu_completion_wait(iommu); |
5d8b53cf | 1501 | |
5d8b53cf JR |
1502 | spin_unlock_irqrestore(&domain->lock, flags); |
1503 | ||
1504 | return virt_addr; | |
5b28df6f JR |
1505 | |
1506 | out_free: | |
1507 | ||
1508 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1509 | ||
1510 | return NULL; | |
5d8b53cf JR |
1511 | } |
1512 | ||
431b2a20 JR |
1513 | /* |
1514 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 1515 | */ |
5d8b53cf JR |
1516 | static void free_coherent(struct device *dev, size_t size, |
1517 | void *virt_addr, dma_addr_t dma_addr) | |
1518 | { | |
1519 | unsigned long flags; | |
1520 | struct amd_iommu *iommu; | |
1521 | struct protection_domain *domain; | |
1522 | u16 devid; | |
1523 | ||
dbcc112e JR |
1524 | if (!check_device(dev)) |
1525 | return; | |
1526 | ||
5d8b53cf JR |
1527 | get_device_resources(dev, &iommu, &domain, &devid); |
1528 | ||
1529 | if (!iommu || !domain) | |
1530 | goto free_mem; | |
1531 | ||
5b28df6f JR |
1532 | if (!dma_ops_domain(domain)) |
1533 | goto free_mem; | |
1534 | ||
5d8b53cf JR |
1535 | spin_lock_irqsave(&domain->lock, flags); |
1536 | ||
1537 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 1538 | |
09ee17eb | 1539 | iommu_completion_wait(iommu); |
5d8b53cf JR |
1540 | |
1541 | spin_unlock_irqrestore(&domain->lock, flags); | |
1542 | ||
1543 | free_mem: | |
1544 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1545 | } | |
1546 | ||
b39ba6ad JR |
1547 | /* |
1548 | * This function is called by the DMA layer to find out if we can handle a | |
1549 | * particular device. It is part of the dma_ops. | |
1550 | */ | |
1551 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
1552 | { | |
1553 | u16 bdf; | |
1554 | struct pci_dev *pcidev; | |
1555 | ||
1556 | /* No device or no PCI device */ | |
1557 | if (!dev || dev->bus != &pci_bus_type) | |
1558 | return 0; | |
1559 | ||
1560 | pcidev = to_pci_dev(dev); | |
1561 | ||
1562 | bdf = calc_devid(pcidev->bus->number, pcidev->devfn); | |
1563 | ||
1564 | /* Out of our scope? */ | |
1565 | if (bdf > amd_iommu_last_bdf) | |
1566 | return 0; | |
1567 | ||
1568 | return 1; | |
1569 | } | |
1570 | ||
c432f3df | 1571 | /* |
431b2a20 JR |
1572 | * The function for pre-allocating protection domains. |
1573 | * | |
c432f3df JR |
1574 | * If the driver core informs the DMA layer if a driver grabs a device |
1575 | * we don't need to preallocate the protection domains anymore. | |
1576 | * For now we have to. | |
1577 | */ | |
1578 | void prealloc_protection_domains(void) | |
1579 | { | |
1580 | struct pci_dev *dev = NULL; | |
1581 | struct dma_ops_domain *dma_dom; | |
1582 | struct amd_iommu *iommu; | |
1583 | int order = amd_iommu_aperture_order; | |
1584 | u16 devid; | |
1585 | ||
1586 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
edcb34da | 1587 | devid = calc_devid(dev->bus->number, dev->devfn); |
3a61ec38 | 1588 | if (devid > amd_iommu_last_bdf) |
c432f3df JR |
1589 | continue; |
1590 | devid = amd_iommu_alias_table[devid]; | |
1591 | if (domain_for_device(devid)) | |
1592 | continue; | |
1593 | iommu = amd_iommu_rlookup_table[devid]; | |
1594 | if (!iommu) | |
1595 | continue; | |
1596 | dma_dom = dma_ops_domain_alloc(iommu, order); | |
1597 | if (!dma_dom) | |
1598 | continue; | |
1599 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
1600 | dma_dom->target_dev = devid; |
1601 | ||
1602 | list_add_tail(&dma_dom->list, &iommu_pd_list); | |
c432f3df JR |
1603 | } |
1604 | } | |
1605 | ||
6631ee9d JR |
1606 | static struct dma_mapping_ops amd_iommu_dma_ops = { |
1607 | .alloc_coherent = alloc_coherent, | |
1608 | .free_coherent = free_coherent, | |
1609 | .map_single = map_single, | |
1610 | .unmap_single = unmap_single, | |
1611 | .map_sg = map_sg, | |
1612 | .unmap_sg = unmap_sg, | |
b39ba6ad | 1613 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
1614 | }; |
1615 | ||
431b2a20 JR |
1616 | /* |
1617 | * The function which clues the AMD IOMMU driver into dma_ops. | |
1618 | */ | |
6631ee9d JR |
1619 | int __init amd_iommu_init_dma_ops(void) |
1620 | { | |
1621 | struct amd_iommu *iommu; | |
1622 | int order = amd_iommu_aperture_order; | |
1623 | int ret; | |
1624 | ||
431b2a20 JR |
1625 | /* |
1626 | * first allocate a default protection domain for every IOMMU we | |
1627 | * found in the system. Devices not assigned to any other | |
1628 | * protection domain will be assigned to the default one. | |
1629 | */ | |
6631ee9d JR |
1630 | list_for_each_entry(iommu, &amd_iommu_list, list) { |
1631 | iommu->default_dom = dma_ops_domain_alloc(iommu, order); | |
1632 | if (iommu->default_dom == NULL) | |
1633 | return -ENOMEM; | |
e2dc14a2 | 1634 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
1635 | ret = iommu_init_unity_mappings(iommu); |
1636 | if (ret) | |
1637 | goto free_domains; | |
1638 | } | |
1639 | ||
431b2a20 JR |
1640 | /* |
1641 | * If device isolation is enabled, pre-allocate the protection | |
1642 | * domains for each device. | |
1643 | */ | |
6631ee9d JR |
1644 | if (amd_iommu_isolate) |
1645 | prealloc_protection_domains(); | |
1646 | ||
1647 | iommu_detected = 1; | |
1648 | force_iommu = 1; | |
1649 | bad_dma_address = 0; | |
92af4e29 | 1650 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
1651 | gart_iommu_aperture_disabled = 1; |
1652 | gart_iommu_aperture = 0; | |
92af4e29 | 1653 | #endif |
6631ee9d | 1654 | |
431b2a20 | 1655 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
1656 | dma_ops = &amd_iommu_dma_ops; |
1657 | ||
26961efe JR |
1658 | #ifdef CONFIG_IOMMU_API |
1659 | register_iommu(&amd_iommu_ops); | |
1660 | #endif | |
1661 | ||
e275a2a0 JR |
1662 | bus_register_notifier(&pci_bus_type, &device_nb); |
1663 | ||
7f26508b JR |
1664 | amd_iommu_stats_init(); |
1665 | ||
6631ee9d JR |
1666 | return 0; |
1667 | ||
1668 | free_domains: | |
1669 | ||
1670 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
1671 | if (iommu->default_dom) | |
1672 | dma_ops_domain_free(iommu->default_dom); | |
1673 | } | |
1674 | ||
1675 | return ret; | |
1676 | } | |
6d98cd80 JR |
1677 | |
1678 | /***************************************************************************** | |
1679 | * | |
1680 | * The following functions belong to the exported interface of AMD IOMMU | |
1681 | * | |
1682 | * This interface allows access to lower level functions of the IOMMU | |
1683 | * like protection domain handling and assignement of devices to domains | |
1684 | * which is not possible with the dma_ops interface. | |
1685 | * | |
1686 | *****************************************************************************/ | |
1687 | ||
1688 | #ifdef CONFIG_IOMMU_API | |
1689 | ||
1690 | static void cleanup_domain(struct protection_domain *domain) | |
1691 | { | |
1692 | unsigned long flags; | |
1693 | u16 devid; | |
1694 | ||
1695 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1696 | ||
1697 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) | |
1698 | if (amd_iommu_pd_table[devid] == domain) | |
1699 | __detach_device(domain, devid); | |
1700 | ||
1701 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1702 | } | |
1703 | ||
c156e347 JR |
1704 | static int amd_iommu_domain_init(struct iommu_domain *dom) |
1705 | { | |
1706 | struct protection_domain *domain; | |
1707 | ||
1708 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
1709 | if (!domain) | |
1710 | return -ENOMEM; | |
1711 | ||
1712 | spin_lock_init(&domain->lock); | |
1713 | domain->mode = PAGE_MODE_3_LEVEL; | |
1714 | domain->id = domain_id_alloc(); | |
1715 | if (!domain->id) | |
1716 | goto out_free; | |
1717 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
1718 | if (!domain->pt_root) | |
1719 | goto out_free; | |
1720 | ||
1721 | dom->priv = domain; | |
1722 | ||
1723 | return 0; | |
1724 | ||
1725 | out_free: | |
1726 | kfree(domain); | |
1727 | ||
1728 | return -ENOMEM; | |
1729 | } | |
1730 | ||
98383fc3 JR |
1731 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
1732 | { | |
1733 | struct protection_domain *domain = dom->priv; | |
1734 | ||
1735 | if (!domain) | |
1736 | return; | |
1737 | ||
1738 | if (domain->dev_cnt > 0) | |
1739 | cleanup_domain(domain); | |
1740 | ||
1741 | BUG_ON(domain->dev_cnt != 0); | |
1742 | ||
1743 | free_pagetable(domain); | |
1744 | ||
1745 | domain_id_free(domain->id); | |
1746 | ||
1747 | kfree(domain); | |
1748 | ||
1749 | dom->priv = NULL; | |
1750 | } | |
1751 | ||
684f2888 JR |
1752 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
1753 | struct device *dev) | |
1754 | { | |
1755 | struct protection_domain *domain = dom->priv; | |
1756 | struct amd_iommu *iommu; | |
1757 | struct pci_dev *pdev; | |
1758 | u16 devid; | |
1759 | ||
1760 | if (dev->bus != &pci_bus_type) | |
1761 | return; | |
1762 | ||
1763 | pdev = to_pci_dev(dev); | |
1764 | ||
1765 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1766 | ||
1767 | if (devid > 0) | |
1768 | detach_device(domain, devid); | |
1769 | ||
1770 | iommu = amd_iommu_rlookup_table[devid]; | |
1771 | if (!iommu) | |
1772 | return; | |
1773 | ||
1774 | iommu_queue_inv_dev_entry(iommu, devid); | |
1775 | iommu_completion_wait(iommu); | |
1776 | } | |
1777 | ||
01106066 JR |
1778 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
1779 | struct device *dev) | |
1780 | { | |
1781 | struct protection_domain *domain = dom->priv; | |
1782 | struct protection_domain *old_domain; | |
1783 | struct amd_iommu *iommu; | |
1784 | struct pci_dev *pdev; | |
1785 | u16 devid; | |
1786 | ||
1787 | if (dev->bus != &pci_bus_type) | |
1788 | return -EINVAL; | |
1789 | ||
1790 | pdev = to_pci_dev(dev); | |
1791 | ||
1792 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1793 | ||
1794 | if (devid >= amd_iommu_last_bdf || | |
1795 | devid != amd_iommu_alias_table[devid]) | |
1796 | return -EINVAL; | |
1797 | ||
1798 | iommu = amd_iommu_rlookup_table[devid]; | |
1799 | if (!iommu) | |
1800 | return -EINVAL; | |
1801 | ||
1802 | old_domain = domain_for_device(devid); | |
1803 | if (old_domain) | |
1804 | return -EBUSY; | |
1805 | ||
1806 | attach_device(iommu, domain, devid); | |
1807 | ||
1808 | iommu_completion_wait(iommu); | |
1809 | ||
1810 | return 0; | |
1811 | } | |
1812 | ||
c6229ca6 JR |
1813 | static int amd_iommu_map_range(struct iommu_domain *dom, |
1814 | unsigned long iova, phys_addr_t paddr, | |
1815 | size_t size, int iommu_prot) | |
1816 | { | |
1817 | struct protection_domain *domain = dom->priv; | |
1818 | unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE); | |
1819 | int prot = 0; | |
1820 | int ret; | |
1821 | ||
1822 | if (iommu_prot & IOMMU_READ) | |
1823 | prot |= IOMMU_PROT_IR; | |
1824 | if (iommu_prot & IOMMU_WRITE) | |
1825 | prot |= IOMMU_PROT_IW; | |
1826 | ||
1827 | iova &= PAGE_MASK; | |
1828 | paddr &= PAGE_MASK; | |
1829 | ||
1830 | for (i = 0; i < npages; ++i) { | |
1831 | ret = iommu_map_page(domain, iova, paddr, prot); | |
1832 | if (ret) | |
1833 | return ret; | |
1834 | ||
1835 | iova += PAGE_SIZE; | |
1836 | paddr += PAGE_SIZE; | |
1837 | } | |
1838 | ||
1839 | return 0; | |
1840 | } | |
1841 | ||
eb74ff6c JR |
1842 | static void amd_iommu_unmap_range(struct iommu_domain *dom, |
1843 | unsigned long iova, size_t size) | |
1844 | { | |
1845 | ||
1846 | struct protection_domain *domain = dom->priv; | |
1847 | unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE); | |
1848 | ||
1849 | iova &= PAGE_MASK; | |
1850 | ||
1851 | for (i = 0; i < npages; ++i) { | |
1852 | iommu_unmap_page(domain, iova); | |
1853 | iova += PAGE_SIZE; | |
1854 | } | |
1855 | ||
1856 | iommu_flush_domain(domain->id); | |
1857 | } | |
1858 | ||
645c4c8d JR |
1859 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
1860 | unsigned long iova) | |
1861 | { | |
1862 | struct protection_domain *domain = dom->priv; | |
1863 | unsigned long offset = iova & ~PAGE_MASK; | |
1864 | phys_addr_t paddr; | |
1865 | u64 *pte; | |
1866 | ||
1867 | pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)]; | |
1868 | ||
1869 | if (!IOMMU_PTE_PRESENT(*pte)) | |
1870 | return 0; | |
1871 | ||
1872 | pte = IOMMU_PTE_PAGE(*pte); | |
1873 | pte = &pte[IOMMU_PTE_L1_INDEX(iova)]; | |
1874 | ||
1875 | if (!IOMMU_PTE_PRESENT(*pte)) | |
1876 | return 0; | |
1877 | ||
1878 | pte = IOMMU_PTE_PAGE(*pte); | |
1879 | pte = &pte[IOMMU_PTE_L0_INDEX(iova)]; | |
1880 | ||
1881 | if (!IOMMU_PTE_PRESENT(*pte)) | |
1882 | return 0; | |
1883 | ||
1884 | paddr = *pte & IOMMU_PAGE_MASK; | |
1885 | paddr |= offset; | |
1886 | ||
1887 | return paddr; | |
1888 | } | |
1889 | ||
26961efe JR |
1890 | static struct iommu_ops amd_iommu_ops = { |
1891 | .domain_init = amd_iommu_domain_init, | |
1892 | .domain_destroy = amd_iommu_domain_destroy, | |
1893 | .attach_dev = amd_iommu_attach_device, | |
1894 | .detach_dev = amd_iommu_detach_device, | |
1895 | .map = amd_iommu_map_range, | |
1896 | .unmap = amd_iommu_unmap_range, | |
1897 | .iova_to_phys = amd_iommu_iova_to_phys, | |
1898 | }; | |
1899 | ||
6d98cd80 | 1900 | #endif |