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Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
8f47e163 | 4 | * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
1da177e4 LT |
5 | * |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
cdd6c482 | 17 | #include <linux/perf_event.h> |
1da177e4 | 18 | #include <linux/kernel_stat.h> |
d1de36f5 | 19 | #include <linux/mc146818rtc.h> |
70a20025 | 20 | #include <linux/acpi_pmtmr.h> |
d1de36f5 IM |
21 | #include <linux/clockchips.h> |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/bootmem.h> | |
24 | #include <linux/ftrace.h> | |
25 | #include <linux/ioport.h> | |
e83a5fdc | 26 | #include <linux/module.h> |
f3c6ea1b | 27 | #include <linux/syscore_ops.h> |
d1de36f5 IM |
28 | #include <linux/delay.h> |
29 | #include <linux/timex.h> | |
334955ef | 30 | #include <linux/i8253.h> |
6e1cb38a | 31 | #include <linux/dmar.h> |
d1de36f5 IM |
32 | #include <linux/init.h> |
33 | #include <linux/cpu.h> | |
34 | #include <linux/dmi.h> | |
d1de36f5 IM |
35 | #include <linux/smp.h> |
36 | #include <linux/mm.h> | |
1da177e4 | 37 | |
83ab8514 | 38 | #include <asm/trace/irq_vectors.h> |
8a8f422d | 39 | #include <asm/irq_remapping.h> |
cdd6c482 | 40 | #include <asm/perf_event.h> |
736decac | 41 | #include <asm/x86_init.h> |
1da177e4 | 42 | #include <asm/pgalloc.h> |
60063497 | 43 | #include <linux/atomic.h> |
1da177e4 | 44 | #include <asm/mpspec.h> |
d1de36f5 | 45 | #include <asm/i8259.h> |
73dea47f | 46 | #include <asm/proto.h> |
2c8c0e6b | 47 | #include <asm/apic.h> |
7167d08e | 48 | #include <asm/io_apic.h> |
d1de36f5 IM |
49 | #include <asm/desc.h> |
50 | #include <asm/hpet.h> | |
51 | #include <asm/idle.h> | |
52 | #include <asm/mtrr.h> | |
16f871bc | 53 | #include <asm/time.h> |
2bc13797 | 54 | #include <asm/smp.h> |
be71b855 | 55 | #include <asm/mce.h> |
8c3ba8d0 | 56 | #include <asm/tsc.h> |
2904ed8d | 57 | #include <asm/hypervisor.h> |
1da177e4 | 58 | |
ec70de8b | 59 | unsigned int num_processors; |
fdbecd9f | 60 | |
148f9bb8 | 61 | unsigned disabled_cpus; |
fdbecd9f | 62 | |
ec70de8b BG |
63 | /* Processor that is doing the boot up */ |
64 | unsigned int boot_cpu_physical_apicid = -1U; | |
cc08e04c | 65 | EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); |
5af5573e | 66 | |
80e5609c | 67 | /* |
fdbecd9f | 68 | * The highest APIC ID seen during enumeration. |
80e5609c | 69 | */ |
a491cc90 | 70 | static unsigned int max_physical_apicid; |
5af5573e | 71 | |
80e5609c | 72 | /* |
fdbecd9f | 73 | * Bitmask of physically existing CPUs: |
80e5609c | 74 | */ |
ec70de8b BG |
75 | physid_mask_t phys_cpu_present_map; |
76 | ||
151e0c7d HD |
77 | /* |
78 | * Processor to be disabled specified by kernel parameter | |
79 | * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to | |
80 | * avoid undefined behaviour caused by sending INIT from AP to BSP. | |
81 | */ | |
5b4d1dbc | 82 | static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID; |
151e0c7d | 83 | |
ec70de8b BG |
84 | /* |
85 | * Map cpu index to physical APIC ID | |
86 | */ | |
0816b0f0 VZ |
87 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); |
88 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); | |
ec70de8b BG |
89 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); |
90 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); | |
80e5609c | 91 | |
b3c51170 | 92 | #ifdef CONFIG_X86_32 |
4c321ff8 | 93 | |
4c321ff8 TH |
94 | /* |
95 | * On x86_32, the mapping between cpu and logical apicid may vary | |
96 | * depending on apic in use. The following early percpu variable is | |
97 | * used for the mapping. This is where the behaviors of x86_64 and 32 | |
98 | * actually diverge. Let's keep it ugly for now. | |
99 | */ | |
0816b0f0 | 100 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); |
4c321ff8 | 101 | |
f28c0ae2 YL |
102 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ |
103 | static int enabled_via_apicbase; | |
104 | ||
c0eaa453 CG |
105 | /* |
106 | * Handle interrupt mode configuration register (IMCR). | |
107 | * This register controls whether the interrupt signals | |
108 | * that reach the BSP come from the master PIC or from the | |
109 | * local APIC. Before entering Symmetric I/O Mode, either | |
110 | * the BIOS or the operating system must switch out of | |
111 | * PIC Mode by changing the IMCR. | |
112 | */ | |
5cda395f | 113 | static inline void imcr_pic_to_apic(void) |
c0eaa453 CG |
114 | { |
115 | /* select IMCR register */ | |
116 | outb(0x70, 0x22); | |
117 | /* NMI and 8259 INTR go through APIC */ | |
118 | outb(0x01, 0x23); | |
119 | } | |
120 | ||
5cda395f | 121 | static inline void imcr_apic_to_pic(void) |
c0eaa453 CG |
122 | { |
123 | /* select IMCR register */ | |
124 | outb(0x70, 0x22); | |
125 | /* NMI and 8259 INTR go directly to BSP */ | |
126 | outb(0x00, 0x23); | |
127 | } | |
b3c51170 YL |
128 | #endif |
129 | ||
279f1461 SS |
130 | /* |
131 | * Knob to control our willingness to enable the local APIC. | |
132 | * | |
133 | * +1=force-enable | |
134 | */ | |
135 | static int force_enable_local_apic __initdata; | |
dc9788f4 | 136 | |
279f1461 SS |
137 | /* |
138 | * APIC command line parameters | |
139 | */ | |
140 | static int __init parse_lapic(char *arg) | |
141 | { | |
142 | if (config_enabled(CONFIG_X86_32) && !arg) | |
143 | force_enable_local_apic = 1; | |
27cf9298 | 144 | else if (arg && !strncmp(arg, "notscdeadline", 13)) |
279f1461 SS |
145 | setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); |
146 | return 0; | |
147 | } | |
148 | early_param("lapic", parse_lapic); | |
149 | ||
b3c51170 | 150 | #ifdef CONFIG_X86_64 |
bc1d99c1 | 151 | static int apic_calibrate_pmtmr __initdata; |
b3c51170 YL |
152 | static __init int setup_apicpmtimer(char *s) |
153 | { | |
154 | apic_calibrate_pmtmr = 1; | |
155 | notsc_setup(NULL); | |
156 | return 0; | |
157 | } | |
158 | __setup("apicpmtimer", setup_apicpmtimer); | |
159 | #endif | |
160 | ||
b3c51170 YL |
161 | unsigned long mp_lapic_addr; |
162 | int disable_apic; | |
163 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ | |
25874a29 | 164 | static int disable_apic_timer __initdata; |
e83a5fdc | 165 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
166 | int local_apic_timer_c2_ok; |
167 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
168 | ||
2414e021 | 169 | int first_system_vector = FIRST_SYSTEM_VECTOR; |
efa2559f | 170 | |
e83a5fdc HS |
171 | /* |
172 | * Debug level, exported for io_apic.c | |
173 | */ | |
baa13188 | 174 | unsigned int apic_verbosity; |
e83a5fdc | 175 | |
89c38c28 CG |
176 | int pic_mode; |
177 | ||
bab4b27c AS |
178 | /* Have we found an MP table */ |
179 | int smp_found_config; | |
180 | ||
39928722 AD |
181 | static struct resource lapic_resource = { |
182 | .name = "Local APIC", | |
183 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
184 | }; | |
185 | ||
1ade93ef | 186 | unsigned int lapic_timer_frequency = 0; |
d03030e9 | 187 | |
0e078e2f | 188 | static void apic_pm_activate(void); |
ba7eda4c | 189 | |
d3432896 AK |
190 | static unsigned long apic_phys; |
191 | ||
0e078e2f TG |
192 | /* |
193 | * Get the LAPIC version | |
194 | */ | |
195 | static inline int lapic_get_version(void) | |
ba7eda4c | 196 | { |
0e078e2f | 197 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
198 | } |
199 | ||
0e078e2f | 200 | /* |
9c803869 | 201 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
202 | */ |
203 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 204 | { |
9c803869 | 205 | #ifdef CONFIG_X86_64 |
0e078e2f | 206 | return 1; |
9c803869 CG |
207 | #else |
208 | return APIC_INTEGRATED(lapic_get_version()); | |
209 | #endif | |
ba7eda4c TG |
210 | } |
211 | ||
212 | /* | |
0e078e2f | 213 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 214 | */ |
0e078e2f | 215 | static int modern_apic(void) |
ba7eda4c | 216 | { |
0e078e2f TG |
217 | /* AMD systems use old APIC versions, so check the CPU */ |
218 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
219 | boot_cpu_data.x86 >= 0xf) | |
220 | return 1; | |
221 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
222 | } |
223 | ||
08306ce6 | 224 | /* |
a933c618 CG |
225 | * right after this call apic become NOOP driven |
226 | * so apic->write/read doesn't do anything | |
08306ce6 | 227 | */ |
25874a29 | 228 | static void __init apic_disable(void) |
08306ce6 | 229 | { |
f88f2b4f | 230 | pr_info("APIC: switched to apic NOOP\n"); |
a933c618 | 231 | apic = &apic_noop; |
08306ce6 CG |
232 | } |
233 | ||
c1eeb2de | 234 | void native_apic_wait_icr_idle(void) |
8339e9fb FLV |
235 | { |
236 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
237 | cpu_relax(); | |
238 | } | |
239 | ||
c1eeb2de | 240 | u32 native_safe_apic_wait_icr_idle(void) |
8339e9fb | 241 | { |
3c6bb07a | 242 | u32 send_status; |
8339e9fb FLV |
243 | int timeout; |
244 | ||
245 | timeout = 0; | |
246 | do { | |
247 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
248 | if (!send_status) | |
249 | break; | |
b49d7d87 | 250 | inc_irq_stat(icr_read_retry_count); |
8339e9fb FLV |
251 | udelay(100); |
252 | } while (timeout++ < 1000); | |
253 | ||
254 | return send_status; | |
255 | } | |
256 | ||
c1eeb2de | 257 | void native_apic_icr_write(u32 low, u32 id) |
1b374e4d | 258 | { |
ea7bdc65 JK |
259 | unsigned long flags; |
260 | ||
261 | local_irq_save(flags); | |
ed4e5ec1 | 262 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
1b374e4d | 263 | apic_write(APIC_ICR, low); |
ea7bdc65 | 264 | local_irq_restore(flags); |
1b374e4d SS |
265 | } |
266 | ||
c1eeb2de | 267 | u64 native_apic_icr_read(void) |
1b374e4d SS |
268 | { |
269 | u32 icr1, icr2; | |
270 | ||
271 | icr2 = apic_read(APIC_ICR2); | |
272 | icr1 = apic_read(APIC_ICR); | |
273 | ||
cf9768d7 | 274 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
275 | } |
276 | ||
7c37e48b CG |
277 | #ifdef CONFIG_X86_32 |
278 | /** | |
279 | * get_physical_broadcast - Get number of physical broadcast IDs | |
280 | */ | |
281 | int get_physical_broadcast(void) | |
282 | { | |
283 | return modern_apic() ? 0xff : 0xf; | |
284 | } | |
285 | #endif | |
286 | ||
0e078e2f TG |
287 | /** |
288 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
289 | */ | |
37e650c7 | 290 | int lapic_get_maxlvt(void) |
1da177e4 | 291 | { |
36a028de | 292 | unsigned int v; |
1da177e4 LT |
293 | |
294 | v = apic_read(APIC_LVR); | |
36a028de CG |
295 | /* |
296 | * - we always have APIC integrated on 64bit mode | |
297 | * - 82489DXs do not report # of LVT entries | |
298 | */ | |
299 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; | |
1da177e4 LT |
300 | } |
301 | ||
274cfe59 CG |
302 | /* |
303 | * Local APIC timer | |
304 | */ | |
305 | ||
c40aaec6 | 306 | /* Clock divisor */ |
c40aaec6 | 307 | #define APIC_DIVISOR 16 |
279f1461 | 308 | #define TSC_DIVISOR 32 |
f07f4f90 | 309 | |
0e078e2f TG |
310 | /* |
311 | * This function sets up the local APIC timer, with a timeout of | |
312 | * 'clocks' APIC bus clock. During calibration we actually call | |
313 | * this function twice on the boot CPU, once with a bogus timeout | |
314 | * value, second time for real. The other (noncalibrating) CPUs | |
315 | * call this function only once, with the real, calibrated value. | |
316 | * | |
317 | * We do reads before writes even if unnecessary, to get around the | |
318 | * P5 APIC double write bug. | |
319 | */ | |
0e078e2f | 320 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 321 | { |
0e078e2f | 322 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 323 | |
0e078e2f TG |
324 | lvtt_value = LOCAL_TIMER_VECTOR; |
325 | if (!oneshot) | |
326 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
279f1461 SS |
327 | else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) |
328 | lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; | |
329 | ||
f07f4f90 CG |
330 | if (!lapic_is_integrated()) |
331 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
332 | ||
0e078e2f TG |
333 | if (!irqen) |
334 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 335 | |
0e078e2f | 336 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 | 337 | |
279f1461 SS |
338 | if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { |
339 | printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); | |
340 | return; | |
341 | } | |
342 | ||
1da177e4 | 343 | /* |
0e078e2f | 344 | * Divide PICLK by 16 |
1da177e4 | 345 | */ |
0e078e2f | 346 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
347 | apic_write(APIC_TDCR, |
348 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
349 | APIC_TDR_DIV_16); | |
0e078e2f TG |
350 | |
351 | if (!oneshot) | |
f07f4f90 | 352 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
353 | } |
354 | ||
0e078e2f | 355 | /* |
a68c439b | 356 | * Setup extended LVT, AMD specific |
7b83dae7 | 357 | * |
a68c439b RR |
358 | * Software should use the LVT offsets the BIOS provides. The offsets |
359 | * are determined by the subsystems using it like those for MCE | |
360 | * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts | |
361 | * are supported. Beginning with family 10h at least 4 offsets are | |
362 | * available. | |
286f5718 | 363 | * |
a68c439b RR |
364 | * Since the offsets must be consistent for all cores, we keep track |
365 | * of the LVT offsets in software and reserve the offset for the same | |
366 | * vector also to be used on other cores. An offset is freed by | |
367 | * setting the entry to APIC_EILVT_MASKED. | |
368 | * | |
369 | * If the BIOS is right, there should be no conflicts. Otherwise a | |
370 | * "[Firmware Bug]: ..." error message is generated. However, if | |
371 | * software does not properly determines the offsets, it is not | |
372 | * necessarily a BIOS bug. | |
0e078e2f | 373 | */ |
7b83dae7 | 374 | |
a68c439b RR |
375 | static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; |
376 | ||
377 | static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) | |
378 | { | |
379 | return (old & APIC_EILVT_MASKED) | |
380 | || (new == APIC_EILVT_MASKED) | |
381 | || ((new & ~APIC_EILVT_MASKED) == old); | |
382 | } | |
383 | ||
384 | static unsigned int reserve_eilvt_offset(int offset, unsigned int new) | |
385 | { | |
8abc3122 | 386 | unsigned int rsvd, vector; |
a68c439b RR |
387 | |
388 | if (offset >= APIC_EILVT_NR_MAX) | |
389 | return ~0; | |
390 | ||
8abc3122 | 391 | rsvd = atomic_read(&eilvt_offsets[offset]); |
a68c439b | 392 | do { |
8abc3122 RR |
393 | vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ |
394 | if (vector && !eilvt_entry_is_changeable(vector, new)) | |
a68c439b RR |
395 | /* may not change if vectors are different */ |
396 | return rsvd; | |
397 | rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); | |
398 | } while (rsvd != new); | |
399 | ||
8abc3122 RR |
400 | rsvd &= ~APIC_EILVT_MASKED; |
401 | if (rsvd && rsvd != vector) | |
402 | pr_info("LVT offset %d assigned for vector 0x%02x\n", | |
403 | offset, rsvd); | |
404 | ||
a68c439b RR |
405 | return new; |
406 | } | |
407 | ||
408 | /* | |
409 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
cbf74cea RR |
410 | * enables the vector. See also the BKDGs. Must be called with |
411 | * preemption disabled. | |
a68c439b RR |
412 | */ |
413 | ||
27afdf20 | 414 | int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) |
1da177e4 | 415 | { |
a68c439b RR |
416 | unsigned long reg = APIC_EILVTn(offset); |
417 | unsigned int new, old, reserved; | |
418 | ||
419 | new = (mask << 16) | (msg_type << 8) | vector; | |
420 | old = apic_read(reg); | |
421 | reserved = reserve_eilvt_offset(offset, new); | |
422 | ||
423 | if (reserved != new) { | |
eb48c9cb RR |
424 | pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " |
425 | "vector 0x%x, but the register is already in use for " | |
426 | "vector 0x%x on another cpu\n", | |
427 | smp_processor_id(), reg, offset, new, reserved); | |
a68c439b RR |
428 | return -EINVAL; |
429 | } | |
430 | ||
431 | if (!eilvt_entry_is_changeable(old, new)) { | |
eb48c9cb RR |
432 | pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " |
433 | "vector 0x%x, but the register is already in use for " | |
434 | "vector 0x%x on this cpu\n", | |
435 | smp_processor_id(), reg, offset, new, old); | |
a68c439b RR |
436 | return -EBUSY; |
437 | } | |
438 | ||
439 | apic_write(reg, new); | |
a8fcf1a2 | 440 | |
a68c439b | 441 | return 0; |
1da177e4 | 442 | } |
27afdf20 | 443 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt); |
7b83dae7 | 444 | |
0e078e2f TG |
445 | /* |
446 | * Program the next event, relative to now | |
447 | */ | |
448 | static int lapic_next_event(unsigned long delta, | |
449 | struct clock_event_device *evt) | |
1da177e4 | 450 | { |
0e078e2f TG |
451 | apic_write(APIC_TMICT, delta); |
452 | return 0; | |
1da177e4 LT |
453 | } |
454 | ||
279f1461 SS |
455 | static int lapic_next_deadline(unsigned long delta, |
456 | struct clock_event_device *evt) | |
457 | { | |
458 | u64 tsc; | |
459 | ||
460 | rdtscll(tsc); | |
461 | wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); | |
462 | return 0; | |
463 | } | |
464 | ||
0e078e2f TG |
465 | /* |
466 | * Setup the lapic timer in periodic or oneshot mode | |
467 | */ | |
468 | static void lapic_timer_setup(enum clock_event_mode mode, | |
469 | struct clock_event_device *evt) | |
9b7711f0 HS |
470 | { |
471 | unsigned long flags; | |
0e078e2f | 472 | unsigned int v; |
9b7711f0 | 473 | |
0e078e2f TG |
474 | /* Lapic used as dummy for broadcast ? */ |
475 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
476 | return; |
477 | ||
478 | local_irq_save(flags); | |
479 | ||
0e078e2f TG |
480 | switch (mode) { |
481 | case CLOCK_EVT_MODE_PERIODIC: | |
482 | case CLOCK_EVT_MODE_ONESHOT: | |
1ade93ef | 483 | __setup_APIC_LVTT(lapic_timer_frequency, |
0e078e2f TG |
484 | mode != CLOCK_EVT_MODE_PERIODIC, 1); |
485 | break; | |
486 | case CLOCK_EVT_MODE_UNUSED: | |
487 | case CLOCK_EVT_MODE_SHUTDOWN: | |
488 | v = apic_read(APIC_LVTT); | |
489 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
490 | apic_write(APIC_LVTT, v); | |
6f9b4100 | 491 | apic_write(APIC_TMICT, 0); |
0e078e2f TG |
492 | break; |
493 | case CLOCK_EVT_MODE_RESUME: | |
494 | /* Nothing to do here */ | |
495 | break; | |
496 | } | |
9b7711f0 HS |
497 | |
498 | local_irq_restore(flags); | |
499 | } | |
500 | ||
1da177e4 | 501 | /* |
0e078e2f | 502 | * Local APIC timer broadcast function |
1da177e4 | 503 | */ |
9628937d | 504 | static void lapic_timer_broadcast(const struct cpumask *mask) |
1da177e4 | 505 | { |
0e078e2f | 506 | #ifdef CONFIG_SMP |
dac5f412 | 507 | apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); |
0e078e2f TG |
508 | #endif |
509 | } | |
1da177e4 | 510 | |
25874a29 HK |
511 | |
512 | /* | |
513 | * The local apic timer can be used for any function which is CPU local. | |
514 | */ | |
515 | static struct clock_event_device lapic_clockevent = { | |
516 | .name = "lapic", | |
517 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
518 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
519 | .shift = 32, | |
520 | .set_mode = lapic_timer_setup, | |
521 | .set_next_event = lapic_next_event, | |
522 | .broadcast = lapic_timer_broadcast, | |
523 | .rating = 100, | |
524 | .irq = -1, | |
525 | }; | |
526 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
527 | ||
0e078e2f | 528 | /* |
421f91d2 | 529 | * Setup the local APIC timer for this CPU. Copy the initialized values |
0e078e2f TG |
530 | * of the boot CPU and register the clock event in the framework. |
531 | */ | |
148f9bb8 | 532 | static void setup_APIC_timer(void) |
0e078e2f | 533 | { |
89cbc767 | 534 | struct clock_event_device *levt = this_cpu_ptr(&lapic_events); |
1da177e4 | 535 | |
349c004e | 536 | if (this_cpu_has(X86_FEATURE_ARAT)) { |
db954b58 VP |
537 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; |
538 | /* Make LAPIC timer preferrable over percpu HPET */ | |
539 | lapic_clockevent.rating = 150; | |
540 | } | |
541 | ||
0e078e2f | 542 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
320ab2b0 | 543 | levt->cpumask = cpumask_of(smp_processor_id()); |
1da177e4 | 544 | |
279f1461 SS |
545 | if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { |
546 | levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | | |
547 | CLOCK_EVT_FEAT_DUMMY); | |
548 | levt->set_next_event = lapic_next_deadline; | |
549 | clockevents_config_and_register(levt, | |
550 | (tsc_khz / TSC_DIVISOR) * 1000, | |
551 | 0xF, ~0UL); | |
552 | } else | |
553 | clockevents_register_device(levt); | |
0e078e2f | 554 | } |
1da177e4 | 555 | |
2f04fa88 YL |
556 | /* |
557 | * In this functions we calibrate APIC bus clocks to the external timer. | |
558 | * | |
559 | * We want to do the calibration only once since we want to have local timer | |
560 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
561 | * frequency. | |
562 | * | |
563 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
564 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
565 | * readout is broken, so it never gets out of the wait loop again. This was | |
566 | * also reported by others. | |
567 | * | |
568 | * Monitoring the jiffies value is inaccurate and the clockevents | |
569 | * infrastructure allows us to do a simple substitution of the interrupt | |
570 | * handler. | |
571 | * | |
572 | * The calibration routine also uses the pm_timer when possible, as the PIT | |
573 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
574 | * back to normal later in the boot process). | |
575 | */ | |
576 | ||
577 | #define LAPIC_CAL_LOOPS (HZ/10) | |
578 | ||
579 | static __initdata int lapic_cal_loops = -1; | |
580 | static __initdata long lapic_cal_t1, lapic_cal_t2; | |
581 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
582 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
583 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
584 | ||
585 | /* | |
586 | * Temporary interrupt handler. | |
587 | */ | |
588 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
589 | { | |
590 | unsigned long long tsc = 0; | |
591 | long tapic = apic_read(APIC_TMCCT); | |
592 | unsigned long pm = acpi_pm_read_early(); | |
593 | ||
594 | if (cpu_has_tsc) | |
595 | rdtscll(tsc); | |
596 | ||
597 | switch (lapic_cal_loops++) { | |
598 | case 0: | |
599 | lapic_cal_t1 = tapic; | |
600 | lapic_cal_tsc1 = tsc; | |
601 | lapic_cal_pm1 = pm; | |
602 | lapic_cal_j1 = jiffies; | |
603 | break; | |
604 | ||
605 | case LAPIC_CAL_LOOPS: | |
606 | lapic_cal_t2 = tapic; | |
607 | lapic_cal_tsc2 = tsc; | |
608 | if (pm < lapic_cal_pm1) | |
609 | pm += ACPI_PM_OVRRUN; | |
610 | lapic_cal_pm2 = pm; | |
611 | lapic_cal_j2 = jiffies; | |
612 | break; | |
613 | } | |
614 | } | |
615 | ||
754ef0cd YI |
616 | static int __init |
617 | calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) | |
b189892d CG |
618 | { |
619 | const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; | |
620 | const long pm_thresh = pm_100ms / 100; | |
621 | unsigned long mult; | |
622 | u64 res; | |
623 | ||
624 | #ifndef CONFIG_X86_PM_TIMER | |
625 | return -1; | |
626 | #endif | |
627 | ||
39ba5d43 | 628 | apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); |
b189892d CG |
629 | |
630 | /* Check, if the PM timer is available */ | |
631 | if (!deltapm) | |
632 | return -1; | |
633 | ||
634 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
635 | ||
636 | if (deltapm > (pm_100ms - pm_thresh) && | |
637 | deltapm < (pm_100ms + pm_thresh)) { | |
39ba5d43 | 638 | apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); |
754ef0cd YI |
639 | return 0; |
640 | } | |
641 | ||
642 | res = (((u64)deltapm) * mult) >> 22; | |
643 | do_div(res, 1000000); | |
644 | pr_warning("APIC calibration not consistent " | |
39ba5d43 | 645 | "with PM-Timer: %ldms instead of 100ms\n",(long)res); |
754ef0cd YI |
646 | |
647 | /* Correct the lapic counter value */ | |
648 | res = (((u64)(*delta)) * pm_100ms); | |
649 | do_div(res, deltapm); | |
650 | pr_info("APIC delta adjusted to PM-Timer: " | |
651 | "%lu (%ld)\n", (unsigned long)res, *delta); | |
652 | *delta = (long)res; | |
653 | ||
654 | /* Correct the tsc counter value */ | |
655 | if (cpu_has_tsc) { | |
656 | res = (((u64)(*deltatsc)) * pm_100ms); | |
b189892d | 657 | do_div(res, deltapm); |
754ef0cd | 658 | apic_printk(APIC_VERBOSE, "TSC delta adjusted to " |
3235dc3f | 659 | "PM-Timer: %lu (%ld)\n", |
754ef0cd YI |
660 | (unsigned long)res, *deltatsc); |
661 | *deltatsc = (long)res; | |
b189892d CG |
662 | } |
663 | ||
664 | return 0; | |
665 | } | |
666 | ||
2f04fa88 YL |
667 | static int __init calibrate_APIC_clock(void) |
668 | { | |
89cbc767 | 669 | struct clock_event_device *levt = this_cpu_ptr(&lapic_events); |
2f04fa88 YL |
670 | void (*real_handler)(struct clock_event_device *dev); |
671 | unsigned long deltaj; | |
754ef0cd | 672 | long delta, deltatsc; |
2f04fa88 YL |
673 | int pm_referenced = 0; |
674 | ||
1ade93ef JP |
675 | /** |
676 | * check if lapic timer has already been calibrated by platform | |
677 | * specific routine, such as tsc calibration code. if so, we just fill | |
678 | * in the clockevent structure and return. | |
679 | */ | |
680 | ||
279f1461 SS |
681 | if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { |
682 | return 0; | |
683 | } else if (lapic_timer_frequency) { | |
1ade93ef JP |
684 | apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", |
685 | lapic_timer_frequency); | |
686 | lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, | |
687 | TICK_NSEC, lapic_clockevent.shift); | |
688 | lapic_clockevent.max_delta_ns = | |
689 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
690 | lapic_clockevent.min_delta_ns = | |
691 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
692 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
693 | return 0; | |
694 | } | |
695 | ||
279f1461 SS |
696 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
697 | "calibrating APIC timer ...\n"); | |
698 | ||
2f04fa88 YL |
699 | local_irq_disable(); |
700 | ||
701 | /* Replace the global interrupt handler */ | |
702 | real_handler = global_clock_event->event_handler; | |
703 | global_clock_event->event_handler = lapic_cal_handler; | |
704 | ||
705 | /* | |
81608f3c | 706 | * Setup the APIC counter to maximum. There is no way the lapic |
2f04fa88 YL |
707 | * can underflow in the 100ms detection time frame |
708 | */ | |
81608f3c | 709 | __setup_APIC_LVTT(0xffffffff, 0, 0); |
2f04fa88 YL |
710 | |
711 | /* Let the interrupts run */ | |
712 | local_irq_enable(); | |
713 | ||
714 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
715 | cpu_relax(); | |
716 | ||
717 | local_irq_disable(); | |
718 | ||
719 | /* Restore the real event handler */ | |
720 | global_clock_event->event_handler = real_handler; | |
721 | ||
722 | /* Build delta t1-t2 as apic timer counts down */ | |
723 | delta = lapic_cal_t1 - lapic_cal_t2; | |
724 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
725 | ||
754ef0cd YI |
726 | deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); |
727 | ||
b189892d CG |
728 | /* we trust the PM based calibration if possible */ |
729 | pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, | |
754ef0cd | 730 | &delta, &deltatsc); |
2f04fa88 YL |
731 | |
732 | /* Calculate the scaled math multiplication factor */ | |
733 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, | |
734 | lapic_clockevent.shift); | |
735 | lapic_clockevent.max_delta_ns = | |
4aed89d6 | 736 | clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); |
2f04fa88 YL |
737 | lapic_clockevent.min_delta_ns = |
738 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
739 | ||
1ade93ef | 740 | lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; |
2f04fa88 YL |
741 | |
742 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
411462f6 | 743 | apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); |
2f04fa88 | 744 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", |
1ade93ef | 745 | lapic_timer_frequency); |
2f04fa88 YL |
746 | |
747 | if (cpu_has_tsc) { | |
2f04fa88 YL |
748 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
749 | "%ld.%04ld MHz.\n", | |
754ef0cd YI |
750 | (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), |
751 | (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
2f04fa88 YL |
752 | } |
753 | ||
754 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
755 | "%u.%04u MHz.\n", | |
1ade93ef JP |
756 | lapic_timer_frequency / (1000000 / HZ), |
757 | lapic_timer_frequency % (1000000 / HZ)); | |
2f04fa88 YL |
758 | |
759 | /* | |
760 | * Do a sanity check on the APIC calibration result | |
761 | */ | |
1ade93ef | 762 | if (lapic_timer_frequency < (1000000 / HZ)) { |
2f04fa88 | 763 | local_irq_enable(); |
ba21ebb6 | 764 | pr_warning("APIC frequency too slow, disabling apic timer\n"); |
2f04fa88 YL |
765 | return -1; |
766 | } | |
767 | ||
768 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; | |
769 | ||
b189892d CG |
770 | /* |
771 | * PM timer calibration failed or not turned on | |
772 | * so lets try APIC timer based calibration | |
773 | */ | |
2f04fa88 YL |
774 | if (!pm_referenced) { |
775 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | |
776 | ||
777 | /* | |
778 | * Setup the apic timer manually | |
779 | */ | |
780 | levt->event_handler = lapic_cal_handler; | |
781 | lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); | |
782 | lapic_cal_loops = -1; | |
783 | ||
784 | /* Let the interrupts run */ | |
785 | local_irq_enable(); | |
786 | ||
787 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
788 | cpu_relax(); | |
789 | ||
2f04fa88 YL |
790 | /* Stop the lapic timer */ |
791 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); | |
792 | ||
2f04fa88 YL |
793 | /* Jiffies delta */ |
794 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
795 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
796 | ||
797 | /* Check, if the jiffies result is consistent */ | |
798 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) | |
799 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); | |
800 | else | |
801 | levt->features |= CLOCK_EVT_FEAT_DUMMY; | |
802 | } else | |
803 | local_irq_enable(); | |
804 | ||
805 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { | |
e423e33e | 806 | pr_warning("APIC timer disabled due to verification failure\n"); |
2f04fa88 YL |
807 | return -1; |
808 | } | |
809 | ||
810 | return 0; | |
811 | } | |
812 | ||
e83a5fdc HS |
813 | /* |
814 | * Setup the boot APIC | |
815 | * | |
816 | * Calibrate and verify the result. | |
817 | */ | |
0e078e2f TG |
818 | void __init setup_boot_APIC_clock(void) |
819 | { | |
820 | /* | |
274cfe59 CG |
821 | * The local apic timer can be disabled via the kernel |
822 | * commandline or from the CPU detection code. Register the lapic | |
823 | * timer as a dummy clock event source on SMP systems, so the | |
824 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
825 | */ |
826 | if (disable_apic_timer) { | |
ba21ebb6 | 827 | pr_info("Disabling APIC timer\n"); |
0e078e2f | 828 | /* No broadcast on UP ! */ |
9d09951d TG |
829 | if (num_possible_cpus() > 1) { |
830 | lapic_clockevent.mult = 1; | |
0e078e2f | 831 | setup_APIC_timer(); |
9d09951d | 832 | } |
0e078e2f TG |
833 | return; |
834 | } | |
835 | ||
89b3b1f4 | 836 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
837 | /* No broadcast on UP ! */ |
838 | if (num_possible_cpus() > 1) | |
839 | setup_APIC_timer(); | |
840 | return; | |
841 | } | |
842 | ||
0e078e2f TG |
843 | /* |
844 | * If nmi_watchdog is set to IO_APIC, we need the | |
845 | * PIT/HPET going. Otherwise register lapic as a dummy | |
846 | * device. | |
847 | */ | |
072b198a | 848 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; |
0e078e2f | 849 | |
274cfe59 | 850 | /* Setup the lapic or request the broadcast */ |
0e078e2f TG |
851 | setup_APIC_timer(); |
852 | } | |
853 | ||
148f9bb8 | 854 | void setup_secondary_APIC_clock(void) |
0e078e2f | 855 | { |
0e078e2f TG |
856 | setup_APIC_timer(); |
857 | } | |
858 | ||
859 | /* | |
860 | * The guts of the apic timer interrupt | |
861 | */ | |
862 | static void local_apic_timer_interrupt(void) | |
863 | { | |
864 | int cpu = smp_processor_id(); | |
865 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
866 | ||
867 | /* | |
868 | * Normally we should not be here till LAPIC has been initialized but | |
869 | * in some cases like kdump, its possible that there is a pending LAPIC | |
870 | * timer interrupt from previous kernel's context and is delivered in | |
871 | * new kernel the moment interrupts are enabled. | |
872 | * | |
873 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
874 | * its possible that when we get here evt->event_handler is NULL. | |
875 | * Check for event_handler being NULL and discard the interrupt as | |
876 | * spurious. | |
877 | */ | |
878 | if (!evt->event_handler) { | |
ba21ebb6 | 879 | pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); |
0e078e2f TG |
880 | /* Switch it off */ |
881 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
882 | return; | |
883 | } | |
884 | ||
885 | /* | |
886 | * the NMI deadlock-detector uses this. | |
887 | */ | |
915b0d01 | 888 | inc_irq_stat(apic_timer_irqs); |
0e078e2f TG |
889 | |
890 | evt->event_handler(evt); | |
891 | } | |
892 | ||
893 | /* | |
894 | * Local APIC timer interrupt. This is the most natural way for doing | |
895 | * local interrupts, but local timer interrupts can be emulated by | |
896 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
897 | * | |
898 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
899 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
900 | */ | |
1d9090e2 | 901 | __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) |
0e078e2f TG |
902 | { |
903 | struct pt_regs *old_regs = set_irq_regs(regs); | |
904 | ||
905 | /* | |
906 | * NOTE! We'd better ACK the irq immediately, | |
907 | * because timer handling can be slow. | |
eddc0e92 | 908 | * |
0e078e2f TG |
909 | * update_process_times() expects us to have done irq_enter(). |
910 | * Besides, if we don't timer interrupts ignore the global | |
911 | * interrupt lock, which is the WrongThing (tm) to do. | |
0e078e2f | 912 | */ |
eddc0e92 | 913 | entering_ack_irq(); |
0e078e2f | 914 | local_apic_timer_interrupt(); |
eddc0e92 | 915 | exiting_irq(); |
274cfe59 | 916 | |
0e078e2f TG |
917 | set_irq_regs(old_regs); |
918 | } | |
919 | ||
1d9090e2 | 920 | __visible void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs) |
cf910e83 SA |
921 | { |
922 | struct pt_regs *old_regs = set_irq_regs(regs); | |
923 | ||
0e078e2f | 924 | /* |
cf910e83 SA |
925 | * NOTE! We'd better ACK the irq immediately, |
926 | * because timer handling can be slow. | |
927 | * | |
0e078e2f TG |
928 | * update_process_times() expects us to have done irq_enter(). |
929 | * Besides, if we don't timer interrupts ignore the global | |
930 | * interrupt lock, which is the WrongThing (tm) to do. | |
931 | */ | |
cf910e83 SA |
932 | entering_ack_irq(); |
933 | trace_local_timer_entry(LOCAL_TIMER_VECTOR); | |
0e078e2f | 934 | local_apic_timer_interrupt(); |
cf910e83 SA |
935 | trace_local_timer_exit(LOCAL_TIMER_VECTOR); |
936 | exiting_irq(); | |
274cfe59 | 937 | |
0e078e2f TG |
938 | set_irq_regs(old_regs); |
939 | } | |
940 | ||
941 | int setup_profiling_timer(unsigned int multiplier) | |
942 | { | |
943 | return -EINVAL; | |
944 | } | |
945 | ||
0e078e2f TG |
946 | /* |
947 | * Local APIC start and shutdown | |
948 | */ | |
949 | ||
950 | /** | |
951 | * clear_local_APIC - shutdown the local APIC | |
952 | * | |
953 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
954 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
955 | * leftovers during boot. | |
956 | */ | |
957 | void clear_local_APIC(void) | |
958 | { | |
2584a82d | 959 | int maxlvt; |
0e078e2f TG |
960 | u32 v; |
961 | ||
d3432896 | 962 | /* APIC hasn't been mapped yet */ |
fc1edaf9 | 963 | if (!x2apic_mode && !apic_phys) |
d3432896 AK |
964 | return; |
965 | ||
966 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
967 | /* |
968 | * Masking an LVT entry can trigger a local APIC error | |
969 | * if the vector is zero. Mask LVTERR first to prevent this. | |
970 | */ | |
971 | if (maxlvt >= 3) { | |
972 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
973 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
974 | } | |
975 | /* | |
976 | * Careful: we have to set masks only first to deassert | |
977 | * any level-triggered sources. | |
978 | */ | |
979 | v = apic_read(APIC_LVTT); | |
980 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
981 | v = apic_read(APIC_LVT0); | |
982 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
983 | v = apic_read(APIC_LVT1); | |
984 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
985 | if (maxlvt >= 4) { | |
986 | v = apic_read(APIC_LVTPC); | |
987 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
988 | } | |
989 | ||
6764014b | 990 | /* lets not touch this if we didn't frob it */ |
4efc0670 | 991 | #ifdef CONFIG_X86_THERMAL_VECTOR |
6764014b CG |
992 | if (maxlvt >= 5) { |
993 | v = apic_read(APIC_LVTTHMR); | |
994 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
995 | } | |
996 | #endif | |
5ca8681c AK |
997 | #ifdef CONFIG_X86_MCE_INTEL |
998 | if (maxlvt >= 6) { | |
999 | v = apic_read(APIC_LVTCMCI); | |
1000 | if (!(v & APIC_LVT_MASKED)) | |
1001 | apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); | |
1002 | } | |
1003 | #endif | |
1004 | ||
0e078e2f TG |
1005 | /* |
1006 | * Clean APIC state for other OSs: | |
1007 | */ | |
1008 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
1009 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1010 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
1011 | if (maxlvt >= 3) | |
1012 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
1013 | if (maxlvt >= 4) | |
1014 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
1015 | |
1016 | /* Integrated APIC (!82489DX) ? */ | |
1017 | if (lapic_is_integrated()) { | |
1018 | if (maxlvt > 3) | |
1019 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
1020 | apic_write(APIC_ESR, 0); | |
1021 | apic_read(APIC_ESR); | |
1022 | } | |
0e078e2f TG |
1023 | } |
1024 | ||
1025 | /** | |
1026 | * disable_local_APIC - clear and disable the local APIC | |
1027 | */ | |
1028 | void disable_local_APIC(void) | |
1029 | { | |
1030 | unsigned int value; | |
1031 | ||
4a13ad0b | 1032 | /* APIC hasn't been mapped yet */ |
fd19dce7 | 1033 | if (!x2apic_mode && !apic_phys) |
4a13ad0b JB |
1034 | return; |
1035 | ||
0e078e2f TG |
1036 | clear_local_APIC(); |
1037 | ||
1038 | /* | |
1039 | * Disable APIC (implies clearing of registers | |
1040 | * for 82489DX!). | |
1041 | */ | |
1042 | value = apic_read(APIC_SPIV); | |
1043 | value &= ~APIC_SPIV_APIC_ENABLED; | |
1044 | apic_write(APIC_SPIV, value); | |
990b183e CG |
1045 | |
1046 | #ifdef CONFIG_X86_32 | |
1047 | /* | |
1048 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
1049 | * restore the disabled state. | |
1050 | */ | |
1051 | if (enabled_via_apicbase) { | |
1052 | unsigned int l, h; | |
1053 | ||
1054 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1055 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
1056 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1057 | } | |
1058 | #endif | |
0e078e2f TG |
1059 | } |
1060 | ||
fe4024dc CG |
1061 | /* |
1062 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
1063 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
1064 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
1065 | * for the case where Linux didn't enable the LAPIC. | |
1066 | */ | |
0e078e2f TG |
1067 | void lapic_shutdown(void) |
1068 | { | |
1069 | unsigned long flags; | |
1070 | ||
8312136f | 1071 | if (!cpu_has_apic && !apic_from_smp_config()) |
0e078e2f TG |
1072 | return; |
1073 | ||
1074 | local_irq_save(flags); | |
1075 | ||
fe4024dc CG |
1076 | #ifdef CONFIG_X86_32 |
1077 | if (!enabled_via_apicbase) | |
1078 | clear_local_APIC(); | |
1079 | else | |
1080 | #endif | |
1081 | disable_local_APIC(); | |
1082 | ||
0e078e2f TG |
1083 | |
1084 | local_irq_restore(flags); | |
1085 | } | |
1086 | ||
1087 | /* | |
1088 | * This is to verify that we're looking at a real local APIC. | |
1089 | * Check these against your board if the CPUs aren't getting | |
1090 | * started for no apparent reason. | |
1091 | */ | |
1092 | int __init verify_local_APIC(void) | |
1093 | { | |
1094 | unsigned int reg0, reg1; | |
1095 | ||
1096 | /* | |
1097 | * The version register is read-only in a real APIC. | |
1098 | */ | |
1099 | reg0 = apic_read(APIC_LVR); | |
1100 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
1101 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
1102 | reg1 = apic_read(APIC_LVR); | |
1103 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
1104 | ||
1105 | /* | |
1106 | * The two version reads above should print the same | |
1107 | * numbers. If the second one is different, then we | |
1108 | * poke at a non-APIC. | |
1109 | */ | |
1110 | if (reg1 != reg0) | |
1111 | return 0; | |
1112 | ||
1113 | /* | |
1114 | * Check if the version looks reasonably. | |
1115 | */ | |
1116 | reg1 = GET_APIC_VERSION(reg0); | |
1117 | if (reg1 == 0x00 || reg1 == 0xff) | |
1118 | return 0; | |
1119 | reg1 = lapic_get_maxlvt(); | |
1120 | if (reg1 < 0x02 || reg1 == 0xff) | |
1121 | return 0; | |
1122 | ||
1123 | /* | |
1124 | * The ID register is read/write in a real APIC. | |
1125 | */ | |
2d7a66d0 | 1126 | reg0 = apic_read(APIC_ID); |
0e078e2f | 1127 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
5b812727 | 1128 | apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); |
2d7a66d0 | 1129 | reg1 = apic_read(APIC_ID); |
0e078e2f TG |
1130 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
1131 | apic_write(APIC_ID, reg0); | |
5b812727 | 1132 | if (reg1 != (reg0 ^ apic->apic_id_mask)) |
0e078e2f TG |
1133 | return 0; |
1134 | ||
1135 | /* | |
1da177e4 LT |
1136 | * The next two are just to see if we have sane values. |
1137 | * They're only really relevant if we're in Virtual Wire | |
1138 | * compatibility mode, but most boxes are anymore. | |
1139 | */ | |
1140 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 1141 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
1142 | reg1 = apic_read(APIC_LVT1); |
1143 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
1144 | ||
1145 | return 1; | |
1146 | } | |
1147 | ||
0e078e2f TG |
1148 | /** |
1149 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
1150 | */ | |
1da177e4 LT |
1151 | void __init sync_Arb_IDs(void) |
1152 | { | |
296cb951 CG |
1153 | /* |
1154 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
1155 | * needed on AMD. | |
1156 | */ | |
1157 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
1158 | return; |
1159 | ||
1160 | /* | |
1161 | * Wait for idle. | |
1162 | */ | |
1163 | apic_wait_icr_idle(); | |
1164 | ||
1165 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
1166 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
1167 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
1168 | } |
1169 | ||
1da177e4 LT |
1170 | /* |
1171 | * An initial setup of the virtual wire mode. | |
1172 | */ | |
1173 | void __init init_bsp_APIC(void) | |
1174 | { | |
11a8e778 | 1175 | unsigned int value; |
1da177e4 LT |
1176 | |
1177 | /* | |
1178 | * Don't do the setup now if we have a SMP BIOS as the | |
1179 | * through-I/O-APIC virtual wire mode might be active. | |
1180 | */ | |
1181 | if (smp_found_config || !cpu_has_apic) | |
1182 | return; | |
1183 | ||
1da177e4 LT |
1184 | /* |
1185 | * Do not trust the local APIC being empty at bootup. | |
1186 | */ | |
1187 | clear_local_APIC(); | |
1188 | ||
1189 | /* | |
1190 | * Enable APIC. | |
1191 | */ | |
1192 | value = apic_read(APIC_SPIV); | |
1193 | value &= ~APIC_VECTOR_MASK; | |
1194 | value |= APIC_SPIV_APIC_ENABLED; | |
638c0411 CG |
1195 | |
1196 | #ifdef CONFIG_X86_32 | |
1197 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
1198 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
1199 | (boot_cpu_data.x86 == 15)) | |
1200 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1201 | else | |
1202 | #endif | |
1203 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 1204 | value |= SPURIOUS_APIC_VECTOR; |
11a8e778 | 1205 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1206 | |
1207 | /* | |
1208 | * Set up the virtual wire mode. | |
1209 | */ | |
11a8e778 | 1210 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 1211 | value = APIC_DM_NMI; |
638c0411 CG |
1212 | if (!lapic_is_integrated()) /* 82489DX */ |
1213 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1214 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
1215 | } |
1216 | ||
148f9bb8 | 1217 | static void lapic_setup_esr(void) |
c43da2f5 | 1218 | { |
9df08f10 CG |
1219 | unsigned int oldvalue, value, maxlvt; |
1220 | ||
1221 | if (!lapic_is_integrated()) { | |
ba21ebb6 | 1222 | pr_info("No ESR for 82489DX.\n"); |
9df08f10 CG |
1223 | return; |
1224 | } | |
c43da2f5 | 1225 | |
08125d3e | 1226 | if (apic->disable_esr) { |
c43da2f5 | 1227 | /* |
9df08f10 CG |
1228 | * Something untraceable is creating bad interrupts on |
1229 | * secondary quads ... for the moment, just leave the | |
1230 | * ESR disabled - we can't do anything useful with the | |
1231 | * errors anyway - mbligh | |
c43da2f5 | 1232 | */ |
ba21ebb6 | 1233 | pr_info("Leaving ESR disabled.\n"); |
9df08f10 | 1234 | return; |
c43da2f5 | 1235 | } |
9df08f10 CG |
1236 | |
1237 | maxlvt = lapic_get_maxlvt(); | |
1238 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1239 | apic_write(APIC_ESR, 0); | |
1240 | oldvalue = apic_read(APIC_ESR); | |
1241 | ||
1242 | /* enables sending errors */ | |
1243 | value = ERROR_APIC_VECTOR; | |
1244 | apic_write(APIC_LVTERR, value); | |
1245 | ||
1246 | /* | |
1247 | * spec says clear errors after enabling vector. | |
1248 | */ | |
1249 | if (maxlvt > 3) | |
1250 | apic_write(APIC_ESR, 0); | |
1251 | value = apic_read(APIC_ESR); | |
1252 | if (value != oldvalue) | |
1253 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
1254 | "vector: 0x%08x after: 0x%08x\n", | |
1255 | oldvalue, value); | |
c43da2f5 CG |
1256 | } |
1257 | ||
0e078e2f TG |
1258 | /** |
1259 | * setup_local_APIC - setup the local APIC | |
0aa002fe TH |
1260 | * |
1261 | * Used to setup local APIC while initializing BSP or bringin up APs. | |
1262 | * Always called with preemption disabled. | |
0e078e2f | 1263 | */ |
148f9bb8 | 1264 | void setup_local_APIC(void) |
1da177e4 | 1265 | { |
0aa002fe | 1266 | int cpu = smp_processor_id(); |
8c3ba8d0 KJ |
1267 | unsigned int value, queued; |
1268 | int i, j, acked = 0; | |
1269 | unsigned long long tsc = 0, ntsc; | |
b47dcbdc | 1270 | long long max_loops = cpu_khz ? cpu_khz : 1000000; |
8c3ba8d0 KJ |
1271 | |
1272 | if (cpu_has_tsc) | |
1273 | rdtscll(tsc); | |
1da177e4 | 1274 | |
f1182638 | 1275 | if (disable_apic) { |
7167d08e | 1276 | disable_ioapic_support(); |
f1182638 JB |
1277 | return; |
1278 | } | |
1279 | ||
89c38c28 CG |
1280 | #ifdef CONFIG_X86_32 |
1281 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
08125d3e | 1282 | if (lapic_is_integrated() && apic->disable_esr) { |
89c38c28 CG |
1283 | apic_write(APIC_ESR, 0); |
1284 | apic_write(APIC_ESR, 0); | |
1285 | apic_write(APIC_ESR, 0); | |
1286 | apic_write(APIC_ESR, 0); | |
1287 | } | |
1288 | #endif | |
cdd6c482 | 1289 | perf_events_lapic_init(); |
89c38c28 | 1290 | |
1da177e4 LT |
1291 | /* |
1292 | * Double-check whether this APIC is really registered. | |
1293 | * This is meaningless in clustered apic mode, so we skip it. | |
1294 | */ | |
c2777f98 | 1295 | BUG_ON(!apic->apic_id_registered()); |
1da177e4 LT |
1296 | |
1297 | /* | |
1298 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1299 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
1300 | * document number 292116). So here it goes... | |
1301 | */ | |
a5c43296 | 1302 | apic->init_apic_ldr(); |
1da177e4 | 1303 | |
6f802c4b TH |
1304 | #ifdef CONFIG_X86_32 |
1305 | /* | |
acb8bc09 TH |
1306 | * APIC LDR is initialized. If logical_apicid mapping was |
1307 | * initialized during get_smp_config(), make sure it matches the | |
1308 | * actual value. | |
6f802c4b | 1309 | */ |
acb8bc09 TH |
1310 | i = early_per_cpu(x86_cpu_to_logical_apicid, cpu); |
1311 | WARN_ON(i != BAD_APICID && i != logical_smp_processor_id()); | |
1312 | /* always use the value from LDR */ | |
6f802c4b TH |
1313 | early_per_cpu(x86_cpu_to_logical_apicid, cpu) = |
1314 | logical_smp_processor_id(); | |
1315 | #endif | |
1316 | ||
1da177e4 LT |
1317 | /* |
1318 | * Set Task Priority to 'accept all'. We never change this | |
1319 | * later on. | |
1320 | */ | |
1321 | value = apic_read(APIC_TASKPRI); | |
1322 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 1323 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1324 | |
da7ed9f9 VG |
1325 | /* |
1326 | * After a crash, we no longer service the interrupts and a pending | |
1327 | * interrupt from previous kernel might still have ISR bit set. | |
1328 | * | |
1329 | * Most probably by now CPU has serviced that pending interrupt and | |
1330 | * it might not have done the ack_APIC_irq() because it thought, | |
1331 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1332 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1333 | * the interrupt. Hence a vector might get locked. It was noticed | |
1334 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1335 | */ | |
8c3ba8d0 KJ |
1336 | do { |
1337 | queued = 0; | |
1338 | for (i = APIC_ISR_NR - 1; i >= 0; i--) | |
1339 | queued |= apic_read(APIC_IRR + i*0x10); | |
1340 | ||
1341 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1342 | value = apic_read(APIC_ISR + i*0x10); | |
1343 | for (j = 31; j >= 0; j--) { | |
1344 | if (value & (1<<j)) { | |
1345 | ack_APIC_irq(); | |
1346 | acked++; | |
1347 | } | |
1348 | } | |
da7ed9f9 | 1349 | } |
8c3ba8d0 KJ |
1350 | if (acked > 256) { |
1351 | printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", | |
1352 | acked); | |
1353 | break; | |
1354 | } | |
42fa4250 | 1355 | if (queued) { |
b47dcbdc | 1356 | if (cpu_has_tsc && cpu_khz) { |
42fa4250 SF |
1357 | rdtscll(ntsc); |
1358 | max_loops = (cpu_khz << 10) - (ntsc - tsc); | |
1359 | } else | |
1360 | max_loops--; | |
1361 | } | |
8c3ba8d0 KJ |
1362 | } while (queued && max_loops > 0); |
1363 | WARN_ON(max_loops <= 0); | |
da7ed9f9 | 1364 | |
1da177e4 LT |
1365 | /* |
1366 | * Now that we are all set up, enable the APIC | |
1367 | */ | |
1368 | value = apic_read(APIC_SPIV); | |
1369 | value &= ~APIC_VECTOR_MASK; | |
1370 | /* | |
1371 | * Enable APIC | |
1372 | */ | |
1373 | value |= APIC_SPIV_APIC_ENABLED; | |
1374 | ||
89c38c28 CG |
1375 | #ifdef CONFIG_X86_32 |
1376 | /* | |
1377 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1378 | * certain networking cards. If high frequency interrupts are | |
1379 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1380 | * entry is masked/unmasked at a high rate as well then sooner or | |
1381 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1382 | * from the device. If focus CPU is disabled then the hang goes | |
1383 | * away, oh well :-( | |
1384 | * | |
1385 | * [ This bug can be reproduced easily with a level-triggered | |
1386 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1387 | * BX chipset. ] | |
1388 | */ | |
1389 | /* | |
1390 | * Actually disabling the focus CPU check just makes the hang less | |
1391 | * frequent as it makes the interrupt distributon model be more | |
1392 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1393 | * See also the comment in end_level_ioapic_irq(). --macro | |
1394 | */ | |
1395 | ||
1396 | /* | |
1397 | * - enable focus processor (bit==0) | |
1398 | * - 64bit mode always use processor focus | |
1399 | * so no need to set it | |
1400 | */ | |
1401 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1402 | #endif | |
3f14c746 | 1403 | |
1da177e4 LT |
1404 | /* |
1405 | * Set spurious IRQ vector | |
1406 | */ | |
1407 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 1408 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1409 | |
1410 | /* | |
1411 | * Set up LVT0, LVT1: | |
1412 | * | |
1413 | * set up through-local-APIC on the BP's LINT0. This is not | |
1414 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
1415 | * we delegate interrupts to the 8259A. | |
1416 | */ | |
1417 | /* | |
1418 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1419 | */ | |
1420 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
0aa002fe | 1421 | if (!cpu && (pic_mode || !value)) { |
1da177e4 | 1422 | value = APIC_DM_EXTINT; |
0aa002fe | 1423 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); |
1da177e4 LT |
1424 | } else { |
1425 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
0aa002fe | 1426 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); |
1da177e4 | 1427 | } |
11a8e778 | 1428 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1429 | |
1430 | /* | |
1431 | * only the BP should see the LINT1 NMI signal, obviously. | |
1432 | */ | |
0aa002fe | 1433 | if (!cpu) |
1da177e4 LT |
1434 | value = APIC_DM_NMI; |
1435 | else | |
1436 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
89c38c28 CG |
1437 | if (!lapic_is_integrated()) /* 82489DX */ |
1438 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1439 | apic_write(APIC_LVT1, value); |
89c38c28 | 1440 | |
be71b855 AK |
1441 | #ifdef CONFIG_X86_MCE_INTEL |
1442 | /* Recheck CMCI information after local APIC is up on CPU #0 */ | |
0aa002fe | 1443 | if (!cpu) |
be71b855 AK |
1444 | cmci_recheck(); |
1445 | #endif | |
739f33b3 | 1446 | } |
1da177e4 | 1447 | |
148f9bb8 | 1448 | void end_local_APIC_setup(void) |
739f33b3 AK |
1449 | { |
1450 | lapic_setup_esr(); | |
fa6b95fc CG |
1451 | |
1452 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1453 | { |
1454 | unsigned int value; | |
1455 | /* Disable the local apic timer */ | |
1456 | value = apic_read(APIC_LVTT); | |
1457 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1458 | apic_write(APIC_LVTT, value); | |
1459 | } | |
fa6b95fc CG |
1460 | #endif |
1461 | ||
0e078e2f | 1462 | apic_pm_activate(); |
2fb270f3 JB |
1463 | } |
1464 | ||
1465 | void __init bsp_end_local_APIC_setup(void) | |
1466 | { | |
1467 | end_local_APIC_setup(); | |
7f7fbf45 KK |
1468 | |
1469 | /* | |
1470 | * Now that local APIC setup is completed for BP, configure the fault | |
1471 | * handling for interrupt remapping. | |
1472 | */ | |
70733e0c | 1473 | irq_remap_enable_fault_handling(); |
7f7fbf45 | 1474 | |
1da177e4 | 1475 | } |
1da177e4 | 1476 | |
06cd9a7d | 1477 | #ifdef CONFIG_X86_X2APIC |
bfb05070 | 1478 | int x2apic_mode; |
12e189d3 TG |
1479 | |
1480 | enum { | |
1481 | X2APIC_OFF, | |
1482 | X2APIC_ON, | |
1483 | X2APIC_DISABLED, | |
1484 | }; | |
1485 | static int x2apic_state; | |
1486 | ||
44e25ff9 TG |
1487 | static inline void __x2apic_disable(void) |
1488 | { | |
1489 | u64 msr; | |
1490 | ||
659006bf TG |
1491 | if (cpu_has_apic) |
1492 | return; | |
1493 | ||
44e25ff9 TG |
1494 | rdmsrl(MSR_IA32_APICBASE, msr); |
1495 | if (!(msr & X2APIC_ENABLE)) | |
1496 | return; | |
1497 | /* Disable xapic and x2apic first and then reenable xapic mode */ | |
1498 | wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); | |
1499 | wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); | |
1500 | printk_once(KERN_INFO "x2apic disabled\n"); | |
1501 | } | |
1502 | ||
659006bf TG |
1503 | static inline void __x2apic_enable(void) |
1504 | { | |
1505 | u64 msr; | |
1506 | ||
1507 | rdmsrl(MSR_IA32_APICBASE, msr); | |
1508 | if (msr & X2APIC_ENABLE) | |
1509 | return; | |
1510 | wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); | |
1511 | printk_once(KERN_INFO "x2apic enabled\n"); | |
1512 | } | |
1513 | ||
bfb05070 TG |
1514 | static int __init setup_nox2apic(char *str) |
1515 | { | |
1516 | if (x2apic_enabled()) { | |
1517 | int apicid = native_apic_msr_read(APIC_ID); | |
1518 | ||
1519 | if (apicid >= 255) { | |
1520 | pr_warning("Apicid: %08x, cannot enforce nox2apic\n", | |
1521 | apicid); | |
1522 | return 0; | |
1523 | } | |
44e25ff9 TG |
1524 | pr_warning("x2apic already enabled.\n"); |
1525 | __x2apic_disable(); | |
1526 | } | |
1527 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); | |
12e189d3 | 1528 | x2apic_state = X2APIC_DISABLED; |
44e25ff9 | 1529 | x2apic_mode = 0; |
bfb05070 TG |
1530 | return 0; |
1531 | } | |
1532 | early_param("nox2apic", setup_nox2apic); | |
1533 | ||
659006bf TG |
1534 | /* Called from cpu_init() to enable x2apic on (secondary) cpus */ |
1535 | void x2apic_setup(void) | |
1536 | { | |
1537 | /* | |
1538 | * If x2apic is not in ON state, disable it if already enabled | |
1539 | * from BIOS. | |
1540 | */ | |
1541 | if (x2apic_state != X2APIC_ON) { | |
1542 | __x2apic_disable(); | |
1543 | return; | |
1544 | } | |
1545 | __x2apic_enable(); | |
1546 | } | |
1547 | ||
44e25ff9 | 1548 | static __init void x2apic_disable(void) |
fb209bd8 | 1549 | { |
6d2d49d2 | 1550 | u32 x2apic_id; |
fb209bd8 | 1551 | |
6d2d49d2 TG |
1552 | if (x2apic_state != X2APIC_ON) |
1553 | goto out; | |
fb209bd8 | 1554 | |
6d2d49d2 TG |
1555 | x2apic_id = read_apic_id(); |
1556 | if (x2apic_id >= 255) | |
1557 | panic("Cannot disable x2apic, id: %08x\n", x2apic_id); | |
9aa16365 | 1558 | |
6d2d49d2 TG |
1559 | __x2apic_disable(); |
1560 | register_lapic_address(mp_lapic_addr); | |
1561 | out: | |
12e189d3 | 1562 | x2apic_state = X2APIC_DISABLED; |
6d2d49d2 | 1563 | x2apic_mode = 0; |
fb209bd8 YL |
1564 | } |
1565 | ||
659006bf | 1566 | static __init void x2apic_enable(void) |
6e1cb38a | 1567 | { |
659006bf | 1568 | if (x2apic_state != X2APIC_OFF) |
06cd9a7d YL |
1569 | return; |
1570 | ||
659006bf | 1571 | x2apic_mode = 1; |
12e189d3 | 1572 | x2apic_state = X2APIC_ON; |
659006bf | 1573 | __x2apic_enable(); |
6e1cb38a | 1574 | } |
d524165c | 1575 | |
62e61633 | 1576 | static __init void try_to_enable_x2apic(int remap_mode) |
07806c50 | 1577 | { |
659006bf | 1578 | if (x2apic_state == X2APIC_DISABLED) |
07806c50 JL |
1579 | return; |
1580 | ||
62e61633 | 1581 | if (remap_mode != IRQ_REMAP_X2APIC_MODE) { |
07806c50 JL |
1582 | /* IR is required if there is APIC ID > 255 even when running |
1583 | * under KVM | |
1584 | */ | |
1585 | if (max_physical_apicid > 255 || | |
5fcee53c JL |
1586 | (IS_ENABLED(CONFIG_HYPERVISOR_GUEST) && |
1587 | !hypervisor_x2apic_available())) { | |
62e61633 | 1588 | pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); |
44e25ff9 | 1589 | x2apic_disable(); |
07806c50 JL |
1590 | return; |
1591 | } | |
1592 | ||
1593 | /* | |
1594 | * without IR all CPUs can be addressed by IOAPIC/MSI | |
1595 | * only in physical mode | |
1596 | */ | |
55eae7de | 1597 | x2apic_phys = 1; |
07806c50 | 1598 | } |
659006bf | 1599 | x2apic_enable(); |
55eae7de TG |
1600 | } |
1601 | ||
1602 | void __init check_x2apic(void) | |
1603 | { | |
1604 | if (x2apic_enabled()) { | |
1605 | pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); | |
1606 | x2apic_mode = 1; | |
12e189d3 TG |
1607 | x2apic_state = X2APIC_ON; |
1608 | } else if (!cpu_has_x2apic) { | |
1609 | x2apic_state = X2APIC_DISABLED; | |
55eae7de TG |
1610 | } |
1611 | } | |
1612 | #else /* CONFIG_X86_X2APIC */ | |
1613 | static int __init validate_x2apic(void) | |
1614 | { | |
1615 | if (!apic_is_x2apic_enabled()) | |
1616 | return 0; | |
1617 | /* | |
1618 | * Checkme: Can we simply turn off x2apic here instead of panic? | |
1619 | */ | |
1620 | panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); | |
1621 | } | |
1622 | early_initcall(validate_x2apic); | |
1623 | ||
62e61633 | 1624 | static inline void try_to_enable_x2apic(int remap_mode) { } |
659006bf | 1625 | static inline void __x2apic_enable(void) { } |
55eae7de TG |
1626 | #endif /* !CONFIG_X86_X2APIC */ |
1627 | ||
1628 | static int __init try_to_enable_IR(void) | |
1629 | { | |
1630 | #ifdef CONFIG_X86_IO_APIC | |
1631 | if (!x2apic_enabled() && skip_ioapic_setup) { | |
1632 | pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); | |
1633 | return -1; | |
1634 | } | |
ce69a784 | 1635 | #endif |
55eae7de | 1636 | return irq_remapping_enable(); |
ce69a784 GN |
1637 | } |
1638 | ||
1639 | void __init enable_IR_x2apic(void) | |
1640 | { | |
1641 | unsigned long flags; | |
07806c50 | 1642 | int ret, ir_stat; |
b7f42ab2 | 1643 | |
07806c50 JL |
1644 | ir_stat = irq_remapping_prepare(); |
1645 | if (ir_stat < 0 && !x2apic_supported()) | |
e670761f | 1646 | return; |
ce69a784 | 1647 | |
31dce14a | 1648 | ret = save_ioapic_entries(); |
5ffa4eb2 | 1649 | if (ret) { |
ba21ebb6 | 1650 | pr_info("Saving IO-APIC state failed: %d\n", ret); |
fb209bd8 | 1651 | return; |
5ffa4eb2 | 1652 | } |
6e1cb38a | 1653 | |
05c3dc2c | 1654 | local_irq_save(flags); |
b81bb373 | 1655 | legacy_pic->mask_all(); |
31dce14a | 1656 | mask_ioapic_entries(); |
05c3dc2c | 1657 | |
07806c50 JL |
1658 | /* If irq_remapping_prepare() succeded, try to enable it */ |
1659 | if (ir_stat >= 0) | |
1660 | ir_stat = try_to_enable_IR(); | |
1661 | /* ir_stat contains the remap mode or an error code */ | |
1662 | try_to_enable_x2apic(ir_stat); | |
a31bc327 | 1663 | |
07806c50 | 1664 | if (ir_stat < 0) |
31dce14a | 1665 | restore_ioapic_entries(); |
b81bb373 | 1666 | legacy_pic->restore_mask(); |
6e1cb38a | 1667 | local_irq_restore(flags); |
6e1cb38a | 1668 | } |
93758238 | 1669 | |
be7a656f | 1670 | #ifdef CONFIG_X86_64 |
1da177e4 LT |
1671 | /* |
1672 | * Detect and enable local APICs on non-SMP boards. | |
1673 | * Original code written by Keir Fraser. | |
1674 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1675 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1676 | */ |
0e078e2f | 1677 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1678 | { |
1679 | if (!cpu_has_apic) { | |
ba21ebb6 | 1680 | pr_info("No local APIC present\n"); |
1da177e4 LT |
1681 | return -1; |
1682 | } | |
1683 | ||
1684 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1da177e4 LT |
1685 | return 0; |
1686 | } | |
be7a656f | 1687 | #else |
5a7ae78f | 1688 | |
25874a29 | 1689 | static int __init apic_verify(void) |
5a7ae78f TG |
1690 | { |
1691 | u32 features, h, l; | |
1692 | ||
1693 | /* | |
1694 | * The APIC feature bit should now be enabled | |
1695 | * in `cpuid' | |
1696 | */ | |
1697 | features = cpuid_edx(1); | |
1698 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
1699 | pr_warning("Could not enable APIC!\n"); | |
1700 | return -1; | |
1701 | } | |
1702 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | |
1703 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1704 | ||
1705 | /* The BIOS may have set up the APIC at some other address */ | |
cbf2829b BD |
1706 | if (boot_cpu_data.x86 >= 6) { |
1707 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1708 | if (l & MSR_IA32_APICBASE_ENABLE) | |
1709 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1710 | } | |
5a7ae78f TG |
1711 | |
1712 | pr_info("Found and enabled local APIC!\n"); | |
1713 | return 0; | |
1714 | } | |
1715 | ||
25874a29 | 1716 | int __init apic_force_enable(unsigned long addr) |
5a7ae78f TG |
1717 | { |
1718 | u32 h, l; | |
1719 | ||
1720 | if (disable_apic) | |
1721 | return -1; | |
1722 | ||
1723 | /* | |
1724 | * Some BIOSes disable the local APIC in the APIC_BASE | |
1725 | * MSR. This can only be done in software for Intel P6 or later | |
1726 | * and AMD K7 (Model > 1) or later. | |
1727 | */ | |
cbf2829b BD |
1728 | if (boot_cpu_data.x86 >= 6) { |
1729 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1730 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
1731 | pr_info("Local APIC disabled by BIOS -- reenabling.\n"); | |
1732 | l &= ~MSR_IA32_APICBASE_BASE; | |
1733 | l |= MSR_IA32_APICBASE_ENABLE | addr; | |
1734 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1735 | enabled_via_apicbase = 1; | |
1736 | } | |
5a7ae78f TG |
1737 | } |
1738 | return apic_verify(); | |
1739 | } | |
1740 | ||
be7a656f YL |
1741 | /* |
1742 | * Detect and initialize APIC | |
1743 | */ | |
1744 | static int __init detect_init_APIC(void) | |
1745 | { | |
be7a656f YL |
1746 | /* Disabled by kernel option? */ |
1747 | if (disable_apic) | |
1748 | return -1; | |
1749 | ||
1750 | switch (boot_cpu_data.x86_vendor) { | |
1751 | case X86_VENDOR_AMD: | |
1752 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
85877061 | 1753 | (boot_cpu_data.x86 >= 15)) |
be7a656f YL |
1754 | break; |
1755 | goto no_apic; | |
1756 | case X86_VENDOR_INTEL: | |
1757 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
1758 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
1759 | break; | |
1760 | goto no_apic; | |
1761 | default: | |
1762 | goto no_apic; | |
1763 | } | |
1764 | ||
1765 | if (!cpu_has_apic) { | |
1766 | /* | |
1767 | * Over-ride BIOS and try to enable the local APIC only if | |
1768 | * "lapic" specified. | |
1769 | */ | |
1770 | if (!force_enable_local_apic) { | |
ba21ebb6 CG |
1771 | pr_info("Local APIC disabled by BIOS -- " |
1772 | "you can enable it with \"lapic\"\n"); | |
be7a656f YL |
1773 | return -1; |
1774 | } | |
a906fdaa | 1775 | if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) |
5a7ae78f TG |
1776 | return -1; |
1777 | } else { | |
1778 | if (apic_verify()) | |
1779 | return -1; | |
be7a656f | 1780 | } |
be7a656f YL |
1781 | |
1782 | apic_pm_activate(); | |
1783 | ||
1784 | return 0; | |
1785 | ||
1786 | no_apic: | |
ba21ebb6 | 1787 | pr_info("No local APIC present or hardware disabled\n"); |
be7a656f YL |
1788 | return -1; |
1789 | } | |
1790 | #endif | |
1da177e4 | 1791 | |
0e078e2f TG |
1792 | /** |
1793 | * init_apic_mappings - initialize APIC mappings | |
1794 | */ | |
1da177e4 LT |
1795 | void __init init_apic_mappings(void) |
1796 | { | |
4401da61 YL |
1797 | unsigned int new_apicid; |
1798 | ||
fc1edaf9 | 1799 | if (x2apic_mode) { |
4c9961d5 | 1800 | boot_cpu_physical_apicid = read_apic_id(); |
6e1cb38a SS |
1801 | return; |
1802 | } | |
1803 | ||
4797f6b0 | 1804 | /* If no local APIC can be found return early */ |
1da177e4 | 1805 | if (!smp_found_config && detect_init_APIC()) { |
4797f6b0 YL |
1806 | /* lets NOP'ify apic operations */ |
1807 | pr_info("APIC: disable apic facility\n"); | |
1808 | apic_disable(); | |
1809 | } else { | |
1da177e4 LT |
1810 | apic_phys = mp_lapic_addr; |
1811 | ||
4797f6b0 YL |
1812 | /* |
1813 | * acpi lapic path already maps that address in | |
1814 | * acpi_register_lapic_address() | |
1815 | */ | |
5989cd6a | 1816 | if (!acpi_lapic && !smp_found_config) |
326a2e6b | 1817 | register_lapic_address(apic_phys); |
cec6be6d | 1818 | } |
1da177e4 LT |
1819 | |
1820 | /* | |
1821 | * Fetch the APIC ID of the BSP in case we have a | |
1822 | * default configuration (or the MP table is broken). | |
1823 | */ | |
4401da61 YL |
1824 | new_apicid = read_apic_id(); |
1825 | if (boot_cpu_physical_apicid != new_apicid) { | |
1826 | boot_cpu_physical_apicid = new_apicid; | |
103428e5 CG |
1827 | /* |
1828 | * yeah -- we lie about apic_version | |
1829 | * in case if apic was disabled via boot option | |
1830 | * but it's not a problem for SMP compiled kernel | |
1831 | * since smp_sanity_check is prepared for such a case | |
1832 | * and disable smp mode | |
1833 | */ | |
4401da61 YL |
1834 | apic_version[new_apicid] = |
1835 | GET_APIC_VERSION(apic_read(APIC_LVR)); | |
08306ce6 | 1836 | } |
1da177e4 LT |
1837 | } |
1838 | ||
c0104d38 YL |
1839 | void __init register_lapic_address(unsigned long address) |
1840 | { | |
1841 | mp_lapic_addr = address; | |
1842 | ||
0450193b YL |
1843 | if (!x2apic_mode) { |
1844 | set_fixmap_nocache(FIX_APIC_BASE, address); | |
1845 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", | |
1846 | APIC_BASE, mp_lapic_addr); | |
1847 | } | |
c0104d38 YL |
1848 | if (boot_cpu_physical_apicid == -1U) { |
1849 | boot_cpu_physical_apicid = read_apic_id(); | |
1850 | apic_version[boot_cpu_physical_apicid] = | |
1851 | GET_APIC_VERSION(apic_read(APIC_LVR)); | |
1852 | } | |
1853 | } | |
1854 | ||
1da177e4 | 1855 | /* |
0e078e2f TG |
1856 | * This initializes the IO-APIC and APIC hardware if this is |
1857 | * a UP kernel. | |
1da177e4 | 1858 | */ |
56d91f13 | 1859 | int apic_version[MAX_LOCAL_APIC]; |
1b313f4a | 1860 | |
0e078e2f | 1861 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1862 | { |
0e078e2f | 1863 | if (disable_apic) { |
ba21ebb6 | 1864 | pr_info("Apic disabled\n"); |
0e078e2f TG |
1865 | return -1; |
1866 | } | |
f1182638 | 1867 | #ifdef CONFIG_X86_64 |
0e078e2f TG |
1868 | if (!cpu_has_apic) { |
1869 | disable_apic = 1; | |
ba21ebb6 | 1870 | pr_info("Apic disabled by BIOS\n"); |
0e078e2f TG |
1871 | return -1; |
1872 | } | |
fa2bd35a YL |
1873 | #else |
1874 | if (!smp_found_config && !cpu_has_apic) | |
1875 | return -1; | |
1876 | ||
1877 | /* | |
1878 | * Complain if the BIOS pretends there is one. | |
1879 | */ | |
1880 | if (!cpu_has_apic && | |
1881 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
ba21ebb6 CG |
1882 | pr_err("BIOS bug, local APIC 0x%x not detected!...\n", |
1883 | boot_cpu_physical_apicid); | |
fa2bd35a YL |
1884 | return -1; |
1885 | } | |
1886 | #endif | |
1887 | ||
72ce0165 | 1888 | default_setup_apic_routing(); |
6e1cb38a | 1889 | |
0e078e2f | 1890 | verify_local_APIC(); |
b5841765 GC |
1891 | connect_bsp_APIC(); |
1892 | ||
fa2bd35a | 1893 | #ifdef CONFIG_X86_64 |
c70dcb74 | 1894 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
fa2bd35a YL |
1895 | #else |
1896 | /* | |
1897 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1898 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1899 | * might be zero if read from MP tables. Get it from LAPIC. | |
1900 | */ | |
1901 | # ifdef CONFIG_CRASH_DUMP | |
1902 | boot_cpu_physical_apicid = read_apic_id(); | |
1903 | # endif | |
1904 | #endif | |
1905 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); | |
0e078e2f | 1906 | setup_local_APIC(); |
1da177e4 | 1907 | |
88d0f550 | 1908 | #ifdef CONFIG_X86_IO_APIC |
739f33b3 AK |
1909 | /* |
1910 | * Now enable IO-APICs, actually call clear_IO_APIC | |
98c061b6 | 1911 | * We need clear_IO_APIC before enabling error vector |
739f33b3 AK |
1912 | */ |
1913 | if (!skip_ioapic_setup && nr_ioapics) | |
1914 | enable_IO_APIC(); | |
fa2bd35a | 1915 | #endif |
739f33b3 | 1916 | |
2fb270f3 | 1917 | bsp_end_local_APIC_setup(); |
739f33b3 | 1918 | |
fa2bd35a | 1919 | #ifdef CONFIG_X86_IO_APIC |
0e078e2f TG |
1920 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
1921 | setup_IO_APIC(); | |
98c061b6 | 1922 | else { |
0e078e2f | 1923 | nr_ioapics = 0; |
98c061b6 | 1924 | } |
fa2bd35a YL |
1925 | #endif |
1926 | ||
736decac | 1927 | x86_init.timers.setup_percpu_clockev(); |
0e078e2f | 1928 | return 0; |
1da177e4 LT |
1929 | } |
1930 | ||
1931 | /* | |
0e078e2f | 1932 | * Local APIC interrupts |
1da177e4 LT |
1933 | */ |
1934 | ||
0e078e2f TG |
1935 | /* |
1936 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1937 | */ | |
2414e021 | 1938 | static inline void __smp_spurious_interrupt(u8 vector) |
1da177e4 | 1939 | { |
dc1528dd YL |
1940 | u32 v; |
1941 | ||
1da177e4 | 1942 | /* |
0e078e2f TG |
1943 | * Check if this really is a spurious interrupt and ACK it |
1944 | * if it is a vectored one. Just in case... | |
1945 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1946 | */ |
2414e021 JB |
1947 | v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); |
1948 | if (v & (1 << (vector & 0x1f))) | |
0e078e2f | 1949 | ack_APIC_irq(); |
c4d58cbd | 1950 | |
915b0d01 HS |
1951 | inc_irq_stat(irq_spurious_count); |
1952 | ||
dc1528dd | 1953 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ |
2414e021 JB |
1954 | pr_info("spurious APIC interrupt through vector %02x on CPU#%d, " |
1955 | "should never happen.\n", vector, smp_processor_id()); | |
eddc0e92 SA |
1956 | } |
1957 | ||
1d9090e2 | 1958 | __visible void smp_spurious_interrupt(struct pt_regs *regs) |
eddc0e92 SA |
1959 | { |
1960 | entering_irq(); | |
2414e021 | 1961 | __smp_spurious_interrupt(~regs->orig_ax); |
eddc0e92 | 1962 | exiting_irq(); |
0e078e2f | 1963 | } |
1da177e4 | 1964 | |
1d9090e2 | 1965 | __visible void smp_trace_spurious_interrupt(struct pt_regs *regs) |
cf910e83 | 1966 | { |
2414e021 JB |
1967 | u8 vector = ~regs->orig_ax; |
1968 | ||
cf910e83 | 1969 | entering_irq(); |
2414e021 JB |
1970 | trace_spurious_apic_entry(vector); |
1971 | __smp_spurious_interrupt(vector); | |
1972 | trace_spurious_apic_exit(vector); | |
cf910e83 | 1973 | exiting_irq(); |
0e078e2f | 1974 | } |
1da177e4 | 1975 | |
0e078e2f TG |
1976 | /* |
1977 | * This interrupt should never happen with our APIC/SMP architecture | |
1978 | */ | |
eddc0e92 | 1979 | static inline void __smp_error_interrupt(struct pt_regs *regs) |
0e078e2f | 1980 | { |
60283df7 | 1981 | u32 v; |
2b398bd9 YS |
1982 | u32 i = 0; |
1983 | static const char * const error_interrupt_reason[] = { | |
1984 | "Send CS error", /* APIC Error Bit 0 */ | |
1985 | "Receive CS error", /* APIC Error Bit 1 */ | |
1986 | "Send accept error", /* APIC Error Bit 2 */ | |
1987 | "Receive accept error", /* APIC Error Bit 3 */ | |
1988 | "Redirectable IPI", /* APIC Error Bit 4 */ | |
1989 | "Send illegal vector", /* APIC Error Bit 5 */ | |
1990 | "Received illegal vector", /* APIC Error Bit 6 */ | |
1991 | "Illegal register address", /* APIC Error Bit 7 */ | |
1992 | }; | |
1da177e4 | 1993 | |
0e078e2f | 1994 | /* First tickle the hardware, only then report what went on. -- REW */ |
023de4a0 MR |
1995 | if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ |
1996 | apic_write(APIC_ESR, 0); | |
60283df7 | 1997 | v = apic_read(APIC_ESR); |
0e078e2f TG |
1998 | ack_APIC_irq(); |
1999 | atomic_inc(&irq_err_count); | |
ba7eda4c | 2000 | |
60283df7 RW |
2001 | apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", |
2002 | smp_processor_id(), v); | |
2b398bd9 | 2003 | |
60283df7 RW |
2004 | v &= 0xff; |
2005 | while (v) { | |
2006 | if (v & 0x1) | |
2b398bd9 YS |
2007 | apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); |
2008 | i++; | |
60283df7 | 2009 | v >>= 1; |
4b8073e4 | 2010 | } |
2b398bd9 YS |
2011 | |
2012 | apic_printk(APIC_DEBUG, KERN_CONT "\n"); | |
2013 | ||
eddc0e92 SA |
2014 | } |
2015 | ||
1d9090e2 | 2016 | __visible void smp_error_interrupt(struct pt_regs *regs) |
eddc0e92 SA |
2017 | { |
2018 | entering_irq(); | |
2019 | __smp_error_interrupt(regs); | |
2020 | exiting_irq(); | |
1da177e4 LT |
2021 | } |
2022 | ||
1d9090e2 | 2023 | __visible void smp_trace_error_interrupt(struct pt_regs *regs) |
cf910e83 SA |
2024 | { |
2025 | entering_irq(); | |
2026 | trace_error_apic_entry(ERROR_APIC_VECTOR); | |
2027 | __smp_error_interrupt(regs); | |
2028 | trace_error_apic_exit(ERROR_APIC_VECTOR); | |
2029 | exiting_irq(); | |
1da177e4 LT |
2030 | } |
2031 | ||
b5841765 | 2032 | /** |
36c9d674 CG |
2033 | * connect_bsp_APIC - attach the APIC to the interrupt system |
2034 | */ | |
b5841765 GC |
2035 | void __init connect_bsp_APIC(void) |
2036 | { | |
36c9d674 CG |
2037 | #ifdef CONFIG_X86_32 |
2038 | if (pic_mode) { | |
2039 | /* | |
2040 | * Do not trust the local APIC being empty at bootup. | |
2041 | */ | |
2042 | clear_local_APIC(); | |
2043 | /* | |
2044 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
2045 | * local APIC to INT and NMI lines. | |
2046 | */ | |
2047 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
2048 | "enabling APIC mode.\n"); | |
c0eaa453 | 2049 | imcr_pic_to_apic(); |
36c9d674 CG |
2050 | } |
2051 | #endif | |
b5841765 GC |
2052 | } |
2053 | ||
274cfe59 CG |
2054 | /** |
2055 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
2056 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
2057 | * | |
2058 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
2059 | * APIC is disabled. | |
2060 | */ | |
0e078e2f | 2061 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 2062 | { |
1b4ee4e4 CG |
2063 | unsigned int value; |
2064 | ||
c177b0bc CG |
2065 | #ifdef CONFIG_X86_32 |
2066 | if (pic_mode) { | |
2067 | /* | |
2068 | * Put the board back into PIC mode (has an effect only on | |
2069 | * certain older boards). Note that APIC interrupts, including | |
2070 | * IPIs, won't work beyond this point! The only exception are | |
2071 | * INIT IPIs. | |
2072 | */ | |
2073 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
2074 | "entering PIC mode.\n"); | |
c0eaa453 | 2075 | imcr_apic_to_pic(); |
c177b0bc CG |
2076 | return; |
2077 | } | |
2078 | #endif | |
2079 | ||
0e078e2f | 2080 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 2081 | |
0e078e2f TG |
2082 | /* For the spurious interrupt use vector F, and enable it */ |
2083 | value = apic_read(APIC_SPIV); | |
2084 | value &= ~APIC_VECTOR_MASK; | |
2085 | value |= APIC_SPIV_APIC_ENABLED; | |
2086 | value |= 0xf; | |
2087 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 2088 | |
0e078e2f TG |
2089 | if (!virt_wire_setup) { |
2090 | /* | |
2091 | * For LVT0 make it edge triggered, active high, | |
2092 | * external and enabled | |
2093 | */ | |
2094 | value = apic_read(APIC_LVT0); | |
2095 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
2096 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
2097 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
2098 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
2099 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
2100 | apic_write(APIC_LVT0, value); | |
2101 | } else { | |
2102 | /* Disable LVT0 */ | |
2103 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
2104 | } | |
b8ce3359 | 2105 | |
c177b0bc CG |
2106 | /* |
2107 | * For LVT1 make it edge triggered, active high, | |
2108 | * nmi and enabled | |
2109 | */ | |
0e078e2f TG |
2110 | value = apic_read(APIC_LVT1); |
2111 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
2112 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
2113 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
2114 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
2115 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
2116 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
2117 | } |
2118 | ||
7e1f85f9 | 2119 | int generic_processor_info(int apicid, int version) |
be8a5685 | 2120 | { |
14cb6dcf VG |
2121 | int cpu, max = nr_cpu_ids; |
2122 | bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, | |
2123 | phys_cpu_present_map); | |
2124 | ||
151e0c7d HD |
2125 | /* |
2126 | * boot_cpu_physical_apicid is designed to have the apicid | |
2127 | * returned by read_apic_id(), i.e, the apicid of the | |
2128 | * currently booting-up processor. However, on some platforms, | |
5b4d1dbc | 2129 | * it is temporarily modified by the apicid reported as BSP |
151e0c7d HD |
2130 | * through MP table. Concretely: |
2131 | * | |
2132 | * - arch/x86/kernel/mpparse.c: MP_processor_info() | |
2133 | * - arch/x86/mm/amdtopology.c: amd_numa_init() | |
151e0c7d HD |
2134 | * |
2135 | * This function is executed with the modified | |
2136 | * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel | |
2137 | * parameter doesn't work to disable APs on kdump 2nd kernel. | |
2138 | * | |
2139 | * Since fixing handling of boot_cpu_physical_apicid requires | |
2140 | * another discussion and tests on each platform, we leave it | |
2141 | * for now and here we use read_apic_id() directly in this | |
2142 | * function, generic_processor_info(). | |
2143 | */ | |
2144 | if (disabled_cpu_apicid != BAD_APICID && | |
2145 | disabled_cpu_apicid != read_apic_id() && | |
2146 | disabled_cpu_apicid == apicid) { | |
2147 | int thiscpu = num_processors + disabled_cpus; | |
2148 | ||
5b4d1dbc | 2149 | pr_warning("APIC: Disabling requested cpu." |
151e0c7d HD |
2150 | " Processor %d/0x%x ignored.\n", |
2151 | thiscpu, apicid); | |
2152 | ||
2153 | disabled_cpus++; | |
2154 | return -ENODEV; | |
2155 | } | |
2156 | ||
14cb6dcf VG |
2157 | /* |
2158 | * If boot cpu has not been detected yet, then only allow upto | |
2159 | * nr_cpu_ids - 1 processors and keep one slot free for boot cpu | |
2160 | */ | |
2161 | if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && | |
2162 | apicid != boot_cpu_physical_apicid) { | |
2163 | int thiscpu = max + disabled_cpus - 1; | |
2164 | ||
2165 | pr_warning( | |
2166 | "ACPI: NR_CPUS/possible_cpus limit of %i almost" | |
2167 | " reached. Keeping one slot for boot cpu." | |
2168 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); | |
2169 | ||
2170 | disabled_cpus++; | |
7e1f85f9 | 2171 | return -ENODEV; |
14cb6dcf | 2172 | } |
be8a5685 | 2173 | |
3b11ce7f | 2174 | if (num_processors >= nr_cpu_ids) { |
3b11ce7f MT |
2175 | int thiscpu = max + disabled_cpus; |
2176 | ||
2177 | pr_warning( | |
2178 | "ACPI: NR_CPUS/possible_cpus limit of %i reached." | |
2179 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); | |
2180 | ||
2181 | disabled_cpus++; | |
7e1f85f9 | 2182 | return -EINVAL; |
be8a5685 AS |
2183 | } |
2184 | ||
2185 | num_processors++; | |
be8a5685 AS |
2186 | if (apicid == boot_cpu_physical_apicid) { |
2187 | /* | |
2188 | * x86_bios_cpu_apicid is required to have processors listed | |
2189 | * in same order as logical cpu numbers. Hence the first | |
2190 | * entry is BSP, and so on. | |
e5fea868 YL |
2191 | * boot_cpu_init() already hold bit 0 in cpu_present_mask |
2192 | * for BSP. | |
be8a5685 AS |
2193 | */ |
2194 | cpu = 0; | |
e5fea868 YL |
2195 | } else |
2196 | cpu = cpumask_next_zero(-1, cpu_present_mask); | |
2197 | ||
2198 | /* | |
2199 | * Validate version | |
2200 | */ | |
2201 | if (version == 0x0) { | |
2202 | pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", | |
2203 | cpu, apicid); | |
2204 | version = 0x10; | |
be8a5685 | 2205 | } |
e5fea868 YL |
2206 | apic_version[apicid] = version; |
2207 | ||
2208 | if (version != apic_version[boot_cpu_physical_apicid]) { | |
2209 | pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", | |
2210 | apic_version[boot_cpu_physical_apicid], cpu, version); | |
2211 | } | |
2212 | ||
2213 | physid_set(apicid, phys_cpu_present_map); | |
e0da3364 YL |
2214 | if (apicid > max_physical_apicid) |
2215 | max_physical_apicid = apicid; | |
2216 | ||
3e5095d1 | 2217 | #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) |
f10fcd47 TH |
2218 | early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; |
2219 | early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1b313f4a | 2220 | #endif |
acb8bc09 TH |
2221 | #ifdef CONFIG_X86_32 |
2222 | early_per_cpu(x86_cpu_to_logical_apicid, cpu) = | |
2223 | apic->x86_32_early_logical_apicid(cpu); | |
2224 | #endif | |
1de88cd4 MT |
2225 | set_cpu_possible(cpu, true); |
2226 | set_cpu_present(cpu, true); | |
7e1f85f9 JL |
2227 | |
2228 | return cpu; | |
be8a5685 AS |
2229 | } |
2230 | ||
0c81c746 SS |
2231 | int hard_smp_processor_id(void) |
2232 | { | |
2233 | return read_apic_id(); | |
2234 | } | |
1dcdd3d1 IM |
2235 | |
2236 | void default_init_apic_ldr(void) | |
2237 | { | |
2238 | unsigned long val; | |
2239 | ||
2240 | apic_write(APIC_DFR, APIC_DFR_VALUE); | |
2241 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; | |
2242 | val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); | |
2243 | apic_write(APIC_LDR, val); | |
2244 | } | |
2245 | ||
ff164324 AG |
2246 | int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
2247 | const struct cpumask *andmask, | |
2248 | unsigned int *apicid) | |
6398268d | 2249 | { |
ea3807ea | 2250 | unsigned int cpu; |
6398268d AG |
2251 | |
2252 | for_each_cpu_and(cpu, cpumask, andmask) { | |
2253 | if (cpumask_test_cpu(cpu, cpu_online_mask)) | |
2254 | break; | |
2255 | } | |
ff164324 | 2256 | |
ea3807ea | 2257 | if (likely(cpu < nr_cpu_ids)) { |
a5a39156 AG |
2258 | *apicid = per_cpu(x86_cpu_to_apicid, cpu); |
2259 | return 0; | |
a5a39156 | 2260 | } |
ea3807ea AG |
2261 | |
2262 | return -EINVAL; | |
6398268d AG |
2263 | } |
2264 | ||
1551df64 MT |
2265 | /* |
2266 | * Override the generic EOI implementation with an optimized version. | |
2267 | * Only called during early boot when only one CPU is active and with | |
2268 | * interrupts disabled, so we know this does not race with actual APIC driver | |
2269 | * use. | |
2270 | */ | |
2271 | void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) | |
2272 | { | |
2273 | struct apic **drv; | |
2274 | ||
2275 | for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { | |
2276 | /* Should happen once for each apic */ | |
2277 | WARN_ON((*drv)->eoi_write == eoi_write); | |
2278 | (*drv)->eoi_write = eoi_write; | |
2279 | } | |
2280 | } | |
2281 | ||
89039b37 | 2282 | /* |
0e078e2f | 2283 | * Power management |
89039b37 | 2284 | */ |
0e078e2f TG |
2285 | #ifdef CONFIG_PM |
2286 | ||
2287 | static struct { | |
274cfe59 CG |
2288 | /* |
2289 | * 'active' is true if the local APIC was enabled by us and | |
2290 | * not the BIOS; this signifies that we are also responsible | |
2291 | * for disabling it before entering apm/acpi suspend | |
2292 | */ | |
0e078e2f TG |
2293 | int active; |
2294 | /* r/w apic fields */ | |
2295 | unsigned int apic_id; | |
2296 | unsigned int apic_taskpri; | |
2297 | unsigned int apic_ldr; | |
2298 | unsigned int apic_dfr; | |
2299 | unsigned int apic_spiv; | |
2300 | unsigned int apic_lvtt; | |
2301 | unsigned int apic_lvtpc; | |
2302 | unsigned int apic_lvt0; | |
2303 | unsigned int apic_lvt1; | |
2304 | unsigned int apic_lvterr; | |
2305 | unsigned int apic_tmict; | |
2306 | unsigned int apic_tdcr; | |
2307 | unsigned int apic_thmr; | |
2308 | } apic_pm_state; | |
2309 | ||
f3c6ea1b | 2310 | static int lapic_suspend(void) |
0e078e2f TG |
2311 | { |
2312 | unsigned long flags; | |
2313 | int maxlvt; | |
89039b37 | 2314 | |
0e078e2f TG |
2315 | if (!apic_pm_state.active) |
2316 | return 0; | |
89039b37 | 2317 | |
0e078e2f | 2318 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 2319 | |
2d7a66d0 | 2320 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
2321 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
2322 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
2323 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
2324 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
2325 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
2326 | if (maxlvt >= 4) | |
2327 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
2328 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
2329 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
2330 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
2331 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
2332 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
4efc0670 | 2333 | #ifdef CONFIG_X86_THERMAL_VECTOR |
0e078e2f TG |
2334 | if (maxlvt >= 5) |
2335 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
2336 | #endif | |
24968cfd | 2337 | |
0e078e2f TG |
2338 | local_irq_save(flags); |
2339 | disable_local_APIC(); | |
fc1edaf9 | 2340 | |
70733e0c | 2341 | irq_remapping_disable(); |
fc1edaf9 | 2342 | |
0e078e2f TG |
2343 | local_irq_restore(flags); |
2344 | return 0; | |
1da177e4 LT |
2345 | } |
2346 | ||
f3c6ea1b | 2347 | static void lapic_resume(void) |
1da177e4 | 2348 | { |
0e078e2f TG |
2349 | unsigned int l, h; |
2350 | unsigned long flags; | |
31dce14a | 2351 | int maxlvt; |
b24696bc | 2352 | |
0e078e2f | 2353 | if (!apic_pm_state.active) |
f3c6ea1b | 2354 | return; |
89b831ef | 2355 | |
0e078e2f | 2356 | local_irq_save(flags); |
336224ba JR |
2357 | |
2358 | /* | |
2359 | * IO-APIC and PIC have their own resume routines. | |
2360 | * We just mask them here to make sure the interrupt | |
2361 | * subsystem is completely quiet while we enable x2apic | |
2362 | * and interrupt-remapping. | |
2363 | */ | |
2364 | mask_ioapic_entries(); | |
2365 | legacy_pic->mask_all(); | |
92206c90 | 2366 | |
659006bf TG |
2367 | if (x2apic_mode) { |
2368 | __x2apic_enable(); | |
2369 | } else { | |
92206c90 CG |
2370 | /* |
2371 | * Make sure the APICBASE points to the right address | |
2372 | * | |
2373 | * FIXME! This will be wrong if we ever support suspend on | |
2374 | * SMP! We'll need to do this as part of the CPU restore! | |
2375 | */ | |
cbf2829b BD |
2376 | if (boot_cpu_data.x86 >= 6) { |
2377 | rdmsr(MSR_IA32_APICBASE, l, h); | |
2378 | l &= ~MSR_IA32_APICBASE_BASE; | |
2379 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
2380 | wrmsr(MSR_IA32_APICBASE, l, h); | |
2381 | } | |
d5e629a6 | 2382 | } |
6e1cb38a | 2383 | |
b24696bc | 2384 | maxlvt = lapic_get_maxlvt(); |
0e078e2f TG |
2385 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
2386 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
2387 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
2388 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
2389 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
2390 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
2391 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
2392 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
71c69f7f | 2393 | #if defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
2394 | if (maxlvt >= 5) |
2395 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
2396 | #endif | |
2397 | if (maxlvt >= 4) | |
2398 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
2399 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
2400 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
2401 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
2402 | apic_write(APIC_ESR, 0); | |
2403 | apic_read(APIC_ESR); | |
2404 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
2405 | apic_write(APIC_ESR, 0); | |
2406 | apic_read(APIC_ESR); | |
92206c90 | 2407 | |
70733e0c | 2408 | irq_remapping_reenable(x2apic_mode); |
31dce14a | 2409 | |
0e078e2f | 2410 | local_irq_restore(flags); |
0e078e2f | 2411 | } |
b8ce3359 | 2412 | |
274cfe59 CG |
2413 | /* |
2414 | * This device has no shutdown method - fully functioning local APICs | |
2415 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
2416 | */ | |
2417 | ||
f3c6ea1b | 2418 | static struct syscore_ops lapic_syscore_ops = { |
0e078e2f TG |
2419 | .resume = lapic_resume, |
2420 | .suspend = lapic_suspend, | |
2421 | }; | |
b8ce3359 | 2422 | |
148f9bb8 | 2423 | static void apic_pm_activate(void) |
0e078e2f TG |
2424 | { |
2425 | apic_pm_state.active = 1; | |
1da177e4 LT |
2426 | } |
2427 | ||
0e078e2f | 2428 | static int __init init_lapic_sysfs(void) |
1da177e4 | 2429 | { |
0e078e2f | 2430 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ |
f3c6ea1b RW |
2431 | if (cpu_has_apic) |
2432 | register_syscore_ops(&lapic_syscore_ops); | |
e83a5fdc | 2433 | |
f3c6ea1b | 2434 | return 0; |
1da177e4 | 2435 | } |
b24696bc FY |
2436 | |
2437 | /* local apic needs to resume before other devices access its registers. */ | |
2438 | core_initcall(init_lapic_sysfs); | |
0e078e2f TG |
2439 | |
2440 | #else /* CONFIG_PM */ | |
2441 | ||
2442 | static void apic_pm_activate(void) { } | |
2443 | ||
2444 | #endif /* CONFIG_PM */ | |
1da177e4 | 2445 | |
f28c0ae2 | 2446 | #ifdef CONFIG_X86_64 |
e0e42142 | 2447 | |
148f9bb8 PG |
2448 | static int multi_checked; |
2449 | static int multi; | |
e0e42142 | 2450 | |
148f9bb8 | 2451 | static int set_multi(const struct dmi_system_id *d) |
e0e42142 YL |
2452 | { |
2453 | if (multi) | |
2454 | return 0; | |
6f0aced6 | 2455 | pr_info("APIC: %s detected, Multi Chassis\n", d->ident); |
e0e42142 YL |
2456 | multi = 1; |
2457 | return 0; | |
2458 | } | |
2459 | ||
148f9bb8 | 2460 | static const struct dmi_system_id multi_dmi_table[] = { |
e0e42142 YL |
2461 | { |
2462 | .callback = set_multi, | |
2463 | .ident = "IBM System Summit2", | |
2464 | .matches = { | |
2465 | DMI_MATCH(DMI_SYS_VENDOR, "IBM"), | |
2466 | DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), | |
2467 | }, | |
2468 | }, | |
2469 | {} | |
2470 | }; | |
2471 | ||
148f9bb8 | 2472 | static void dmi_check_multi(void) |
e0e42142 YL |
2473 | { |
2474 | if (multi_checked) | |
2475 | return; | |
2476 | ||
2477 | dmi_check_system(multi_dmi_table); | |
2478 | multi_checked = 1; | |
2479 | } | |
2480 | ||
2481 | /* | |
2482 | * apic_is_clustered_box() -- Check if we can expect good TSC | |
2483 | * | |
2484 | * Thus far, the major user of this is IBM's Summit2 series: | |
2485 | * Clustered boxes may have unsynced TSC problems if they are | |
2486 | * multi-chassis. | |
2487 | * Use DMI to check them | |
2488 | */ | |
148f9bb8 | 2489 | int apic_is_clustered_box(void) |
e0e42142 YL |
2490 | { |
2491 | dmi_check_multi(); | |
411cf9ee | 2492 | return multi; |
1da177e4 | 2493 | } |
f28c0ae2 | 2494 | #endif |
1da177e4 LT |
2495 | |
2496 | /* | |
0e078e2f | 2497 | * APIC command line parameters |
1da177e4 | 2498 | */ |
789fa735 | 2499 | static int __init setup_disableapic(char *arg) |
6935d1f9 | 2500 | { |
1da177e4 | 2501 | disable_apic = 1; |
9175fc06 | 2502 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
2503 | return 0; |
2504 | } | |
2505 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 2506 | |
2c8c0e6b | 2507 | /* same as disableapic, for compatibility */ |
789fa735 | 2508 | static int __init setup_nolapic(char *arg) |
6935d1f9 | 2509 | { |
789fa735 | 2510 | return setup_disableapic(arg); |
6935d1f9 | 2511 | } |
2c8c0e6b | 2512 | early_param("nolapic", setup_nolapic); |
1da177e4 | 2513 | |
2e7c2838 LT |
2514 | static int __init parse_lapic_timer_c2_ok(char *arg) |
2515 | { | |
2516 | local_apic_timer_c2_ok = 1; | |
2517 | return 0; | |
2518 | } | |
2519 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
2520 | ||
36fef094 | 2521 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 2522 | { |
1da177e4 | 2523 | disable_apic_timer = 1; |
36fef094 | 2524 | return 0; |
6935d1f9 | 2525 | } |
36fef094 CG |
2526 | early_param("noapictimer", parse_disable_apic_timer); |
2527 | ||
2528 | static int __init parse_nolapic_timer(char *arg) | |
2529 | { | |
2530 | disable_apic_timer = 1; | |
2531 | return 0; | |
6935d1f9 | 2532 | } |
36fef094 | 2533 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 2534 | |
79af9bec CG |
2535 | static int __init apic_set_verbosity(char *arg) |
2536 | { | |
2537 | if (!arg) { | |
2538 | #ifdef CONFIG_X86_64 | |
2539 | skip_ioapic_setup = 0; | |
79af9bec CG |
2540 | return 0; |
2541 | #endif | |
2542 | return -EINVAL; | |
2543 | } | |
2544 | ||
2545 | if (strcmp("debug", arg) == 0) | |
2546 | apic_verbosity = APIC_DEBUG; | |
2547 | else if (strcmp("verbose", arg) == 0) | |
2548 | apic_verbosity = APIC_VERBOSE; | |
2549 | else { | |
ba21ebb6 | 2550 | pr_warning("APIC Verbosity level %s not recognised" |
79af9bec CG |
2551 | " use apic=verbose or apic=debug\n", arg); |
2552 | return -EINVAL; | |
2553 | } | |
2554 | ||
2555 | return 0; | |
2556 | } | |
2557 | early_param("apic", apic_set_verbosity); | |
2558 | ||
1e934dda YL |
2559 | static int __init lapic_insert_resource(void) |
2560 | { | |
2561 | if (!apic_phys) | |
2562 | return -1; | |
2563 | ||
2564 | /* Put local APIC into the resource map. */ | |
2565 | lapic_resource.start = apic_phys; | |
2566 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
2567 | insert_resource(&iomem_resource, &lapic_resource); | |
2568 | ||
2569 | return 0; | |
2570 | } | |
2571 | ||
2572 | /* | |
2573 | * need call insert after e820_reserve_resources() | |
2574 | * that is using request_resource | |
2575 | */ | |
2576 | late_initcall(lapic_insert_resource); | |
151e0c7d HD |
2577 | |
2578 | static int __init apic_set_disabled_cpu_apicid(char *arg) | |
2579 | { | |
2580 | if (!arg || !get_option(&arg, &disabled_cpu_apicid)) | |
2581 | return -EINVAL; | |
2582 | ||
2583 | return 0; | |
2584 | } | |
2585 | early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); |