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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
39928722 | 26 | #include <linux/ioport.h> |
ba7eda4c | 27 | #include <linux/clockchips.h> |
70a20025 | 28 | #include <linux/acpi_pmtmr.h> |
e83a5fdc | 29 | #include <linux/module.h> |
1da177e4 LT |
30 | |
31 | #include <asm/atomic.h> | |
32 | #include <asm/smp.h> | |
33 | #include <asm/mtrr.h> | |
34 | #include <asm/mpspec.h> | |
e83a5fdc | 35 | #include <asm/hpet.h> |
1da177e4 | 36 | #include <asm/pgalloc.h> |
75152114 | 37 | #include <asm/nmi.h> |
95833c83 | 38 | #include <asm/idle.h> |
73dea47f AK |
39 | #include <asm/proto.h> |
40 | #include <asm/timex.h> | |
2c8c0e6b | 41 | #include <asm/apic.h> |
1da177e4 | 42 | |
5af5573e | 43 | #include <mach_ipi.h> |
dd46e3ca | 44 | #include <mach_apic.h> |
5af5573e | 45 | |
aa276e1c | 46 | static int disable_apic_timer __cpuinitdata; |
bc1d99c1 | 47 | static int apic_calibrate_pmtmr __initdata; |
0e078e2f | 48 | int disable_apic; |
1da177e4 | 49 | |
e83a5fdc | 50 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
51 | int local_apic_timer_c2_ok; |
52 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
53 | ||
e83a5fdc HS |
54 | /* |
55 | * Debug level, exported for io_apic.c | |
56 | */ | |
57 | int apic_verbosity; | |
58 | ||
bab4b27c AS |
59 | /* Have we found an MP table */ |
60 | int smp_found_config; | |
61 | ||
39928722 AD |
62 | static struct resource lapic_resource = { |
63 | .name = "Local APIC", | |
64 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
65 | }; | |
66 | ||
d03030e9 TG |
67 | static unsigned int calibration_result; |
68 | ||
ba7eda4c TG |
69 | static int lapic_next_event(unsigned long delta, |
70 | struct clock_event_device *evt); | |
71 | static void lapic_timer_setup(enum clock_event_mode mode, | |
72 | struct clock_event_device *evt); | |
ba7eda4c | 73 | static void lapic_timer_broadcast(cpumask_t mask); |
0e078e2f | 74 | static void apic_pm_activate(void); |
ba7eda4c TG |
75 | |
76 | static struct clock_event_device lapic_clockevent = { | |
77 | .name = "lapic", | |
78 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
79 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
80 | .shift = 32, | |
81 | .set_mode = lapic_timer_setup, | |
82 | .set_next_event = lapic_next_event, | |
83 | .broadcast = lapic_timer_broadcast, | |
84 | .rating = 100, | |
85 | .irq = -1, | |
86 | }; | |
87 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
88 | ||
d3432896 AK |
89 | static unsigned long apic_phys; |
90 | ||
3f530709 AS |
91 | unsigned long mp_lapic_addr; |
92 | ||
be8a5685 | 93 | unsigned int __cpuinitdata maxcpus = NR_CPUS; |
0e078e2f TG |
94 | /* |
95 | * Get the LAPIC version | |
96 | */ | |
97 | static inline int lapic_get_version(void) | |
ba7eda4c | 98 | { |
0e078e2f | 99 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
100 | } |
101 | ||
0e078e2f TG |
102 | /* |
103 | * Check, if the APIC is integrated or a seperate chip | |
104 | */ | |
105 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 106 | { |
0e078e2f | 107 | return 1; |
ba7eda4c TG |
108 | } |
109 | ||
110 | /* | |
0e078e2f | 111 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 112 | */ |
0e078e2f | 113 | static int modern_apic(void) |
ba7eda4c | 114 | { |
0e078e2f TG |
115 | /* AMD systems use old APIC versions, so check the CPU */ |
116 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
117 | boot_cpu_data.x86 >= 0xf) | |
118 | return 1; | |
119 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
120 | } |
121 | ||
8339e9fb FLV |
122 | void apic_wait_icr_idle(void) |
123 | { | |
124 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
125 | cpu_relax(); | |
126 | } | |
127 | ||
3c6bb07a | 128 | u32 safe_apic_wait_icr_idle(void) |
8339e9fb | 129 | { |
3c6bb07a | 130 | u32 send_status; |
8339e9fb FLV |
131 | int timeout; |
132 | ||
133 | timeout = 0; | |
134 | do { | |
135 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
136 | if (!send_status) | |
137 | break; | |
138 | udelay(100); | |
139 | } while (timeout++ < 1000); | |
140 | ||
141 | return send_status; | |
142 | } | |
143 | ||
0e078e2f TG |
144 | /** |
145 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
146 | */ | |
e9427101 | 147 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 148 | { |
11a8e778 | 149 | unsigned int v; |
6935d1f9 TG |
150 | |
151 | /* unmask and set to NMI */ | |
152 | v = APIC_DM_NMI; | |
11a8e778 | 153 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
154 | } |
155 | ||
0e078e2f TG |
156 | /** |
157 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
158 | */ | |
37e650c7 | 159 | int lapic_get_maxlvt(void) |
1da177e4 | 160 | { |
11a8e778 | 161 | unsigned int v, maxlvt; |
1da177e4 LT |
162 | |
163 | v = apic_read(APIC_LVR); | |
1da177e4 LT |
164 | maxlvt = GET_APIC_MAXLVT(v); |
165 | return maxlvt; | |
166 | } | |
167 | ||
0e078e2f TG |
168 | /* |
169 | * This function sets up the local APIC timer, with a timeout of | |
170 | * 'clocks' APIC bus clock. During calibration we actually call | |
171 | * this function twice on the boot CPU, once with a bogus timeout | |
172 | * value, second time for real. The other (noncalibrating) CPUs | |
173 | * call this function only once, with the real, calibrated value. | |
174 | * | |
175 | * We do reads before writes even if unnecessary, to get around the | |
176 | * P5 APIC double write bug. | |
177 | */ | |
178 | ||
179 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) | |
1da177e4 | 180 | { |
0e078e2f | 181 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 182 | |
0e078e2f TG |
183 | lvtt_value = LOCAL_TIMER_VECTOR; |
184 | if (!oneshot) | |
185 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
186 | if (!irqen) | |
187 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 188 | |
0e078e2f | 189 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
190 | |
191 | /* | |
0e078e2f | 192 | * Divide PICLK by 16 |
1da177e4 | 193 | */ |
0e078e2f TG |
194 | tmp_value = apic_read(APIC_TDCR); |
195 | apic_write(APIC_TDCR, (tmp_value | |
196 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | |
197 | | APIC_TDR_DIV_16); | |
198 | ||
199 | if (!oneshot) | |
200 | apic_write(APIC_TMICT, clocks); | |
1da177e4 LT |
201 | } |
202 | ||
0e078e2f | 203 | /* |
7b83dae7 RR |
204 | * Setup extended LVT, AMD specific (K8, family 10h) |
205 | * | |
206 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
207 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
0e078e2f | 208 | */ |
7b83dae7 RR |
209 | |
210 | #define APIC_EILVT_LVTOFF_MCE 0 | |
211 | #define APIC_EILVT_LVTOFF_IBS 1 | |
212 | ||
213 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
1da177e4 | 214 | { |
7b83dae7 | 215 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; |
0e078e2f | 216 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; |
a8fcf1a2 | 217 | |
0e078e2f | 218 | apic_write(reg, v); |
1da177e4 LT |
219 | } |
220 | ||
7b83dae7 RR |
221 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) |
222 | { | |
223 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
224 | return APIC_EILVT_LVTOFF_MCE; | |
225 | } | |
226 | ||
227 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
228 | { | |
229 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
230 | return APIC_EILVT_LVTOFF_IBS; | |
231 | } | |
232 | ||
0e078e2f TG |
233 | /* |
234 | * Program the next event, relative to now | |
235 | */ | |
236 | static int lapic_next_event(unsigned long delta, | |
237 | struct clock_event_device *evt) | |
1da177e4 | 238 | { |
0e078e2f TG |
239 | apic_write(APIC_TMICT, delta); |
240 | return 0; | |
1da177e4 LT |
241 | } |
242 | ||
0e078e2f TG |
243 | /* |
244 | * Setup the lapic timer in periodic or oneshot mode | |
245 | */ | |
246 | static void lapic_timer_setup(enum clock_event_mode mode, | |
247 | struct clock_event_device *evt) | |
9b7711f0 HS |
248 | { |
249 | unsigned long flags; | |
0e078e2f | 250 | unsigned int v; |
9b7711f0 | 251 | |
0e078e2f TG |
252 | /* Lapic used as dummy for broadcast ? */ |
253 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
254 | return; |
255 | ||
256 | local_irq_save(flags); | |
257 | ||
0e078e2f TG |
258 | switch (mode) { |
259 | case CLOCK_EVT_MODE_PERIODIC: | |
260 | case CLOCK_EVT_MODE_ONESHOT: | |
261 | __setup_APIC_LVTT(calibration_result, | |
262 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
263 | break; | |
264 | case CLOCK_EVT_MODE_UNUSED: | |
265 | case CLOCK_EVT_MODE_SHUTDOWN: | |
266 | v = apic_read(APIC_LVTT); | |
267 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
268 | apic_write(APIC_LVTT, v); | |
269 | break; | |
270 | case CLOCK_EVT_MODE_RESUME: | |
271 | /* Nothing to do here */ | |
272 | break; | |
273 | } | |
9b7711f0 HS |
274 | |
275 | local_irq_restore(flags); | |
276 | } | |
277 | ||
1da177e4 | 278 | /* |
0e078e2f | 279 | * Local APIC timer broadcast function |
1da177e4 | 280 | */ |
0e078e2f | 281 | static void lapic_timer_broadcast(cpumask_t mask) |
1da177e4 | 282 | { |
0e078e2f TG |
283 | #ifdef CONFIG_SMP |
284 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
285 | #endif | |
286 | } | |
1da177e4 | 287 | |
0e078e2f TG |
288 | /* |
289 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
290 | * of the boot CPU and register the clock event in the framework. | |
291 | */ | |
292 | static void setup_APIC_timer(void) | |
293 | { | |
294 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 295 | |
0e078e2f TG |
296 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
297 | levt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
1da177e4 | 298 | |
0e078e2f TG |
299 | clockevents_register_device(levt); |
300 | } | |
1da177e4 | 301 | |
0e078e2f TG |
302 | /* |
303 | * In this function we calibrate APIC bus clocks to the external | |
304 | * timer. Unfortunately we cannot use jiffies and the timer irq | |
305 | * to calibrate, since some later bootup code depends on getting | |
306 | * the first irq? Ugh. | |
307 | * | |
308 | * We want to do the calibration only once since we | |
309 | * want to have local timer irqs syncron. CPUs connected | |
310 | * by the same APIC bus have the very same bus frequency. | |
311 | * And we want to have irqs off anyways, no accidental | |
312 | * APIC irq that way. | |
313 | */ | |
314 | ||
315 | #define TICK_COUNT 100000000 | |
316 | ||
317 | static void __init calibrate_APIC_clock(void) | |
318 | { | |
319 | unsigned apic, apic_start; | |
320 | unsigned long tsc, tsc_start; | |
321 | int result; | |
322 | ||
323 | local_irq_disable(); | |
324 | ||
325 | /* | |
326 | * Put whatever arbitrary (but long enough) timeout | |
327 | * value into the APIC clock, we just want to get the | |
328 | * counter running for calibration. | |
329 | * | |
330 | * No interrupt enable ! | |
331 | */ | |
332 | __setup_APIC_LVTT(250000000, 0, 0); | |
333 | ||
334 | apic_start = apic_read(APIC_TMCCT); | |
335 | #ifdef CONFIG_X86_PM_TIMER | |
336 | if (apic_calibrate_pmtmr && pmtmr_ioport) { | |
337 | pmtimer_wait(5000); /* 5ms wait */ | |
338 | apic = apic_read(APIC_TMCCT); | |
339 | result = (apic_start - apic) * 1000L / 5; | |
340 | } else | |
341 | #endif | |
342 | { | |
343 | rdtscll(tsc_start); | |
344 | ||
345 | do { | |
346 | apic = apic_read(APIC_TMCCT); | |
347 | rdtscll(tsc); | |
348 | } while ((tsc - tsc_start) < TICK_COUNT && | |
349 | (apic_start - apic) < TICK_COUNT); | |
350 | ||
351 | result = (apic_start - apic) * 1000L * tsc_khz / | |
352 | (tsc - tsc_start); | |
353 | } | |
354 | ||
355 | local_irq_enable(); | |
356 | ||
357 | printk(KERN_DEBUG "APIC timer calibration result %d\n", result); | |
358 | ||
359 | printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n", | |
360 | result / 1000 / 1000, result / 1000 % 1000); | |
361 | ||
362 | /* Calculate the scaled math multiplication factor */ | |
877084fb AM |
363 | lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC, |
364 | lapic_clockevent.shift); | |
0e078e2f TG |
365 | lapic_clockevent.max_delta_ns = |
366 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
367 | lapic_clockevent.min_delta_ns = | |
368 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
369 | ||
370 | calibration_result = result / HZ; | |
371 | } | |
372 | ||
e83a5fdc HS |
373 | /* |
374 | * Setup the boot APIC | |
375 | * | |
376 | * Calibrate and verify the result. | |
377 | */ | |
0e078e2f TG |
378 | void __init setup_boot_APIC_clock(void) |
379 | { | |
380 | /* | |
381 | * The local apic timer can be disabled via the kernel commandline. | |
382 | * Register the lapic timer as a dummy clock event source on SMP | |
383 | * systems, so the broadcast mechanism is used. On UP systems simply | |
384 | * ignore it. | |
385 | */ | |
386 | if (disable_apic_timer) { | |
387 | printk(KERN_INFO "Disabling APIC timer\n"); | |
388 | /* No broadcast on UP ! */ | |
9d09951d TG |
389 | if (num_possible_cpus() > 1) { |
390 | lapic_clockevent.mult = 1; | |
0e078e2f | 391 | setup_APIC_timer(); |
9d09951d | 392 | } |
0e078e2f TG |
393 | return; |
394 | } | |
395 | ||
396 | printk(KERN_INFO "Using local APIC timer interrupts.\n"); | |
397 | calibrate_APIC_clock(); | |
398 | ||
c2b84b30 TG |
399 | /* |
400 | * Do a sanity check on the APIC calibration result | |
401 | */ | |
402 | if (calibration_result < (1000000 / HZ)) { | |
403 | printk(KERN_WARNING | |
404 | "APIC frequency too slow, disabling apic timer\n"); | |
405 | /* No broadcast on UP ! */ | |
406 | if (num_possible_cpus() > 1) | |
407 | setup_APIC_timer(); | |
408 | return; | |
409 | } | |
410 | ||
0e078e2f TG |
411 | /* |
412 | * If nmi_watchdog is set to IO_APIC, we need the | |
413 | * PIT/HPET going. Otherwise register lapic as a dummy | |
414 | * device. | |
415 | */ | |
416 | if (nmi_watchdog != NMI_IO_APIC) | |
417 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
418 | else | |
419 | printk(KERN_WARNING "APIC timer registered as dummy," | |
420 | " due to nmi_watchdog=1!\n"); | |
421 | ||
422 | setup_APIC_timer(); | |
423 | } | |
424 | ||
0e078e2f TG |
425 | void __cpuinit setup_secondary_APIC_clock(void) |
426 | { | |
0e078e2f TG |
427 | setup_APIC_timer(); |
428 | } | |
429 | ||
430 | /* | |
431 | * The guts of the apic timer interrupt | |
432 | */ | |
433 | static void local_apic_timer_interrupt(void) | |
434 | { | |
435 | int cpu = smp_processor_id(); | |
436 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
437 | ||
438 | /* | |
439 | * Normally we should not be here till LAPIC has been initialized but | |
440 | * in some cases like kdump, its possible that there is a pending LAPIC | |
441 | * timer interrupt from previous kernel's context and is delivered in | |
442 | * new kernel the moment interrupts are enabled. | |
443 | * | |
444 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
445 | * its possible that when we get here evt->event_handler is NULL. | |
446 | * Check for event_handler being NULL and discard the interrupt as | |
447 | * spurious. | |
448 | */ | |
449 | if (!evt->event_handler) { | |
450 | printk(KERN_WARNING | |
451 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | |
452 | /* Switch it off */ | |
453 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
454 | return; | |
455 | } | |
456 | ||
457 | /* | |
458 | * the NMI deadlock-detector uses this. | |
459 | */ | |
460 | add_pda(apic_timer_irqs, 1); | |
461 | ||
462 | evt->event_handler(evt); | |
463 | } | |
464 | ||
465 | /* | |
466 | * Local APIC timer interrupt. This is the most natural way for doing | |
467 | * local interrupts, but local timer interrupts can be emulated by | |
468 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
469 | * | |
470 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
471 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
472 | */ | |
473 | void smp_apic_timer_interrupt(struct pt_regs *regs) | |
474 | { | |
475 | struct pt_regs *old_regs = set_irq_regs(regs); | |
476 | ||
477 | /* | |
478 | * NOTE! We'd better ACK the irq immediately, | |
479 | * because timer handling can be slow. | |
480 | */ | |
481 | ack_APIC_irq(); | |
482 | /* | |
483 | * update_process_times() expects us to have done irq_enter(). | |
484 | * Besides, if we don't timer interrupts ignore the global | |
485 | * interrupt lock, which is the WrongThing (tm) to do. | |
486 | */ | |
487 | exit_idle(); | |
488 | irq_enter(); | |
489 | local_apic_timer_interrupt(); | |
490 | irq_exit(); | |
491 | set_irq_regs(old_regs); | |
492 | } | |
493 | ||
494 | int setup_profiling_timer(unsigned int multiplier) | |
495 | { | |
496 | return -EINVAL; | |
497 | } | |
498 | ||
499 | ||
500 | /* | |
501 | * Local APIC start and shutdown | |
502 | */ | |
503 | ||
504 | /** | |
505 | * clear_local_APIC - shutdown the local APIC | |
506 | * | |
507 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
508 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
509 | * leftovers during boot. | |
510 | */ | |
511 | void clear_local_APIC(void) | |
512 | { | |
2584a82d | 513 | int maxlvt; |
0e078e2f TG |
514 | u32 v; |
515 | ||
d3432896 AK |
516 | /* APIC hasn't been mapped yet */ |
517 | if (!apic_phys) | |
518 | return; | |
519 | ||
520 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
521 | /* |
522 | * Masking an LVT entry can trigger a local APIC error | |
523 | * if the vector is zero. Mask LVTERR first to prevent this. | |
524 | */ | |
525 | if (maxlvt >= 3) { | |
526 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
527 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
528 | } | |
529 | /* | |
530 | * Careful: we have to set masks only first to deassert | |
531 | * any level-triggered sources. | |
532 | */ | |
533 | v = apic_read(APIC_LVTT); | |
534 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
535 | v = apic_read(APIC_LVT0); | |
536 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
537 | v = apic_read(APIC_LVT1); | |
538 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
539 | if (maxlvt >= 4) { | |
540 | v = apic_read(APIC_LVTPC); | |
541 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
542 | } | |
543 | ||
544 | /* | |
545 | * Clean APIC state for other OSs: | |
546 | */ | |
547 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
548 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
549 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
550 | if (maxlvt >= 3) | |
551 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
552 | if (maxlvt >= 4) | |
553 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
554 | apic_write(APIC_ESR, 0); | |
555 | apic_read(APIC_ESR); | |
556 | } | |
557 | ||
558 | /** | |
559 | * disable_local_APIC - clear and disable the local APIC | |
560 | */ | |
561 | void disable_local_APIC(void) | |
562 | { | |
563 | unsigned int value; | |
564 | ||
565 | clear_local_APIC(); | |
566 | ||
567 | /* | |
568 | * Disable APIC (implies clearing of registers | |
569 | * for 82489DX!). | |
570 | */ | |
571 | value = apic_read(APIC_SPIV); | |
572 | value &= ~APIC_SPIV_APIC_ENABLED; | |
573 | apic_write(APIC_SPIV, value); | |
574 | } | |
575 | ||
576 | void lapic_shutdown(void) | |
577 | { | |
578 | unsigned long flags; | |
579 | ||
580 | if (!cpu_has_apic) | |
581 | return; | |
582 | ||
583 | local_irq_save(flags); | |
584 | ||
585 | disable_local_APIC(); | |
586 | ||
587 | local_irq_restore(flags); | |
588 | } | |
589 | ||
590 | /* | |
591 | * This is to verify that we're looking at a real local APIC. | |
592 | * Check these against your board if the CPUs aren't getting | |
593 | * started for no apparent reason. | |
594 | */ | |
595 | int __init verify_local_APIC(void) | |
596 | { | |
597 | unsigned int reg0, reg1; | |
598 | ||
599 | /* | |
600 | * The version register is read-only in a real APIC. | |
601 | */ | |
602 | reg0 = apic_read(APIC_LVR); | |
603 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
604 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
605 | reg1 = apic_read(APIC_LVR); | |
606 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
607 | ||
608 | /* | |
609 | * The two version reads above should print the same | |
610 | * numbers. If the second one is different, then we | |
611 | * poke at a non-APIC. | |
612 | */ | |
613 | if (reg1 != reg0) | |
614 | return 0; | |
615 | ||
616 | /* | |
617 | * Check if the version looks reasonably. | |
618 | */ | |
619 | reg1 = GET_APIC_VERSION(reg0); | |
620 | if (reg1 == 0x00 || reg1 == 0xff) | |
621 | return 0; | |
622 | reg1 = lapic_get_maxlvt(); | |
623 | if (reg1 < 0x02 || reg1 == 0xff) | |
624 | return 0; | |
625 | ||
626 | /* | |
627 | * The ID register is read/write in a real APIC. | |
628 | */ | |
05f2d12c | 629 | reg0 = read_apic_id(); |
0e078e2f TG |
630 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
631 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
05f2d12c | 632 | reg1 = read_apic_id(); |
0e078e2f TG |
633 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
634 | apic_write(APIC_ID, reg0); | |
635 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
636 | return 0; | |
637 | ||
638 | /* | |
1da177e4 LT |
639 | * The next two are just to see if we have sane values. |
640 | * They're only really relevant if we're in Virtual Wire | |
641 | * compatibility mode, but most boxes are anymore. | |
642 | */ | |
643 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 644 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
645 | reg1 = apic_read(APIC_LVT1); |
646 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
647 | ||
648 | return 1; | |
649 | } | |
650 | ||
0e078e2f TG |
651 | /** |
652 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
653 | */ | |
1da177e4 LT |
654 | void __init sync_Arb_IDs(void) |
655 | { | |
656 | /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */ | |
0e078e2f | 657 | if (modern_apic()) |
1da177e4 LT |
658 | return; |
659 | ||
660 | /* | |
661 | * Wait for idle. | |
662 | */ | |
663 | apic_wait_icr_idle(); | |
664 | ||
665 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
11a8e778 | 666 | apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG |
1da177e4 LT |
667 | | APIC_DM_INIT); |
668 | } | |
669 | ||
1da177e4 LT |
670 | /* |
671 | * An initial setup of the virtual wire mode. | |
672 | */ | |
673 | void __init init_bsp_APIC(void) | |
674 | { | |
11a8e778 | 675 | unsigned int value; |
1da177e4 LT |
676 | |
677 | /* | |
678 | * Don't do the setup now if we have a SMP BIOS as the | |
679 | * through-I/O-APIC virtual wire mode might be active. | |
680 | */ | |
681 | if (smp_found_config || !cpu_has_apic) | |
682 | return; | |
683 | ||
684 | value = apic_read(APIC_LVR); | |
1da177e4 LT |
685 | |
686 | /* | |
687 | * Do not trust the local APIC being empty at bootup. | |
688 | */ | |
689 | clear_local_APIC(); | |
690 | ||
691 | /* | |
692 | * Enable APIC. | |
693 | */ | |
694 | value = apic_read(APIC_SPIV); | |
695 | value &= ~APIC_VECTOR_MASK; | |
696 | value |= APIC_SPIV_APIC_ENABLED; | |
697 | value |= APIC_SPIV_FOCUS_DISABLED; | |
698 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 699 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
700 | |
701 | /* | |
702 | * Set up the virtual wire mode. | |
703 | */ | |
11a8e778 | 704 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 705 | value = APIC_DM_NMI; |
11a8e778 | 706 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
707 | } |
708 | ||
0e078e2f TG |
709 | /** |
710 | * setup_local_APIC - setup the local APIC | |
711 | */ | |
712 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 713 | { |
739f33b3 | 714 | unsigned int value; |
da7ed9f9 | 715 | int i, j; |
1da177e4 | 716 | |
ac23d4ee | 717 | preempt_disable(); |
1da177e4 | 718 | value = apic_read(APIC_LVR); |
1da177e4 | 719 | |
fe7414a2 | 720 | BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f); |
1da177e4 LT |
721 | |
722 | /* | |
723 | * Double-check whether this APIC is really registered. | |
724 | * This is meaningless in clustered apic mode, so we skip it. | |
725 | */ | |
726 | if (!apic_id_registered()) | |
727 | BUG(); | |
728 | ||
729 | /* | |
730 | * Intel recommends to set DFR, LDR and TPR before enabling | |
731 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
732 | * document number 292116). So here it goes... | |
733 | */ | |
734 | init_apic_ldr(); | |
735 | ||
736 | /* | |
737 | * Set Task Priority to 'accept all'. We never change this | |
738 | * later on. | |
739 | */ | |
740 | value = apic_read(APIC_TASKPRI); | |
741 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 742 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 743 | |
da7ed9f9 VG |
744 | /* |
745 | * After a crash, we no longer service the interrupts and a pending | |
746 | * interrupt from previous kernel might still have ISR bit set. | |
747 | * | |
748 | * Most probably by now CPU has serviced that pending interrupt and | |
749 | * it might not have done the ack_APIC_irq() because it thought, | |
750 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
751 | * does not clear the ISR bit and cpu thinks it has already serivced | |
752 | * the interrupt. Hence a vector might get locked. It was noticed | |
753 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
754 | */ | |
755 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
756 | value = apic_read(APIC_ISR + i*0x10); | |
757 | for (j = 31; j >= 0; j--) { | |
758 | if (value & (1<<j)) | |
759 | ack_APIC_irq(); | |
760 | } | |
761 | } | |
762 | ||
1da177e4 LT |
763 | /* |
764 | * Now that we are all set up, enable the APIC | |
765 | */ | |
766 | value = apic_read(APIC_SPIV); | |
767 | value &= ~APIC_VECTOR_MASK; | |
768 | /* | |
769 | * Enable APIC | |
770 | */ | |
771 | value |= APIC_SPIV_APIC_ENABLED; | |
772 | ||
3f14c746 AK |
773 | /* We always use processor focus */ |
774 | ||
1da177e4 LT |
775 | /* |
776 | * Set spurious IRQ vector | |
777 | */ | |
778 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 779 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
780 | |
781 | /* | |
782 | * Set up LVT0, LVT1: | |
783 | * | |
784 | * set up through-local-APIC on the BP's LINT0. This is not | |
785 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
786 | * we delegate interrupts to the 8259A. | |
787 | */ | |
788 | /* | |
789 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
790 | */ | |
791 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
a8fcf1a2 | 792 | if (!smp_processor_id() && !value) { |
1da177e4 | 793 | value = APIC_DM_EXTINT; |
bc1d99c1 CW |
794 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
795 | smp_processor_id()); | |
1da177e4 LT |
796 | } else { |
797 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 CW |
798 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
799 | smp_processor_id()); | |
1da177e4 | 800 | } |
11a8e778 | 801 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
802 | |
803 | /* | |
804 | * only the BP should see the LINT1 NMI signal, obviously. | |
805 | */ | |
806 | if (!smp_processor_id()) | |
807 | value = APIC_DM_NMI; | |
808 | else | |
809 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
11a8e778 | 810 | apic_write(APIC_LVT1, value); |
ac23d4ee | 811 | preempt_enable(); |
739f33b3 | 812 | } |
1da177e4 | 813 | |
a4928cff | 814 | static void __cpuinit lapic_setup_esr(void) |
739f33b3 AK |
815 | { |
816 | unsigned maxlvt = lapic_get_maxlvt(); | |
817 | ||
818 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR); | |
1c69524c | 819 | /* |
739f33b3 | 820 | * spec says clear errors after enabling vector. |
1c69524c | 821 | */ |
739f33b3 AK |
822 | if (maxlvt > 3) |
823 | apic_write(APIC_ESR, 0); | |
824 | } | |
1da177e4 | 825 | |
739f33b3 AK |
826 | void __cpuinit end_local_APIC_setup(void) |
827 | { | |
828 | lapic_setup_esr(); | |
1da177e4 | 829 | nmi_watchdog_default(); |
f2802e7f | 830 | setup_apic_nmi_watchdog(NULL); |
0e078e2f | 831 | apic_pm_activate(); |
1da177e4 | 832 | } |
1da177e4 LT |
833 | |
834 | /* | |
835 | * Detect and enable local APICs on non-SMP boards. | |
836 | * Original code written by Keir Fraser. | |
837 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 838 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 839 | */ |
0e078e2f | 840 | static int __init detect_init_APIC(void) |
1da177e4 LT |
841 | { |
842 | if (!cpu_has_apic) { | |
843 | printk(KERN_INFO "No local APIC present\n"); | |
844 | return -1; | |
845 | } | |
846 | ||
847 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
c70dcb74 | 848 | boot_cpu_physical_apicid = 0; |
1da177e4 LT |
849 | return 0; |
850 | } | |
851 | ||
8643f9d0 YL |
852 | void __init early_init_lapic_mapping(void) |
853 | { | |
431ee79d | 854 | unsigned long phys_addr; |
8643f9d0 YL |
855 | |
856 | /* | |
857 | * If no local APIC can be found then go out | |
858 | * : it means there is no mpatable and MADT | |
859 | */ | |
860 | if (!smp_found_config) | |
861 | return; | |
862 | ||
431ee79d | 863 | phys_addr = mp_lapic_addr; |
8643f9d0 | 864 | |
431ee79d | 865 | set_fixmap_nocache(FIX_APIC_BASE, phys_addr); |
8643f9d0 | 866 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
431ee79d | 867 | APIC_BASE, phys_addr); |
8643f9d0 YL |
868 | |
869 | /* | |
870 | * Fetch the APIC ID of the BSP in case we have a | |
871 | * default configuration (or the MP table is broken). | |
872 | */ | |
05f2d12c | 873 | boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id()); |
8643f9d0 YL |
874 | } |
875 | ||
0e078e2f TG |
876 | /** |
877 | * init_apic_mappings - initialize APIC mappings | |
878 | */ | |
1da177e4 LT |
879 | void __init init_apic_mappings(void) |
880 | { | |
1da177e4 LT |
881 | /* |
882 | * If no local APIC can be found then set up a fake all | |
883 | * zeroes page to simulate the local APIC and another | |
884 | * one for the IO-APIC. | |
885 | */ | |
886 | if (!smp_found_config && detect_init_APIC()) { | |
887 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
888 | apic_phys = __pa(apic_phys); | |
889 | } else | |
890 | apic_phys = mp_lapic_addr; | |
891 | ||
892 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
7ffeeb1e YL |
893 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
894 | APIC_BASE, apic_phys); | |
1da177e4 LT |
895 | |
896 | /* | |
897 | * Fetch the APIC ID of the BSP in case we have a | |
898 | * default configuration (or the MP table is broken). | |
899 | */ | |
05f2d12c | 900 | boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id()); |
1da177e4 LT |
901 | } |
902 | ||
903 | /* | |
0e078e2f TG |
904 | * This initializes the IO-APIC and APIC hardware if this is |
905 | * a UP kernel. | |
1da177e4 | 906 | */ |
0e078e2f | 907 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 908 | { |
0e078e2f TG |
909 | if (disable_apic) { |
910 | printk(KERN_INFO "Apic disabled\n"); | |
911 | return -1; | |
912 | } | |
913 | if (!cpu_has_apic) { | |
914 | disable_apic = 1; | |
915 | printk(KERN_INFO "Apic disabled by BIOS\n"); | |
916 | return -1; | |
917 | } | |
1da177e4 | 918 | |
0e078e2f | 919 | verify_local_APIC(); |
1da177e4 | 920 | |
b5841765 GC |
921 | connect_bsp_APIC(); |
922 | ||
b6df1b8b | 923 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
c70dcb74 | 924 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
1da177e4 | 925 | |
0e078e2f | 926 | setup_local_APIC(); |
1da177e4 | 927 | |
739f33b3 AK |
928 | /* |
929 | * Now enable IO-APICs, actually call clear_IO_APIC | |
930 | * We need clear_IO_APIC before enabling vector on BP | |
931 | */ | |
932 | if (!skip_ioapic_setup && nr_ioapics) | |
933 | enable_IO_APIC(); | |
934 | ||
acae7d90 MR |
935 | if (!smp_found_config || skip_ioapic_setup || !nr_ioapics) |
936 | localise_nmi_watchdog(); | |
739f33b3 AK |
937 | end_local_APIC_setup(); |
938 | ||
0e078e2f TG |
939 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
940 | setup_IO_APIC(); | |
941 | else | |
942 | nr_ioapics = 0; | |
943 | setup_boot_APIC_clock(); | |
944 | check_nmi_watchdog(); | |
945 | return 0; | |
1da177e4 LT |
946 | } |
947 | ||
948 | /* | |
0e078e2f | 949 | * Local APIC interrupts |
1da177e4 LT |
950 | */ |
951 | ||
0e078e2f TG |
952 | /* |
953 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
954 | */ | |
955 | asmlinkage void smp_spurious_interrupt(void) | |
1da177e4 | 956 | { |
0e078e2f TG |
957 | unsigned int v; |
958 | exit_idle(); | |
959 | irq_enter(); | |
1da177e4 | 960 | /* |
0e078e2f TG |
961 | * Check if this really is a spurious interrupt and ACK it |
962 | * if it is a vectored one. Just in case... | |
963 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 964 | */ |
0e078e2f TG |
965 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
966 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
967 | ack_APIC_irq(); | |
c4d58cbd | 968 | |
0e078e2f TG |
969 | add_pda(irq_spurious_count, 1); |
970 | irq_exit(); | |
971 | } | |
1da177e4 | 972 | |
0e078e2f TG |
973 | /* |
974 | * This interrupt should never happen with our APIC/SMP architecture | |
975 | */ | |
976 | asmlinkage void smp_error_interrupt(void) | |
977 | { | |
978 | unsigned int v, v1; | |
1da177e4 | 979 | |
0e078e2f TG |
980 | exit_idle(); |
981 | irq_enter(); | |
982 | /* First tickle the hardware, only then report what went on. -- REW */ | |
983 | v = apic_read(APIC_ESR); | |
984 | apic_write(APIC_ESR, 0); | |
985 | v1 = apic_read(APIC_ESR); | |
986 | ack_APIC_irq(); | |
987 | atomic_inc(&irq_err_count); | |
ba7eda4c | 988 | |
0e078e2f TG |
989 | /* Here is what the APIC error bits mean: |
990 | 0: Send CS error | |
991 | 1: Receive CS error | |
992 | 2: Send accept error | |
993 | 3: Receive accept error | |
994 | 4: Reserved | |
995 | 5: Send illegal vector | |
996 | 6: Received illegal vector | |
997 | 7: Illegal register address | |
998 | */ | |
999 | printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n", | |
1000 | smp_processor_id(), v , v1); | |
1001 | irq_exit(); | |
1da177e4 LT |
1002 | } |
1003 | ||
b5841765 GC |
1004 | /** |
1005 | * * connect_bsp_APIC - attach the APIC to the interrupt system | |
1006 | * */ | |
1007 | void __init connect_bsp_APIC(void) | |
1008 | { | |
1009 | enable_apic_mode(); | |
1010 | } | |
1011 | ||
0e078e2f | 1012 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1013 | { |
0e078e2f TG |
1014 | /* Go back to Virtual Wire compatibility mode */ |
1015 | unsigned long value; | |
1da177e4 | 1016 | |
0e078e2f TG |
1017 | /* For the spurious interrupt use vector F, and enable it */ |
1018 | value = apic_read(APIC_SPIV); | |
1019 | value &= ~APIC_VECTOR_MASK; | |
1020 | value |= APIC_SPIV_APIC_ENABLED; | |
1021 | value |= 0xf; | |
1022 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1023 | |
0e078e2f TG |
1024 | if (!virt_wire_setup) { |
1025 | /* | |
1026 | * For LVT0 make it edge triggered, active high, | |
1027 | * external and enabled | |
1028 | */ | |
1029 | value = apic_read(APIC_LVT0); | |
1030 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1031 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1032 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1033 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1034 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1035 | apic_write(APIC_LVT0, value); | |
1036 | } else { | |
1037 | /* Disable LVT0 */ | |
1038 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1039 | } | |
b8ce3359 | 1040 | |
0e078e2f TG |
1041 | /* For LVT1 make it edge triggered, active high, nmi and enabled */ |
1042 | value = apic_read(APIC_LVT1); | |
1043 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1044 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1045 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1046 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1047 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1048 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1049 | } |
1050 | ||
be8a5685 AS |
1051 | void __cpuinit generic_processor_info(int apicid, int version) |
1052 | { | |
1053 | int cpu; | |
1054 | cpumask_t tmp_map; | |
1055 | ||
1056 | if (num_processors >= NR_CPUS) { | |
1057 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." | |
1058 | " Processor ignored.\n", NR_CPUS); | |
1059 | return; | |
1060 | } | |
1061 | ||
1062 | if (num_processors >= maxcpus) { | |
1063 | printk(KERN_WARNING "WARNING: maxcpus limit of %i reached." | |
1064 | " Processor ignored.\n", maxcpus); | |
1065 | return; | |
1066 | } | |
1067 | ||
1068 | num_processors++; | |
1069 | cpus_complement(tmp_map, cpu_present_map); | |
1070 | cpu = first_cpu(tmp_map); | |
1071 | ||
1072 | physid_set(apicid, phys_cpu_present_map); | |
1073 | if (apicid == boot_cpu_physical_apicid) { | |
1074 | /* | |
1075 | * x86_bios_cpu_apicid is required to have processors listed | |
1076 | * in same order as logical cpu numbers. Hence the first | |
1077 | * entry is BSP, and so on. | |
1078 | */ | |
1079 | cpu = 0; | |
1080 | } | |
e0da3364 YL |
1081 | if (apicid > max_physical_apicid) |
1082 | max_physical_apicid = apicid; | |
1083 | ||
be8a5685 | 1084 | /* are we being called early in kernel startup? */ |
23ca4bba MT |
1085 | if (early_per_cpu_ptr(x86_cpu_to_apicid)) { |
1086 | u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid); | |
1087 | u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); | |
be8a5685 AS |
1088 | |
1089 | cpu_to_apicid[cpu] = apicid; | |
1090 | bios_cpu_apicid[cpu] = apicid; | |
1091 | } else { | |
1092 | per_cpu(x86_cpu_to_apicid, cpu) = apicid; | |
1093 | per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1094 | } | |
1095 | ||
1096 | cpu_set(cpu, cpu_possible_map); | |
1097 | cpu_set(cpu, cpu_present_map); | |
1098 | } | |
1099 | ||
89039b37 | 1100 | /* |
0e078e2f | 1101 | * Power management |
89039b37 | 1102 | */ |
0e078e2f TG |
1103 | #ifdef CONFIG_PM |
1104 | ||
1105 | static struct { | |
1106 | /* 'active' is true if the local APIC was enabled by us and | |
1107 | not the BIOS; this signifies that we are also responsible | |
1108 | for disabling it before entering apm/acpi suspend */ | |
1109 | int active; | |
1110 | /* r/w apic fields */ | |
1111 | unsigned int apic_id; | |
1112 | unsigned int apic_taskpri; | |
1113 | unsigned int apic_ldr; | |
1114 | unsigned int apic_dfr; | |
1115 | unsigned int apic_spiv; | |
1116 | unsigned int apic_lvtt; | |
1117 | unsigned int apic_lvtpc; | |
1118 | unsigned int apic_lvt0; | |
1119 | unsigned int apic_lvt1; | |
1120 | unsigned int apic_lvterr; | |
1121 | unsigned int apic_tmict; | |
1122 | unsigned int apic_tdcr; | |
1123 | unsigned int apic_thmr; | |
1124 | } apic_pm_state; | |
1125 | ||
1126 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1127 | { | |
1128 | unsigned long flags; | |
1129 | int maxlvt; | |
89039b37 | 1130 | |
0e078e2f TG |
1131 | if (!apic_pm_state.active) |
1132 | return 0; | |
89039b37 | 1133 | |
0e078e2f | 1134 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 1135 | |
05f2d12c | 1136 | apic_pm_state.apic_id = read_apic_id(); |
0e078e2f TG |
1137 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
1138 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1139 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1140 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1141 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1142 | if (maxlvt >= 4) | |
1143 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1144 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1145 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1146 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1147 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1148 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
1149 | #ifdef CONFIG_X86_MCE_INTEL | |
1150 | if (maxlvt >= 5) | |
1151 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1152 | #endif | |
1153 | local_irq_save(flags); | |
1154 | disable_local_APIC(); | |
1155 | local_irq_restore(flags); | |
1156 | return 0; | |
1da177e4 LT |
1157 | } |
1158 | ||
0e078e2f | 1159 | static int lapic_resume(struct sys_device *dev) |
1da177e4 | 1160 | { |
0e078e2f TG |
1161 | unsigned int l, h; |
1162 | unsigned long flags; | |
1163 | int maxlvt; | |
1da177e4 | 1164 | |
0e078e2f TG |
1165 | if (!apic_pm_state.active) |
1166 | return 0; | |
89b831ef | 1167 | |
0e078e2f | 1168 | maxlvt = lapic_get_maxlvt(); |
1da177e4 | 1169 | |
0e078e2f TG |
1170 | local_irq_save(flags); |
1171 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1172 | l &= ~MSR_IA32_APICBASE_BASE; | |
1173 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1174 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1175 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); | |
1176 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1177 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1178 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1179 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1180 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1181 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1182 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
1183 | #ifdef CONFIG_X86_MCE_INTEL | |
1184 | if (maxlvt >= 5) | |
1185 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1186 | #endif | |
1187 | if (maxlvt >= 4) | |
1188 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1189 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
1190 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
1191 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
1192 | apic_write(APIC_ESR, 0); | |
1193 | apic_read(APIC_ESR); | |
1194 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
1195 | apic_write(APIC_ESR, 0); | |
1196 | apic_read(APIC_ESR); | |
1197 | local_irq_restore(flags); | |
1198 | return 0; | |
1199 | } | |
b8ce3359 | 1200 | |
0e078e2f TG |
1201 | static struct sysdev_class lapic_sysclass = { |
1202 | .name = "lapic", | |
1203 | .resume = lapic_resume, | |
1204 | .suspend = lapic_suspend, | |
1205 | }; | |
b8ce3359 | 1206 | |
0e078e2f | 1207 | static struct sys_device device_lapic = { |
e83a5fdc HS |
1208 | .id = 0, |
1209 | .cls = &lapic_sysclass, | |
0e078e2f | 1210 | }; |
b8ce3359 | 1211 | |
0e078e2f TG |
1212 | static void __cpuinit apic_pm_activate(void) |
1213 | { | |
1214 | apic_pm_state.active = 1; | |
1da177e4 LT |
1215 | } |
1216 | ||
0e078e2f | 1217 | static int __init init_lapic_sysfs(void) |
1da177e4 | 1218 | { |
0e078e2f | 1219 | int error; |
e83a5fdc | 1220 | |
0e078e2f TG |
1221 | if (!cpu_has_apic) |
1222 | return 0; | |
1223 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
e83a5fdc | 1224 | |
0e078e2f TG |
1225 | error = sysdev_class_register(&lapic_sysclass); |
1226 | if (!error) | |
1227 | error = sysdev_register(&device_lapic); | |
1228 | return error; | |
1da177e4 | 1229 | } |
0e078e2f TG |
1230 | device_initcall(init_lapic_sysfs); |
1231 | ||
1232 | #else /* CONFIG_PM */ | |
1233 | ||
1234 | static void apic_pm_activate(void) { } | |
1235 | ||
1236 | #endif /* CONFIG_PM */ | |
1da177e4 LT |
1237 | |
1238 | /* | |
f8bf3c65 | 1239 | * apic_is_clustered_box() -- Check if we can expect good TSC |
1da177e4 LT |
1240 | * |
1241 | * Thus far, the major user of this is IBM's Summit2 series: | |
1242 | * | |
637029c6 | 1243 | * Clustered boxes may have unsynced TSC problems if they are |
1da177e4 LT |
1244 | * multi-chassis. Use available data to take a good guess. |
1245 | * If in doubt, go HPET. | |
1246 | */ | |
f8bf3c65 | 1247 | __cpuinit int apic_is_clustered_box(void) |
1da177e4 LT |
1248 | { |
1249 | int i, clusters, zeros; | |
1250 | unsigned id; | |
322850af | 1251 | u16 *bios_cpu_apicid; |
1da177e4 LT |
1252 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
1253 | ||
322850af YL |
1254 | /* |
1255 | * there is not this kind of box with AMD CPU yet. | |
1256 | * Some AMD box with quadcore cpu and 8 sockets apicid | |
1257 | * will be [4, 0x23] or [8, 0x27] could be thought to | |
f8fffa45 | 1258 | * vsmp box still need checking... |
322850af | 1259 | */ |
1cb68487 | 1260 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box()) |
322850af YL |
1261 | return 0; |
1262 | ||
23ca4bba | 1263 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); |
376ec33f | 1264 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 LT |
1265 | |
1266 | for (i = 0; i < NR_CPUS; i++) { | |
e8c10ef9 | 1267 | /* are we being called early in kernel startup? */ |
693e3c56 MT |
1268 | if (bios_cpu_apicid) { |
1269 | id = bios_cpu_apicid[i]; | |
e8c10ef9 | 1270 | } |
1271 | else if (i < nr_cpu_ids) { | |
1272 | if (cpu_present(i)) | |
1273 | id = per_cpu(x86_bios_cpu_apicid, i); | |
1274 | else | |
1275 | continue; | |
1276 | } | |
1277 | else | |
1278 | break; | |
1279 | ||
1da177e4 LT |
1280 | if (id != BAD_APICID) |
1281 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
1282 | } | |
1283 | ||
1284 | /* Problem: Partially populated chassis may not have CPUs in some of | |
1285 | * the APIC clusters they have been allocated. Only present CPUs have | |
602a54a8 | 1286 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
1287 | * Since clusters are allocated sequentially, count zeros only if | |
1288 | * they are bounded by ones. | |
1da177e4 LT |
1289 | */ |
1290 | clusters = 0; | |
1291 | zeros = 0; | |
1292 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
1293 | if (test_bit(i, clustermap)) { | |
1294 | clusters += 1 + zeros; | |
1295 | zeros = 0; | |
1296 | } else | |
1297 | ++zeros; | |
1298 | } | |
1299 | ||
1cb68487 RT |
1300 | /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
1301 | * not guaranteed to be synced between boards | |
1302 | */ | |
1303 | if (is_vsmp_box() && clusters > 1) | |
1304 | return 1; | |
1305 | ||
1da177e4 | 1306 | /* |
f8bf3c65 | 1307 | * If clusters > 2, then should be multi-chassis. |
1da177e4 LT |
1308 | * May have to revisit this when multi-core + hyperthreaded CPUs come |
1309 | * out, but AFAIK this will work even for them. | |
1310 | */ | |
1311 | return (clusters > 2); | |
1312 | } | |
1313 | ||
1314 | /* | |
0e078e2f | 1315 | * APIC command line parameters |
1da177e4 | 1316 | */ |
0e078e2f | 1317 | static int __init apic_set_verbosity(char *str) |
1da177e4 | 1318 | { |
0e078e2f TG |
1319 | if (str == NULL) { |
1320 | skip_ioapic_setup = 0; | |
1321 | ioapic_force = 1; | |
1322 | return 0; | |
1da177e4 | 1323 | } |
0e078e2f TG |
1324 | if (strcmp("debug", str) == 0) |
1325 | apic_verbosity = APIC_DEBUG; | |
1326 | else if (strcmp("verbose", str) == 0) | |
1327 | apic_verbosity = APIC_VERBOSE; | |
1328 | else { | |
1329 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | |
1330 | " use apic=verbose or apic=debug\n", str); | |
1331 | return -EINVAL; | |
1da177e4 LT |
1332 | } |
1333 | ||
1da177e4 LT |
1334 | return 0; |
1335 | } | |
0e078e2f | 1336 | early_param("apic", apic_set_verbosity); |
1da177e4 | 1337 | |
6935d1f9 TG |
1338 | static __init int setup_disableapic(char *str) |
1339 | { | |
1da177e4 | 1340 | disable_apic = 1; |
53756d37 | 1341 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
2c8c0e6b AK |
1342 | return 0; |
1343 | } | |
1344 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 1345 | |
2c8c0e6b | 1346 | /* same as disableapic, for compatibility */ |
6935d1f9 TG |
1347 | static __init int setup_nolapic(char *str) |
1348 | { | |
2c8c0e6b | 1349 | return setup_disableapic(str); |
6935d1f9 | 1350 | } |
2c8c0e6b | 1351 | early_param("nolapic", setup_nolapic); |
1da177e4 | 1352 | |
2e7c2838 LT |
1353 | static int __init parse_lapic_timer_c2_ok(char *arg) |
1354 | { | |
1355 | local_apic_timer_c2_ok = 1; | |
1356 | return 0; | |
1357 | } | |
1358 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
1359 | ||
6935d1f9 TG |
1360 | static __init int setup_noapictimer(char *str) |
1361 | { | |
73dea47f | 1362 | if (str[0] != ' ' && str[0] != 0) |
9b41046c | 1363 | return 0; |
1da177e4 | 1364 | disable_apic_timer = 1; |
9b41046c | 1365 | return 1; |
6935d1f9 | 1366 | } |
9f75e9b7 | 1367 | __setup("noapictimer", setup_noapictimer); |
73dea47f | 1368 | |
0c3749c4 AK |
1369 | static __init int setup_apicpmtimer(char *s) |
1370 | { | |
1371 | apic_calibrate_pmtmr = 1; | |
7fd67843 | 1372 | notsc_setup(NULL); |
b8ce3359 | 1373 | return 0; |
0c3749c4 AK |
1374 | } |
1375 | __setup("apicpmtimer", setup_apicpmtimer); | |
1376 | ||
1e934dda YL |
1377 | static int __init lapic_insert_resource(void) |
1378 | { | |
1379 | if (!apic_phys) | |
1380 | return -1; | |
1381 | ||
1382 | /* Put local APIC into the resource map. */ | |
1383 | lapic_resource.start = apic_phys; | |
1384 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
1385 | insert_resource(&iomem_resource, &lapic_resource); | |
1386 | ||
1387 | return 0; | |
1388 | } | |
1389 | ||
1390 | /* | |
1391 | * need call insert after e820_reserve_resources() | |
1392 | * that is using request_resource | |
1393 | */ | |
1394 | late_initcall(lapic_insert_resource); |