]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
39928722 | 26 | #include <linux/ioport.h> |
ba7eda4c | 27 | #include <linux/clockchips.h> |
70a20025 | 28 | #include <linux/acpi_pmtmr.h> |
e83a5fdc | 29 | #include <linux/module.h> |
6e1cb38a | 30 | #include <linux/dmar.h> |
1da177e4 LT |
31 | |
32 | #include <asm/atomic.h> | |
33 | #include <asm/smp.h> | |
34 | #include <asm/mtrr.h> | |
35 | #include <asm/mpspec.h> | |
efa2559f | 36 | #include <asm/desc.h> |
e83a5fdc | 37 | #include <asm/hpet.h> |
1da177e4 | 38 | #include <asm/pgalloc.h> |
75152114 | 39 | #include <asm/nmi.h> |
95833c83 | 40 | #include <asm/idle.h> |
73dea47f AK |
41 | #include <asm/proto.h> |
42 | #include <asm/timex.h> | |
2c8c0e6b | 43 | #include <asm/apic.h> |
6e1cb38a | 44 | #include <asm/i8259.h> |
1da177e4 | 45 | |
5af5573e | 46 | #include <mach_ipi.h> |
dd46e3ca | 47 | #include <mach_apic.h> |
5af5573e | 48 | |
80e5609c CG |
49 | /* |
50 | * Sanity check | |
51 | */ | |
52 | #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F) | |
53 | # error SPURIOUS_APIC_VECTOR definition error | |
54 | #endif | |
55 | ||
b3c51170 YL |
56 | #ifdef CONFIG_X86_32 |
57 | /* | |
58 | * Knob to control our willingness to enable the local APIC. | |
59 | * | |
60 | * +1=force-enable | |
61 | */ | |
62 | static int force_enable_local_apic; | |
63 | /* | |
64 | * APIC command line parameters | |
65 | */ | |
66 | static int __init parse_lapic(char *arg) | |
67 | { | |
68 | force_enable_local_apic = 1; | |
69 | return 0; | |
70 | } | |
71 | early_param("lapic", parse_lapic); | |
72 | #endif | |
73 | ||
74 | #ifdef CONFIG_X86_64 | |
bc1d99c1 | 75 | static int apic_calibrate_pmtmr __initdata; |
b3c51170 YL |
76 | static __init int setup_apicpmtimer(char *s) |
77 | { | |
78 | apic_calibrate_pmtmr = 1; | |
79 | notsc_setup(NULL); | |
80 | return 0; | |
81 | } | |
82 | __setup("apicpmtimer", setup_apicpmtimer); | |
83 | #endif | |
84 | ||
6e1cb38a | 85 | int disable_x2apic; |
89027d35 | 86 | int x2apic; |
6e1cb38a SS |
87 | /* x2apic enabled before OS handover */ |
88 | int x2apic_preenabled; | |
1da177e4 | 89 | |
b3c51170 YL |
90 | unsigned long mp_lapic_addr; |
91 | int disable_apic; | |
92 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ | |
93 | static int disable_apic_timer __cpuinitdata; | |
e83a5fdc | 94 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
95 | int local_apic_timer_c2_ok; |
96 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
97 | ||
efa2559f YL |
98 | int first_system_vector = 0xfe; |
99 | ||
100 | char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE}; | |
101 | ||
e83a5fdc HS |
102 | /* |
103 | * Debug level, exported for io_apic.c | |
104 | */ | |
baa13188 | 105 | unsigned int apic_verbosity; |
e83a5fdc | 106 | |
89c38c28 CG |
107 | int pic_mode; |
108 | ||
bab4b27c AS |
109 | /* Have we found an MP table */ |
110 | int smp_found_config; | |
111 | ||
39928722 AD |
112 | static struct resource lapic_resource = { |
113 | .name = "Local APIC", | |
114 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
115 | }; | |
116 | ||
d03030e9 TG |
117 | static unsigned int calibration_result; |
118 | ||
ba7eda4c TG |
119 | static int lapic_next_event(unsigned long delta, |
120 | struct clock_event_device *evt); | |
121 | static void lapic_timer_setup(enum clock_event_mode mode, | |
122 | struct clock_event_device *evt); | |
ba7eda4c | 123 | static void lapic_timer_broadcast(cpumask_t mask); |
0e078e2f | 124 | static void apic_pm_activate(void); |
ba7eda4c | 125 | |
274cfe59 CG |
126 | /* |
127 | * The local apic timer can be used for any function which is CPU local. | |
128 | */ | |
ba7eda4c TG |
129 | static struct clock_event_device lapic_clockevent = { |
130 | .name = "lapic", | |
131 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
132 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
133 | .shift = 32, | |
134 | .set_mode = lapic_timer_setup, | |
135 | .set_next_event = lapic_next_event, | |
136 | .broadcast = lapic_timer_broadcast, | |
137 | .rating = 100, | |
138 | .irq = -1, | |
139 | }; | |
140 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
141 | ||
d3432896 AK |
142 | static unsigned long apic_phys; |
143 | ||
0e078e2f TG |
144 | /* |
145 | * Get the LAPIC version | |
146 | */ | |
147 | static inline int lapic_get_version(void) | |
ba7eda4c | 148 | { |
0e078e2f | 149 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
150 | } |
151 | ||
0e078e2f | 152 | /* |
9c803869 | 153 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
154 | */ |
155 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 156 | { |
9c803869 | 157 | #ifdef CONFIG_X86_64 |
0e078e2f | 158 | return 1; |
9c803869 CG |
159 | #else |
160 | return APIC_INTEGRATED(lapic_get_version()); | |
161 | #endif | |
ba7eda4c TG |
162 | } |
163 | ||
164 | /* | |
0e078e2f | 165 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 166 | */ |
0e078e2f | 167 | static int modern_apic(void) |
ba7eda4c | 168 | { |
0e078e2f TG |
169 | /* AMD systems use old APIC versions, so check the CPU */ |
170 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
171 | boot_cpu_data.x86 >= 0xf) | |
172 | return 1; | |
173 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
174 | } |
175 | ||
274cfe59 CG |
176 | /* |
177 | * Paravirt kernels also might be using these below ops. So we still | |
178 | * use generic apic_read()/apic_write(), which might be pointing to different | |
179 | * ops in PARAVIRT case. | |
180 | */ | |
1b374e4d | 181 | void xapic_wait_icr_idle(void) |
8339e9fb FLV |
182 | { |
183 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
184 | cpu_relax(); | |
185 | } | |
186 | ||
1b374e4d | 187 | u32 safe_xapic_wait_icr_idle(void) |
8339e9fb | 188 | { |
3c6bb07a | 189 | u32 send_status; |
8339e9fb FLV |
190 | int timeout; |
191 | ||
192 | timeout = 0; | |
193 | do { | |
194 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
195 | if (!send_status) | |
196 | break; | |
197 | udelay(100); | |
198 | } while (timeout++ < 1000); | |
199 | ||
200 | return send_status; | |
201 | } | |
202 | ||
1b374e4d SS |
203 | void xapic_icr_write(u32 low, u32 id) |
204 | { | |
ed4e5ec1 | 205 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
1b374e4d SS |
206 | apic_write(APIC_ICR, low); |
207 | } | |
208 | ||
209 | u64 xapic_icr_read(void) | |
210 | { | |
211 | u32 icr1, icr2; | |
212 | ||
213 | icr2 = apic_read(APIC_ICR2); | |
214 | icr1 = apic_read(APIC_ICR); | |
215 | ||
cf9768d7 | 216 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
217 | } |
218 | ||
219 | static struct apic_ops xapic_ops = { | |
220 | .read = native_apic_mem_read, | |
221 | .write = native_apic_mem_write, | |
1b374e4d SS |
222 | .icr_read = xapic_icr_read, |
223 | .icr_write = xapic_icr_write, | |
224 | .wait_icr_idle = xapic_wait_icr_idle, | |
225 | .safe_wait_icr_idle = safe_xapic_wait_icr_idle, | |
226 | }; | |
227 | ||
228 | struct apic_ops __read_mostly *apic_ops = &xapic_ops; | |
1b374e4d SS |
229 | EXPORT_SYMBOL_GPL(apic_ops); |
230 | ||
13c88fb5 SS |
231 | static void x2apic_wait_icr_idle(void) |
232 | { | |
233 | /* no need to wait for icr idle in x2apic */ | |
234 | return; | |
235 | } | |
236 | ||
237 | static u32 safe_x2apic_wait_icr_idle(void) | |
238 | { | |
239 | /* no need to wait for icr idle in x2apic */ | |
240 | return 0; | |
241 | } | |
242 | ||
243 | void x2apic_icr_write(u32 low, u32 id) | |
244 | { | |
245 | wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); | |
246 | } | |
247 | ||
248 | u64 x2apic_icr_read(void) | |
249 | { | |
250 | unsigned long val; | |
251 | ||
252 | rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); | |
253 | return val; | |
254 | } | |
255 | ||
256 | static struct apic_ops x2apic_ops = { | |
257 | .read = native_apic_msr_read, | |
258 | .write = native_apic_msr_write, | |
13c88fb5 SS |
259 | .icr_read = x2apic_icr_read, |
260 | .icr_write = x2apic_icr_write, | |
261 | .wait_icr_idle = x2apic_wait_icr_idle, | |
262 | .safe_wait_icr_idle = safe_x2apic_wait_icr_idle, | |
263 | }; | |
264 | ||
0e078e2f TG |
265 | /** |
266 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
267 | */ | |
e9427101 | 268 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 269 | { |
11a8e778 | 270 | unsigned int v; |
6935d1f9 TG |
271 | |
272 | /* unmask and set to NMI */ | |
273 | v = APIC_DM_NMI; | |
d4c63ec0 CG |
274 | |
275 | /* Level triggered for 82489DX (32bit mode) */ | |
276 | if (!lapic_is_integrated()) | |
277 | v |= APIC_LVT_LEVEL_TRIGGER; | |
278 | ||
11a8e778 | 279 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
280 | } |
281 | ||
7c37e48b CG |
282 | #ifdef CONFIG_X86_32 |
283 | /** | |
284 | * get_physical_broadcast - Get number of physical broadcast IDs | |
285 | */ | |
286 | int get_physical_broadcast(void) | |
287 | { | |
288 | return modern_apic() ? 0xff : 0xf; | |
289 | } | |
290 | #endif | |
291 | ||
0e078e2f TG |
292 | /** |
293 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
294 | */ | |
37e650c7 | 295 | int lapic_get_maxlvt(void) |
1da177e4 | 296 | { |
36a028de | 297 | unsigned int v; |
1da177e4 LT |
298 | |
299 | v = apic_read(APIC_LVR); | |
36a028de CG |
300 | /* |
301 | * - we always have APIC integrated on 64bit mode | |
302 | * - 82489DXs do not report # of LVT entries | |
303 | */ | |
304 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; | |
1da177e4 LT |
305 | } |
306 | ||
274cfe59 CG |
307 | /* |
308 | * Local APIC timer | |
309 | */ | |
310 | ||
c40aaec6 CG |
311 | /* Clock divisor */ |
312 | #ifdef CONFG_X86_64 | |
f07f4f90 | 313 | #define APIC_DIVISOR 1 |
c40aaec6 CG |
314 | #else |
315 | #define APIC_DIVISOR 16 | |
316 | #endif | |
f07f4f90 | 317 | |
0e078e2f TG |
318 | /* |
319 | * This function sets up the local APIC timer, with a timeout of | |
320 | * 'clocks' APIC bus clock. During calibration we actually call | |
321 | * this function twice on the boot CPU, once with a bogus timeout | |
322 | * value, second time for real. The other (noncalibrating) CPUs | |
323 | * call this function only once, with the real, calibrated value. | |
324 | * | |
325 | * We do reads before writes even if unnecessary, to get around the | |
326 | * P5 APIC double write bug. | |
327 | */ | |
0e078e2f | 328 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 329 | { |
0e078e2f | 330 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 331 | |
0e078e2f TG |
332 | lvtt_value = LOCAL_TIMER_VECTOR; |
333 | if (!oneshot) | |
334 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
f07f4f90 CG |
335 | if (!lapic_is_integrated()) |
336 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
337 | ||
0e078e2f TG |
338 | if (!irqen) |
339 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 340 | |
0e078e2f | 341 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
342 | |
343 | /* | |
0e078e2f | 344 | * Divide PICLK by 16 |
1da177e4 | 345 | */ |
0e078e2f | 346 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
347 | apic_write(APIC_TDCR, |
348 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
349 | APIC_TDR_DIV_16); | |
0e078e2f TG |
350 | |
351 | if (!oneshot) | |
f07f4f90 | 352 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
353 | } |
354 | ||
0e078e2f | 355 | /* |
7b83dae7 RR |
356 | * Setup extended LVT, AMD specific (K8, family 10h) |
357 | * | |
358 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
359 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
286f5718 RR |
360 | * |
361 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
362 | * enables the vector. See also the BKDGs. | |
0e078e2f | 363 | */ |
7b83dae7 RR |
364 | |
365 | #define APIC_EILVT_LVTOFF_MCE 0 | |
366 | #define APIC_EILVT_LVTOFF_IBS 1 | |
367 | ||
368 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
1da177e4 | 369 | { |
7b83dae7 | 370 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; |
0e078e2f | 371 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; |
a8fcf1a2 | 372 | |
0e078e2f | 373 | apic_write(reg, v); |
1da177e4 LT |
374 | } |
375 | ||
7b83dae7 RR |
376 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) |
377 | { | |
378 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
379 | return APIC_EILVT_LVTOFF_MCE; | |
380 | } | |
381 | ||
382 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
383 | { | |
384 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
385 | return APIC_EILVT_LVTOFF_IBS; | |
386 | } | |
6aa360e6 | 387 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs); |
7b83dae7 | 388 | |
0e078e2f TG |
389 | /* |
390 | * Program the next event, relative to now | |
391 | */ | |
392 | static int lapic_next_event(unsigned long delta, | |
393 | struct clock_event_device *evt) | |
1da177e4 | 394 | { |
0e078e2f TG |
395 | apic_write(APIC_TMICT, delta); |
396 | return 0; | |
1da177e4 LT |
397 | } |
398 | ||
0e078e2f TG |
399 | /* |
400 | * Setup the lapic timer in periodic or oneshot mode | |
401 | */ | |
402 | static void lapic_timer_setup(enum clock_event_mode mode, | |
403 | struct clock_event_device *evt) | |
9b7711f0 HS |
404 | { |
405 | unsigned long flags; | |
0e078e2f | 406 | unsigned int v; |
9b7711f0 | 407 | |
0e078e2f TG |
408 | /* Lapic used as dummy for broadcast ? */ |
409 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
410 | return; |
411 | ||
412 | local_irq_save(flags); | |
413 | ||
0e078e2f TG |
414 | switch (mode) { |
415 | case CLOCK_EVT_MODE_PERIODIC: | |
416 | case CLOCK_EVT_MODE_ONESHOT: | |
417 | __setup_APIC_LVTT(calibration_result, | |
418 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
419 | break; | |
420 | case CLOCK_EVT_MODE_UNUSED: | |
421 | case CLOCK_EVT_MODE_SHUTDOWN: | |
422 | v = apic_read(APIC_LVTT); | |
423 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
424 | apic_write(APIC_LVTT, v); | |
425 | break; | |
426 | case CLOCK_EVT_MODE_RESUME: | |
427 | /* Nothing to do here */ | |
428 | break; | |
429 | } | |
9b7711f0 HS |
430 | |
431 | local_irq_restore(flags); | |
432 | } | |
433 | ||
1da177e4 | 434 | /* |
0e078e2f | 435 | * Local APIC timer broadcast function |
1da177e4 | 436 | */ |
0e078e2f | 437 | static void lapic_timer_broadcast(cpumask_t mask) |
1da177e4 | 438 | { |
0e078e2f TG |
439 | #ifdef CONFIG_SMP |
440 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
441 | #endif | |
442 | } | |
1da177e4 | 443 | |
0e078e2f TG |
444 | /* |
445 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
446 | * of the boot CPU and register the clock event in the framework. | |
447 | */ | |
db4b5525 | 448 | static void __cpuinit setup_APIC_timer(void) |
0e078e2f TG |
449 | { |
450 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 451 | |
0e078e2f TG |
452 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
453 | levt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
1da177e4 | 454 | |
0e078e2f TG |
455 | clockevents_register_device(levt); |
456 | } | |
1da177e4 | 457 | |
0e078e2f TG |
458 | /* |
459 | * In this function we calibrate APIC bus clocks to the external | |
460 | * timer. Unfortunately we cannot use jiffies and the timer irq | |
461 | * to calibrate, since some later bootup code depends on getting | |
462 | * the first irq? Ugh. | |
463 | * | |
464 | * We want to do the calibration only once since we | |
465 | * want to have local timer irqs syncron. CPUs connected | |
466 | * by the same APIC bus have the very same bus frequency. | |
467 | * And we want to have irqs off anyways, no accidental | |
468 | * APIC irq that way. | |
469 | */ | |
470 | ||
471 | #define TICK_COUNT 100000000 | |
472 | ||
89b3b1f4 | 473 | static int __init calibrate_APIC_clock(void) |
0e078e2f TG |
474 | { |
475 | unsigned apic, apic_start; | |
476 | unsigned long tsc, tsc_start; | |
477 | int result; | |
478 | ||
479 | local_irq_disable(); | |
480 | ||
481 | /* | |
482 | * Put whatever arbitrary (but long enough) timeout | |
483 | * value into the APIC clock, we just want to get the | |
484 | * counter running for calibration. | |
485 | * | |
486 | * No interrupt enable ! | |
487 | */ | |
488 | __setup_APIC_LVTT(250000000, 0, 0); | |
489 | ||
490 | apic_start = apic_read(APIC_TMCCT); | |
491 | #ifdef CONFIG_X86_PM_TIMER | |
492 | if (apic_calibrate_pmtmr && pmtmr_ioport) { | |
493 | pmtimer_wait(5000); /* 5ms wait */ | |
494 | apic = apic_read(APIC_TMCCT); | |
495 | result = (apic_start - apic) * 1000L / 5; | |
496 | } else | |
497 | #endif | |
498 | { | |
499 | rdtscll(tsc_start); | |
500 | ||
501 | do { | |
502 | apic = apic_read(APIC_TMCCT); | |
503 | rdtscll(tsc); | |
504 | } while ((tsc - tsc_start) < TICK_COUNT && | |
505 | (apic_start - apic) < TICK_COUNT); | |
506 | ||
507 | result = (apic_start - apic) * 1000L * tsc_khz / | |
508 | (tsc - tsc_start); | |
509 | } | |
510 | ||
511 | local_irq_enable(); | |
512 | ||
513 | printk(KERN_DEBUG "APIC timer calibration result %d\n", result); | |
514 | ||
515 | printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n", | |
516 | result / 1000 / 1000, result / 1000 % 1000); | |
517 | ||
518 | /* Calculate the scaled math multiplication factor */ | |
877084fb AM |
519 | lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC, |
520 | lapic_clockevent.shift); | |
0e078e2f TG |
521 | lapic_clockevent.max_delta_ns = |
522 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
523 | lapic_clockevent.min_delta_ns = | |
524 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
525 | ||
f07f4f90 | 526 | calibration_result = (result * APIC_DIVISOR) / HZ; |
89b3b1f4 CG |
527 | |
528 | /* | |
529 | * Do a sanity check on the APIC calibration result | |
530 | */ | |
531 | if (calibration_result < (1000000 / HZ)) { | |
532 | printk(KERN_WARNING | |
533 | "APIC frequency too slow, disabling apic timer\n"); | |
534 | return -1; | |
535 | } | |
536 | ||
537 | return 0; | |
0e078e2f TG |
538 | } |
539 | ||
e83a5fdc HS |
540 | /* |
541 | * Setup the boot APIC | |
542 | * | |
543 | * Calibrate and verify the result. | |
544 | */ | |
0e078e2f TG |
545 | void __init setup_boot_APIC_clock(void) |
546 | { | |
547 | /* | |
274cfe59 CG |
548 | * The local apic timer can be disabled via the kernel |
549 | * commandline or from the CPU detection code. Register the lapic | |
550 | * timer as a dummy clock event source on SMP systems, so the | |
551 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
552 | */ |
553 | if (disable_apic_timer) { | |
554 | printk(KERN_INFO "Disabling APIC timer\n"); | |
555 | /* No broadcast on UP ! */ | |
9d09951d TG |
556 | if (num_possible_cpus() > 1) { |
557 | lapic_clockevent.mult = 1; | |
0e078e2f | 558 | setup_APIC_timer(); |
9d09951d | 559 | } |
0e078e2f TG |
560 | return; |
561 | } | |
562 | ||
274cfe59 CG |
563 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
564 | "calibrating APIC timer ...\n"); | |
565 | ||
89b3b1f4 | 566 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
567 | /* No broadcast on UP ! */ |
568 | if (num_possible_cpus() > 1) | |
569 | setup_APIC_timer(); | |
570 | return; | |
571 | } | |
572 | ||
0e078e2f TG |
573 | /* |
574 | * If nmi_watchdog is set to IO_APIC, we need the | |
575 | * PIT/HPET going. Otherwise register lapic as a dummy | |
576 | * device. | |
577 | */ | |
578 | if (nmi_watchdog != NMI_IO_APIC) | |
579 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
580 | else | |
581 | printk(KERN_WARNING "APIC timer registered as dummy," | |
116f570e | 582 | " due to nmi_watchdog=%d!\n", nmi_watchdog); |
0e078e2f | 583 | |
274cfe59 | 584 | /* Setup the lapic or request the broadcast */ |
0e078e2f TG |
585 | setup_APIC_timer(); |
586 | } | |
587 | ||
0e078e2f TG |
588 | void __cpuinit setup_secondary_APIC_clock(void) |
589 | { | |
0e078e2f TG |
590 | setup_APIC_timer(); |
591 | } | |
592 | ||
593 | /* | |
594 | * The guts of the apic timer interrupt | |
595 | */ | |
596 | static void local_apic_timer_interrupt(void) | |
597 | { | |
598 | int cpu = smp_processor_id(); | |
599 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
600 | ||
601 | /* | |
602 | * Normally we should not be here till LAPIC has been initialized but | |
603 | * in some cases like kdump, its possible that there is a pending LAPIC | |
604 | * timer interrupt from previous kernel's context and is delivered in | |
605 | * new kernel the moment interrupts are enabled. | |
606 | * | |
607 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
608 | * its possible that when we get here evt->event_handler is NULL. | |
609 | * Check for event_handler being NULL and discard the interrupt as | |
610 | * spurious. | |
611 | */ | |
612 | if (!evt->event_handler) { | |
613 | printk(KERN_WARNING | |
614 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | |
615 | /* Switch it off */ | |
616 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
617 | return; | |
618 | } | |
619 | ||
620 | /* | |
621 | * the NMI deadlock-detector uses this. | |
622 | */ | |
0b23e8cf | 623 | #ifdef CONFIG_X86_64 |
0e078e2f | 624 | add_pda(apic_timer_irqs, 1); |
0b23e8cf CG |
625 | #else |
626 | per_cpu(irq_stat, cpu).apic_timer_irqs++; | |
627 | #endif | |
0e078e2f TG |
628 | |
629 | evt->event_handler(evt); | |
630 | } | |
631 | ||
632 | /* | |
633 | * Local APIC timer interrupt. This is the most natural way for doing | |
634 | * local interrupts, but local timer interrupts can be emulated by | |
635 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
636 | * | |
637 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
638 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
639 | */ | |
640 | void smp_apic_timer_interrupt(struct pt_regs *regs) | |
641 | { | |
642 | struct pt_regs *old_regs = set_irq_regs(regs); | |
643 | ||
644 | /* | |
645 | * NOTE! We'd better ACK the irq immediately, | |
646 | * because timer handling can be slow. | |
647 | */ | |
648 | ack_APIC_irq(); | |
649 | /* | |
650 | * update_process_times() expects us to have done irq_enter(). | |
651 | * Besides, if we don't timer interrupts ignore the global | |
652 | * interrupt lock, which is the WrongThing (tm) to do. | |
653 | */ | |
6460bc73 | 654 | #ifdef CONFIG_X86_64 |
0e078e2f | 655 | exit_idle(); |
6460bc73 | 656 | #endif |
0e078e2f TG |
657 | irq_enter(); |
658 | local_apic_timer_interrupt(); | |
659 | irq_exit(); | |
274cfe59 | 660 | |
0e078e2f TG |
661 | set_irq_regs(old_regs); |
662 | } | |
663 | ||
664 | int setup_profiling_timer(unsigned int multiplier) | |
665 | { | |
666 | return -EINVAL; | |
667 | } | |
668 | ||
669 | ||
670 | /* | |
671 | * Local APIC start and shutdown | |
672 | */ | |
673 | ||
674 | /** | |
675 | * clear_local_APIC - shutdown the local APIC | |
676 | * | |
677 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
678 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
679 | * leftovers during boot. | |
680 | */ | |
681 | void clear_local_APIC(void) | |
682 | { | |
2584a82d | 683 | int maxlvt; |
0e078e2f TG |
684 | u32 v; |
685 | ||
d3432896 AK |
686 | /* APIC hasn't been mapped yet */ |
687 | if (!apic_phys) | |
688 | return; | |
689 | ||
690 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
691 | /* |
692 | * Masking an LVT entry can trigger a local APIC error | |
693 | * if the vector is zero. Mask LVTERR first to prevent this. | |
694 | */ | |
695 | if (maxlvt >= 3) { | |
696 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
697 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
698 | } | |
699 | /* | |
700 | * Careful: we have to set masks only first to deassert | |
701 | * any level-triggered sources. | |
702 | */ | |
703 | v = apic_read(APIC_LVTT); | |
704 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
705 | v = apic_read(APIC_LVT0); | |
706 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
707 | v = apic_read(APIC_LVT1); | |
708 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
709 | if (maxlvt >= 4) { | |
710 | v = apic_read(APIC_LVTPC); | |
711 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
712 | } | |
713 | ||
6764014b CG |
714 | /* lets not touch this if we didn't frob it */ |
715 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL) | |
716 | if (maxlvt >= 5) { | |
717 | v = apic_read(APIC_LVTTHMR); | |
718 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
719 | } | |
720 | #endif | |
0e078e2f TG |
721 | /* |
722 | * Clean APIC state for other OSs: | |
723 | */ | |
724 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
725 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
726 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
727 | if (maxlvt >= 3) | |
728 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
729 | if (maxlvt >= 4) | |
730 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
731 | |
732 | /* Integrated APIC (!82489DX) ? */ | |
733 | if (lapic_is_integrated()) { | |
734 | if (maxlvt > 3) | |
735 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
736 | apic_write(APIC_ESR, 0); | |
737 | apic_read(APIC_ESR); | |
738 | } | |
0e078e2f TG |
739 | } |
740 | ||
741 | /** | |
742 | * disable_local_APIC - clear and disable the local APIC | |
743 | */ | |
744 | void disable_local_APIC(void) | |
745 | { | |
746 | unsigned int value; | |
747 | ||
748 | clear_local_APIC(); | |
749 | ||
750 | /* | |
751 | * Disable APIC (implies clearing of registers | |
752 | * for 82489DX!). | |
753 | */ | |
754 | value = apic_read(APIC_SPIV); | |
755 | value &= ~APIC_SPIV_APIC_ENABLED; | |
756 | apic_write(APIC_SPIV, value); | |
990b183e CG |
757 | |
758 | #ifdef CONFIG_X86_32 | |
759 | /* | |
760 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
761 | * restore the disabled state. | |
762 | */ | |
763 | if (enabled_via_apicbase) { | |
764 | unsigned int l, h; | |
765 | ||
766 | rdmsr(MSR_IA32_APICBASE, l, h); | |
767 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
768 | wrmsr(MSR_IA32_APICBASE, l, h); | |
769 | } | |
770 | #endif | |
0e078e2f TG |
771 | } |
772 | ||
fe4024dc CG |
773 | /* |
774 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
775 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
776 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
777 | * for the case where Linux didn't enable the LAPIC. | |
778 | */ | |
0e078e2f TG |
779 | void lapic_shutdown(void) |
780 | { | |
781 | unsigned long flags; | |
782 | ||
783 | if (!cpu_has_apic) | |
784 | return; | |
785 | ||
786 | local_irq_save(flags); | |
787 | ||
fe4024dc CG |
788 | #ifdef CONFIG_X86_32 |
789 | if (!enabled_via_apicbase) | |
790 | clear_local_APIC(); | |
791 | else | |
792 | #endif | |
793 | disable_local_APIC(); | |
794 | ||
0e078e2f TG |
795 | |
796 | local_irq_restore(flags); | |
797 | } | |
798 | ||
799 | /* | |
800 | * This is to verify that we're looking at a real local APIC. | |
801 | * Check these against your board if the CPUs aren't getting | |
802 | * started for no apparent reason. | |
803 | */ | |
804 | int __init verify_local_APIC(void) | |
805 | { | |
806 | unsigned int reg0, reg1; | |
807 | ||
808 | /* | |
809 | * The version register is read-only in a real APIC. | |
810 | */ | |
811 | reg0 = apic_read(APIC_LVR); | |
812 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
813 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
814 | reg1 = apic_read(APIC_LVR); | |
815 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
816 | ||
817 | /* | |
818 | * The two version reads above should print the same | |
819 | * numbers. If the second one is different, then we | |
820 | * poke at a non-APIC. | |
821 | */ | |
822 | if (reg1 != reg0) | |
823 | return 0; | |
824 | ||
825 | /* | |
826 | * Check if the version looks reasonably. | |
827 | */ | |
828 | reg1 = GET_APIC_VERSION(reg0); | |
829 | if (reg1 == 0x00 || reg1 == 0xff) | |
830 | return 0; | |
831 | reg1 = lapic_get_maxlvt(); | |
832 | if (reg1 < 0x02 || reg1 == 0xff) | |
833 | return 0; | |
834 | ||
835 | /* | |
836 | * The ID register is read/write in a real APIC. | |
837 | */ | |
2d7a66d0 | 838 | reg0 = apic_read(APIC_ID); |
0e078e2f TG |
839 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
840 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
2d7a66d0 | 841 | reg1 = apic_read(APIC_ID); |
0e078e2f TG |
842 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
843 | apic_write(APIC_ID, reg0); | |
844 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
845 | return 0; | |
846 | ||
847 | /* | |
1da177e4 LT |
848 | * The next two are just to see if we have sane values. |
849 | * They're only really relevant if we're in Virtual Wire | |
850 | * compatibility mode, but most boxes are anymore. | |
851 | */ | |
852 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 853 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
854 | reg1 = apic_read(APIC_LVT1); |
855 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
856 | ||
857 | return 1; | |
858 | } | |
859 | ||
0e078e2f TG |
860 | /** |
861 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
862 | */ | |
1da177e4 LT |
863 | void __init sync_Arb_IDs(void) |
864 | { | |
296cb951 CG |
865 | /* |
866 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
867 | * needed on AMD. | |
868 | */ | |
869 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
870 | return; |
871 | ||
872 | /* | |
873 | * Wait for idle. | |
874 | */ | |
875 | apic_wait_icr_idle(); | |
876 | ||
877 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
878 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
879 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
880 | } |
881 | ||
1da177e4 LT |
882 | /* |
883 | * An initial setup of the virtual wire mode. | |
884 | */ | |
885 | void __init init_bsp_APIC(void) | |
886 | { | |
11a8e778 | 887 | unsigned int value; |
1da177e4 LT |
888 | |
889 | /* | |
890 | * Don't do the setup now if we have a SMP BIOS as the | |
891 | * through-I/O-APIC virtual wire mode might be active. | |
892 | */ | |
893 | if (smp_found_config || !cpu_has_apic) | |
894 | return; | |
895 | ||
1da177e4 LT |
896 | /* |
897 | * Do not trust the local APIC being empty at bootup. | |
898 | */ | |
899 | clear_local_APIC(); | |
900 | ||
901 | /* | |
902 | * Enable APIC. | |
903 | */ | |
904 | value = apic_read(APIC_SPIV); | |
905 | value &= ~APIC_VECTOR_MASK; | |
906 | value |= APIC_SPIV_APIC_ENABLED; | |
638c0411 CG |
907 | |
908 | #ifdef CONFIG_X86_32 | |
909 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
910 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
911 | (boot_cpu_data.x86 == 15)) | |
912 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
913 | else | |
914 | #endif | |
915 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 916 | value |= SPURIOUS_APIC_VECTOR; |
11a8e778 | 917 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
918 | |
919 | /* | |
920 | * Set up the virtual wire mode. | |
921 | */ | |
11a8e778 | 922 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 923 | value = APIC_DM_NMI; |
638c0411 CG |
924 | if (!lapic_is_integrated()) /* 82489DX */ |
925 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 926 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
927 | } |
928 | ||
c43da2f5 CG |
929 | static void __cpuinit lapic_setup_esr(void) |
930 | { | |
931 | unsigned long oldvalue, value, maxlvt; | |
932 | if (lapic_is_integrated() && !esr_disable) { | |
933 | if (esr_disable) { | |
934 | /* | |
935 | * Something untraceable is creating bad interrupts on | |
936 | * secondary quads ... for the moment, just leave the | |
937 | * ESR disabled - we can't do anything useful with the | |
938 | * errors anyway - mbligh | |
939 | */ | |
940 | printk(KERN_INFO "Leaving ESR disabled.\n"); | |
941 | return; | |
942 | } | |
943 | /* !82489DX */ | |
944 | maxlvt = lapic_get_maxlvt(); | |
945 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
946 | apic_write(APIC_ESR, 0); | |
947 | oldvalue = apic_read(APIC_ESR); | |
948 | ||
949 | /* enables sending errors */ | |
950 | value = ERROR_APIC_VECTOR; | |
951 | apic_write(APIC_LVTERR, value); | |
952 | /* | |
953 | * spec says clear errors after enabling vector. | |
954 | */ | |
955 | if (maxlvt > 3) | |
956 | apic_write(APIC_ESR, 0); | |
957 | value = apic_read(APIC_ESR); | |
958 | if (value != oldvalue) | |
959 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
960 | "vector: 0x%08lx after: 0x%08lx\n", | |
961 | oldvalue, value); | |
962 | } else { | |
963 | printk(KERN_INFO "No ESR for 82489DX.\n"); | |
964 | } | |
965 | } | |
966 | ||
967 | ||
0e078e2f TG |
968 | /** |
969 | * setup_local_APIC - setup the local APIC | |
970 | */ | |
971 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 972 | { |
739f33b3 | 973 | unsigned int value; |
da7ed9f9 | 974 | int i, j; |
1da177e4 | 975 | |
89c38c28 CG |
976 | #ifdef CONFIG_X86_32 |
977 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
978 | if (esr_disable) { | |
979 | apic_write(APIC_ESR, 0); | |
980 | apic_write(APIC_ESR, 0); | |
981 | apic_write(APIC_ESR, 0); | |
982 | apic_write(APIC_ESR, 0); | |
983 | } | |
984 | #endif | |
985 | ||
ac23d4ee | 986 | preempt_disable(); |
1da177e4 | 987 | |
1da177e4 LT |
988 | /* |
989 | * Double-check whether this APIC is really registered. | |
990 | * This is meaningless in clustered apic mode, so we skip it. | |
991 | */ | |
992 | if (!apic_id_registered()) | |
993 | BUG(); | |
994 | ||
995 | /* | |
996 | * Intel recommends to set DFR, LDR and TPR before enabling | |
997 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
998 | * document number 292116). So here it goes... | |
999 | */ | |
1000 | init_apic_ldr(); | |
1001 | ||
1002 | /* | |
1003 | * Set Task Priority to 'accept all'. We never change this | |
1004 | * later on. | |
1005 | */ | |
1006 | value = apic_read(APIC_TASKPRI); | |
1007 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 1008 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1009 | |
da7ed9f9 VG |
1010 | /* |
1011 | * After a crash, we no longer service the interrupts and a pending | |
1012 | * interrupt from previous kernel might still have ISR bit set. | |
1013 | * | |
1014 | * Most probably by now CPU has serviced that pending interrupt and | |
1015 | * it might not have done the ack_APIC_irq() because it thought, | |
1016 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1017 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1018 | * the interrupt. Hence a vector might get locked. It was noticed | |
1019 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1020 | */ | |
1021 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1022 | value = apic_read(APIC_ISR + i*0x10); | |
1023 | for (j = 31; j >= 0; j--) { | |
1024 | if (value & (1<<j)) | |
1025 | ack_APIC_irq(); | |
1026 | } | |
1027 | } | |
1028 | ||
1da177e4 LT |
1029 | /* |
1030 | * Now that we are all set up, enable the APIC | |
1031 | */ | |
1032 | value = apic_read(APIC_SPIV); | |
1033 | value &= ~APIC_VECTOR_MASK; | |
1034 | /* | |
1035 | * Enable APIC | |
1036 | */ | |
1037 | value |= APIC_SPIV_APIC_ENABLED; | |
1038 | ||
89c38c28 CG |
1039 | #ifdef CONFIG_X86_32 |
1040 | /* | |
1041 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1042 | * certain networking cards. If high frequency interrupts are | |
1043 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1044 | * entry is masked/unmasked at a high rate as well then sooner or | |
1045 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1046 | * from the device. If focus CPU is disabled then the hang goes | |
1047 | * away, oh well :-( | |
1048 | * | |
1049 | * [ This bug can be reproduced easily with a level-triggered | |
1050 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1051 | * BX chipset. ] | |
1052 | */ | |
1053 | /* | |
1054 | * Actually disabling the focus CPU check just makes the hang less | |
1055 | * frequent as it makes the interrupt distributon model be more | |
1056 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1057 | * See also the comment in end_level_ioapic_irq(). --macro | |
1058 | */ | |
1059 | ||
1060 | /* | |
1061 | * - enable focus processor (bit==0) | |
1062 | * - 64bit mode always use processor focus | |
1063 | * so no need to set it | |
1064 | */ | |
1065 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1066 | #endif | |
3f14c746 | 1067 | |
1da177e4 LT |
1068 | /* |
1069 | * Set spurious IRQ vector | |
1070 | */ | |
1071 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 1072 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1073 | |
1074 | /* | |
1075 | * Set up LVT0, LVT1: | |
1076 | * | |
1077 | * set up through-local-APIC on the BP's LINT0. This is not | |
1078 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
1079 | * we delegate interrupts to the 8259A. | |
1080 | */ | |
1081 | /* | |
1082 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1083 | */ | |
1084 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
89c38c28 | 1085 | if (!smp_processor_id() && (pic_mode || !value)) { |
1da177e4 | 1086 | value = APIC_DM_EXTINT; |
bc1d99c1 | 1087 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
89c38c28 | 1088 | smp_processor_id()); |
1da177e4 LT |
1089 | } else { |
1090 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 | 1091 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
89c38c28 | 1092 | smp_processor_id()); |
1da177e4 | 1093 | } |
11a8e778 | 1094 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1095 | |
1096 | /* | |
1097 | * only the BP should see the LINT1 NMI signal, obviously. | |
1098 | */ | |
1099 | if (!smp_processor_id()) | |
1100 | value = APIC_DM_NMI; | |
1101 | else | |
1102 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
89c38c28 CG |
1103 | if (!lapic_is_integrated()) /* 82489DX */ |
1104 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1105 | apic_write(APIC_LVT1, value); |
89c38c28 | 1106 | |
ac23d4ee | 1107 | preempt_enable(); |
739f33b3 | 1108 | } |
1da177e4 | 1109 | |
739f33b3 AK |
1110 | void __cpuinit end_local_APIC_setup(void) |
1111 | { | |
1112 | lapic_setup_esr(); | |
fa6b95fc CG |
1113 | |
1114 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1115 | { |
1116 | unsigned int value; | |
1117 | /* Disable the local apic timer */ | |
1118 | value = apic_read(APIC_LVTT); | |
1119 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1120 | apic_write(APIC_LVTT, value); | |
1121 | } | |
fa6b95fc CG |
1122 | #endif |
1123 | ||
f2802e7f | 1124 | setup_apic_nmi_watchdog(NULL); |
0e078e2f | 1125 | apic_pm_activate(); |
1da177e4 | 1126 | } |
1da177e4 | 1127 | |
6e1cb38a SS |
1128 | void check_x2apic(void) |
1129 | { | |
1130 | int msr, msr2; | |
1131 | ||
1132 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1133 | ||
1134 | if (msr & X2APIC_ENABLE) { | |
1135 | printk("x2apic enabled by BIOS, switching to x2apic ops\n"); | |
1136 | x2apic_preenabled = x2apic = 1; | |
1137 | apic_ops = &x2apic_ops; | |
1138 | } | |
1139 | } | |
1140 | ||
1141 | void enable_x2apic(void) | |
1142 | { | |
1143 | int msr, msr2; | |
1144 | ||
1145 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1146 | if (!(msr & X2APIC_ENABLE)) { | |
1147 | printk("Enabling x2apic\n"); | |
1148 | wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); | |
1149 | } | |
1150 | } | |
1151 | ||
1152 | void enable_IR_x2apic(void) | |
1153 | { | |
1154 | #ifdef CONFIG_INTR_REMAP | |
1155 | int ret; | |
1156 | unsigned long flags; | |
1157 | ||
1158 | if (!cpu_has_x2apic) | |
1159 | return; | |
1160 | ||
1161 | if (!x2apic_preenabled && disable_x2apic) { | |
1162 | printk(KERN_INFO | |
1163 | "Skipped enabling x2apic and Interrupt-remapping " | |
1164 | "because of nox2apic\n"); | |
1165 | return; | |
1166 | } | |
1167 | ||
1168 | if (x2apic_preenabled && disable_x2apic) | |
1169 | panic("Bios already enabled x2apic, can't enforce nox2apic"); | |
1170 | ||
1171 | if (!x2apic_preenabled && skip_ioapic_setup) { | |
1172 | printk(KERN_INFO | |
1173 | "Skipped enabling x2apic and Interrupt-remapping " | |
1174 | "because of skipping io-apic setup\n"); | |
1175 | return; | |
1176 | } | |
1177 | ||
1178 | ret = dmar_table_init(); | |
1179 | if (ret) { | |
1180 | printk(KERN_INFO | |
1181 | "dmar_table_init() failed with %d:\n", ret); | |
1182 | ||
1183 | if (x2apic_preenabled) | |
1184 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1185 | else | |
1186 | printk(KERN_INFO | |
1187 | "Not enabling x2apic,Intr-remapping\n"); | |
1188 | return; | |
1189 | } | |
1190 | ||
1191 | local_irq_save(flags); | |
1192 | mask_8259A(); | |
1193 | save_mask_IO_APIC_setup(); | |
1194 | ||
1195 | ret = enable_intr_remapping(1); | |
1196 | ||
1197 | if (ret && x2apic_preenabled) { | |
1198 | local_irq_restore(flags); | |
1199 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1200 | } | |
1201 | ||
1202 | if (ret) | |
1203 | goto end; | |
1204 | ||
1205 | if (!x2apic) { | |
1206 | x2apic = 1; | |
1207 | apic_ops = &x2apic_ops; | |
1208 | enable_x2apic(); | |
1209 | } | |
1210 | end: | |
1211 | if (ret) | |
1212 | /* | |
1213 | * IR enabling failed | |
1214 | */ | |
1215 | restore_IO_APIC_setup(); | |
1216 | else | |
1217 | reinit_intr_remapped_IO_APIC(x2apic_preenabled); | |
1218 | ||
1219 | unmask_8259A(); | |
1220 | local_irq_restore(flags); | |
1221 | ||
1222 | if (!ret) { | |
1223 | if (!x2apic_preenabled) | |
1224 | printk(KERN_INFO | |
1225 | "Enabled x2apic and interrupt-remapping\n"); | |
1226 | else | |
1227 | printk(KERN_INFO | |
1228 | "Enabled Interrupt-remapping\n"); | |
1229 | } else | |
1230 | printk(KERN_ERR | |
1231 | "Failed to enable Interrupt-remapping and x2apic\n"); | |
1232 | #else | |
1233 | if (!cpu_has_x2apic) | |
1234 | return; | |
1235 | ||
1236 | if (x2apic_preenabled) | |
1237 | panic("x2apic enabled prior OS handover," | |
1238 | " enable CONFIG_INTR_REMAP"); | |
1239 | ||
1240 | printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping " | |
1241 | " and x2apic\n"); | |
1242 | #endif | |
1243 | ||
1244 | return; | |
1245 | } | |
1246 | ||
1da177e4 LT |
1247 | /* |
1248 | * Detect and enable local APICs on non-SMP boards. | |
1249 | * Original code written by Keir Fraser. | |
1250 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1251 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1252 | */ |
0e078e2f | 1253 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1254 | { |
1255 | if (!cpu_has_apic) { | |
1256 | printk(KERN_INFO "No local APIC present\n"); | |
1257 | return -1; | |
1258 | } | |
1259 | ||
1260 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
c70dcb74 | 1261 | boot_cpu_physical_apicid = 0; |
1da177e4 LT |
1262 | return 0; |
1263 | } | |
1264 | ||
8643f9d0 YL |
1265 | void __init early_init_lapic_mapping(void) |
1266 | { | |
431ee79d | 1267 | unsigned long phys_addr; |
8643f9d0 YL |
1268 | |
1269 | /* | |
1270 | * If no local APIC can be found then go out | |
1271 | * : it means there is no mpatable and MADT | |
1272 | */ | |
1273 | if (!smp_found_config) | |
1274 | return; | |
1275 | ||
431ee79d | 1276 | phys_addr = mp_lapic_addr; |
8643f9d0 | 1277 | |
431ee79d | 1278 | set_fixmap_nocache(FIX_APIC_BASE, phys_addr); |
8643f9d0 | 1279 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
431ee79d | 1280 | APIC_BASE, phys_addr); |
8643f9d0 YL |
1281 | |
1282 | /* | |
1283 | * Fetch the APIC ID of the BSP in case we have a | |
1284 | * default configuration (or the MP table is broken). | |
1285 | */ | |
4c9961d5 | 1286 | boot_cpu_physical_apicid = read_apic_id(); |
8643f9d0 YL |
1287 | } |
1288 | ||
0e078e2f TG |
1289 | /** |
1290 | * init_apic_mappings - initialize APIC mappings | |
1291 | */ | |
1da177e4 LT |
1292 | void __init init_apic_mappings(void) |
1293 | { | |
6e1cb38a | 1294 | if (x2apic) { |
4c9961d5 | 1295 | boot_cpu_physical_apicid = read_apic_id(); |
6e1cb38a SS |
1296 | return; |
1297 | } | |
1298 | ||
1da177e4 LT |
1299 | /* |
1300 | * If no local APIC can be found then set up a fake all | |
1301 | * zeroes page to simulate the local APIC and another | |
1302 | * one for the IO-APIC. | |
1303 | */ | |
1304 | if (!smp_found_config && detect_init_APIC()) { | |
1305 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1306 | apic_phys = __pa(apic_phys); | |
1307 | } else | |
1308 | apic_phys = mp_lapic_addr; | |
1309 | ||
1310 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
7ffeeb1e YL |
1311 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
1312 | APIC_BASE, apic_phys); | |
1da177e4 LT |
1313 | |
1314 | /* | |
1315 | * Fetch the APIC ID of the BSP in case we have a | |
1316 | * default configuration (or the MP table is broken). | |
1317 | */ | |
4c9961d5 | 1318 | boot_cpu_physical_apicid = read_apic_id(); |
1da177e4 LT |
1319 | } |
1320 | ||
1321 | /* | |
0e078e2f TG |
1322 | * This initializes the IO-APIC and APIC hardware if this is |
1323 | * a UP kernel. | |
1da177e4 | 1324 | */ |
1b313f4a CG |
1325 | int apic_version[MAX_APICS]; |
1326 | ||
0e078e2f | 1327 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1328 | { |
0e078e2f TG |
1329 | if (disable_apic) { |
1330 | printk(KERN_INFO "Apic disabled\n"); | |
1331 | return -1; | |
1332 | } | |
1333 | if (!cpu_has_apic) { | |
1334 | disable_apic = 1; | |
1335 | printk(KERN_INFO "Apic disabled by BIOS\n"); | |
1336 | return -1; | |
1337 | } | |
1da177e4 | 1338 | |
6e1cb38a SS |
1339 | enable_IR_x2apic(); |
1340 | setup_apic_routing(); | |
1341 | ||
0e078e2f | 1342 | verify_local_APIC(); |
1da177e4 | 1343 | |
b5841765 GC |
1344 | connect_bsp_APIC(); |
1345 | ||
b6df1b8b | 1346 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
c70dcb74 | 1347 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
1da177e4 | 1348 | |
0e078e2f | 1349 | setup_local_APIC(); |
1da177e4 | 1350 | |
739f33b3 AK |
1351 | /* |
1352 | * Now enable IO-APICs, actually call clear_IO_APIC | |
1353 | * We need clear_IO_APIC before enabling vector on BP | |
1354 | */ | |
1355 | if (!skip_ioapic_setup && nr_ioapics) | |
1356 | enable_IO_APIC(); | |
1357 | ||
acae7d90 MR |
1358 | if (!smp_found_config || skip_ioapic_setup || !nr_ioapics) |
1359 | localise_nmi_watchdog(); | |
739f33b3 AK |
1360 | end_local_APIC_setup(); |
1361 | ||
0e078e2f TG |
1362 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
1363 | setup_IO_APIC(); | |
1364 | else | |
1365 | nr_ioapics = 0; | |
1366 | setup_boot_APIC_clock(); | |
1367 | check_nmi_watchdog(); | |
1368 | return 0; | |
1da177e4 LT |
1369 | } |
1370 | ||
1371 | /* | |
0e078e2f | 1372 | * Local APIC interrupts |
1da177e4 LT |
1373 | */ |
1374 | ||
0e078e2f TG |
1375 | /* |
1376 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1377 | */ | |
1378 | asmlinkage void smp_spurious_interrupt(void) | |
1da177e4 | 1379 | { |
0e078e2f TG |
1380 | unsigned int v; |
1381 | exit_idle(); | |
1382 | irq_enter(); | |
1da177e4 | 1383 | /* |
0e078e2f TG |
1384 | * Check if this really is a spurious interrupt and ACK it |
1385 | * if it is a vectored one. Just in case... | |
1386 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1387 | */ |
0e078e2f TG |
1388 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
1389 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1390 | ack_APIC_irq(); | |
c4d58cbd | 1391 | |
0e078e2f TG |
1392 | add_pda(irq_spurious_count, 1); |
1393 | irq_exit(); | |
1394 | } | |
1da177e4 | 1395 | |
0e078e2f TG |
1396 | /* |
1397 | * This interrupt should never happen with our APIC/SMP architecture | |
1398 | */ | |
1399 | asmlinkage void smp_error_interrupt(void) | |
1400 | { | |
1401 | unsigned int v, v1; | |
1da177e4 | 1402 | |
0e078e2f TG |
1403 | exit_idle(); |
1404 | irq_enter(); | |
1405 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1406 | v = apic_read(APIC_ESR); | |
1407 | apic_write(APIC_ESR, 0); | |
1408 | v1 = apic_read(APIC_ESR); | |
1409 | ack_APIC_irq(); | |
1410 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1411 | |
0e078e2f TG |
1412 | /* Here is what the APIC error bits mean: |
1413 | 0: Send CS error | |
1414 | 1: Receive CS error | |
1415 | 2: Send accept error | |
1416 | 3: Receive accept error | |
1417 | 4: Reserved | |
1418 | 5: Send illegal vector | |
1419 | 6: Received illegal vector | |
1420 | 7: Illegal register address | |
1421 | */ | |
1422 | printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n", | |
1423 | smp_processor_id(), v , v1); | |
1424 | irq_exit(); | |
1da177e4 LT |
1425 | } |
1426 | ||
b5841765 | 1427 | /** |
36c9d674 CG |
1428 | * connect_bsp_APIC - attach the APIC to the interrupt system |
1429 | */ | |
b5841765 GC |
1430 | void __init connect_bsp_APIC(void) |
1431 | { | |
36c9d674 CG |
1432 | #ifdef CONFIG_X86_32 |
1433 | if (pic_mode) { | |
1434 | /* | |
1435 | * Do not trust the local APIC being empty at bootup. | |
1436 | */ | |
1437 | clear_local_APIC(); | |
1438 | /* | |
1439 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1440 | * local APIC to INT and NMI lines. | |
1441 | */ | |
1442 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1443 | "enabling APIC mode.\n"); | |
1444 | outb(0x70, 0x22); | |
1445 | outb(0x01, 0x23); | |
1446 | } | |
1447 | #endif | |
b5841765 GC |
1448 | enable_apic_mode(); |
1449 | } | |
1450 | ||
274cfe59 CG |
1451 | /** |
1452 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1453 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1454 | * | |
1455 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1456 | * APIC is disabled. | |
1457 | */ | |
0e078e2f | 1458 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1459 | { |
1b4ee4e4 CG |
1460 | unsigned int value; |
1461 | ||
c177b0bc CG |
1462 | #ifdef CONFIG_X86_32 |
1463 | if (pic_mode) { | |
1464 | /* | |
1465 | * Put the board back into PIC mode (has an effect only on | |
1466 | * certain older boards). Note that APIC interrupts, including | |
1467 | * IPIs, won't work beyond this point! The only exception are | |
1468 | * INIT IPIs. | |
1469 | */ | |
1470 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1471 | "entering PIC mode.\n"); | |
1472 | outb(0x70, 0x22); | |
1473 | outb(0x00, 0x23); | |
1474 | return; | |
1475 | } | |
1476 | #endif | |
1477 | ||
0e078e2f | 1478 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 1479 | |
0e078e2f TG |
1480 | /* For the spurious interrupt use vector F, and enable it */ |
1481 | value = apic_read(APIC_SPIV); | |
1482 | value &= ~APIC_VECTOR_MASK; | |
1483 | value |= APIC_SPIV_APIC_ENABLED; | |
1484 | value |= 0xf; | |
1485 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1486 | |
0e078e2f TG |
1487 | if (!virt_wire_setup) { |
1488 | /* | |
1489 | * For LVT0 make it edge triggered, active high, | |
1490 | * external and enabled | |
1491 | */ | |
1492 | value = apic_read(APIC_LVT0); | |
1493 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1494 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1495 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1496 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1497 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1498 | apic_write(APIC_LVT0, value); | |
1499 | } else { | |
1500 | /* Disable LVT0 */ | |
1501 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1502 | } | |
b8ce3359 | 1503 | |
c177b0bc CG |
1504 | /* |
1505 | * For LVT1 make it edge triggered, active high, | |
1506 | * nmi and enabled | |
1507 | */ | |
0e078e2f TG |
1508 | value = apic_read(APIC_LVT1); |
1509 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1510 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1511 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1512 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1513 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1514 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1515 | } |
1516 | ||
be8a5685 AS |
1517 | void __cpuinit generic_processor_info(int apicid, int version) |
1518 | { | |
1519 | int cpu; | |
1520 | cpumask_t tmp_map; | |
1521 | ||
1b313f4a CG |
1522 | /* |
1523 | * Validate version | |
1524 | */ | |
1525 | if (version == 0x0) { | |
1526 | printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! " | |
1527 | "fixing up to 0x10. (tell your hw vendor)\n", | |
1528 | version); | |
1529 | version = 0x10; | |
be8a5685 | 1530 | } |
1b313f4a | 1531 | apic_version[apicid] = version; |
be8a5685 | 1532 | |
be8a5685 AS |
1533 | if (num_processors >= NR_CPUS) { |
1534 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." | |
1b313f4a | 1535 | " Processor ignored.\n", NR_CPUS); |
be8a5685 AS |
1536 | return; |
1537 | } | |
1538 | ||
1539 | num_processors++; | |
1540 | cpus_complement(tmp_map, cpu_present_map); | |
1541 | cpu = first_cpu(tmp_map); | |
1542 | ||
1543 | physid_set(apicid, phys_cpu_present_map); | |
1544 | if (apicid == boot_cpu_physical_apicid) { | |
1545 | /* | |
1546 | * x86_bios_cpu_apicid is required to have processors listed | |
1547 | * in same order as logical cpu numbers. Hence the first | |
1548 | * entry is BSP, and so on. | |
1549 | */ | |
1550 | cpu = 0; | |
1551 | } | |
e0da3364 YL |
1552 | if (apicid > max_physical_apicid) |
1553 | max_physical_apicid = apicid; | |
1554 | ||
1b313f4a CG |
1555 | #ifdef CONFIG_X86_32 |
1556 | /* | |
1557 | * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y | |
1558 | * but we need to work other dependencies like SMP_SUSPEND etc | |
1559 | * before this can be done without some confusion. | |
1560 | * if (CPU_HOTPLUG_ENABLED || num_processors > 8) | |
1561 | * - Ashok Raj <ashok.raj@intel.com> | |
1562 | */ | |
1563 | if (max_physical_apicid >= 8) { | |
1564 | switch (boot_cpu_data.x86_vendor) { | |
1565 | case X86_VENDOR_INTEL: | |
1566 | if (!APIC_XAPIC(version)) { | |
1567 | def_to_bigsmp = 0; | |
1568 | break; | |
1569 | } | |
1570 | /* If P4 and above fall through */ | |
1571 | case X86_VENDOR_AMD: | |
1572 | def_to_bigsmp = 1; | |
1573 | } | |
1574 | } | |
1575 | #endif | |
1576 | ||
1577 | #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64) | |
be8a5685 | 1578 | /* are we being called early in kernel startup? */ |
23ca4bba MT |
1579 | if (early_per_cpu_ptr(x86_cpu_to_apicid)) { |
1580 | u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid); | |
1581 | u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); | |
be8a5685 AS |
1582 | |
1583 | cpu_to_apicid[cpu] = apicid; | |
1584 | bios_cpu_apicid[cpu] = apicid; | |
1585 | } else { | |
1586 | per_cpu(x86_cpu_to_apicid, cpu) = apicid; | |
1587 | per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1588 | } | |
1b313f4a | 1589 | #endif |
be8a5685 AS |
1590 | |
1591 | cpu_set(cpu, cpu_possible_map); | |
1592 | cpu_set(cpu, cpu_present_map); | |
1593 | } | |
1594 | ||
0c81c746 SS |
1595 | int hard_smp_processor_id(void) |
1596 | { | |
1597 | return read_apic_id(); | |
1598 | } | |
1599 | ||
89039b37 | 1600 | /* |
0e078e2f | 1601 | * Power management |
89039b37 | 1602 | */ |
0e078e2f TG |
1603 | #ifdef CONFIG_PM |
1604 | ||
1605 | static struct { | |
274cfe59 CG |
1606 | /* |
1607 | * 'active' is true if the local APIC was enabled by us and | |
1608 | * not the BIOS; this signifies that we are also responsible | |
1609 | * for disabling it before entering apm/acpi suspend | |
1610 | */ | |
0e078e2f TG |
1611 | int active; |
1612 | /* r/w apic fields */ | |
1613 | unsigned int apic_id; | |
1614 | unsigned int apic_taskpri; | |
1615 | unsigned int apic_ldr; | |
1616 | unsigned int apic_dfr; | |
1617 | unsigned int apic_spiv; | |
1618 | unsigned int apic_lvtt; | |
1619 | unsigned int apic_lvtpc; | |
1620 | unsigned int apic_lvt0; | |
1621 | unsigned int apic_lvt1; | |
1622 | unsigned int apic_lvterr; | |
1623 | unsigned int apic_tmict; | |
1624 | unsigned int apic_tdcr; | |
1625 | unsigned int apic_thmr; | |
1626 | } apic_pm_state; | |
1627 | ||
1628 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1629 | { | |
1630 | unsigned long flags; | |
1631 | int maxlvt; | |
89039b37 | 1632 | |
0e078e2f TG |
1633 | if (!apic_pm_state.active) |
1634 | return 0; | |
89039b37 | 1635 | |
0e078e2f | 1636 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 1637 | |
2d7a66d0 | 1638 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
1639 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
1640 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1641 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1642 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1643 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1644 | if (maxlvt >= 4) | |
1645 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1646 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1647 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1648 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1649 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1650 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
24968cfd | 1651 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
1652 | if (maxlvt >= 5) |
1653 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1654 | #endif | |
24968cfd | 1655 | |
0e078e2f TG |
1656 | local_irq_save(flags); |
1657 | disable_local_APIC(); | |
1658 | local_irq_restore(flags); | |
1659 | return 0; | |
1da177e4 LT |
1660 | } |
1661 | ||
0e078e2f | 1662 | static int lapic_resume(struct sys_device *dev) |
1da177e4 | 1663 | { |
0e078e2f TG |
1664 | unsigned int l, h; |
1665 | unsigned long flags; | |
1666 | int maxlvt; | |
1da177e4 | 1667 | |
0e078e2f TG |
1668 | if (!apic_pm_state.active) |
1669 | return 0; | |
89b831ef | 1670 | |
0e078e2f | 1671 | maxlvt = lapic_get_maxlvt(); |
1da177e4 | 1672 | |
0e078e2f | 1673 | local_irq_save(flags); |
92206c90 CG |
1674 | |
1675 | #ifdef CONFIG_X86_64 | |
1676 | if (x2apic) | |
1677 | enable_x2apic(); | |
1678 | else | |
1679 | #endif | |
d5e629a6 | 1680 | { |
92206c90 CG |
1681 | /* |
1682 | * Make sure the APICBASE points to the right address | |
1683 | * | |
1684 | * FIXME! This will be wrong if we ever support suspend on | |
1685 | * SMP! We'll need to do this as part of the CPU restore! | |
1686 | */ | |
6e1cb38a SS |
1687 | rdmsr(MSR_IA32_APICBASE, l, h); |
1688 | l &= ~MSR_IA32_APICBASE_BASE; | |
1689 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1690 | wrmsr(MSR_IA32_APICBASE, l, h); | |
d5e629a6 | 1691 | } |
6e1cb38a | 1692 | |
0e078e2f TG |
1693 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
1694 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1695 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1696 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1697 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1698 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1699 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1700 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
92206c90 | 1701 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
1702 | if (maxlvt >= 5) |
1703 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1704 | #endif | |
1705 | if (maxlvt >= 4) | |
1706 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1707 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
1708 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
1709 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
1710 | apic_write(APIC_ESR, 0); | |
1711 | apic_read(APIC_ESR); | |
1712 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
1713 | apic_write(APIC_ESR, 0); | |
1714 | apic_read(APIC_ESR); | |
92206c90 | 1715 | |
0e078e2f | 1716 | local_irq_restore(flags); |
92206c90 | 1717 | |
0e078e2f TG |
1718 | return 0; |
1719 | } | |
b8ce3359 | 1720 | |
274cfe59 CG |
1721 | /* |
1722 | * This device has no shutdown method - fully functioning local APICs | |
1723 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
1724 | */ | |
1725 | ||
0e078e2f TG |
1726 | static struct sysdev_class lapic_sysclass = { |
1727 | .name = "lapic", | |
1728 | .resume = lapic_resume, | |
1729 | .suspend = lapic_suspend, | |
1730 | }; | |
b8ce3359 | 1731 | |
0e078e2f | 1732 | static struct sys_device device_lapic = { |
e83a5fdc HS |
1733 | .id = 0, |
1734 | .cls = &lapic_sysclass, | |
0e078e2f | 1735 | }; |
b8ce3359 | 1736 | |
0e078e2f TG |
1737 | static void __cpuinit apic_pm_activate(void) |
1738 | { | |
1739 | apic_pm_state.active = 1; | |
1da177e4 LT |
1740 | } |
1741 | ||
0e078e2f | 1742 | static int __init init_lapic_sysfs(void) |
1da177e4 | 1743 | { |
0e078e2f | 1744 | int error; |
e83a5fdc | 1745 | |
0e078e2f TG |
1746 | if (!cpu_has_apic) |
1747 | return 0; | |
1748 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
e83a5fdc | 1749 | |
0e078e2f TG |
1750 | error = sysdev_class_register(&lapic_sysclass); |
1751 | if (!error) | |
1752 | error = sysdev_register(&device_lapic); | |
1753 | return error; | |
1da177e4 | 1754 | } |
0e078e2f TG |
1755 | device_initcall(init_lapic_sysfs); |
1756 | ||
1757 | #else /* CONFIG_PM */ | |
1758 | ||
1759 | static void apic_pm_activate(void) { } | |
1760 | ||
1761 | #endif /* CONFIG_PM */ | |
1da177e4 LT |
1762 | |
1763 | /* | |
f8bf3c65 | 1764 | * apic_is_clustered_box() -- Check if we can expect good TSC |
1da177e4 LT |
1765 | * |
1766 | * Thus far, the major user of this is IBM's Summit2 series: | |
1767 | * | |
637029c6 | 1768 | * Clustered boxes may have unsynced TSC problems if they are |
1da177e4 LT |
1769 | * multi-chassis. Use available data to take a good guess. |
1770 | * If in doubt, go HPET. | |
1771 | */ | |
f8bf3c65 | 1772 | __cpuinit int apic_is_clustered_box(void) |
1da177e4 LT |
1773 | { |
1774 | int i, clusters, zeros; | |
1775 | unsigned id; | |
322850af | 1776 | u16 *bios_cpu_apicid; |
1da177e4 LT |
1777 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
1778 | ||
322850af YL |
1779 | /* |
1780 | * there is not this kind of box with AMD CPU yet. | |
1781 | * Some AMD box with quadcore cpu and 8 sockets apicid | |
1782 | * will be [4, 0x23] or [8, 0x27] could be thought to | |
f8fffa45 | 1783 | * vsmp box still need checking... |
322850af | 1784 | */ |
1cb68487 | 1785 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box()) |
322850af YL |
1786 | return 0; |
1787 | ||
23ca4bba | 1788 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); |
376ec33f | 1789 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 LT |
1790 | |
1791 | for (i = 0; i < NR_CPUS; i++) { | |
e8c10ef9 | 1792 | /* are we being called early in kernel startup? */ |
693e3c56 MT |
1793 | if (bios_cpu_apicid) { |
1794 | id = bios_cpu_apicid[i]; | |
e8c10ef9 | 1795 | } |
1796 | else if (i < nr_cpu_ids) { | |
1797 | if (cpu_present(i)) | |
1798 | id = per_cpu(x86_bios_cpu_apicid, i); | |
1799 | else | |
1800 | continue; | |
1801 | } | |
1802 | else | |
1803 | break; | |
1804 | ||
1da177e4 LT |
1805 | if (id != BAD_APICID) |
1806 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
1807 | } | |
1808 | ||
1809 | /* Problem: Partially populated chassis may not have CPUs in some of | |
1810 | * the APIC clusters they have been allocated. Only present CPUs have | |
602a54a8 | 1811 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
1812 | * Since clusters are allocated sequentially, count zeros only if | |
1813 | * they are bounded by ones. | |
1da177e4 LT |
1814 | */ |
1815 | clusters = 0; | |
1816 | zeros = 0; | |
1817 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
1818 | if (test_bit(i, clustermap)) { | |
1819 | clusters += 1 + zeros; | |
1820 | zeros = 0; | |
1821 | } else | |
1822 | ++zeros; | |
1823 | } | |
1824 | ||
1cb68487 RT |
1825 | /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
1826 | * not guaranteed to be synced between boards | |
1827 | */ | |
1828 | if (is_vsmp_box() && clusters > 1) | |
1829 | return 1; | |
1830 | ||
1da177e4 | 1831 | /* |
f8bf3c65 | 1832 | * If clusters > 2, then should be multi-chassis. |
1da177e4 LT |
1833 | * May have to revisit this when multi-core + hyperthreaded CPUs come |
1834 | * out, but AFAIK this will work even for them. | |
1835 | */ | |
1836 | return (clusters > 2); | |
1837 | } | |
1838 | ||
6e1cb38a | 1839 | static __init int setup_nox2apic(char *str) |
1da177e4 | 1840 | { |
6e1cb38a SS |
1841 | disable_x2apic = 1; |
1842 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_X2APIC); | |
1da177e4 LT |
1843 | return 0; |
1844 | } | |
6e1cb38a | 1845 | early_param("nox2apic", setup_nox2apic); |
1da177e4 | 1846 | |
1da177e4 | 1847 | |
1da177e4 | 1848 | /* |
0e078e2f | 1849 | * APIC command line parameters |
1da177e4 | 1850 | */ |
789fa735 | 1851 | static int __init setup_disableapic(char *arg) |
6935d1f9 | 1852 | { |
1da177e4 | 1853 | disable_apic = 1; |
9175fc06 | 1854 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
1855 | return 0; |
1856 | } | |
1857 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 1858 | |
2c8c0e6b | 1859 | /* same as disableapic, for compatibility */ |
789fa735 | 1860 | static int __init setup_nolapic(char *arg) |
6935d1f9 | 1861 | { |
789fa735 | 1862 | return setup_disableapic(arg); |
6935d1f9 | 1863 | } |
2c8c0e6b | 1864 | early_param("nolapic", setup_nolapic); |
1da177e4 | 1865 | |
2e7c2838 LT |
1866 | static int __init parse_lapic_timer_c2_ok(char *arg) |
1867 | { | |
1868 | local_apic_timer_c2_ok = 1; | |
1869 | return 0; | |
1870 | } | |
1871 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
1872 | ||
36fef094 | 1873 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 1874 | { |
1da177e4 | 1875 | disable_apic_timer = 1; |
36fef094 | 1876 | return 0; |
6935d1f9 | 1877 | } |
36fef094 CG |
1878 | early_param("noapictimer", parse_disable_apic_timer); |
1879 | ||
1880 | static int __init parse_nolapic_timer(char *arg) | |
1881 | { | |
1882 | disable_apic_timer = 1; | |
1883 | return 0; | |
6935d1f9 | 1884 | } |
36fef094 | 1885 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 1886 | |
79af9bec CG |
1887 | static int __init apic_set_verbosity(char *arg) |
1888 | { | |
1889 | if (!arg) { | |
1890 | #ifdef CONFIG_X86_64 | |
1891 | skip_ioapic_setup = 0; | |
79af9bec CG |
1892 | return 0; |
1893 | #endif | |
1894 | return -EINVAL; | |
1895 | } | |
1896 | ||
1897 | if (strcmp("debug", arg) == 0) | |
1898 | apic_verbosity = APIC_DEBUG; | |
1899 | else if (strcmp("verbose", arg) == 0) | |
1900 | apic_verbosity = APIC_VERBOSE; | |
1901 | else { | |
1902 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | |
1903 | " use apic=verbose or apic=debug\n", arg); | |
1904 | return -EINVAL; | |
1905 | } | |
1906 | ||
1907 | return 0; | |
1908 | } | |
1909 | early_param("apic", apic_set_verbosity); | |
1910 | ||
1e934dda YL |
1911 | static int __init lapic_insert_resource(void) |
1912 | { | |
1913 | if (!apic_phys) | |
1914 | return -1; | |
1915 | ||
1916 | /* Put local APIC into the resource map. */ | |
1917 | lapic_resource.start = apic_phys; | |
1918 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
1919 | insert_resource(&iomem_resource, &lapic_resource); | |
1920 | ||
1921 | return 0; | |
1922 | } | |
1923 | ||
1924 | /* | |
1925 | * need call insert after e820_reserve_resources() | |
1926 | * that is using request_resource | |
1927 | */ | |
1928 | late_initcall(lapic_insert_resource); |