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1da177e4 LT |
1 | #include <linux/init.h> |
2 | #include <linux/bitops.h> | |
3 | #include <linux/mm.h> | |
8d71a2ea | 4 | |
8bdbd962 | 5 | #include <linux/io.h> |
1da177e4 | 6 | #include <asm/processor.h> |
d3f7eae1 | 7 | #include <asm/apic.h> |
1f442d70 | 8 | #include <asm/cpu.h> |
42937e81 | 9 | #include <asm/pci-direct.h> |
1da177e4 | 10 | |
8d71a2ea YL |
11 | #ifdef CONFIG_X86_64 |
12 | # include <asm/numa_64.h> | |
13 | # include <asm/mmconfig.h> | |
14 | # include <asm/cacheflush.h> | |
15 | #endif | |
16 | ||
1da177e4 LT |
17 | #include "cpu.h" |
18 | ||
6c62aa4a | 19 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
20 | /* |
21 | * B step AMD K6 before B 9730xxxx have hardware bugs that can cause | |
22 | * misexecution of code under Linux. Owners of such processors should | |
23 | * contact AMD for precise details and a CPU swap. | |
24 | * | |
25 | * See http://www.multimania.com/poulot/k6bug.html | |
26 | * http://www.amd.com/K6/k6docs/revgd.html | |
27 | * | |
28 | * The following test is erm.. interesting. AMD neglected to up | |
29 | * the chip setting when fixing the bug but they also tweaked some | |
30 | * performance at the same time.. | |
31 | */ | |
fb87a298 | 32 | |
1da177e4 LT |
33 | extern void vide(void); |
34 | __asm__(".align 4\nvide: ret"); | |
35 | ||
11fdd252 YL |
36 | static void __cpuinit init_amd_k5(struct cpuinfo_x86 *c) |
37 | { | |
38 | /* | |
39 | * General Systems BIOSen alias the cpu frequency registers | |
40 | * of the Elan at 0x000df000. Unfortuantly, one of the Linux | |
41 | * drivers subsequently pokes it, and changes the CPU speed. | |
42 | * Workaround : Remove the unneeded alias. | |
43 | */ | |
44 | #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ | |
45 | #define CBAR_ENB (0x80000000) | |
46 | #define CBAR_KEY (0X000000CB) | |
47 | if (c->x86_model == 9 || c->x86_model == 10) { | |
8bdbd962 AC |
48 | if (inl(CBAR) & CBAR_ENB) |
49 | outl(0 | CBAR_KEY, CBAR); | |
11fdd252 YL |
50 | } |
51 | } | |
52 | ||
53 | ||
54 | static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c) | |
55 | { | |
56 | u32 l, h; | |
57 | int mbytes = num_physpages >> (20-PAGE_SHIFT); | |
58 | ||
59 | if (c->x86_model < 6) { | |
60 | /* Based on AMD doc 20734R - June 2000 */ | |
61 | if (c->x86_model == 0) { | |
62 | clear_cpu_cap(c, X86_FEATURE_APIC); | |
63 | set_cpu_cap(c, X86_FEATURE_PGE); | |
64 | } | |
65 | return; | |
66 | } | |
67 | ||
68 | if (c->x86_model == 6 && c->x86_mask == 1) { | |
69 | const int K6_BUG_LOOP = 1000000; | |
70 | int n; | |
71 | void (*f_vide)(void); | |
72 | unsigned long d, d2; | |
73 | ||
74 | printk(KERN_INFO "AMD K6 stepping B detected - "); | |
75 | ||
76 | /* | |
77 | * It looks like AMD fixed the 2.6.2 bug and improved indirect | |
78 | * calls at the same time. | |
79 | */ | |
80 | ||
81 | n = K6_BUG_LOOP; | |
82 | f_vide = vide; | |
83 | rdtscl(d); | |
84 | while (n--) | |
85 | f_vide(); | |
86 | rdtscl(d2); | |
87 | d = d2-d; | |
88 | ||
89 | if (d > 20*K6_BUG_LOOP) | |
8bdbd962 AC |
90 | printk(KERN_CONT |
91 | "system stability may be impaired when more than 32 MB are used.\n"); | |
11fdd252 | 92 | else |
8bdbd962 | 93 | printk(KERN_CONT "probably OK (after B9730xxxx).\n"); |
11fdd252 YL |
94 | printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n"); |
95 | } | |
96 | ||
97 | /* K6 with old style WHCR */ | |
98 | if (c->x86_model < 8 || | |
99 | (c->x86_model == 8 && c->x86_mask < 8)) { | |
100 | /* We can only write allocate on the low 508Mb */ | |
101 | if (mbytes > 508) | |
102 | mbytes = 508; | |
103 | ||
104 | rdmsr(MSR_K6_WHCR, l, h); | |
105 | if ((l&0x0000FFFF) == 0) { | |
106 | unsigned long flags; | |
107 | l = (1<<0)|((mbytes/4)<<1); | |
108 | local_irq_save(flags); | |
109 | wbinvd(); | |
110 | wrmsr(MSR_K6_WHCR, l, h); | |
111 | local_irq_restore(flags); | |
112 | printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n", | |
113 | mbytes); | |
114 | } | |
115 | return; | |
116 | } | |
117 | ||
118 | if ((c->x86_model == 8 && c->x86_mask > 7) || | |
119 | c->x86_model == 9 || c->x86_model == 13) { | |
120 | /* The more serious chips .. */ | |
121 | ||
122 | if (mbytes > 4092) | |
123 | mbytes = 4092; | |
124 | ||
125 | rdmsr(MSR_K6_WHCR, l, h); | |
126 | if ((l&0xFFFF0000) == 0) { | |
127 | unsigned long flags; | |
128 | l = ((mbytes>>2)<<22)|(1<<16); | |
129 | local_irq_save(flags); | |
130 | wbinvd(); | |
131 | wrmsr(MSR_K6_WHCR, l, h); | |
132 | local_irq_restore(flags); | |
133 | printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n", | |
134 | mbytes); | |
135 | } | |
136 | ||
137 | return; | |
138 | } | |
139 | ||
140 | if (c->x86_model == 10) { | |
141 | /* AMD Geode LX is model 10 */ | |
142 | /* placeholder for any needed mods */ | |
143 | return; | |
144 | } | |
145 | } | |
146 | ||
1f442d70 YL |
147 | static void __cpuinit amd_k7_smp_check(struct cpuinfo_x86 *c) |
148 | { | |
149 | #ifdef CONFIG_SMP | |
150 | /* calling is from identify_secondary_cpu() ? */ | |
151 | if (c->cpu_index == boot_cpu_id) | |
152 | return; | |
153 | ||
154 | /* | |
155 | * Certain Athlons might work (for various values of 'work') in SMP | |
156 | * but they are not certified as MP capable. | |
157 | */ | |
158 | /* Athlon 660/661 is valid. */ | |
159 | if ((c->x86_model == 6) && ((c->x86_mask == 0) || | |
160 | (c->x86_mask == 1))) | |
161 | goto valid_k7; | |
162 | ||
163 | /* Duron 670 is valid */ | |
164 | if ((c->x86_model == 7) && (c->x86_mask == 0)) | |
165 | goto valid_k7; | |
166 | ||
167 | /* | |
168 | * Athlon 662, Duron 671, and Athlon >model 7 have capability | |
169 | * bit. It's worth noting that the A5 stepping (662) of some | |
170 | * Athlon XP's have the MP bit set. | |
171 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for | |
172 | * more. | |
173 | */ | |
174 | if (((c->x86_model == 6) && (c->x86_mask >= 2)) || | |
175 | ((c->x86_model == 7) && (c->x86_mask >= 1)) || | |
176 | (c->x86_model > 7)) | |
177 | if (cpu_has_mp) | |
178 | goto valid_k7; | |
179 | ||
180 | /* If we get here, not a certified SMP capable AMD system. */ | |
181 | ||
182 | /* | |
183 | * Don't taint if we are running SMP kernel on a single non-MP | |
184 | * approved Athlon | |
185 | */ | |
186 | WARN_ONCE(1, "WARNING: This combination of AMD" | |
7da8b6dd | 187 | " processors is not suitable for SMP.\n"); |
1f442d70 YL |
188 | if (!test_taint(TAINT_UNSAFE_SMP)) |
189 | add_taint(TAINT_UNSAFE_SMP); | |
190 | ||
191 | valid_k7: | |
192 | ; | |
193 | #endif | |
194 | } | |
195 | ||
11fdd252 YL |
196 | static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c) |
197 | { | |
198 | u32 l, h; | |
199 | ||
200 | /* | |
201 | * Bit 15 of Athlon specific MSR 15, needs to be 0 | |
202 | * to enable SSE on Palomino/Morgan/Barton CPU's. | |
203 | * If the BIOS didn't enable it already, enable it here. | |
204 | */ | |
205 | if (c->x86_model >= 6 && c->x86_model <= 10) { | |
206 | if (!cpu_has(c, X86_FEATURE_XMM)) { | |
207 | printk(KERN_INFO "Enabling disabled K7/SSE Support.\n"); | |
208 | rdmsr(MSR_K7_HWCR, l, h); | |
209 | l &= ~0x00008000; | |
210 | wrmsr(MSR_K7_HWCR, l, h); | |
211 | set_cpu_cap(c, X86_FEATURE_XMM); | |
212 | } | |
213 | } | |
214 | ||
215 | /* | |
216 | * It's been determined by AMD that Athlons since model 8 stepping 1 | |
217 | * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx | |
218 | * As per AMD technical note 27212 0.2 | |
219 | */ | |
220 | if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) { | |
221 | rdmsr(MSR_K7_CLK_CTL, l, h); | |
222 | if ((l & 0xfff00000) != 0x20000000) { | |
8bdbd962 AC |
223 | printk(KERN_INFO |
224 | "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", | |
225 | l, ((l & 0x000fffff)|0x20000000)); | |
11fdd252 YL |
226 | wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); |
227 | } | |
228 | } | |
229 | ||
230 | set_cpu_cap(c, X86_FEATURE_K7); | |
1f442d70 YL |
231 | |
232 | amd_k7_smp_check(c); | |
11fdd252 | 233 | } |
6c62aa4a YL |
234 | #endif |
235 | ||
236 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) | |
237 | static int __cpuinit nearby_node(int apicid) | |
238 | { | |
239 | int i, node; | |
240 | ||
241 | for (i = apicid - 1; i >= 0; i--) { | |
242 | node = apicid_to_node[i]; | |
243 | if (node != NUMA_NO_NODE && node_online(node)) | |
244 | return node; | |
245 | } | |
246 | for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { | |
247 | node = apicid_to_node[i]; | |
248 | if (node != NUMA_NO_NODE && node_online(node)) | |
249 | return node; | |
250 | } | |
251 | return first_node(node_online_map); /* Shouldn't happen */ | |
252 | } | |
253 | #endif | |
11fdd252 | 254 | |
4a376ec3 AH |
255 | /* |
256 | * Fixup core topology information for AMD multi-node processors. | |
257 | * Assumption 1: Number of cores in each internal node is the same. | |
258 | * Assumption 2: Mixed systems with both single-node and dual-node | |
259 | * processors are not supported. | |
260 | */ | |
261 | #ifdef CONFIG_X86_HT | |
262 | static void __cpuinit amd_fixup_dcm(struct cpuinfo_x86 *c) | |
263 | { | |
264 | #ifdef CONFIG_PCI | |
265 | u32 t, cpn; | |
266 | u8 n, n_id; | |
267 | int cpu = smp_processor_id(); | |
268 | ||
269 | /* fixup topology information only once for a core */ | |
270 | if (cpu_has(c, X86_FEATURE_AMD_DCM)) | |
271 | return; | |
272 | ||
273 | /* check for multi-node processor on boot cpu */ | |
274 | t = read_pci_config(0, 24, 3, 0xe8); | |
275 | if (!(t & (1 << 29))) | |
276 | return; | |
277 | ||
278 | set_cpu_cap(c, X86_FEATURE_AMD_DCM); | |
279 | ||
280 | /* cores per node: each internal node has half the number of cores */ | |
281 | cpn = c->x86_max_cores >> 1; | |
282 | ||
283 | /* even-numbered NB_id of this dual-node processor */ | |
284 | n = c->phys_proc_id << 1; | |
285 | ||
286 | /* | |
287 | * determine internal node id and assign cores fifty-fifty to | |
288 | * each node of the dual-node processor | |
289 | */ | |
290 | t = read_pci_config(0, 24 + n, 3, 0xe8); | |
291 | n = (t>>30) & 0x3; | |
292 | if (n == 0) { | |
293 | if (c->cpu_core_id < cpn) | |
294 | n_id = 0; | |
295 | else | |
296 | n_id = 1; | |
297 | } else { | |
298 | if (c->cpu_core_id < cpn) | |
299 | n_id = 1; | |
300 | else | |
301 | n_id = 0; | |
302 | } | |
303 | ||
304 | /* compute entire NodeID, use llc_shared_map to store sibling info */ | |
305 | per_cpu(cpu_llc_id, cpu) = (c->phys_proc_id << 1) + n_id; | |
306 | ||
307 | /* fixup core id to be in range from 0 to cpn */ | |
308 | c->cpu_core_id = c->cpu_core_id % cpn; | |
309 | #endif | |
310 | } | |
311 | #endif | |
312 | ||
11fdd252 YL |
313 | /* |
314 | * On a AMD dual core setup the lower bits of the APIC id distingush the cores. | |
315 | * Assumes number of cores is a power of two. | |
316 | */ | |
317 | static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c) | |
318 | { | |
319 | #ifdef CONFIG_X86_HT | |
320 | unsigned bits; | |
99bd0c0f | 321 | int cpu = smp_processor_id(); |
11fdd252 YL |
322 | |
323 | bits = c->x86_coreid_bits; | |
11fdd252 YL |
324 | /* Low order bits define the core id (index of core in socket) */ |
325 | c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); | |
326 | /* Convert the initial APIC ID into the socket ID */ | |
327 | c->phys_proc_id = c->initial_apicid >> bits; | |
99bd0c0f AH |
328 | /* use socket ID also for last level cache */ |
329 | per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; | |
4a376ec3 AH |
330 | /* fixup topology information on multi-node processors */ |
331 | if ((c->x86 == 0x10) && (c->x86_model == 9)) | |
332 | amd_fixup_dcm(c); | |
11fdd252 YL |
333 | #endif |
334 | } | |
335 | ||
6a812691 AH |
336 | int amd_get_nb_id(int cpu) |
337 | { | |
338 | int id = 0; | |
339 | #ifdef CONFIG_SMP | |
340 | id = per_cpu(cpu_llc_id, cpu); | |
341 | #endif | |
342 | return id; | |
343 | } | |
344 | EXPORT_SYMBOL_GPL(amd_get_nb_id); | |
345 | ||
6c62aa4a YL |
346 | static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c) |
347 | { | |
348 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) | |
349 | int cpu = smp_processor_id(); | |
350 | int node; | |
0d96b9ff | 351 | unsigned apicid = c->apicid; |
6c62aa4a | 352 | |
4a376ec3 | 353 | node = per_cpu(cpu_llc_id, cpu); |
6c62aa4a | 354 | |
6c62aa4a YL |
355 | if (apicid_to_node[apicid] != NUMA_NO_NODE) |
356 | node = apicid_to_node[apicid]; | |
357 | if (!node_online(node)) { | |
358 | /* Two possibilities here: | |
359 | - The CPU is missing memory and no node was created. | |
360 | In that case try picking one from a nearby CPU | |
361 | - The APIC IDs differ from the HyperTransport node IDs | |
362 | which the K8 northbridge parsing fills in. | |
363 | Assume they are all increased by a constant offset, | |
364 | but in the same order as the HT nodeids. | |
365 | If that doesn't result in a usable node fall back to the | |
366 | path for the previous case. */ | |
367 | ||
368 | int ht_nodeid = c->initial_apicid; | |
369 | ||
370 | if (ht_nodeid >= 0 && | |
371 | apicid_to_node[ht_nodeid] != NUMA_NO_NODE) | |
372 | node = apicid_to_node[ht_nodeid]; | |
373 | /* Pick a nearby node */ | |
374 | if (!node_online(node)) | |
375 | node = nearby_node(apicid); | |
376 | } | |
377 | numa_set_node(cpu, node); | |
378 | ||
823b259b | 379 | printk(KERN_INFO "CPU %d/0x%x -> Node %d\n", cpu, apicid, node); |
6c62aa4a YL |
380 | #endif |
381 | } | |
382 | ||
11fdd252 YL |
383 | static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c) |
384 | { | |
385 | #ifdef CONFIG_X86_HT | |
386 | unsigned bits, ecx; | |
387 | ||
388 | /* Multi core CPU? */ | |
389 | if (c->extended_cpuid_level < 0x80000008) | |
390 | return; | |
391 | ||
392 | ecx = cpuid_ecx(0x80000008); | |
393 | ||
394 | c->x86_max_cores = (ecx & 0xff) + 1; | |
395 | ||
396 | /* CPU telling us the core id bits shift? */ | |
397 | bits = (ecx >> 12) & 0xF; | |
398 | ||
399 | /* Otherwise recompute */ | |
400 | if (bits == 0) { | |
401 | while ((1 << bits) < c->x86_max_cores) | |
402 | bits++; | |
403 | } | |
404 | ||
405 | c->x86_coreid_bits = bits; | |
406 | #endif | |
407 | } | |
408 | ||
03ae5768 | 409 | static void __cpuinit early_init_amd(struct cpuinfo_x86 *c) |
2b16a235 | 410 | { |
11fdd252 YL |
411 | early_init_amd_mc(c); |
412 | ||
40fb1715 VP |
413 | /* |
414 | * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate | |
415 | * with P/T states and does not stop in deep C-states | |
416 | */ | |
417 | if (c->x86_power & (1 << 8)) { | |
e3224234 | 418 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); |
40fb1715 VP |
419 | set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); |
420 | } | |
5fef55fd | 421 | |
6c62aa4a YL |
422 | #ifdef CONFIG_X86_64 |
423 | set_cpu_cap(c, X86_FEATURE_SYSCALL32); | |
424 | #else | |
5fef55fd | 425 | /* Set MTRR capability flag if appropriate */ |
6c62aa4a YL |
426 | if (c->x86 == 5) |
427 | if (c->x86_model == 13 || c->x86_model == 9 || | |
428 | (c->x86_model == 8 && c->x86_mask >= 8)) | |
429 | set_cpu_cap(c, X86_FEATURE_K6_MTRR); | |
430 | #endif | |
42937e81 AH |
431 | #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) |
432 | /* check CPU config space for extended APIC ID */ | |
2cb07860 | 433 | if (cpu_has_apic && c->x86 >= 0xf) { |
42937e81 AH |
434 | unsigned int val; |
435 | val = read_pci_config(0, 24, 0, 0x68); | |
436 | if ((val & ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18))) | |
437 | set_cpu_cap(c, X86_FEATURE_EXTD_APICID); | |
438 | } | |
439 | #endif | |
2b16a235 AK |
440 | } |
441 | ||
b4af3f7c | 442 | static void __cpuinit init_amd(struct cpuinfo_x86 *c) |
1da177e4 | 443 | { |
7d318d77 | 444 | #ifdef CONFIG_SMP |
3c92c2ba | 445 | unsigned long long value; |
7d318d77 | 446 | |
fb87a298 PC |
447 | /* |
448 | * Disable TLB flush filter by setting HWCR.FFDIS on K8 | |
7d318d77 AK |
449 | * bit 6 of msr C001_0015 |
450 | * | |
451 | * Errata 63 for SH-B3 steppings | |
452 | * Errata 122 for all steppings (F+ have it disabled by default) | |
453 | */ | |
11fdd252 | 454 | if (c->x86 == 0xf) { |
7d318d77 AK |
455 | rdmsrl(MSR_K7_HWCR, value); |
456 | value |= 1 << 6; | |
457 | wrmsrl(MSR_K7_HWCR, value); | |
458 | } | |
459 | #endif | |
460 | ||
2b16a235 AK |
461 | early_init_amd(c); |
462 | ||
fb87a298 PC |
463 | /* |
464 | * Bit 31 in normal CPUID used for nonstandard 3DNow ID; | |
16282a8e | 465 | * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway |
fb87a298 | 466 | */ |
16282a8e | 467 | clear_cpu_cap(c, 0*32+31); |
fb87a298 | 468 | |
6c62aa4a YL |
469 | #ifdef CONFIG_X86_64 |
470 | /* On C+ stepping K8 rep microcode works well for copy/memset */ | |
471 | if (c->x86 == 0xf) { | |
472 | u32 level; | |
473 | ||
474 | level = cpuid_eax(1); | |
8bdbd962 | 475 | if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) |
6c62aa4a | 476 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); |
fbd8b181 KW |
477 | |
478 | /* | |
479 | * Some BIOSes incorrectly force this feature, but only K8 | |
480 | * revision D (model = 0x14) and later actually support it. | |
6b0f43dd | 481 | * (AMD Erratum #110, docId: 25759). |
fbd8b181 | 482 | */ |
6b0f43dd BP |
483 | if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { |
484 | u64 val; | |
485 | ||
fbd8b181 | 486 | clear_cpu_cap(c, X86_FEATURE_LAHF_LM); |
6b0f43dd BP |
487 | if (!rdmsrl_amd_safe(0xc001100d, &val)) { |
488 | val &= ~(1ULL << 32); | |
489 | wrmsrl_amd_safe(0xc001100d, val); | |
490 | } | |
491 | } | |
492 | ||
6c62aa4a YL |
493 | } |
494 | if (c->x86 == 0x10 || c->x86 == 0x11) | |
495 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); | |
0d96b9ff YL |
496 | |
497 | /* get apicid instead of initial apic id from cpuid */ | |
498 | c->apicid = hard_smp_processor_id(); | |
6c62aa4a YL |
499 | #else |
500 | ||
501 | /* | |
502 | * FIXME: We should handle the K5 here. Set up the write | |
503 | * range and also turn on MSR 83 bits 4 and 31 (write alloc, | |
504 | * no bus pipeline) | |
505 | */ | |
506 | ||
fb87a298 PC |
507 | switch (c->x86) { |
508 | case 4: | |
11fdd252 YL |
509 | init_amd_k5(c); |
510 | break; | |
fb87a298 | 511 | case 5: |
11fdd252 | 512 | init_amd_k6(c); |
1da177e4 | 513 | break; |
11fdd252 YL |
514 | case 6: /* An Athlon/Duron */ |
515 | init_amd_k7(c); | |
1da177e4 LT |
516 | break; |
517 | } | |
11fdd252 YL |
518 | |
519 | /* K6s reports MCEs but don't actually have all the MSRs */ | |
520 | if (c->x86 < 6) | |
521 | clear_cpu_cap(c, X86_FEATURE_MCE); | |
6c62aa4a | 522 | #endif |
11fdd252 | 523 | |
6c62aa4a | 524 | /* Enable workaround for FXSAVE leak */ |
18bd057b | 525 | if (c->x86 >= 6) |
16282a8e | 526 | set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK); |
1da177e4 | 527 | |
11fdd252 YL |
528 | if (!c->x86_model_id[0]) { |
529 | switch (c->x86) { | |
530 | case 0xf: | |
531 | /* Should distinguish Models here, but this is only | |
532 | a fallback anyways. */ | |
533 | strcpy(c->x86_model_id, "Hammer"); | |
534 | break; | |
535 | } | |
536 | } | |
3dd9d514 | 537 | |
11fdd252 | 538 | display_cacheinfo(c); |
3dd9d514 | 539 | |
11fdd252 | 540 | /* Multi core CPU? */ |
6c62aa4a | 541 | if (c->extended_cpuid_level >= 0x80000008) { |
11fdd252 | 542 | amd_detect_cmp(c); |
6c62aa4a YL |
543 | srat_detect_node(c); |
544 | } | |
faee9a5d | 545 | |
6c62aa4a | 546 | #ifdef CONFIG_X86_32 |
11fdd252 | 547 | detect_ht(c); |
6c62aa4a | 548 | #endif |
39b3a791 | 549 | |
11fdd252 YL |
550 | if (c->extended_cpuid_level >= 0x80000006) { |
551 | if ((c->x86 >= 0x0f) && (cpuid_edx(0x80000006) & 0xf000)) | |
67cddd94 AK |
552 | num_cache_leaves = 4; |
553 | else | |
554 | num_cache_leaves = 3; | |
555 | } | |
3556ddfa | 556 | |
11fdd252 YL |
557 | if (c->x86 >= 0xf && c->x86 <= 0x11) |
558 | set_cpu_cap(c, X86_FEATURE_K8); | |
de421863 | 559 | |
11fdd252 YL |
560 | if (cpu_has_xmm2) { |
561 | /* MFENCE stops RDTSC speculation */ | |
16282a8e | 562 | set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); |
11fdd252 | 563 | } |
6c62aa4a YL |
564 | |
565 | #ifdef CONFIG_X86_64 | |
566 | if (c->x86 == 0x10) { | |
567 | /* do this for boot cpu */ | |
568 | if (c == &boot_cpu_data) | |
569 | check_enable_amd_mmconf_dmi(); | |
570 | ||
571 | fam10h_check_enable_mmcfg(); | |
572 | } | |
573 | ||
574 | if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) { | |
575 | unsigned long long tseg; | |
576 | ||
577 | /* | |
578 | * Split up direct mapping around the TSEG SMM area. | |
579 | * Don't do it for gbpages because there seems very little | |
580 | * benefit in doing so. | |
581 | */ | |
582 | if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { | |
8bdbd962 AC |
583 | printk(KERN_DEBUG "tseg: %010llx\n", tseg); |
584 | if ((tseg>>PMD_SHIFT) < | |
6c62aa4a | 585 | (max_low_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) || |
8bdbd962 | 586 | ((tseg>>PMD_SHIFT) < |
6c62aa4a | 587 | (max_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) && |
8bdbd962 AC |
588 | (tseg>>PMD_SHIFT) >= (1ULL<<(32 - PMD_SHIFT)))) |
589 | set_memory_4k((unsigned long)__va(tseg), 1); | |
6c62aa4a YL |
590 | } |
591 | } | |
592 | #endif | |
1da177e4 LT |
593 | } |
594 | ||
6c62aa4a | 595 | #ifdef CONFIG_X86_32 |
8bdbd962 AC |
596 | static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, |
597 | unsigned int size) | |
1da177e4 LT |
598 | { |
599 | /* AMD errata T13 (order #21922) */ | |
600 | if ((c->x86 == 6)) { | |
8bdbd962 AC |
601 | /* Duron Rev A0 */ |
602 | if (c->x86_model == 3 && c->x86_mask == 0) | |
1da177e4 | 603 | size = 64; |
8bdbd962 | 604 | /* Tbird rev A1/A2 */ |
1da177e4 | 605 | if (c->x86_model == 4 && |
8bdbd962 | 606 | (c->x86_mask == 0 || c->x86_mask == 1)) |
1da177e4 LT |
607 | size = 256; |
608 | } | |
609 | return size; | |
610 | } | |
6c62aa4a | 611 | #endif |
1da177e4 | 612 | |
02dde8b4 | 613 | static const struct cpu_dev __cpuinitconst amd_cpu_dev = { |
1da177e4 | 614 | .c_vendor = "AMD", |
fb87a298 | 615 | .c_ident = { "AuthenticAMD" }, |
6c62aa4a | 616 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
617 | .c_models = { |
618 | { .vendor = X86_VENDOR_AMD, .family = 4, .model_names = | |
619 | { | |
620 | [3] = "486 DX/2", | |
621 | [7] = "486 DX/2-WB", | |
fb87a298 PC |
622 | [8] = "486 DX/4", |
623 | [9] = "486 DX/4-WB", | |
1da177e4 | 624 | [14] = "Am5x86-WT", |
fb87a298 | 625 | [15] = "Am5x86-WB" |
1da177e4 LT |
626 | } |
627 | }, | |
628 | }, | |
6c62aa4a YL |
629 | .c_size_cache = amd_size_cache, |
630 | #endif | |
03ae5768 | 631 | .c_early_init = early_init_amd, |
1da177e4 | 632 | .c_init = init_amd, |
10a434fc | 633 | .c_x86_vendor = X86_VENDOR_AMD, |
1da177e4 LT |
634 | }; |
635 | ||
10a434fc | 636 | cpu_dev_register(amd_cpu_dev); |