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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1353ebb4 | 2 | /* |
1353ebb4 JF |
3 | * Copyright (C) 1994 Linus Torvalds |
4 | * | |
5 | * Cyrix stuff, June 1998 by: | |
6 | * - Rafael R. Reilova (moved everything from head.S), | |
7 | * <rreilova@ececs.uc.edu> | |
8 | * - Channing Corn (tests & fixes), | |
9 | * - Andrew D. Balsa (code cleanup). | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/utsname.h> | |
61dc0f55 | 13 | #include <linux/cpu.h> |
caf7501a | 14 | #include <linux/module.h> |
da285121 DW |
15 | |
16 | #include <asm/nospec-branch.h> | |
17 | #include <asm/cmdline.h> | |
91eb1b79 | 18 | #include <asm/bugs.h> |
1353ebb4 | 19 | #include <asm/processor.h> |
7ebad705 | 20 | #include <asm/processor-flags.h> |
952f07ec | 21 | #include <asm/fpu/internal.h> |
1353ebb4 JF |
22 | #include <asm/msr.h> |
23 | #include <asm/paravirt.h> | |
24 | #include <asm/alternative.h> | |
62a67e12 | 25 | #include <asm/pgtable.h> |
d1163651 | 26 | #include <asm/set_memory.h> |
c995efd5 | 27 | #include <asm/intel-family.h> |
1353ebb4 | 28 | |
da285121 DW |
29 | static void __init spectre_v2_select_mitigation(void); |
30 | ||
1b86883c KRW |
31 | /* |
32 | * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any | |
33 | * writes to SPEC_CTRL contain whatever reserved bits have been set. | |
34 | */ | |
35 | static u64 __ro_after_init x86_spec_ctrl_base; | |
36 | ||
1353ebb4 JF |
37 | void __init check_bugs(void) |
38 | { | |
39 | identify_boot_cpu(); | |
55a36b65 | 40 | |
62a67e12 BP |
41 | if (!IS_ENABLED(CONFIG_SMP)) { |
42 | pr_info("CPU: "); | |
43 | print_cpu_info(&boot_cpu_data); | |
44 | } | |
45 | ||
1b86883c KRW |
46 | /* |
47 | * Read the SPEC_CTRL MSR to account for reserved bits which may | |
48 | * have unknown values. | |
49 | */ | |
50 | if (boot_cpu_has(X86_FEATURE_IBRS)) | |
51 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
52 | ||
da285121 DW |
53 | /* Select the proper spectre mitigation before patching alternatives */ |
54 | spectre_v2_select_mitigation(); | |
55 | ||
62a67e12 | 56 | #ifdef CONFIG_X86_32 |
55a36b65 BP |
57 | /* |
58 | * Check whether we are able to run this kernel safely on SMP. | |
59 | * | |
60 | * - i386 is no longer supported. | |
61 | * - In order to run on anything without a TSC, we need to be | |
62 | * compiled for a i486. | |
63 | */ | |
64 | if (boot_cpu_data.x86 < 4) | |
65 | panic("Kernel requires i486+ for 'invlpg' and other features"); | |
66 | ||
bfe4bb15 MV |
67 | init_utsname()->machine[1] = |
68 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); | |
1353ebb4 | 69 | alternative_instructions(); |
304bceda | 70 | |
4d164092 | 71 | fpu__init_check_bugs(); |
62a67e12 BP |
72 | #else /* CONFIG_X86_64 */ |
73 | alternative_instructions(); | |
74 | ||
75 | /* | |
76 | * Make sure the first 2MB area is not mapped by huge pages | |
77 | * There are typically fixed size MTRRs in there and overlapping | |
78 | * MTRRs into large pages causes slow downs. | |
79 | * | |
80 | * Right now we don't do that with gbpages because there seems | |
81 | * very little benefit for that case. | |
82 | */ | |
83 | if (!direct_gbpages) | |
84 | set_memory_4k((unsigned long)__va(0), 1); | |
85 | #endif | |
1353ebb4 | 86 | } |
61dc0f55 | 87 | |
da285121 DW |
88 | /* The kernel command line selection */ |
89 | enum spectre_v2_mitigation_cmd { | |
90 | SPECTRE_V2_CMD_NONE, | |
91 | SPECTRE_V2_CMD_AUTO, | |
92 | SPECTRE_V2_CMD_FORCE, | |
93 | SPECTRE_V2_CMD_RETPOLINE, | |
94 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, | |
95 | SPECTRE_V2_CMD_RETPOLINE_AMD, | |
96 | }; | |
97 | ||
98 | static const char *spectre_v2_strings[] = { | |
99 | [SPECTRE_V2_NONE] = "Vulnerable", | |
100 | [SPECTRE_V2_RETPOLINE_MINIMAL] = "Vulnerable: Minimal generic ASM retpoline", | |
101 | [SPECTRE_V2_RETPOLINE_MINIMAL_AMD] = "Vulnerable: Minimal AMD ASM retpoline", | |
102 | [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", | |
103 | [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", | |
104 | }; | |
105 | ||
106 | #undef pr_fmt | |
55fa19d3 | 107 | #define pr_fmt(fmt) "Spectre V2 : " fmt |
da285121 DW |
108 | |
109 | static enum spectre_v2_mitigation spectre_v2_enabled = SPECTRE_V2_NONE; | |
caf7501a | 110 | |
1b86883c KRW |
111 | void x86_spec_ctrl_set(u64 val) |
112 | { | |
113 | if (val & ~SPEC_CTRL_IBRS) | |
114 | WARN_ONCE(1, "SPEC_CTRL MSR value 0x%16llx is unknown.\n", val); | |
115 | else | |
116 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base | val); | |
117 | } | |
118 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_set); | |
119 | ||
120 | u64 x86_spec_ctrl_get_default(void) | |
121 | { | |
122 | return x86_spec_ctrl_base; | |
123 | } | |
124 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_get_default); | |
125 | ||
5cf68754 KRW |
126 | void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl) |
127 | { | |
128 | if (!boot_cpu_has(X86_FEATURE_IBRS)) | |
129 | return; | |
130 | if (x86_spec_ctrl_base != guest_spec_ctrl) | |
131 | wrmsrl(MSR_IA32_SPEC_CTRL, guest_spec_ctrl); | |
132 | } | |
133 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_set_guest); | |
134 | ||
135 | void x86_spec_ctrl_restore_host(u64 guest_spec_ctrl) | |
136 | { | |
137 | if (!boot_cpu_has(X86_FEATURE_IBRS)) | |
138 | return; | |
139 | if (x86_spec_ctrl_base != guest_spec_ctrl) | |
140 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
141 | } | |
142 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_restore_host); | |
143 | ||
caf7501a | 144 | #ifdef RETPOLINE |
e383095c TG |
145 | static bool spectre_v2_bad_module; |
146 | ||
caf7501a AK |
147 | bool retpoline_module_ok(bool has_retpoline) |
148 | { | |
149 | if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) | |
150 | return true; | |
151 | ||
e698dcdf | 152 | pr_err("System may be vulnerable to spectre v2\n"); |
caf7501a AK |
153 | spectre_v2_bad_module = true; |
154 | return false; | |
155 | } | |
e383095c TG |
156 | |
157 | static inline const char *spectre_v2_module_string(void) | |
158 | { | |
159 | return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; | |
160 | } | |
161 | #else | |
162 | static inline const char *spectre_v2_module_string(void) { return ""; } | |
caf7501a | 163 | #endif |
da285121 DW |
164 | |
165 | static void __init spec2_print_if_insecure(const char *reason) | |
166 | { | |
167 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
9005c683 | 168 | pr_info("%s selected on command line.\n", reason); |
da285121 DW |
169 | } |
170 | ||
171 | static void __init spec2_print_if_secure(const char *reason) | |
172 | { | |
173 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
9005c683 | 174 | pr_info("%s selected on command line.\n", reason); |
da285121 DW |
175 | } |
176 | ||
177 | static inline bool retp_compiler(void) | |
178 | { | |
179 | return __is_defined(RETPOLINE); | |
180 | } | |
181 | ||
182 | static inline bool match_option(const char *arg, int arglen, const char *opt) | |
183 | { | |
184 | int len = strlen(opt); | |
185 | ||
186 | return len == arglen && !strncmp(arg, opt, len); | |
187 | } | |
188 | ||
9005c683 KA |
189 | static const struct { |
190 | const char *option; | |
191 | enum spectre_v2_mitigation_cmd cmd; | |
192 | bool secure; | |
193 | } mitigation_options[] = { | |
194 | { "off", SPECTRE_V2_CMD_NONE, false }, | |
195 | { "on", SPECTRE_V2_CMD_FORCE, true }, | |
196 | { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, | |
197 | { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, | |
198 | { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, | |
199 | { "auto", SPECTRE_V2_CMD_AUTO, false }, | |
200 | }; | |
201 | ||
da285121 DW |
202 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) |
203 | { | |
204 | char arg[20]; | |
9005c683 KA |
205 | int ret, i; |
206 | enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; | |
207 | ||
208 | if (cmdline_find_option_bool(boot_command_line, "nospectre_v2")) | |
209 | return SPECTRE_V2_CMD_NONE; | |
210 | else { | |
21e433bd | 211 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); |
9005c683 KA |
212 | if (ret < 0) |
213 | return SPECTRE_V2_CMD_AUTO; | |
214 | ||
215 | for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { | |
216 | if (!match_option(arg, ret, mitigation_options[i].option)) | |
217 | continue; | |
218 | cmd = mitigation_options[i].cmd; | |
219 | break; | |
220 | } | |
221 | ||
222 | if (i >= ARRAY_SIZE(mitigation_options)) { | |
9de29eac | 223 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); |
da285121 DW |
224 | return SPECTRE_V2_CMD_AUTO; |
225 | } | |
226 | } | |
227 | ||
9005c683 KA |
228 | if ((cmd == SPECTRE_V2_CMD_RETPOLINE || |
229 | cmd == SPECTRE_V2_CMD_RETPOLINE_AMD || | |
230 | cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) && | |
231 | !IS_ENABLED(CONFIG_RETPOLINE)) { | |
21e433bd | 232 | pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option); |
da285121 | 233 | return SPECTRE_V2_CMD_AUTO; |
9005c683 KA |
234 | } |
235 | ||
236 | if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD && | |
237 | boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { | |
238 | pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); | |
239 | return SPECTRE_V2_CMD_AUTO; | |
240 | } | |
241 | ||
242 | if (mitigation_options[i].secure) | |
243 | spec2_print_if_secure(mitigation_options[i].option); | |
244 | else | |
245 | spec2_print_if_insecure(mitigation_options[i].option); | |
246 | ||
247 | return cmd; | |
da285121 DW |
248 | } |
249 | ||
c995efd5 DW |
250 | /* Check for Skylake-like CPUs (for RSB handling) */ |
251 | static bool __init is_skylake_era(void) | |
252 | { | |
253 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
254 | boot_cpu_data.x86 == 6) { | |
255 | switch (boot_cpu_data.x86_model) { | |
256 | case INTEL_FAM6_SKYLAKE_MOBILE: | |
257 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
258 | case INTEL_FAM6_SKYLAKE_X: | |
259 | case INTEL_FAM6_KABYLAKE_MOBILE: | |
260 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
261 | return true; | |
262 | } | |
263 | } | |
264 | return false; | |
265 | } | |
266 | ||
da285121 DW |
267 | static void __init spectre_v2_select_mitigation(void) |
268 | { | |
269 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | |
270 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; | |
271 | ||
272 | /* | |
273 | * If the CPU is not affected and the command line mode is NONE or AUTO | |
274 | * then nothing to do. | |
275 | */ | |
276 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && | |
277 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) | |
278 | return; | |
279 | ||
280 | switch (cmd) { | |
281 | case SPECTRE_V2_CMD_NONE: | |
282 | return; | |
283 | ||
284 | case SPECTRE_V2_CMD_FORCE: | |
da285121 | 285 | case SPECTRE_V2_CMD_AUTO: |
9471eee9 DL |
286 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
287 | goto retpoline_auto; | |
288 | break; | |
da285121 DW |
289 | case SPECTRE_V2_CMD_RETPOLINE_AMD: |
290 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
291 | goto retpoline_amd; | |
292 | break; | |
293 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: | |
294 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
295 | goto retpoline_generic; | |
296 | break; | |
297 | case SPECTRE_V2_CMD_RETPOLINE: | |
298 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
299 | goto retpoline_auto; | |
300 | break; | |
301 | } | |
21e433bd | 302 | pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!"); |
da285121 DW |
303 | return; |
304 | ||
305 | retpoline_auto: | |
306 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { | |
307 | retpoline_amd: | |
308 | if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { | |
21e433bd | 309 | pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n"); |
da285121 DW |
310 | goto retpoline_generic; |
311 | } | |
312 | mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD : | |
313 | SPECTRE_V2_RETPOLINE_MINIMAL_AMD; | |
314 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); | |
315 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
316 | } else { | |
317 | retpoline_generic: | |
318 | mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC : | |
319 | SPECTRE_V2_RETPOLINE_MINIMAL; | |
320 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
321 | } | |
322 | ||
323 | spectre_v2_enabled = mode; | |
324 | pr_info("%s\n", spectre_v2_strings[mode]); | |
c995efd5 DW |
325 | |
326 | /* | |
21e433bd | 327 | * If neither SMEP nor PTI are available, there is a risk of |
c995efd5 DW |
328 | * hitting userspace addresses in the RSB after a context switch |
329 | * from a shallow call stack to a deeper one. To prevent this fill | |
330 | * the entire RSB, even when using IBRS. | |
331 | * | |
332 | * Skylake era CPUs have a separate issue with *underflow* of the | |
333 | * RSB, when they will predict 'ret' targets from the generic BTB. | |
334 | * The proper mitigation for this is IBRS. If IBRS is not supported | |
335 | * or deactivated in favour of retpolines the RSB fill on context | |
336 | * switch is required. | |
337 | */ | |
338 | if ((!boot_cpu_has(X86_FEATURE_PTI) && | |
339 | !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) { | |
340 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); | |
21e433bd | 341 | pr_info("Spectre v2 mitigation: Filling RSB on context switch\n"); |
c995efd5 | 342 | } |
20ffa1ca DW |
343 | |
344 | /* Initialize Indirect Branch Prediction Barrier if supported */ | |
2961298e DW |
345 | if (boot_cpu_has(X86_FEATURE_IBPB)) { |
346 | setup_force_cpu_cap(X86_FEATURE_USE_IBPB); | |
21e433bd | 347 | pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n"); |
20ffa1ca | 348 | } |
dd84441a DW |
349 | |
350 | /* | |
351 | * Retpoline means the kernel is safe because it has no indirect | |
352 | * branches. But firmware isn't, so use IBRS to protect that. | |
353 | */ | |
354 | if (boot_cpu_has(X86_FEATURE_IBRS)) { | |
355 | setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); | |
356 | pr_info("Enabling Restricted Speculation for firmware calls\n"); | |
357 | } | |
da285121 DW |
358 | } |
359 | ||
360 | #undef pr_fmt | |
361 | ||
61dc0f55 | 362 | #ifdef CONFIG_SYSFS |
d1059518 KRW |
363 | |
364 | ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, | |
365 | char *buf, unsigned int bug) | |
61dc0f55 | 366 | { |
d1059518 | 367 | if (!boot_cpu_has_bug(bug)) |
61dc0f55 | 368 | return sprintf(buf, "Not affected\n"); |
d1059518 KRW |
369 | |
370 | switch (bug) { | |
371 | case X86_BUG_CPU_MELTDOWN: | |
372 | if (boot_cpu_has(X86_FEATURE_PTI)) | |
373 | return sprintf(buf, "Mitigation: PTI\n"); | |
374 | ||
375 | break; | |
376 | ||
377 | case X86_BUG_SPECTRE_V1: | |
378 | return sprintf(buf, "Mitigation: __user pointer sanitization\n"); | |
379 | ||
380 | case X86_BUG_SPECTRE_V2: | |
381 | return sprintf(buf, "%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], | |
382 | boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "", | |
383 | boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", | |
384 | spectre_v2_module_string()); | |
385 | ||
386 | default: | |
387 | break; | |
388 | } | |
389 | ||
61dc0f55 TG |
390 | return sprintf(buf, "Vulnerable\n"); |
391 | } | |
392 | ||
d1059518 KRW |
393 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) |
394 | { | |
395 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); | |
396 | } | |
397 | ||
21e433bd | 398 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 399 | { |
d1059518 | 400 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
61dc0f55 TG |
401 | } |
402 | ||
21e433bd | 403 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 404 | { |
d1059518 | 405 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); |
61dc0f55 TG |
406 | } |
407 | #endif |