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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1353ebb4 | 2 | /* |
1353ebb4 JF |
3 | * Copyright (C) 1994 Linus Torvalds |
4 | * | |
5 | * Cyrix stuff, June 1998 by: | |
6 | * - Rafael R. Reilova (moved everything from head.S), | |
7 | * <rreilova@ececs.uc.edu> | |
8 | * - Channing Corn (tests & fixes), | |
9 | * - Andrew D. Balsa (code cleanup). | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/utsname.h> | |
61dc0f55 | 13 | #include <linux/cpu.h> |
caf7501a | 14 | #include <linux/module.h> |
a73ec77e TG |
15 | #include <linux/nospec.h> |
16 | #include <linux/prctl.h> | |
da285121 | 17 | |
28a27752 | 18 | #include <asm/spec-ctrl.h> |
da285121 | 19 | #include <asm/cmdline.h> |
91eb1b79 | 20 | #include <asm/bugs.h> |
1353ebb4 | 21 | #include <asm/processor.h> |
7ebad705 | 22 | #include <asm/processor-flags.h> |
952f07ec | 23 | #include <asm/fpu/internal.h> |
1353ebb4 JF |
24 | #include <asm/msr.h> |
25 | #include <asm/paravirt.h> | |
26 | #include <asm/alternative.h> | |
62a67e12 | 27 | #include <asm/pgtable.h> |
d1163651 | 28 | #include <asm/set_memory.h> |
c995efd5 | 29 | #include <asm/intel-family.h> |
1353ebb4 | 30 | |
da285121 | 31 | static void __init spectre_v2_select_mitigation(void); |
24f7fc83 | 32 | static void __init ssb_select_mitigation(void); |
da285121 | 33 | |
1b86883c KRW |
34 | /* |
35 | * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any | |
36 | * writes to SPEC_CTRL contain whatever reserved bits have been set. | |
37 | */ | |
885f82bf | 38 | u64 __ro_after_init x86_spec_ctrl_base; |
fa8ac498 | 39 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); |
1b86883c | 40 | |
1115a859 KRW |
41 | /* |
42 | * The vendor and possibly platform specific bits which can be modified in | |
43 | * x86_spec_ctrl_base. | |
44 | */ | |
be6fcb54 | 45 | static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS; |
1115a859 | 46 | |
764f3c21 KRW |
47 | /* |
48 | * AMD specific MSR info for Speculative Store Bypass control. | |
9f65fb29 | 49 | * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). |
764f3c21 KRW |
50 | */ |
51 | u64 __ro_after_init x86_amd_ls_cfg_base; | |
9f65fb29 | 52 | u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; |
764f3c21 | 53 | |
1353ebb4 JF |
54 | void __init check_bugs(void) |
55 | { | |
56 | identify_boot_cpu(); | |
55a36b65 | 57 | |
62a67e12 BP |
58 | if (!IS_ENABLED(CONFIG_SMP)) { |
59 | pr_info("CPU: "); | |
60 | print_cpu_info(&boot_cpu_data); | |
61 | } | |
62 | ||
1b86883c KRW |
63 | /* |
64 | * Read the SPEC_CTRL MSR to account for reserved bits which may | |
764f3c21 KRW |
65 | * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD |
66 | * init code as it is not enumerated and depends on the family. | |
1b86883c | 67 | */ |
7eb8956a | 68 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
1b86883c KRW |
69 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
70 | ||
be6fcb54 TG |
71 | /* Allow STIBP in MSR_SPEC_CTRL if supported */ |
72 | if (boot_cpu_has(X86_FEATURE_STIBP)) | |
73 | x86_spec_ctrl_mask |= SPEC_CTRL_STIBP; | |
74 | ||
da285121 DW |
75 | /* Select the proper spectre mitigation before patching alternatives */ |
76 | spectre_v2_select_mitigation(); | |
77 | ||
24f7fc83 KRW |
78 | /* |
79 | * Select proper mitigation for any exposure to the Speculative Store | |
80 | * Bypass vulnerability. | |
81 | */ | |
82 | ssb_select_mitigation(); | |
83 | ||
62a67e12 | 84 | #ifdef CONFIG_X86_32 |
55a36b65 BP |
85 | /* |
86 | * Check whether we are able to run this kernel safely on SMP. | |
87 | * | |
88 | * - i386 is no longer supported. | |
89 | * - In order to run on anything without a TSC, we need to be | |
90 | * compiled for a i486. | |
91 | */ | |
92 | if (boot_cpu_data.x86 < 4) | |
93 | panic("Kernel requires i486+ for 'invlpg' and other features"); | |
94 | ||
bfe4bb15 MV |
95 | init_utsname()->machine[1] = |
96 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); | |
1353ebb4 | 97 | alternative_instructions(); |
304bceda | 98 | |
4d164092 | 99 | fpu__init_check_bugs(); |
62a67e12 BP |
100 | #else /* CONFIG_X86_64 */ |
101 | alternative_instructions(); | |
102 | ||
103 | /* | |
104 | * Make sure the first 2MB area is not mapped by huge pages | |
105 | * There are typically fixed size MTRRs in there and overlapping | |
106 | * MTRRs into large pages causes slow downs. | |
107 | * | |
108 | * Right now we don't do that with gbpages because there seems | |
109 | * very little benefit for that case. | |
110 | */ | |
111 | if (!direct_gbpages) | |
112 | set_memory_4k((unsigned long)__va(0), 1); | |
113 | #endif | |
1353ebb4 | 114 | } |
61dc0f55 | 115 | |
da285121 DW |
116 | /* The kernel command line selection */ |
117 | enum spectre_v2_mitigation_cmd { | |
118 | SPECTRE_V2_CMD_NONE, | |
119 | SPECTRE_V2_CMD_AUTO, | |
120 | SPECTRE_V2_CMD_FORCE, | |
121 | SPECTRE_V2_CMD_RETPOLINE, | |
122 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, | |
123 | SPECTRE_V2_CMD_RETPOLINE_AMD, | |
124 | }; | |
125 | ||
126 | static const char *spectre_v2_strings[] = { | |
127 | [SPECTRE_V2_NONE] = "Vulnerable", | |
128 | [SPECTRE_V2_RETPOLINE_MINIMAL] = "Vulnerable: Minimal generic ASM retpoline", | |
129 | [SPECTRE_V2_RETPOLINE_MINIMAL_AMD] = "Vulnerable: Minimal AMD ASM retpoline", | |
130 | [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", | |
131 | [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", | |
132 | }; | |
133 | ||
134 | #undef pr_fmt | |
55fa19d3 | 135 | #define pr_fmt(fmt) "Spectre V2 : " fmt |
da285121 | 136 | |
f9544b2b KC |
137 | static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = |
138 | SPECTRE_V2_NONE; | |
caf7501a | 139 | |
cc69b349 BP |
140 | void |
141 | x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) | |
5cf68754 | 142 | { |
be6fcb54 | 143 | u64 msrval, guestval, hostval = x86_spec_ctrl_base; |
cc69b349 | 144 | struct thread_info *ti = current_thread_info(); |
885f82bf | 145 | |
7eb8956a | 146 | /* Is MSR_SPEC_CTRL implemented ? */ |
cc69b349 | 147 | if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { |
be6fcb54 TG |
148 | /* |
149 | * Restrict guest_spec_ctrl to supported values. Clear the | |
150 | * modifiable bits in the host base value and or the | |
151 | * modifiable bits from the guest value. | |
152 | */ | |
153 | guestval = hostval & ~x86_spec_ctrl_mask; | |
154 | guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; | |
155 | ||
cc69b349 BP |
156 | /* SSBD controlled in MSR_SPEC_CTRL */ |
157 | if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) | |
be6fcb54 | 158 | hostval |= ssbd_tif_to_spec_ctrl(ti->flags); |
cc69b349 | 159 | |
be6fcb54 TG |
160 | if (hostval != guestval) { |
161 | msrval = setguest ? guestval : hostval; | |
162 | wrmsrl(MSR_IA32_SPEC_CTRL, msrval); | |
cc69b349 BP |
163 | } |
164 | } | |
47c61b39 TG |
165 | |
166 | /* | |
167 | * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update | |
168 | * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. | |
169 | */ | |
170 | if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && | |
171 | !static_cpu_has(X86_FEATURE_VIRT_SSBD)) | |
172 | return; | |
173 | ||
174 | /* | |
175 | * If the host has SSBD mitigation enabled, force it in the host's | |
176 | * virtual MSR value. If its not permanently enabled, evaluate | |
177 | * current's TIF_SSBD thread flag. | |
178 | */ | |
179 | if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) | |
180 | hostval = SPEC_CTRL_SSBD; | |
181 | else | |
182 | hostval = ssbd_tif_to_spec_ctrl(ti->flags); | |
183 | ||
184 | /* Sanitize the guest value */ | |
185 | guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; | |
186 | ||
187 | if (hostval != guestval) { | |
188 | unsigned long tif; | |
189 | ||
190 | tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : | |
191 | ssbd_spec_ctrl_to_tif(hostval); | |
192 | ||
193 | speculative_store_bypass_update(tif); | |
194 | } | |
5cf68754 | 195 | } |
cc69b349 | 196 | EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); |
5cf68754 | 197 | |
9f65fb29 | 198 | static void x86_amd_ssb_disable(void) |
764f3c21 | 199 | { |
9f65fb29 | 200 | u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; |
764f3c21 | 201 | |
11fb0683 TL |
202 | if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) |
203 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); | |
204 | else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) | |
764f3c21 KRW |
205 | wrmsrl(MSR_AMD64_LS_CFG, msrval); |
206 | } | |
207 | ||
caf7501a | 208 | #ifdef RETPOLINE |
e383095c TG |
209 | static bool spectre_v2_bad_module; |
210 | ||
caf7501a AK |
211 | bool retpoline_module_ok(bool has_retpoline) |
212 | { | |
213 | if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) | |
214 | return true; | |
215 | ||
e698dcdf | 216 | pr_err("System may be vulnerable to spectre v2\n"); |
caf7501a AK |
217 | spectre_v2_bad_module = true; |
218 | return false; | |
219 | } | |
e383095c TG |
220 | |
221 | static inline const char *spectre_v2_module_string(void) | |
222 | { | |
223 | return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; | |
224 | } | |
225 | #else | |
226 | static inline const char *spectre_v2_module_string(void) { return ""; } | |
caf7501a | 227 | #endif |
da285121 DW |
228 | |
229 | static void __init spec2_print_if_insecure(const char *reason) | |
230 | { | |
231 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
9005c683 | 232 | pr_info("%s selected on command line.\n", reason); |
da285121 DW |
233 | } |
234 | ||
235 | static void __init spec2_print_if_secure(const char *reason) | |
236 | { | |
237 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
9005c683 | 238 | pr_info("%s selected on command line.\n", reason); |
da285121 DW |
239 | } |
240 | ||
241 | static inline bool retp_compiler(void) | |
242 | { | |
243 | return __is_defined(RETPOLINE); | |
244 | } | |
245 | ||
246 | static inline bool match_option(const char *arg, int arglen, const char *opt) | |
247 | { | |
248 | int len = strlen(opt); | |
249 | ||
250 | return len == arglen && !strncmp(arg, opt, len); | |
251 | } | |
252 | ||
9005c683 KA |
253 | static const struct { |
254 | const char *option; | |
255 | enum spectre_v2_mitigation_cmd cmd; | |
256 | bool secure; | |
257 | } mitigation_options[] = { | |
258 | { "off", SPECTRE_V2_CMD_NONE, false }, | |
259 | { "on", SPECTRE_V2_CMD_FORCE, true }, | |
260 | { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, | |
261 | { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, | |
262 | { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, | |
263 | { "auto", SPECTRE_V2_CMD_AUTO, false }, | |
264 | }; | |
265 | ||
da285121 DW |
266 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) |
267 | { | |
268 | char arg[20]; | |
9005c683 KA |
269 | int ret, i; |
270 | enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; | |
271 | ||
272 | if (cmdline_find_option_bool(boot_command_line, "nospectre_v2")) | |
273 | return SPECTRE_V2_CMD_NONE; | |
274 | else { | |
21e433bd | 275 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); |
9005c683 KA |
276 | if (ret < 0) |
277 | return SPECTRE_V2_CMD_AUTO; | |
278 | ||
279 | for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { | |
280 | if (!match_option(arg, ret, mitigation_options[i].option)) | |
281 | continue; | |
282 | cmd = mitigation_options[i].cmd; | |
283 | break; | |
284 | } | |
285 | ||
286 | if (i >= ARRAY_SIZE(mitigation_options)) { | |
9de29eac | 287 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); |
da285121 DW |
288 | return SPECTRE_V2_CMD_AUTO; |
289 | } | |
290 | } | |
291 | ||
9005c683 KA |
292 | if ((cmd == SPECTRE_V2_CMD_RETPOLINE || |
293 | cmd == SPECTRE_V2_CMD_RETPOLINE_AMD || | |
294 | cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) && | |
295 | !IS_ENABLED(CONFIG_RETPOLINE)) { | |
21e433bd | 296 | pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option); |
da285121 | 297 | return SPECTRE_V2_CMD_AUTO; |
9005c683 KA |
298 | } |
299 | ||
300 | if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD && | |
301 | boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { | |
302 | pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); | |
303 | return SPECTRE_V2_CMD_AUTO; | |
304 | } | |
305 | ||
306 | if (mitigation_options[i].secure) | |
307 | spec2_print_if_secure(mitigation_options[i].option); | |
308 | else | |
309 | spec2_print_if_insecure(mitigation_options[i].option); | |
310 | ||
311 | return cmd; | |
da285121 DW |
312 | } |
313 | ||
c995efd5 DW |
314 | /* Check for Skylake-like CPUs (for RSB handling) */ |
315 | static bool __init is_skylake_era(void) | |
316 | { | |
317 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
318 | boot_cpu_data.x86 == 6) { | |
319 | switch (boot_cpu_data.x86_model) { | |
320 | case INTEL_FAM6_SKYLAKE_MOBILE: | |
321 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
322 | case INTEL_FAM6_SKYLAKE_X: | |
323 | case INTEL_FAM6_KABYLAKE_MOBILE: | |
324 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
325 | return true; | |
326 | } | |
327 | } | |
328 | return false; | |
329 | } | |
330 | ||
da285121 DW |
331 | static void __init spectre_v2_select_mitigation(void) |
332 | { | |
333 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | |
334 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; | |
335 | ||
336 | /* | |
337 | * If the CPU is not affected and the command line mode is NONE or AUTO | |
338 | * then nothing to do. | |
339 | */ | |
340 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && | |
341 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) | |
342 | return; | |
343 | ||
344 | switch (cmd) { | |
345 | case SPECTRE_V2_CMD_NONE: | |
346 | return; | |
347 | ||
348 | case SPECTRE_V2_CMD_FORCE: | |
da285121 | 349 | case SPECTRE_V2_CMD_AUTO: |
9471eee9 DL |
350 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
351 | goto retpoline_auto; | |
352 | break; | |
da285121 DW |
353 | case SPECTRE_V2_CMD_RETPOLINE_AMD: |
354 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
355 | goto retpoline_amd; | |
356 | break; | |
357 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: | |
358 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
359 | goto retpoline_generic; | |
360 | break; | |
361 | case SPECTRE_V2_CMD_RETPOLINE: | |
362 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
363 | goto retpoline_auto; | |
364 | break; | |
365 | } | |
21e433bd | 366 | pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!"); |
da285121 DW |
367 | return; |
368 | ||
369 | retpoline_auto: | |
370 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { | |
371 | retpoline_amd: | |
372 | if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { | |
21e433bd | 373 | pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n"); |
da285121 DW |
374 | goto retpoline_generic; |
375 | } | |
376 | mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD : | |
377 | SPECTRE_V2_RETPOLINE_MINIMAL_AMD; | |
378 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); | |
379 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
380 | } else { | |
381 | retpoline_generic: | |
382 | mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC : | |
383 | SPECTRE_V2_RETPOLINE_MINIMAL; | |
384 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
385 | } | |
386 | ||
387 | spectre_v2_enabled = mode; | |
388 | pr_info("%s\n", spectre_v2_strings[mode]); | |
c995efd5 DW |
389 | |
390 | /* | |
21e433bd | 391 | * If neither SMEP nor PTI are available, there is a risk of |
c995efd5 DW |
392 | * hitting userspace addresses in the RSB after a context switch |
393 | * from a shallow call stack to a deeper one. To prevent this fill | |
394 | * the entire RSB, even when using IBRS. | |
395 | * | |
396 | * Skylake era CPUs have a separate issue with *underflow* of the | |
397 | * RSB, when they will predict 'ret' targets from the generic BTB. | |
398 | * The proper mitigation for this is IBRS. If IBRS is not supported | |
399 | * or deactivated in favour of retpolines the RSB fill on context | |
400 | * switch is required. | |
401 | */ | |
402 | if ((!boot_cpu_has(X86_FEATURE_PTI) && | |
403 | !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) { | |
404 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); | |
21e433bd | 405 | pr_info("Spectre v2 mitigation: Filling RSB on context switch\n"); |
c995efd5 | 406 | } |
20ffa1ca DW |
407 | |
408 | /* Initialize Indirect Branch Prediction Barrier if supported */ | |
2961298e DW |
409 | if (boot_cpu_has(X86_FEATURE_IBPB)) { |
410 | setup_force_cpu_cap(X86_FEATURE_USE_IBPB); | |
21e433bd | 411 | pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n"); |
20ffa1ca | 412 | } |
dd84441a DW |
413 | |
414 | /* | |
415 | * Retpoline means the kernel is safe because it has no indirect | |
416 | * branches. But firmware isn't, so use IBRS to protect that. | |
417 | */ | |
418 | if (boot_cpu_has(X86_FEATURE_IBRS)) { | |
419 | setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); | |
420 | pr_info("Enabling Restricted Speculation for firmware calls\n"); | |
421 | } | |
da285121 DW |
422 | } |
423 | ||
24f7fc83 KRW |
424 | #undef pr_fmt |
425 | #define pr_fmt(fmt) "Speculative Store Bypass: " fmt | |
426 | ||
f9544b2b | 427 | static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; |
24f7fc83 KRW |
428 | |
429 | /* The kernel command line selection */ | |
430 | enum ssb_mitigation_cmd { | |
431 | SPEC_STORE_BYPASS_CMD_NONE, | |
432 | SPEC_STORE_BYPASS_CMD_AUTO, | |
433 | SPEC_STORE_BYPASS_CMD_ON, | |
a73ec77e | 434 | SPEC_STORE_BYPASS_CMD_PRCTL, |
f21b53b2 | 435 | SPEC_STORE_BYPASS_CMD_SECCOMP, |
24f7fc83 KRW |
436 | }; |
437 | ||
438 | static const char *ssb_strings[] = { | |
439 | [SPEC_STORE_BYPASS_NONE] = "Vulnerable", | |
a73ec77e | 440 | [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", |
f21b53b2 KC |
441 | [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", |
442 | [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", | |
24f7fc83 KRW |
443 | }; |
444 | ||
445 | static const struct { | |
446 | const char *option; | |
447 | enum ssb_mitigation_cmd cmd; | |
448 | } ssb_mitigation_options[] = { | |
f21b53b2 KC |
449 | { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ |
450 | { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ | |
451 | { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ | |
452 | { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ | |
453 | { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ | |
24f7fc83 KRW |
454 | }; |
455 | ||
456 | static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) | |
457 | { | |
458 | enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; | |
459 | char arg[20]; | |
460 | int ret, i; | |
461 | ||
462 | if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) { | |
463 | return SPEC_STORE_BYPASS_CMD_NONE; | |
464 | } else { | |
465 | ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", | |
466 | arg, sizeof(arg)); | |
467 | if (ret < 0) | |
468 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
469 | ||
470 | for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { | |
471 | if (!match_option(arg, ret, ssb_mitigation_options[i].option)) | |
472 | continue; | |
473 | ||
474 | cmd = ssb_mitigation_options[i].cmd; | |
475 | break; | |
476 | } | |
477 | ||
478 | if (i >= ARRAY_SIZE(ssb_mitigation_options)) { | |
479 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
480 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
481 | } | |
482 | } | |
483 | ||
484 | return cmd; | |
485 | } | |
486 | ||
d66d8ff3 | 487 | static enum ssb_mitigation __init __ssb_select_mitigation(void) |
24f7fc83 KRW |
488 | { |
489 | enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; | |
490 | enum ssb_mitigation_cmd cmd; | |
491 | ||
9f65fb29 | 492 | if (!boot_cpu_has(X86_FEATURE_SSBD)) |
24f7fc83 KRW |
493 | return mode; |
494 | ||
495 | cmd = ssb_parse_cmdline(); | |
496 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && | |
497 | (cmd == SPEC_STORE_BYPASS_CMD_NONE || | |
498 | cmd == SPEC_STORE_BYPASS_CMD_AUTO)) | |
499 | return mode; | |
500 | ||
501 | switch (cmd) { | |
502 | case SPEC_STORE_BYPASS_CMD_AUTO: | |
f21b53b2 KC |
503 | case SPEC_STORE_BYPASS_CMD_SECCOMP: |
504 | /* | |
505 | * Choose prctl+seccomp as the default mode if seccomp is | |
506 | * enabled. | |
507 | */ | |
508 | if (IS_ENABLED(CONFIG_SECCOMP)) | |
509 | mode = SPEC_STORE_BYPASS_SECCOMP; | |
510 | else | |
511 | mode = SPEC_STORE_BYPASS_PRCTL; | |
a73ec77e | 512 | break; |
24f7fc83 KRW |
513 | case SPEC_STORE_BYPASS_CMD_ON: |
514 | mode = SPEC_STORE_BYPASS_DISABLE; | |
515 | break; | |
a73ec77e TG |
516 | case SPEC_STORE_BYPASS_CMD_PRCTL: |
517 | mode = SPEC_STORE_BYPASS_PRCTL; | |
518 | break; | |
24f7fc83 KRW |
519 | case SPEC_STORE_BYPASS_CMD_NONE: |
520 | break; | |
521 | } | |
522 | ||
77243971 KRW |
523 | /* |
524 | * We have three CPU feature flags that are in play here: | |
525 | * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. | |
9f65fb29 | 526 | * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass |
77243971 KRW |
527 | * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation |
528 | */ | |
a73ec77e | 529 | if (mode == SPEC_STORE_BYPASS_DISABLE) { |
24f7fc83 | 530 | setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); |
77243971 | 531 | /* |
6ac2f49e KRW |
532 | * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may |
533 | * use a completely different MSR and bit dependent on family. | |
77243971 | 534 | */ |
108fab4b KRW |
535 | if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
536 | x86_amd_ssb_disable(); | |
537 | else { | |
9f65fb29 | 538 | x86_spec_ctrl_base |= SPEC_CTRL_SSBD; |
be6fcb54 | 539 | x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; |
4b59bdb5 | 540 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
77243971 KRW |
541 | } |
542 | } | |
543 | ||
24f7fc83 KRW |
544 | return mode; |
545 | } | |
546 | ||
ffed645e | 547 | static void ssb_select_mitigation(void) |
24f7fc83 KRW |
548 | { |
549 | ssb_mode = __ssb_select_mitigation(); | |
550 | ||
551 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
552 | pr_info("%s\n", ssb_strings[ssb_mode]); | |
553 | } | |
554 | ||
da285121 | 555 | #undef pr_fmt |
f21b53b2 | 556 | #define pr_fmt(fmt) "Speculation prctl: " fmt |
da285121 | 557 | |
7bbf1373 | 558 | static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) |
a73ec77e | 559 | { |
356e4bff | 560 | bool update; |
a73ec77e | 561 | |
f21b53b2 KC |
562 | if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && |
563 | ssb_mode != SPEC_STORE_BYPASS_SECCOMP) | |
a73ec77e TG |
564 | return -ENXIO; |
565 | ||
356e4bff TG |
566 | switch (ctrl) { |
567 | case PR_SPEC_ENABLE: | |
568 | /* If speculation is force disabled, enable is not allowed */ | |
569 | if (task_spec_ssb_force_disable(task)) | |
570 | return -EPERM; | |
571 | task_clear_spec_ssb_disable(task); | |
9f65fb29 | 572 | update = test_and_clear_tsk_thread_flag(task, TIF_SSBD); |
356e4bff TG |
573 | break; |
574 | case PR_SPEC_DISABLE: | |
575 | task_set_spec_ssb_disable(task); | |
9f65fb29 | 576 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
356e4bff TG |
577 | break; |
578 | case PR_SPEC_FORCE_DISABLE: | |
579 | task_set_spec_ssb_disable(task); | |
580 | task_set_spec_ssb_force_disable(task); | |
9f65fb29 | 581 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
356e4bff TG |
582 | break; |
583 | default: | |
584 | return -ERANGE; | |
585 | } | |
a73ec77e | 586 | |
7bbf1373 KC |
587 | /* |
588 | * If being set on non-current task, delay setting the CPU | |
589 | * mitigation until it is next scheduled. | |
590 | */ | |
356e4bff | 591 | if (task == current && update) |
0270be3e | 592 | speculative_store_bypass_update_current(); |
a73ec77e TG |
593 | |
594 | return 0; | |
595 | } | |
596 | ||
8bf37d8c TG |
597 | int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, |
598 | unsigned long ctrl) | |
599 | { | |
600 | switch (which) { | |
601 | case PR_SPEC_STORE_BYPASS: | |
602 | return ssb_prctl_set(task, ctrl); | |
603 | default: | |
604 | return -ENODEV; | |
605 | } | |
606 | } | |
607 | ||
608 | #ifdef CONFIG_SECCOMP | |
609 | void arch_seccomp_spec_mitigate(struct task_struct *task) | |
610 | { | |
f21b53b2 KC |
611 | if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) |
612 | ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
8bf37d8c TG |
613 | } |
614 | #endif | |
615 | ||
7bbf1373 | 616 | static int ssb_prctl_get(struct task_struct *task) |
a73ec77e TG |
617 | { |
618 | switch (ssb_mode) { | |
619 | case SPEC_STORE_BYPASS_DISABLE: | |
620 | return PR_SPEC_DISABLE; | |
f21b53b2 | 621 | case SPEC_STORE_BYPASS_SECCOMP: |
a73ec77e | 622 | case SPEC_STORE_BYPASS_PRCTL: |
356e4bff TG |
623 | if (task_spec_ssb_force_disable(task)) |
624 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
625 | if (task_spec_ssb_disable(task)) | |
a73ec77e TG |
626 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; |
627 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
628 | default: | |
629 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
630 | return PR_SPEC_ENABLE; | |
631 | return PR_SPEC_NOT_AFFECTED; | |
632 | } | |
633 | } | |
634 | ||
7bbf1373 | 635 | int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) |
a73ec77e TG |
636 | { |
637 | switch (which) { | |
638 | case PR_SPEC_STORE_BYPASS: | |
7bbf1373 | 639 | return ssb_prctl_get(task); |
a73ec77e TG |
640 | default: |
641 | return -ENODEV; | |
642 | } | |
643 | } | |
644 | ||
77243971 KRW |
645 | void x86_spec_ctrl_setup_ap(void) |
646 | { | |
7eb8956a | 647 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
4b59bdb5 | 648 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
764f3c21 KRW |
649 | |
650 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) | |
9f65fb29 | 651 | x86_amd_ssb_disable(); |
77243971 KRW |
652 | } |
653 | ||
61dc0f55 | 654 | #ifdef CONFIG_SYSFS |
d1059518 | 655 | |
7bb4d366 | 656 | static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, |
ffed645e | 657 | char *buf, unsigned int bug) |
61dc0f55 | 658 | { |
d1059518 | 659 | if (!boot_cpu_has_bug(bug)) |
61dc0f55 | 660 | return sprintf(buf, "Not affected\n"); |
d1059518 KRW |
661 | |
662 | switch (bug) { | |
663 | case X86_BUG_CPU_MELTDOWN: | |
664 | if (boot_cpu_has(X86_FEATURE_PTI)) | |
665 | return sprintf(buf, "Mitigation: PTI\n"); | |
666 | ||
667 | break; | |
668 | ||
669 | case X86_BUG_SPECTRE_V1: | |
670 | return sprintf(buf, "Mitigation: __user pointer sanitization\n"); | |
671 | ||
672 | case X86_BUG_SPECTRE_V2: | |
673 | return sprintf(buf, "%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], | |
674 | boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "", | |
675 | boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", | |
676 | spectre_v2_module_string()); | |
677 | ||
24f7fc83 KRW |
678 | case X86_BUG_SPEC_STORE_BYPASS: |
679 | return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); | |
680 | ||
d1059518 KRW |
681 | default: |
682 | break; | |
683 | } | |
684 | ||
61dc0f55 TG |
685 | return sprintf(buf, "Vulnerable\n"); |
686 | } | |
687 | ||
d1059518 KRW |
688 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) |
689 | { | |
690 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); | |
691 | } | |
692 | ||
21e433bd | 693 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 694 | { |
d1059518 | 695 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
61dc0f55 TG |
696 | } |
697 | ||
21e433bd | 698 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 699 | { |
d1059518 | 700 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); |
61dc0f55 | 701 | } |
c456442c KRW |
702 | |
703 | ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) | |
704 | { | |
705 | return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); | |
706 | } | |
61dc0f55 | 707 | #endif |