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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1353ebb4 | 2 | /* |
1353ebb4 JF |
3 | * Copyright (C) 1994 Linus Torvalds |
4 | * | |
5 | * Cyrix stuff, June 1998 by: | |
6 | * - Rafael R. Reilova (moved everything from head.S), | |
7 | * <rreilova@ececs.uc.edu> | |
8 | * - Channing Corn (tests & fixes), | |
9 | * - Andrew D. Balsa (code cleanup). | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/utsname.h> | |
61dc0f55 | 13 | #include <linux/cpu.h> |
caf7501a | 14 | #include <linux/module.h> |
a73ec77e TG |
15 | #include <linux/nospec.h> |
16 | #include <linux/prctl.h> | |
a74cfffb | 17 | #include <linux/sched/smt.h> |
da285121 | 18 | |
28a27752 | 19 | #include <asm/spec-ctrl.h> |
da285121 | 20 | #include <asm/cmdline.h> |
91eb1b79 | 21 | #include <asm/bugs.h> |
1353ebb4 | 22 | #include <asm/processor.h> |
7ebad705 | 23 | #include <asm/processor-flags.h> |
952f07ec | 24 | #include <asm/fpu/internal.h> |
1353ebb4 | 25 | #include <asm/msr.h> |
72c6d2db | 26 | #include <asm/vmx.h> |
1353ebb4 JF |
27 | #include <asm/paravirt.h> |
28 | #include <asm/alternative.h> | |
62a67e12 | 29 | #include <asm/pgtable.h> |
d1163651 | 30 | #include <asm/set_memory.h> |
c995efd5 | 31 | #include <asm/intel-family.h> |
17dbca11 | 32 | #include <asm/e820/api.h> |
6cb2b08f | 33 | #include <asm/hypervisor.h> |
1353ebb4 | 34 | |
da285121 | 35 | static void __init spectre_v2_select_mitigation(void); |
24f7fc83 | 36 | static void __init ssb_select_mitigation(void); |
17dbca11 | 37 | static void __init l1tf_select_mitigation(void); |
da285121 | 38 | |
53c613fe JK |
39 | /* The base value of the SPEC_CTRL MSR that always has to be preserved. */ |
40 | u64 x86_spec_ctrl_base; | |
fa8ac498 | 41 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); |
53c613fe | 42 | static DEFINE_MUTEX(spec_ctrl_mutex); |
1b86883c | 43 | |
1115a859 KRW |
44 | /* |
45 | * The vendor and possibly platform specific bits which can be modified in | |
46 | * x86_spec_ctrl_base. | |
47 | */ | |
be6fcb54 | 48 | static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS; |
1115a859 | 49 | |
764f3c21 KRW |
50 | /* |
51 | * AMD specific MSR info for Speculative Store Bypass control. | |
9f65fb29 | 52 | * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). |
764f3c21 KRW |
53 | */ |
54 | u64 __ro_after_init x86_amd_ls_cfg_base; | |
9f65fb29 | 55 | u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; |
764f3c21 | 56 | |
aa77bfb3 | 57 | /* Control conditional STIBP in switch_to() */ |
fa1202ef | 58 | DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp); |
4c71a2b6 TG |
59 | /* Control conditional IBPB in switch_mm() */ |
60 | DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb); | |
61 | /* Control unconditional IBPB in switch_mm() */ | |
62 | DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb); | |
fa1202ef | 63 | |
1353ebb4 JF |
64 | void __init check_bugs(void) |
65 | { | |
66 | identify_boot_cpu(); | |
55a36b65 | 67 | |
fee0aede TG |
68 | /* |
69 | * identify_boot_cpu() initialized SMT support information, let the | |
70 | * core code know. | |
71 | */ | |
bc2d8d26 | 72 | cpu_smt_check_topology_early(); |
fee0aede | 73 | |
62a67e12 BP |
74 | if (!IS_ENABLED(CONFIG_SMP)) { |
75 | pr_info("CPU: "); | |
76 | print_cpu_info(&boot_cpu_data); | |
77 | } | |
78 | ||
1b86883c KRW |
79 | /* |
80 | * Read the SPEC_CTRL MSR to account for reserved bits which may | |
764f3c21 KRW |
81 | * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD |
82 | * init code as it is not enumerated and depends on the family. | |
1b86883c | 83 | */ |
7eb8956a | 84 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
1b86883c KRW |
85 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
86 | ||
be6fcb54 TG |
87 | /* Allow STIBP in MSR_SPEC_CTRL if supported */ |
88 | if (boot_cpu_has(X86_FEATURE_STIBP)) | |
89 | x86_spec_ctrl_mask |= SPEC_CTRL_STIBP; | |
90 | ||
da285121 DW |
91 | /* Select the proper spectre mitigation before patching alternatives */ |
92 | spectre_v2_select_mitigation(); | |
93 | ||
24f7fc83 KRW |
94 | /* |
95 | * Select proper mitigation for any exposure to the Speculative Store | |
96 | * Bypass vulnerability. | |
97 | */ | |
98 | ssb_select_mitigation(); | |
99 | ||
17dbca11 AK |
100 | l1tf_select_mitigation(); |
101 | ||
62a67e12 | 102 | #ifdef CONFIG_X86_32 |
55a36b65 BP |
103 | /* |
104 | * Check whether we are able to run this kernel safely on SMP. | |
105 | * | |
106 | * - i386 is no longer supported. | |
107 | * - In order to run on anything without a TSC, we need to be | |
108 | * compiled for a i486. | |
109 | */ | |
110 | if (boot_cpu_data.x86 < 4) | |
111 | panic("Kernel requires i486+ for 'invlpg' and other features"); | |
112 | ||
bfe4bb15 MV |
113 | init_utsname()->machine[1] = |
114 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); | |
1353ebb4 | 115 | alternative_instructions(); |
304bceda | 116 | |
4d164092 | 117 | fpu__init_check_bugs(); |
62a67e12 BP |
118 | #else /* CONFIG_X86_64 */ |
119 | alternative_instructions(); | |
120 | ||
121 | /* | |
122 | * Make sure the first 2MB area is not mapped by huge pages | |
123 | * There are typically fixed size MTRRs in there and overlapping | |
124 | * MTRRs into large pages causes slow downs. | |
125 | * | |
126 | * Right now we don't do that with gbpages because there seems | |
127 | * very little benefit for that case. | |
128 | */ | |
129 | if (!direct_gbpages) | |
130 | set_memory_4k((unsigned long)__va(0), 1); | |
131 | #endif | |
1353ebb4 | 132 | } |
61dc0f55 | 133 | |
cc69b349 BP |
134 | void |
135 | x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) | |
5cf68754 | 136 | { |
be6fcb54 | 137 | u64 msrval, guestval, hostval = x86_spec_ctrl_base; |
cc69b349 | 138 | struct thread_info *ti = current_thread_info(); |
885f82bf | 139 | |
7eb8956a | 140 | /* Is MSR_SPEC_CTRL implemented ? */ |
cc69b349 | 141 | if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { |
be6fcb54 TG |
142 | /* |
143 | * Restrict guest_spec_ctrl to supported values. Clear the | |
144 | * modifiable bits in the host base value and or the | |
145 | * modifiable bits from the guest value. | |
146 | */ | |
147 | guestval = hostval & ~x86_spec_ctrl_mask; | |
148 | guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; | |
149 | ||
cc69b349 | 150 | /* SSBD controlled in MSR_SPEC_CTRL */ |
612bc3b3 TL |
151 | if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || |
152 | static_cpu_has(X86_FEATURE_AMD_SSBD)) | |
be6fcb54 | 153 | hostval |= ssbd_tif_to_spec_ctrl(ti->flags); |
cc69b349 | 154 | |
5bfbe3ad TC |
155 | /* Conditional STIBP enabled? */ |
156 | if (static_branch_unlikely(&switch_to_cond_stibp)) | |
157 | hostval |= stibp_tif_to_spec_ctrl(ti->flags); | |
158 | ||
be6fcb54 TG |
159 | if (hostval != guestval) { |
160 | msrval = setguest ? guestval : hostval; | |
161 | wrmsrl(MSR_IA32_SPEC_CTRL, msrval); | |
cc69b349 BP |
162 | } |
163 | } | |
47c61b39 TG |
164 | |
165 | /* | |
166 | * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update | |
167 | * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. | |
168 | */ | |
169 | if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && | |
170 | !static_cpu_has(X86_FEATURE_VIRT_SSBD)) | |
171 | return; | |
172 | ||
173 | /* | |
174 | * If the host has SSBD mitigation enabled, force it in the host's | |
175 | * virtual MSR value. If its not permanently enabled, evaluate | |
176 | * current's TIF_SSBD thread flag. | |
177 | */ | |
178 | if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) | |
179 | hostval = SPEC_CTRL_SSBD; | |
180 | else | |
181 | hostval = ssbd_tif_to_spec_ctrl(ti->flags); | |
182 | ||
183 | /* Sanitize the guest value */ | |
184 | guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; | |
185 | ||
186 | if (hostval != guestval) { | |
187 | unsigned long tif; | |
188 | ||
189 | tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : | |
190 | ssbd_spec_ctrl_to_tif(hostval); | |
191 | ||
26c4d75b | 192 | speculation_ctrl_update(tif); |
47c61b39 | 193 | } |
5cf68754 | 194 | } |
cc69b349 | 195 | EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); |
5cf68754 | 196 | |
9f65fb29 | 197 | static void x86_amd_ssb_disable(void) |
764f3c21 | 198 | { |
9f65fb29 | 199 | u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; |
764f3c21 | 200 | |
11fb0683 TL |
201 | if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) |
202 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); | |
203 | else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) | |
764f3c21 KRW |
204 | wrmsrl(MSR_AMD64_LS_CFG, msrval); |
205 | } | |
206 | ||
15d6b7aa TG |
207 | #undef pr_fmt |
208 | #define pr_fmt(fmt) "Spectre V2 : " fmt | |
209 | ||
210 | static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = | |
211 | SPECTRE_V2_NONE; | |
212 | ||
fa1202ef TG |
213 | static enum spectre_v2_user_mitigation spectre_v2_user __ro_after_init = |
214 | SPECTRE_V2_USER_NONE; | |
215 | ||
caf7501a | 216 | #ifdef RETPOLINE |
e383095c TG |
217 | static bool spectre_v2_bad_module; |
218 | ||
caf7501a AK |
219 | bool retpoline_module_ok(bool has_retpoline) |
220 | { | |
221 | if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) | |
222 | return true; | |
223 | ||
e698dcdf | 224 | pr_err("System may be vulnerable to spectre v2\n"); |
caf7501a AK |
225 | spectre_v2_bad_module = true; |
226 | return false; | |
227 | } | |
e383095c TG |
228 | |
229 | static inline const char *spectre_v2_module_string(void) | |
230 | { | |
231 | return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; | |
232 | } | |
233 | #else | |
234 | static inline const char *spectre_v2_module_string(void) { return ""; } | |
caf7501a | 235 | #endif |
da285121 | 236 | |
da285121 DW |
237 | static inline bool match_option(const char *arg, int arglen, const char *opt) |
238 | { | |
239 | int len = strlen(opt); | |
240 | ||
241 | return len == arglen && !strncmp(arg, opt, len); | |
242 | } | |
243 | ||
15d6b7aa TG |
244 | /* The kernel command line selection for spectre v2 */ |
245 | enum spectre_v2_mitigation_cmd { | |
246 | SPECTRE_V2_CMD_NONE, | |
247 | SPECTRE_V2_CMD_AUTO, | |
248 | SPECTRE_V2_CMD_FORCE, | |
249 | SPECTRE_V2_CMD_RETPOLINE, | |
250 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, | |
251 | SPECTRE_V2_CMD_RETPOLINE_AMD, | |
252 | }; | |
253 | ||
fa1202ef TG |
254 | enum spectre_v2_user_cmd { |
255 | SPECTRE_V2_USER_CMD_NONE, | |
256 | SPECTRE_V2_USER_CMD_AUTO, | |
257 | SPECTRE_V2_USER_CMD_FORCE, | |
7cc765a6 | 258 | SPECTRE_V2_USER_CMD_PRCTL, |
55a97402 | 259 | SPECTRE_V2_USER_CMD_PRCTL_IBPB, |
6b3e64c2 | 260 | SPECTRE_V2_USER_CMD_SECCOMP, |
55a97402 | 261 | SPECTRE_V2_USER_CMD_SECCOMP_IBPB, |
fa1202ef TG |
262 | }; |
263 | ||
264 | static const char * const spectre_v2_user_strings[] = { | |
265 | [SPECTRE_V2_USER_NONE] = "User space: Vulnerable", | |
266 | [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection", | |
7cc765a6 | 267 | [SPECTRE_V2_USER_PRCTL] = "User space: Mitigation: STIBP via prctl", |
6b3e64c2 | 268 | [SPECTRE_V2_USER_SECCOMP] = "User space: Mitigation: STIBP via seccomp and prctl", |
fa1202ef TG |
269 | }; |
270 | ||
271 | static const struct { | |
272 | const char *option; | |
273 | enum spectre_v2_user_cmd cmd; | |
274 | bool secure; | |
275 | } v2_user_options[] __initdata = { | |
55a97402 TG |
276 | { "auto", SPECTRE_V2_USER_CMD_AUTO, false }, |
277 | { "off", SPECTRE_V2_USER_CMD_NONE, false }, | |
278 | { "on", SPECTRE_V2_USER_CMD_FORCE, true }, | |
279 | { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false }, | |
280 | { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB, false }, | |
281 | { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false }, | |
282 | { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB, false }, | |
fa1202ef TG |
283 | }; |
284 | ||
285 | static void __init spec_v2_user_print_cond(const char *reason, bool secure) | |
286 | { | |
287 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) | |
288 | pr_info("spectre_v2_user=%s forced on command line.\n", reason); | |
289 | } | |
290 | ||
291 | static enum spectre_v2_user_cmd __init | |
292 | spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd) | |
293 | { | |
294 | char arg[20]; | |
295 | int ret, i; | |
296 | ||
297 | switch (v2_cmd) { | |
298 | case SPECTRE_V2_CMD_NONE: | |
299 | return SPECTRE_V2_USER_CMD_NONE; | |
300 | case SPECTRE_V2_CMD_FORCE: | |
301 | return SPECTRE_V2_USER_CMD_FORCE; | |
302 | default: | |
303 | break; | |
304 | } | |
305 | ||
306 | ret = cmdline_find_option(boot_command_line, "spectre_v2_user", | |
307 | arg, sizeof(arg)); | |
308 | if (ret < 0) | |
309 | return SPECTRE_V2_USER_CMD_AUTO; | |
310 | ||
311 | for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) { | |
312 | if (match_option(arg, ret, v2_user_options[i].option)) { | |
313 | spec_v2_user_print_cond(v2_user_options[i].option, | |
314 | v2_user_options[i].secure); | |
315 | return v2_user_options[i].cmd; | |
316 | } | |
317 | } | |
318 | ||
319 | pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg); | |
320 | return SPECTRE_V2_USER_CMD_AUTO; | |
321 | } | |
322 | ||
323 | static void __init | |
324 | spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd) | |
325 | { | |
326 | enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE; | |
327 | bool smt_possible = IS_ENABLED(CONFIG_SMP); | |
55a97402 | 328 | enum spectre_v2_user_cmd cmd; |
fa1202ef TG |
329 | |
330 | if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP)) | |
331 | return; | |
332 | ||
333 | if (cpu_smt_control == CPU_SMT_FORCE_DISABLED || | |
334 | cpu_smt_control == CPU_SMT_NOT_SUPPORTED) | |
335 | smt_possible = false; | |
336 | ||
55a97402 TG |
337 | cmd = spectre_v2_parse_user_cmdline(v2_cmd); |
338 | switch (cmd) { | |
fa1202ef TG |
339 | case SPECTRE_V2_USER_CMD_NONE: |
340 | goto set_mode; | |
341 | case SPECTRE_V2_USER_CMD_FORCE: | |
342 | mode = SPECTRE_V2_USER_STRICT; | |
343 | break; | |
7cc765a6 | 344 | case SPECTRE_V2_USER_CMD_PRCTL: |
55a97402 | 345 | case SPECTRE_V2_USER_CMD_PRCTL_IBPB: |
7cc765a6 TG |
346 | mode = SPECTRE_V2_USER_PRCTL; |
347 | break; | |
6b3e64c2 TG |
348 | case SPECTRE_V2_USER_CMD_AUTO: |
349 | case SPECTRE_V2_USER_CMD_SECCOMP: | |
55a97402 | 350 | case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: |
6b3e64c2 TG |
351 | if (IS_ENABLED(CONFIG_SECCOMP)) |
352 | mode = SPECTRE_V2_USER_SECCOMP; | |
353 | else | |
354 | mode = SPECTRE_V2_USER_PRCTL; | |
355 | break; | |
fa1202ef TG |
356 | } |
357 | ||
358 | /* Initialize Indirect Branch Prediction Barrier */ | |
359 | if (boot_cpu_has(X86_FEATURE_IBPB)) { | |
360 | setup_force_cpu_cap(X86_FEATURE_USE_IBPB); | |
4c71a2b6 | 361 | |
55a97402 TG |
362 | switch (cmd) { |
363 | case SPECTRE_V2_USER_CMD_FORCE: | |
364 | case SPECTRE_V2_USER_CMD_PRCTL_IBPB: | |
365 | case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: | |
4c71a2b6 TG |
366 | static_branch_enable(&switch_mm_always_ibpb); |
367 | break; | |
55a97402 TG |
368 | case SPECTRE_V2_USER_CMD_PRCTL: |
369 | case SPECTRE_V2_USER_CMD_AUTO: | |
370 | case SPECTRE_V2_USER_CMD_SECCOMP: | |
7cc765a6 TG |
371 | static_branch_enable(&switch_mm_cond_ibpb); |
372 | break; | |
4c71a2b6 TG |
373 | default: |
374 | break; | |
375 | } | |
376 | ||
377 | pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n", | |
55a97402 TG |
378 | static_key_enabled(&switch_mm_always_ibpb) ? |
379 | "always-on" : "conditional"); | |
fa1202ef TG |
380 | } |
381 | ||
aa77bfb3 | 382 | /* If enhanced IBRS is enabled no STIBP required */ |
fa1202ef TG |
383 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) |
384 | return; | |
385 | ||
7cc765a6 | 386 | /* |
aa77bfb3 | 387 | * If SMT is not possible or STIBP is not available clear the STIBP |
7cc765a6 TG |
388 | * mode. |
389 | */ | |
390 | if (!smt_possible || !boot_cpu_has(X86_FEATURE_STIBP)) | |
391 | mode = SPECTRE_V2_USER_NONE; | |
fa1202ef TG |
392 | set_mode: |
393 | spectre_v2_user = mode; | |
394 | /* Only print the STIBP mode when SMT possible */ | |
395 | if (smt_possible) | |
396 | pr_info("%s\n", spectre_v2_user_strings[mode]); | |
397 | } | |
398 | ||
8770709f | 399 | static const char * const spectre_v2_strings[] = { |
15d6b7aa TG |
400 | [SPECTRE_V2_NONE] = "Vulnerable", |
401 | [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", | |
402 | [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", | |
403 | [SPECTRE_V2_IBRS_ENHANCED] = "Mitigation: Enhanced IBRS", | |
404 | }; | |
405 | ||
9005c683 KA |
406 | static const struct { |
407 | const char *option; | |
408 | enum spectre_v2_mitigation_cmd cmd; | |
409 | bool secure; | |
30ba72a9 | 410 | } mitigation_options[] __initdata = { |
15d6b7aa TG |
411 | { "off", SPECTRE_V2_CMD_NONE, false }, |
412 | { "on", SPECTRE_V2_CMD_FORCE, true }, | |
413 | { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, | |
414 | { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, | |
415 | { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, | |
416 | { "auto", SPECTRE_V2_CMD_AUTO, false }, | |
9005c683 KA |
417 | }; |
418 | ||
495d470e | 419 | static void __init spec_v2_print_cond(const char *reason, bool secure) |
15d6b7aa | 420 | { |
495d470e | 421 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) |
15d6b7aa TG |
422 | pr_info("%s selected on command line.\n", reason); |
423 | } | |
424 | ||
da285121 DW |
425 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) |
426 | { | |
15d6b7aa | 427 | enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; |
da285121 | 428 | char arg[20]; |
9005c683 | 429 | int ret, i; |
9005c683 KA |
430 | |
431 | if (cmdline_find_option_bool(boot_command_line, "nospectre_v2")) | |
432 | return SPECTRE_V2_CMD_NONE; | |
9005c683 | 433 | |
24848509 TC |
434 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); |
435 | if (ret < 0) | |
436 | return SPECTRE_V2_CMD_AUTO; | |
437 | ||
438 | for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { | |
439 | if (!match_option(arg, ret, mitigation_options[i].option)) | |
440 | continue; | |
441 | cmd = mitigation_options[i].cmd; | |
442 | break; | |
443 | } | |
444 | ||
445 | if (i >= ARRAY_SIZE(mitigation_options)) { | |
446 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
447 | return SPECTRE_V2_CMD_AUTO; | |
da285121 DW |
448 | } |
449 | ||
9005c683 KA |
450 | if ((cmd == SPECTRE_V2_CMD_RETPOLINE || |
451 | cmd == SPECTRE_V2_CMD_RETPOLINE_AMD || | |
452 | cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) && | |
453 | !IS_ENABLED(CONFIG_RETPOLINE)) { | |
21e433bd | 454 | pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option); |
da285121 | 455 | return SPECTRE_V2_CMD_AUTO; |
9005c683 KA |
456 | } |
457 | ||
458 | if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD && | |
1a576b23 | 459 | boot_cpu_data.x86_vendor != X86_VENDOR_HYGON && |
9005c683 KA |
460 | boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { |
461 | pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); | |
462 | return SPECTRE_V2_CMD_AUTO; | |
463 | } | |
464 | ||
495d470e TG |
465 | spec_v2_print_cond(mitigation_options[i].option, |
466 | mitigation_options[i].secure); | |
9005c683 | 467 | return cmd; |
da285121 DW |
468 | } |
469 | ||
470 | static void __init spectre_v2_select_mitigation(void) | |
471 | { | |
472 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | |
473 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; | |
474 | ||
475 | /* | |
476 | * If the CPU is not affected and the command line mode is NONE or AUTO | |
477 | * then nothing to do. | |
478 | */ | |
479 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && | |
480 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) | |
481 | return; | |
482 | ||
483 | switch (cmd) { | |
484 | case SPECTRE_V2_CMD_NONE: | |
485 | return; | |
486 | ||
487 | case SPECTRE_V2_CMD_FORCE: | |
da285121 | 488 | case SPECTRE_V2_CMD_AUTO: |
706d5168 SP |
489 | if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { |
490 | mode = SPECTRE_V2_IBRS_ENHANCED; | |
491 | /* Force it so VMEXIT will restore correctly */ | |
492 | x86_spec_ctrl_base |= SPEC_CTRL_IBRS; | |
493 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
494 | goto specv2_set_mode; | |
495 | } | |
9471eee9 DL |
496 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
497 | goto retpoline_auto; | |
498 | break; | |
da285121 DW |
499 | case SPECTRE_V2_CMD_RETPOLINE_AMD: |
500 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
501 | goto retpoline_amd; | |
502 | break; | |
503 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: | |
504 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
505 | goto retpoline_generic; | |
506 | break; | |
507 | case SPECTRE_V2_CMD_RETPOLINE: | |
508 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
509 | goto retpoline_auto; | |
510 | break; | |
511 | } | |
21e433bd | 512 | pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!"); |
da285121 DW |
513 | return; |
514 | ||
515 | retpoline_auto: | |
1a576b23 PW |
516 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || |
517 | boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) { | |
da285121 DW |
518 | retpoline_amd: |
519 | if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { | |
21e433bd | 520 | pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n"); |
da285121 DW |
521 | goto retpoline_generic; |
522 | } | |
ef014aae | 523 | mode = SPECTRE_V2_RETPOLINE_AMD; |
da285121 DW |
524 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); |
525 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
526 | } else { | |
527 | retpoline_generic: | |
ef014aae | 528 | mode = SPECTRE_V2_RETPOLINE_GENERIC; |
da285121 DW |
529 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); |
530 | } | |
531 | ||
706d5168 | 532 | specv2_set_mode: |
da285121 DW |
533 | spectre_v2_enabled = mode; |
534 | pr_info("%s\n", spectre_v2_strings[mode]); | |
c995efd5 DW |
535 | |
536 | /* | |
fdf82a78 JK |
537 | * If spectre v2 protection has been enabled, unconditionally fill |
538 | * RSB during a context switch; this protects against two independent | |
539 | * issues: | |
c995efd5 | 540 | * |
fdf82a78 JK |
541 | * - RSB underflow (and switch to BTB) on Skylake+ |
542 | * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs | |
c995efd5 | 543 | */ |
fdf82a78 JK |
544 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); |
545 | pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n"); | |
20ffa1ca | 546 | |
dd84441a DW |
547 | /* |
548 | * Retpoline means the kernel is safe because it has no indirect | |
706d5168 SP |
549 | * branches. Enhanced IBRS protects firmware too, so, enable restricted |
550 | * speculation around firmware calls only when Enhanced IBRS isn't | |
551 | * supported. | |
552 | * | |
553 | * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because | |
554 | * the user might select retpoline on the kernel command line and if | |
555 | * the CPU supports Enhanced IBRS, kernel might un-intentionally not | |
556 | * enable IBRS around firmware calls. | |
dd84441a | 557 | */ |
706d5168 | 558 | if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) { |
dd84441a DW |
559 | setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); |
560 | pr_info("Enabling Restricted Speculation for firmware calls\n"); | |
561 | } | |
53c613fe | 562 | |
fa1202ef TG |
563 | /* Set up IBPB and STIBP depending on the general spectre V2 command */ |
564 | spectre_v2_user_select_mitigation(cmd); | |
565 | ||
53c613fe JK |
566 | /* Enable STIBP if appropriate */ |
567 | arch_smt_update(); | |
da285121 DW |
568 | } |
569 | ||
6893a959 | 570 | static void update_stibp_msr(void * __unused) |
15d6b7aa | 571 | { |
6893a959 | 572 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
15d6b7aa TG |
573 | } |
574 | ||
6893a959 TG |
575 | /* Update x86_spec_ctrl_base in case SMT state changed. */ |
576 | static void update_stibp_strict(void) | |
15d6b7aa | 577 | { |
6893a959 TG |
578 | u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP; |
579 | ||
580 | if (sched_smt_active()) | |
581 | mask |= SPEC_CTRL_STIBP; | |
582 | ||
583 | if (mask == x86_spec_ctrl_base) | |
584 | return; | |
585 | ||
586 | pr_info("Update user space SMT mitigation: STIBP %s\n", | |
587 | mask & SPEC_CTRL_STIBP ? "always-on" : "off"); | |
588 | x86_spec_ctrl_base = mask; | |
589 | on_each_cpu(update_stibp_msr, NULL, 1); | |
15d6b7aa TG |
590 | } |
591 | ||
7cc765a6 TG |
592 | /* Update the static key controlling the evaluation of TIF_SPEC_IB */ |
593 | static void update_indir_branch_cond(void) | |
594 | { | |
595 | if (sched_smt_active()) | |
596 | static_branch_enable(&switch_to_cond_stibp); | |
597 | else | |
598 | static_branch_disable(&switch_to_cond_stibp); | |
599 | } | |
600 | ||
15d6b7aa TG |
601 | void arch_smt_update(void) |
602 | { | |
6893a959 TG |
603 | /* Enhanced IBRS implies STIBP. No update required. */ |
604 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) | |
15d6b7aa TG |
605 | return; |
606 | ||
607 | mutex_lock(&spec_ctrl_mutex); | |
608 | ||
6893a959 TG |
609 | switch (spectre_v2_user) { |
610 | case SPECTRE_V2_USER_NONE: | |
611 | break; | |
612 | case SPECTRE_V2_USER_STRICT: | |
613 | update_stibp_strict(); | |
614 | break; | |
9137bb27 | 615 | case SPECTRE_V2_USER_PRCTL: |
6b3e64c2 | 616 | case SPECTRE_V2_USER_SECCOMP: |
7cc765a6 | 617 | update_indir_branch_cond(); |
9137bb27 | 618 | break; |
15d6b7aa | 619 | } |
6893a959 | 620 | |
15d6b7aa TG |
621 | mutex_unlock(&spec_ctrl_mutex); |
622 | } | |
623 | ||
24f7fc83 KRW |
624 | #undef pr_fmt |
625 | #define pr_fmt(fmt) "Speculative Store Bypass: " fmt | |
626 | ||
f9544b2b | 627 | static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; |
24f7fc83 KRW |
628 | |
629 | /* The kernel command line selection */ | |
630 | enum ssb_mitigation_cmd { | |
631 | SPEC_STORE_BYPASS_CMD_NONE, | |
632 | SPEC_STORE_BYPASS_CMD_AUTO, | |
633 | SPEC_STORE_BYPASS_CMD_ON, | |
a73ec77e | 634 | SPEC_STORE_BYPASS_CMD_PRCTL, |
f21b53b2 | 635 | SPEC_STORE_BYPASS_CMD_SECCOMP, |
24f7fc83 KRW |
636 | }; |
637 | ||
8770709f | 638 | static const char * const ssb_strings[] = { |
24f7fc83 | 639 | [SPEC_STORE_BYPASS_NONE] = "Vulnerable", |
a73ec77e | 640 | [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", |
f21b53b2 KC |
641 | [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", |
642 | [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", | |
24f7fc83 KRW |
643 | }; |
644 | ||
645 | static const struct { | |
646 | const char *option; | |
647 | enum ssb_mitigation_cmd cmd; | |
30ba72a9 | 648 | } ssb_mitigation_options[] __initdata = { |
f21b53b2 KC |
649 | { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ |
650 | { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ | |
651 | { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ | |
652 | { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ | |
653 | { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ | |
24f7fc83 KRW |
654 | }; |
655 | ||
656 | static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) | |
657 | { | |
658 | enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; | |
659 | char arg[20]; | |
660 | int ret, i; | |
661 | ||
662 | if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) { | |
663 | return SPEC_STORE_BYPASS_CMD_NONE; | |
664 | } else { | |
665 | ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", | |
666 | arg, sizeof(arg)); | |
667 | if (ret < 0) | |
668 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
669 | ||
670 | for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { | |
671 | if (!match_option(arg, ret, ssb_mitigation_options[i].option)) | |
672 | continue; | |
673 | ||
674 | cmd = ssb_mitigation_options[i].cmd; | |
675 | break; | |
676 | } | |
677 | ||
678 | if (i >= ARRAY_SIZE(ssb_mitigation_options)) { | |
679 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
680 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
681 | } | |
682 | } | |
683 | ||
684 | return cmd; | |
685 | } | |
686 | ||
d66d8ff3 | 687 | static enum ssb_mitigation __init __ssb_select_mitigation(void) |
24f7fc83 KRW |
688 | { |
689 | enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; | |
690 | enum ssb_mitigation_cmd cmd; | |
691 | ||
9f65fb29 | 692 | if (!boot_cpu_has(X86_FEATURE_SSBD)) |
24f7fc83 KRW |
693 | return mode; |
694 | ||
695 | cmd = ssb_parse_cmdline(); | |
696 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && | |
697 | (cmd == SPEC_STORE_BYPASS_CMD_NONE || | |
698 | cmd == SPEC_STORE_BYPASS_CMD_AUTO)) | |
699 | return mode; | |
700 | ||
701 | switch (cmd) { | |
702 | case SPEC_STORE_BYPASS_CMD_AUTO: | |
f21b53b2 KC |
703 | case SPEC_STORE_BYPASS_CMD_SECCOMP: |
704 | /* | |
705 | * Choose prctl+seccomp as the default mode if seccomp is | |
706 | * enabled. | |
707 | */ | |
708 | if (IS_ENABLED(CONFIG_SECCOMP)) | |
709 | mode = SPEC_STORE_BYPASS_SECCOMP; | |
710 | else | |
711 | mode = SPEC_STORE_BYPASS_PRCTL; | |
a73ec77e | 712 | break; |
24f7fc83 KRW |
713 | case SPEC_STORE_BYPASS_CMD_ON: |
714 | mode = SPEC_STORE_BYPASS_DISABLE; | |
715 | break; | |
a73ec77e TG |
716 | case SPEC_STORE_BYPASS_CMD_PRCTL: |
717 | mode = SPEC_STORE_BYPASS_PRCTL; | |
718 | break; | |
24f7fc83 KRW |
719 | case SPEC_STORE_BYPASS_CMD_NONE: |
720 | break; | |
721 | } | |
722 | ||
77243971 KRW |
723 | /* |
724 | * We have three CPU feature flags that are in play here: | |
725 | * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. | |
9f65fb29 | 726 | * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass |
77243971 KRW |
727 | * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation |
728 | */ | |
a73ec77e | 729 | if (mode == SPEC_STORE_BYPASS_DISABLE) { |
24f7fc83 | 730 | setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); |
77243971 | 731 | /* |
6ac2f49e KRW |
732 | * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may |
733 | * use a completely different MSR and bit dependent on family. | |
77243971 | 734 | */ |
612bc3b3 TL |
735 | if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && |
736 | !static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
108fab4b | 737 | x86_amd_ssb_disable(); |
612bc3b3 | 738 | } else { |
9f65fb29 | 739 | x86_spec_ctrl_base |= SPEC_CTRL_SSBD; |
be6fcb54 | 740 | x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; |
4b59bdb5 | 741 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
77243971 KRW |
742 | } |
743 | } | |
744 | ||
24f7fc83 KRW |
745 | return mode; |
746 | } | |
747 | ||
ffed645e | 748 | static void ssb_select_mitigation(void) |
24f7fc83 KRW |
749 | { |
750 | ssb_mode = __ssb_select_mitigation(); | |
751 | ||
752 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
753 | pr_info("%s\n", ssb_strings[ssb_mode]); | |
754 | } | |
755 | ||
da285121 | 756 | #undef pr_fmt |
f21b53b2 | 757 | #define pr_fmt(fmt) "Speculation prctl: " fmt |
da285121 | 758 | |
6d991ba5 | 759 | static void task_update_spec_tif(struct task_struct *tsk) |
a73ec77e | 760 | { |
6d991ba5 TG |
761 | /* Force the update of the real TIF bits */ |
762 | set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE); | |
e6da8bb6 TG |
763 | |
764 | /* | |
765 | * Immediately update the speculation control MSRs for the current | |
766 | * task, but for a non-current task delay setting the CPU | |
767 | * mitigation until it is scheduled next. | |
768 | * | |
769 | * This can only happen for SECCOMP mitigation. For PRCTL it's | |
770 | * always the current task. | |
771 | */ | |
6d991ba5 | 772 | if (tsk == current) |
e6da8bb6 TG |
773 | speculation_ctrl_update_current(); |
774 | } | |
775 | ||
776 | static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) | |
777 | { | |
f21b53b2 KC |
778 | if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && |
779 | ssb_mode != SPEC_STORE_BYPASS_SECCOMP) | |
a73ec77e TG |
780 | return -ENXIO; |
781 | ||
356e4bff TG |
782 | switch (ctrl) { |
783 | case PR_SPEC_ENABLE: | |
784 | /* If speculation is force disabled, enable is not allowed */ | |
785 | if (task_spec_ssb_force_disable(task)) | |
786 | return -EPERM; | |
787 | task_clear_spec_ssb_disable(task); | |
6d991ba5 | 788 | task_update_spec_tif(task); |
356e4bff TG |
789 | break; |
790 | case PR_SPEC_DISABLE: | |
791 | task_set_spec_ssb_disable(task); | |
6d991ba5 | 792 | task_update_spec_tif(task); |
356e4bff TG |
793 | break; |
794 | case PR_SPEC_FORCE_DISABLE: | |
795 | task_set_spec_ssb_disable(task); | |
796 | task_set_spec_ssb_force_disable(task); | |
6d991ba5 | 797 | task_update_spec_tif(task); |
356e4bff TG |
798 | break; |
799 | default: | |
800 | return -ERANGE; | |
801 | } | |
a73ec77e TG |
802 | return 0; |
803 | } | |
804 | ||
9137bb27 TG |
805 | static int ib_prctl_set(struct task_struct *task, unsigned long ctrl) |
806 | { | |
807 | switch (ctrl) { | |
808 | case PR_SPEC_ENABLE: | |
809 | if (spectre_v2_user == SPECTRE_V2_USER_NONE) | |
810 | return 0; | |
811 | /* | |
812 | * Indirect branch speculation is always disabled in strict | |
813 | * mode. | |
814 | */ | |
815 | if (spectre_v2_user == SPECTRE_V2_USER_STRICT) | |
816 | return -EPERM; | |
817 | task_clear_spec_ib_disable(task); | |
818 | task_update_spec_tif(task); | |
819 | break; | |
820 | case PR_SPEC_DISABLE: | |
821 | case PR_SPEC_FORCE_DISABLE: | |
822 | /* | |
823 | * Indirect branch speculation is always allowed when | |
824 | * mitigation is force disabled. | |
825 | */ | |
826 | if (spectre_v2_user == SPECTRE_V2_USER_NONE) | |
827 | return -EPERM; | |
828 | if (spectre_v2_user == SPECTRE_V2_USER_STRICT) | |
829 | return 0; | |
830 | task_set_spec_ib_disable(task); | |
831 | if (ctrl == PR_SPEC_FORCE_DISABLE) | |
832 | task_set_spec_ib_force_disable(task); | |
833 | task_update_spec_tif(task); | |
834 | break; | |
835 | default: | |
836 | return -ERANGE; | |
837 | } | |
838 | return 0; | |
839 | } | |
840 | ||
8bf37d8c TG |
841 | int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, |
842 | unsigned long ctrl) | |
843 | { | |
844 | switch (which) { | |
845 | case PR_SPEC_STORE_BYPASS: | |
846 | return ssb_prctl_set(task, ctrl); | |
9137bb27 TG |
847 | case PR_SPEC_INDIRECT_BRANCH: |
848 | return ib_prctl_set(task, ctrl); | |
8bf37d8c TG |
849 | default: |
850 | return -ENODEV; | |
851 | } | |
852 | } | |
853 | ||
854 | #ifdef CONFIG_SECCOMP | |
855 | void arch_seccomp_spec_mitigate(struct task_struct *task) | |
856 | { | |
f21b53b2 KC |
857 | if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) |
858 | ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
6b3e64c2 TG |
859 | if (spectre_v2_user == SPECTRE_V2_USER_SECCOMP) |
860 | ib_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
8bf37d8c TG |
861 | } |
862 | #endif | |
863 | ||
7bbf1373 | 864 | static int ssb_prctl_get(struct task_struct *task) |
a73ec77e TG |
865 | { |
866 | switch (ssb_mode) { | |
867 | case SPEC_STORE_BYPASS_DISABLE: | |
868 | return PR_SPEC_DISABLE; | |
f21b53b2 | 869 | case SPEC_STORE_BYPASS_SECCOMP: |
a73ec77e | 870 | case SPEC_STORE_BYPASS_PRCTL: |
356e4bff TG |
871 | if (task_spec_ssb_force_disable(task)) |
872 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
873 | if (task_spec_ssb_disable(task)) | |
a73ec77e TG |
874 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; |
875 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
876 | default: | |
877 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
878 | return PR_SPEC_ENABLE; | |
879 | return PR_SPEC_NOT_AFFECTED; | |
880 | } | |
881 | } | |
882 | ||
9137bb27 TG |
883 | static int ib_prctl_get(struct task_struct *task) |
884 | { | |
885 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
886 | return PR_SPEC_NOT_AFFECTED; | |
887 | ||
888 | switch (spectre_v2_user) { | |
889 | case SPECTRE_V2_USER_NONE: | |
890 | return PR_SPEC_ENABLE; | |
891 | case SPECTRE_V2_USER_PRCTL: | |
6b3e64c2 | 892 | case SPECTRE_V2_USER_SECCOMP: |
9137bb27 TG |
893 | if (task_spec_ib_force_disable(task)) |
894 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
895 | if (task_spec_ib_disable(task)) | |
896 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; | |
897 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
898 | case SPECTRE_V2_USER_STRICT: | |
899 | return PR_SPEC_DISABLE; | |
900 | default: | |
901 | return PR_SPEC_NOT_AFFECTED; | |
902 | } | |
903 | } | |
904 | ||
7bbf1373 | 905 | int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) |
a73ec77e TG |
906 | { |
907 | switch (which) { | |
908 | case PR_SPEC_STORE_BYPASS: | |
7bbf1373 | 909 | return ssb_prctl_get(task); |
9137bb27 TG |
910 | case PR_SPEC_INDIRECT_BRANCH: |
911 | return ib_prctl_get(task); | |
a73ec77e TG |
912 | default: |
913 | return -ENODEV; | |
914 | } | |
915 | } | |
916 | ||
77243971 KRW |
917 | void x86_spec_ctrl_setup_ap(void) |
918 | { | |
7eb8956a | 919 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
4b59bdb5 | 920 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
764f3c21 KRW |
921 | |
922 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) | |
9f65fb29 | 923 | x86_amd_ssb_disable(); |
77243971 KRW |
924 | } |
925 | ||
56563f53 KRW |
926 | #undef pr_fmt |
927 | #define pr_fmt(fmt) "L1TF: " fmt | |
72c6d2db | 928 | |
d90a7a0e JK |
929 | /* Default mitigation for L1TF-affected CPUs */ |
930 | enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH; | |
72c6d2db | 931 | #if IS_ENABLED(CONFIG_KVM_INTEL) |
d90a7a0e | 932 | EXPORT_SYMBOL_GPL(l1tf_mitigation); |
1eb46908 | 933 | #endif |
895ae47f | 934 | enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; |
72c6d2db | 935 | EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation); |
72c6d2db | 936 | |
cc51e542 AK |
937 | /* |
938 | * These CPUs all support 44bits physical address space internally in the | |
939 | * cache but CPUID can report a smaller number of physical address bits. | |
940 | * | |
941 | * The L1TF mitigation uses the top most address bit for the inversion of | |
942 | * non present PTEs. When the installed memory reaches into the top most | |
943 | * address bit due to memory holes, which has been observed on machines | |
944 | * which report 36bits physical address bits and have 32G RAM installed, | |
945 | * then the mitigation range check in l1tf_select_mitigation() triggers. | |
946 | * This is a false positive because the mitigation is still possible due to | |
947 | * the fact that the cache uses 44bit internally. Use the cache bits | |
948 | * instead of the reported physical bits and adjust them on the affected | |
949 | * machines to 44bit if the reported bits are less than 44. | |
950 | */ | |
951 | static void override_cache_bits(struct cpuinfo_x86 *c) | |
952 | { | |
953 | if (c->x86 != 6) | |
954 | return; | |
955 | ||
956 | switch (c->x86_model) { | |
957 | case INTEL_FAM6_NEHALEM: | |
958 | case INTEL_FAM6_WESTMERE: | |
959 | case INTEL_FAM6_SANDYBRIDGE: | |
960 | case INTEL_FAM6_IVYBRIDGE: | |
961 | case INTEL_FAM6_HASWELL_CORE: | |
962 | case INTEL_FAM6_HASWELL_ULT: | |
963 | case INTEL_FAM6_HASWELL_GT3E: | |
964 | case INTEL_FAM6_BROADWELL_CORE: | |
965 | case INTEL_FAM6_BROADWELL_GT3E: | |
966 | case INTEL_FAM6_SKYLAKE_MOBILE: | |
967 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
968 | case INTEL_FAM6_KABYLAKE_MOBILE: | |
969 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
970 | if (c->x86_cache_bits < 44) | |
971 | c->x86_cache_bits = 44; | |
972 | break; | |
973 | } | |
974 | } | |
975 | ||
56563f53 KRW |
976 | static void __init l1tf_select_mitigation(void) |
977 | { | |
978 | u64 half_pa; | |
979 | ||
980 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
981 | return; | |
982 | ||
cc51e542 AK |
983 | override_cache_bits(&boot_cpu_data); |
984 | ||
d90a7a0e JK |
985 | switch (l1tf_mitigation) { |
986 | case L1TF_MITIGATION_OFF: | |
987 | case L1TF_MITIGATION_FLUSH_NOWARN: | |
988 | case L1TF_MITIGATION_FLUSH: | |
989 | break; | |
990 | case L1TF_MITIGATION_FLUSH_NOSMT: | |
991 | case L1TF_MITIGATION_FULL: | |
992 | cpu_smt_disable(false); | |
993 | break; | |
994 | case L1TF_MITIGATION_FULL_FORCE: | |
995 | cpu_smt_disable(true); | |
996 | break; | |
997 | } | |
998 | ||
56563f53 KRW |
999 | #if CONFIG_PGTABLE_LEVELS == 2 |
1000 | pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n"); | |
1001 | return; | |
1002 | #endif | |
1003 | ||
56563f53 KRW |
1004 | half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT; |
1005 | if (e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) { | |
1006 | pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n"); | |
6a012288 VB |
1007 | pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n", |
1008 | half_pa); | |
1009 | pr_info("However, doing so will make a part of your RAM unusable.\n"); | |
1010 | pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html might help you decide.\n"); | |
56563f53 KRW |
1011 | return; |
1012 | } | |
1013 | ||
1014 | setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV); | |
1015 | } | |
d90a7a0e JK |
1016 | |
1017 | static int __init l1tf_cmdline(char *str) | |
1018 | { | |
1019 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
1020 | return 0; | |
1021 | ||
1022 | if (!str) | |
1023 | return -EINVAL; | |
1024 | ||
1025 | if (!strcmp(str, "off")) | |
1026 | l1tf_mitigation = L1TF_MITIGATION_OFF; | |
1027 | else if (!strcmp(str, "flush,nowarn")) | |
1028 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN; | |
1029 | else if (!strcmp(str, "flush")) | |
1030 | l1tf_mitigation = L1TF_MITIGATION_FLUSH; | |
1031 | else if (!strcmp(str, "flush,nosmt")) | |
1032 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; | |
1033 | else if (!strcmp(str, "full")) | |
1034 | l1tf_mitigation = L1TF_MITIGATION_FULL; | |
1035 | else if (!strcmp(str, "full,force")) | |
1036 | l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE; | |
1037 | ||
1038 | return 0; | |
1039 | } | |
1040 | early_param("l1tf", l1tf_cmdline); | |
1041 | ||
56563f53 KRW |
1042 | #undef pr_fmt |
1043 | ||
61dc0f55 | 1044 | #ifdef CONFIG_SYSFS |
d1059518 | 1045 | |
72c6d2db TG |
1046 | #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion" |
1047 | ||
1048 | #if IS_ENABLED(CONFIG_KVM_INTEL) | |
8770709f | 1049 | static const char * const l1tf_vmx_states[] = { |
a7b9020b TG |
1050 | [VMENTER_L1D_FLUSH_AUTO] = "auto", |
1051 | [VMENTER_L1D_FLUSH_NEVER] = "vulnerable", | |
1052 | [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes", | |
1053 | [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes", | |
1054 | [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled", | |
8e0b2b91 | 1055 | [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary" |
72c6d2db TG |
1056 | }; |
1057 | ||
1058 | static ssize_t l1tf_show_state(char *buf) | |
1059 | { | |
1060 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) | |
1061 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
1062 | ||
ea156d19 PB |
1063 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED || |
1064 | (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER && | |
130d6f94 | 1065 | sched_smt_active())) { |
ea156d19 PB |
1066 | return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG, |
1067 | l1tf_vmx_states[l1tf_vmx_mitigation]); | |
130d6f94 | 1068 | } |
ea156d19 PB |
1069 | |
1070 | return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG, | |
1071 | l1tf_vmx_states[l1tf_vmx_mitigation], | |
130d6f94 | 1072 | sched_smt_active() ? "vulnerable" : "disabled"); |
72c6d2db TG |
1073 | } |
1074 | #else | |
1075 | static ssize_t l1tf_show_state(char *buf) | |
1076 | { | |
1077 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
1078 | } | |
1079 | #endif | |
1080 | ||
a8f76ae4 TC |
1081 | static char *stibp_state(void) |
1082 | { | |
34bce7c9 TC |
1083 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) |
1084 | return ""; | |
1085 | ||
fa1202ef TG |
1086 | switch (spectre_v2_user) { |
1087 | case SPECTRE_V2_USER_NONE: | |
1088 | return ", STIBP: disabled"; | |
1089 | case SPECTRE_V2_USER_STRICT: | |
1090 | return ", STIBP: forced"; | |
9137bb27 | 1091 | case SPECTRE_V2_USER_PRCTL: |
6b3e64c2 | 1092 | case SPECTRE_V2_USER_SECCOMP: |
7cc765a6 TG |
1093 | if (static_key_enabled(&switch_to_cond_stibp)) |
1094 | return ", STIBP: conditional"; | |
fa1202ef TG |
1095 | } |
1096 | return ""; | |
a8f76ae4 TC |
1097 | } |
1098 | ||
1099 | static char *ibpb_state(void) | |
1100 | { | |
4c71a2b6 | 1101 | if (boot_cpu_has(X86_FEATURE_IBPB)) { |
7cc765a6 | 1102 | if (static_key_enabled(&switch_mm_always_ibpb)) |
4c71a2b6 | 1103 | return ", IBPB: always-on"; |
7cc765a6 TG |
1104 | if (static_key_enabled(&switch_mm_cond_ibpb)) |
1105 | return ", IBPB: conditional"; | |
1106 | return ", IBPB: disabled"; | |
4c71a2b6 TG |
1107 | } |
1108 | return ""; | |
a8f76ae4 TC |
1109 | } |
1110 | ||
7bb4d366 | 1111 | static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, |
ffed645e | 1112 | char *buf, unsigned int bug) |
61dc0f55 | 1113 | { |
d1059518 | 1114 | if (!boot_cpu_has_bug(bug)) |
61dc0f55 | 1115 | return sprintf(buf, "Not affected\n"); |
d1059518 KRW |
1116 | |
1117 | switch (bug) { | |
1118 | case X86_BUG_CPU_MELTDOWN: | |
1119 | if (boot_cpu_has(X86_FEATURE_PTI)) | |
1120 | return sprintf(buf, "Mitigation: PTI\n"); | |
1121 | ||
6cb2b08f JK |
1122 | if (hypervisor_is_type(X86_HYPER_XEN_PV)) |
1123 | return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n"); | |
1124 | ||
d1059518 KRW |
1125 | break; |
1126 | ||
1127 | case X86_BUG_SPECTRE_V1: | |
1128 | return sprintf(buf, "Mitigation: __user pointer sanitization\n"); | |
1129 | ||
1130 | case X86_BUG_SPECTRE_V2: | |
b86bda04 | 1131 | return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], |
a8f76ae4 | 1132 | ibpb_state(), |
d1059518 | 1133 | boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", |
a8f76ae4 | 1134 | stibp_state(), |
bb4b3b77 | 1135 | boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "", |
d1059518 KRW |
1136 | spectre_v2_module_string()); |
1137 | ||
24f7fc83 KRW |
1138 | case X86_BUG_SPEC_STORE_BYPASS: |
1139 | return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); | |
1140 | ||
17dbca11 AK |
1141 | case X86_BUG_L1TF: |
1142 | if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV)) | |
72c6d2db | 1143 | return l1tf_show_state(buf); |
17dbca11 | 1144 | break; |
d1059518 KRW |
1145 | default: |
1146 | break; | |
1147 | } | |
1148 | ||
61dc0f55 TG |
1149 | return sprintf(buf, "Vulnerable\n"); |
1150 | } | |
1151 | ||
d1059518 KRW |
1152 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) |
1153 | { | |
1154 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); | |
1155 | } | |
1156 | ||
21e433bd | 1157 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 1158 | { |
d1059518 | 1159 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
61dc0f55 TG |
1160 | } |
1161 | ||
21e433bd | 1162 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 1163 | { |
d1059518 | 1164 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); |
61dc0f55 | 1165 | } |
c456442c KRW |
1166 | |
1167 | ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) | |
1168 | { | |
1169 | return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); | |
1170 | } | |
17dbca11 AK |
1171 | |
1172 | ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf) | |
1173 | { | |
1174 | return cpu_show_common(dev, attr, buf, X86_BUG_L1TF); | |
1175 | } | |
61dc0f55 | 1176 | #endif |