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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1353ebb4 | 2 | /* |
1353ebb4 JF |
3 | * Copyright (C) 1994 Linus Torvalds |
4 | * | |
5 | * Cyrix stuff, June 1998 by: | |
6 | * - Rafael R. Reilova (moved everything from head.S), | |
7 | * <rreilova@ececs.uc.edu> | |
8 | * - Channing Corn (tests & fixes), | |
9 | * - Andrew D. Balsa (code cleanup). | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/utsname.h> | |
61dc0f55 | 13 | #include <linux/cpu.h> |
caf7501a | 14 | #include <linux/module.h> |
a73ec77e TG |
15 | #include <linux/nospec.h> |
16 | #include <linux/prctl.h> | |
da285121 | 17 | |
28a27752 | 18 | #include <asm/spec-ctrl.h> |
da285121 | 19 | #include <asm/cmdline.h> |
91eb1b79 | 20 | #include <asm/bugs.h> |
1353ebb4 | 21 | #include <asm/processor.h> |
7ebad705 | 22 | #include <asm/processor-flags.h> |
952f07ec | 23 | #include <asm/fpu/internal.h> |
1353ebb4 | 24 | #include <asm/msr.h> |
72c6d2db | 25 | #include <asm/vmx.h> |
1353ebb4 JF |
26 | #include <asm/paravirt.h> |
27 | #include <asm/alternative.h> | |
62a67e12 | 28 | #include <asm/pgtable.h> |
d1163651 | 29 | #include <asm/set_memory.h> |
c995efd5 | 30 | #include <asm/intel-family.h> |
17dbca11 | 31 | #include <asm/e820/api.h> |
1353ebb4 | 32 | |
da285121 | 33 | static void __init spectre_v2_select_mitigation(void); |
24f7fc83 | 34 | static void __init ssb_select_mitigation(void); |
17dbca11 | 35 | static void __init l1tf_select_mitigation(void); |
da285121 | 36 | |
1b86883c KRW |
37 | /* |
38 | * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any | |
39 | * writes to SPEC_CTRL contain whatever reserved bits have been set. | |
40 | */ | |
885f82bf | 41 | u64 __ro_after_init x86_spec_ctrl_base; |
fa8ac498 | 42 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); |
1b86883c | 43 | |
1115a859 KRW |
44 | /* |
45 | * The vendor and possibly platform specific bits which can be modified in | |
46 | * x86_spec_ctrl_base. | |
47 | */ | |
be6fcb54 | 48 | static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS; |
1115a859 | 49 | |
764f3c21 KRW |
50 | /* |
51 | * AMD specific MSR info for Speculative Store Bypass control. | |
9f65fb29 | 52 | * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). |
764f3c21 KRW |
53 | */ |
54 | u64 __ro_after_init x86_amd_ls_cfg_base; | |
9f65fb29 | 55 | u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; |
764f3c21 | 56 | |
1353ebb4 JF |
57 | void __init check_bugs(void) |
58 | { | |
59 | identify_boot_cpu(); | |
55a36b65 | 60 | |
62a67e12 BP |
61 | if (!IS_ENABLED(CONFIG_SMP)) { |
62 | pr_info("CPU: "); | |
63 | print_cpu_info(&boot_cpu_data); | |
64 | } | |
65 | ||
1b86883c KRW |
66 | /* |
67 | * Read the SPEC_CTRL MSR to account for reserved bits which may | |
764f3c21 KRW |
68 | * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD |
69 | * init code as it is not enumerated and depends on the family. | |
1b86883c | 70 | */ |
7eb8956a | 71 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
1b86883c KRW |
72 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
73 | ||
be6fcb54 TG |
74 | /* Allow STIBP in MSR_SPEC_CTRL if supported */ |
75 | if (boot_cpu_has(X86_FEATURE_STIBP)) | |
76 | x86_spec_ctrl_mask |= SPEC_CTRL_STIBP; | |
77 | ||
da285121 DW |
78 | /* Select the proper spectre mitigation before patching alternatives */ |
79 | spectre_v2_select_mitigation(); | |
80 | ||
24f7fc83 KRW |
81 | /* |
82 | * Select proper mitigation for any exposure to the Speculative Store | |
83 | * Bypass vulnerability. | |
84 | */ | |
85 | ssb_select_mitigation(); | |
86 | ||
17dbca11 AK |
87 | l1tf_select_mitigation(); |
88 | ||
62a67e12 | 89 | #ifdef CONFIG_X86_32 |
55a36b65 BP |
90 | /* |
91 | * Check whether we are able to run this kernel safely on SMP. | |
92 | * | |
93 | * - i386 is no longer supported. | |
94 | * - In order to run on anything without a TSC, we need to be | |
95 | * compiled for a i486. | |
96 | */ | |
97 | if (boot_cpu_data.x86 < 4) | |
98 | panic("Kernel requires i486+ for 'invlpg' and other features"); | |
99 | ||
bfe4bb15 MV |
100 | init_utsname()->machine[1] = |
101 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); | |
1353ebb4 | 102 | alternative_instructions(); |
304bceda | 103 | |
4d164092 | 104 | fpu__init_check_bugs(); |
62a67e12 BP |
105 | #else /* CONFIG_X86_64 */ |
106 | alternative_instructions(); | |
107 | ||
108 | /* | |
109 | * Make sure the first 2MB area is not mapped by huge pages | |
110 | * There are typically fixed size MTRRs in there and overlapping | |
111 | * MTRRs into large pages causes slow downs. | |
112 | * | |
113 | * Right now we don't do that with gbpages because there seems | |
114 | * very little benefit for that case. | |
115 | */ | |
116 | if (!direct_gbpages) | |
117 | set_memory_4k((unsigned long)__va(0), 1); | |
118 | #endif | |
1353ebb4 | 119 | } |
61dc0f55 | 120 | |
da285121 DW |
121 | /* The kernel command line selection */ |
122 | enum spectre_v2_mitigation_cmd { | |
123 | SPECTRE_V2_CMD_NONE, | |
124 | SPECTRE_V2_CMD_AUTO, | |
125 | SPECTRE_V2_CMD_FORCE, | |
126 | SPECTRE_V2_CMD_RETPOLINE, | |
127 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, | |
128 | SPECTRE_V2_CMD_RETPOLINE_AMD, | |
129 | }; | |
130 | ||
131 | static const char *spectre_v2_strings[] = { | |
132 | [SPECTRE_V2_NONE] = "Vulnerable", | |
133 | [SPECTRE_V2_RETPOLINE_MINIMAL] = "Vulnerable: Minimal generic ASM retpoline", | |
134 | [SPECTRE_V2_RETPOLINE_MINIMAL_AMD] = "Vulnerable: Minimal AMD ASM retpoline", | |
135 | [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", | |
136 | [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", | |
137 | }; | |
138 | ||
139 | #undef pr_fmt | |
55fa19d3 | 140 | #define pr_fmt(fmt) "Spectre V2 : " fmt |
da285121 | 141 | |
f9544b2b KC |
142 | static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = |
143 | SPECTRE_V2_NONE; | |
caf7501a | 144 | |
cc69b349 BP |
145 | void |
146 | x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) | |
5cf68754 | 147 | { |
be6fcb54 | 148 | u64 msrval, guestval, hostval = x86_spec_ctrl_base; |
cc69b349 | 149 | struct thread_info *ti = current_thread_info(); |
885f82bf | 150 | |
7eb8956a | 151 | /* Is MSR_SPEC_CTRL implemented ? */ |
cc69b349 | 152 | if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { |
be6fcb54 TG |
153 | /* |
154 | * Restrict guest_spec_ctrl to supported values. Clear the | |
155 | * modifiable bits in the host base value and or the | |
156 | * modifiable bits from the guest value. | |
157 | */ | |
158 | guestval = hostval & ~x86_spec_ctrl_mask; | |
159 | guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; | |
160 | ||
cc69b349 BP |
161 | /* SSBD controlled in MSR_SPEC_CTRL */ |
162 | if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) | |
be6fcb54 | 163 | hostval |= ssbd_tif_to_spec_ctrl(ti->flags); |
cc69b349 | 164 | |
be6fcb54 TG |
165 | if (hostval != guestval) { |
166 | msrval = setguest ? guestval : hostval; | |
167 | wrmsrl(MSR_IA32_SPEC_CTRL, msrval); | |
cc69b349 BP |
168 | } |
169 | } | |
47c61b39 TG |
170 | |
171 | /* | |
172 | * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update | |
173 | * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. | |
174 | */ | |
175 | if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && | |
176 | !static_cpu_has(X86_FEATURE_VIRT_SSBD)) | |
177 | return; | |
178 | ||
179 | /* | |
180 | * If the host has SSBD mitigation enabled, force it in the host's | |
181 | * virtual MSR value. If its not permanently enabled, evaluate | |
182 | * current's TIF_SSBD thread flag. | |
183 | */ | |
184 | if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) | |
185 | hostval = SPEC_CTRL_SSBD; | |
186 | else | |
187 | hostval = ssbd_tif_to_spec_ctrl(ti->flags); | |
188 | ||
189 | /* Sanitize the guest value */ | |
190 | guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; | |
191 | ||
192 | if (hostval != guestval) { | |
193 | unsigned long tif; | |
194 | ||
195 | tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : | |
196 | ssbd_spec_ctrl_to_tif(hostval); | |
197 | ||
198 | speculative_store_bypass_update(tif); | |
199 | } | |
5cf68754 | 200 | } |
cc69b349 | 201 | EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); |
5cf68754 | 202 | |
9f65fb29 | 203 | static void x86_amd_ssb_disable(void) |
764f3c21 | 204 | { |
9f65fb29 | 205 | u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; |
764f3c21 | 206 | |
11fb0683 TL |
207 | if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) |
208 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); | |
209 | else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) | |
764f3c21 KRW |
210 | wrmsrl(MSR_AMD64_LS_CFG, msrval); |
211 | } | |
212 | ||
caf7501a | 213 | #ifdef RETPOLINE |
e383095c TG |
214 | static bool spectre_v2_bad_module; |
215 | ||
caf7501a AK |
216 | bool retpoline_module_ok(bool has_retpoline) |
217 | { | |
218 | if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) | |
219 | return true; | |
220 | ||
e698dcdf | 221 | pr_err("System may be vulnerable to spectre v2\n"); |
caf7501a AK |
222 | spectre_v2_bad_module = true; |
223 | return false; | |
224 | } | |
e383095c TG |
225 | |
226 | static inline const char *spectre_v2_module_string(void) | |
227 | { | |
228 | return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; | |
229 | } | |
230 | #else | |
231 | static inline const char *spectre_v2_module_string(void) { return ""; } | |
caf7501a | 232 | #endif |
da285121 DW |
233 | |
234 | static void __init spec2_print_if_insecure(const char *reason) | |
235 | { | |
236 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
9005c683 | 237 | pr_info("%s selected on command line.\n", reason); |
da285121 DW |
238 | } |
239 | ||
240 | static void __init spec2_print_if_secure(const char *reason) | |
241 | { | |
242 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
9005c683 | 243 | pr_info("%s selected on command line.\n", reason); |
da285121 DW |
244 | } |
245 | ||
246 | static inline bool retp_compiler(void) | |
247 | { | |
248 | return __is_defined(RETPOLINE); | |
249 | } | |
250 | ||
251 | static inline bool match_option(const char *arg, int arglen, const char *opt) | |
252 | { | |
253 | int len = strlen(opt); | |
254 | ||
255 | return len == arglen && !strncmp(arg, opt, len); | |
256 | } | |
257 | ||
9005c683 KA |
258 | static const struct { |
259 | const char *option; | |
260 | enum spectre_v2_mitigation_cmd cmd; | |
261 | bool secure; | |
262 | } mitigation_options[] = { | |
263 | { "off", SPECTRE_V2_CMD_NONE, false }, | |
264 | { "on", SPECTRE_V2_CMD_FORCE, true }, | |
265 | { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, | |
266 | { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, | |
267 | { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, | |
268 | { "auto", SPECTRE_V2_CMD_AUTO, false }, | |
269 | }; | |
270 | ||
da285121 DW |
271 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) |
272 | { | |
273 | char arg[20]; | |
9005c683 KA |
274 | int ret, i; |
275 | enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; | |
276 | ||
277 | if (cmdline_find_option_bool(boot_command_line, "nospectre_v2")) | |
278 | return SPECTRE_V2_CMD_NONE; | |
279 | else { | |
21e433bd | 280 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); |
9005c683 KA |
281 | if (ret < 0) |
282 | return SPECTRE_V2_CMD_AUTO; | |
283 | ||
284 | for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { | |
285 | if (!match_option(arg, ret, mitigation_options[i].option)) | |
286 | continue; | |
287 | cmd = mitigation_options[i].cmd; | |
288 | break; | |
289 | } | |
290 | ||
291 | if (i >= ARRAY_SIZE(mitigation_options)) { | |
9de29eac | 292 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); |
da285121 DW |
293 | return SPECTRE_V2_CMD_AUTO; |
294 | } | |
295 | } | |
296 | ||
9005c683 KA |
297 | if ((cmd == SPECTRE_V2_CMD_RETPOLINE || |
298 | cmd == SPECTRE_V2_CMD_RETPOLINE_AMD || | |
299 | cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) && | |
300 | !IS_ENABLED(CONFIG_RETPOLINE)) { | |
21e433bd | 301 | pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option); |
da285121 | 302 | return SPECTRE_V2_CMD_AUTO; |
9005c683 KA |
303 | } |
304 | ||
305 | if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD && | |
306 | boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { | |
307 | pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); | |
308 | return SPECTRE_V2_CMD_AUTO; | |
309 | } | |
310 | ||
311 | if (mitigation_options[i].secure) | |
312 | spec2_print_if_secure(mitigation_options[i].option); | |
313 | else | |
314 | spec2_print_if_insecure(mitigation_options[i].option); | |
315 | ||
316 | return cmd; | |
da285121 DW |
317 | } |
318 | ||
c995efd5 DW |
319 | /* Check for Skylake-like CPUs (for RSB handling) */ |
320 | static bool __init is_skylake_era(void) | |
321 | { | |
322 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
323 | boot_cpu_data.x86 == 6) { | |
324 | switch (boot_cpu_data.x86_model) { | |
325 | case INTEL_FAM6_SKYLAKE_MOBILE: | |
326 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
327 | case INTEL_FAM6_SKYLAKE_X: | |
328 | case INTEL_FAM6_KABYLAKE_MOBILE: | |
329 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
330 | return true; | |
331 | } | |
332 | } | |
333 | return false; | |
334 | } | |
335 | ||
da285121 DW |
336 | static void __init spectre_v2_select_mitigation(void) |
337 | { | |
338 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | |
339 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; | |
340 | ||
341 | /* | |
342 | * If the CPU is not affected and the command line mode is NONE or AUTO | |
343 | * then nothing to do. | |
344 | */ | |
345 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && | |
346 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) | |
347 | return; | |
348 | ||
349 | switch (cmd) { | |
350 | case SPECTRE_V2_CMD_NONE: | |
351 | return; | |
352 | ||
353 | case SPECTRE_V2_CMD_FORCE: | |
da285121 | 354 | case SPECTRE_V2_CMD_AUTO: |
9471eee9 DL |
355 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
356 | goto retpoline_auto; | |
357 | break; | |
da285121 DW |
358 | case SPECTRE_V2_CMD_RETPOLINE_AMD: |
359 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
360 | goto retpoline_amd; | |
361 | break; | |
362 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: | |
363 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
364 | goto retpoline_generic; | |
365 | break; | |
366 | case SPECTRE_V2_CMD_RETPOLINE: | |
367 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
368 | goto retpoline_auto; | |
369 | break; | |
370 | } | |
21e433bd | 371 | pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!"); |
da285121 DW |
372 | return; |
373 | ||
374 | retpoline_auto: | |
375 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { | |
376 | retpoline_amd: | |
377 | if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { | |
21e433bd | 378 | pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n"); |
da285121 DW |
379 | goto retpoline_generic; |
380 | } | |
381 | mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD : | |
382 | SPECTRE_V2_RETPOLINE_MINIMAL_AMD; | |
383 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); | |
384 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
385 | } else { | |
386 | retpoline_generic: | |
387 | mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC : | |
388 | SPECTRE_V2_RETPOLINE_MINIMAL; | |
389 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
390 | } | |
391 | ||
392 | spectre_v2_enabled = mode; | |
393 | pr_info("%s\n", spectre_v2_strings[mode]); | |
c995efd5 DW |
394 | |
395 | /* | |
21e433bd | 396 | * If neither SMEP nor PTI are available, there is a risk of |
c995efd5 DW |
397 | * hitting userspace addresses in the RSB after a context switch |
398 | * from a shallow call stack to a deeper one. To prevent this fill | |
399 | * the entire RSB, even when using IBRS. | |
400 | * | |
401 | * Skylake era CPUs have a separate issue with *underflow* of the | |
402 | * RSB, when they will predict 'ret' targets from the generic BTB. | |
403 | * The proper mitigation for this is IBRS. If IBRS is not supported | |
404 | * or deactivated in favour of retpolines the RSB fill on context | |
405 | * switch is required. | |
406 | */ | |
407 | if ((!boot_cpu_has(X86_FEATURE_PTI) && | |
408 | !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) { | |
409 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); | |
21e433bd | 410 | pr_info("Spectre v2 mitigation: Filling RSB on context switch\n"); |
c995efd5 | 411 | } |
20ffa1ca DW |
412 | |
413 | /* Initialize Indirect Branch Prediction Barrier if supported */ | |
2961298e DW |
414 | if (boot_cpu_has(X86_FEATURE_IBPB)) { |
415 | setup_force_cpu_cap(X86_FEATURE_USE_IBPB); | |
21e433bd | 416 | pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n"); |
20ffa1ca | 417 | } |
dd84441a DW |
418 | |
419 | /* | |
420 | * Retpoline means the kernel is safe because it has no indirect | |
421 | * branches. But firmware isn't, so use IBRS to protect that. | |
422 | */ | |
423 | if (boot_cpu_has(X86_FEATURE_IBRS)) { | |
424 | setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); | |
425 | pr_info("Enabling Restricted Speculation for firmware calls\n"); | |
426 | } | |
da285121 DW |
427 | } |
428 | ||
24f7fc83 KRW |
429 | #undef pr_fmt |
430 | #define pr_fmt(fmt) "Speculative Store Bypass: " fmt | |
431 | ||
f9544b2b | 432 | static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; |
24f7fc83 KRW |
433 | |
434 | /* The kernel command line selection */ | |
435 | enum ssb_mitigation_cmd { | |
436 | SPEC_STORE_BYPASS_CMD_NONE, | |
437 | SPEC_STORE_BYPASS_CMD_AUTO, | |
438 | SPEC_STORE_BYPASS_CMD_ON, | |
a73ec77e | 439 | SPEC_STORE_BYPASS_CMD_PRCTL, |
f21b53b2 | 440 | SPEC_STORE_BYPASS_CMD_SECCOMP, |
24f7fc83 KRW |
441 | }; |
442 | ||
443 | static const char *ssb_strings[] = { | |
444 | [SPEC_STORE_BYPASS_NONE] = "Vulnerable", | |
a73ec77e | 445 | [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", |
f21b53b2 KC |
446 | [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", |
447 | [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", | |
24f7fc83 KRW |
448 | }; |
449 | ||
450 | static const struct { | |
451 | const char *option; | |
452 | enum ssb_mitigation_cmd cmd; | |
453 | } ssb_mitigation_options[] = { | |
f21b53b2 KC |
454 | { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ |
455 | { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ | |
456 | { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ | |
457 | { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ | |
458 | { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ | |
24f7fc83 KRW |
459 | }; |
460 | ||
461 | static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) | |
462 | { | |
463 | enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; | |
464 | char arg[20]; | |
465 | int ret, i; | |
466 | ||
467 | if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) { | |
468 | return SPEC_STORE_BYPASS_CMD_NONE; | |
469 | } else { | |
470 | ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", | |
471 | arg, sizeof(arg)); | |
472 | if (ret < 0) | |
473 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
474 | ||
475 | for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { | |
476 | if (!match_option(arg, ret, ssb_mitigation_options[i].option)) | |
477 | continue; | |
478 | ||
479 | cmd = ssb_mitigation_options[i].cmd; | |
480 | break; | |
481 | } | |
482 | ||
483 | if (i >= ARRAY_SIZE(ssb_mitigation_options)) { | |
484 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
485 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
486 | } | |
487 | } | |
488 | ||
489 | return cmd; | |
490 | } | |
491 | ||
d66d8ff3 | 492 | static enum ssb_mitigation __init __ssb_select_mitigation(void) |
24f7fc83 KRW |
493 | { |
494 | enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; | |
495 | enum ssb_mitigation_cmd cmd; | |
496 | ||
9f65fb29 | 497 | if (!boot_cpu_has(X86_FEATURE_SSBD)) |
24f7fc83 KRW |
498 | return mode; |
499 | ||
500 | cmd = ssb_parse_cmdline(); | |
501 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && | |
502 | (cmd == SPEC_STORE_BYPASS_CMD_NONE || | |
503 | cmd == SPEC_STORE_BYPASS_CMD_AUTO)) | |
504 | return mode; | |
505 | ||
506 | switch (cmd) { | |
507 | case SPEC_STORE_BYPASS_CMD_AUTO: | |
f21b53b2 KC |
508 | case SPEC_STORE_BYPASS_CMD_SECCOMP: |
509 | /* | |
510 | * Choose prctl+seccomp as the default mode if seccomp is | |
511 | * enabled. | |
512 | */ | |
513 | if (IS_ENABLED(CONFIG_SECCOMP)) | |
514 | mode = SPEC_STORE_BYPASS_SECCOMP; | |
515 | else | |
516 | mode = SPEC_STORE_BYPASS_PRCTL; | |
a73ec77e | 517 | break; |
24f7fc83 KRW |
518 | case SPEC_STORE_BYPASS_CMD_ON: |
519 | mode = SPEC_STORE_BYPASS_DISABLE; | |
520 | break; | |
a73ec77e TG |
521 | case SPEC_STORE_BYPASS_CMD_PRCTL: |
522 | mode = SPEC_STORE_BYPASS_PRCTL; | |
523 | break; | |
24f7fc83 KRW |
524 | case SPEC_STORE_BYPASS_CMD_NONE: |
525 | break; | |
526 | } | |
527 | ||
77243971 KRW |
528 | /* |
529 | * We have three CPU feature flags that are in play here: | |
530 | * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. | |
9f65fb29 | 531 | * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass |
77243971 KRW |
532 | * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation |
533 | */ | |
a73ec77e | 534 | if (mode == SPEC_STORE_BYPASS_DISABLE) { |
24f7fc83 | 535 | setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); |
77243971 | 536 | /* |
6ac2f49e KRW |
537 | * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may |
538 | * use a completely different MSR and bit dependent on family. | |
77243971 | 539 | */ |
108fab4b KRW |
540 | if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
541 | x86_amd_ssb_disable(); | |
542 | else { | |
9f65fb29 | 543 | x86_spec_ctrl_base |= SPEC_CTRL_SSBD; |
be6fcb54 | 544 | x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; |
4b59bdb5 | 545 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
77243971 KRW |
546 | } |
547 | } | |
548 | ||
24f7fc83 KRW |
549 | return mode; |
550 | } | |
551 | ||
ffed645e | 552 | static void ssb_select_mitigation(void) |
24f7fc83 KRW |
553 | { |
554 | ssb_mode = __ssb_select_mitigation(); | |
555 | ||
556 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
557 | pr_info("%s\n", ssb_strings[ssb_mode]); | |
558 | } | |
559 | ||
da285121 | 560 | #undef pr_fmt |
f21b53b2 | 561 | #define pr_fmt(fmt) "Speculation prctl: " fmt |
da285121 | 562 | |
7bbf1373 | 563 | static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) |
a73ec77e | 564 | { |
356e4bff | 565 | bool update; |
a73ec77e | 566 | |
f21b53b2 KC |
567 | if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && |
568 | ssb_mode != SPEC_STORE_BYPASS_SECCOMP) | |
a73ec77e TG |
569 | return -ENXIO; |
570 | ||
356e4bff TG |
571 | switch (ctrl) { |
572 | case PR_SPEC_ENABLE: | |
573 | /* If speculation is force disabled, enable is not allowed */ | |
574 | if (task_spec_ssb_force_disable(task)) | |
575 | return -EPERM; | |
576 | task_clear_spec_ssb_disable(task); | |
9f65fb29 | 577 | update = test_and_clear_tsk_thread_flag(task, TIF_SSBD); |
356e4bff TG |
578 | break; |
579 | case PR_SPEC_DISABLE: | |
580 | task_set_spec_ssb_disable(task); | |
9f65fb29 | 581 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
356e4bff TG |
582 | break; |
583 | case PR_SPEC_FORCE_DISABLE: | |
584 | task_set_spec_ssb_disable(task); | |
585 | task_set_spec_ssb_force_disable(task); | |
9f65fb29 | 586 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
356e4bff TG |
587 | break; |
588 | default: | |
589 | return -ERANGE; | |
590 | } | |
a73ec77e | 591 | |
7bbf1373 KC |
592 | /* |
593 | * If being set on non-current task, delay setting the CPU | |
594 | * mitigation until it is next scheduled. | |
595 | */ | |
356e4bff | 596 | if (task == current && update) |
0270be3e | 597 | speculative_store_bypass_update_current(); |
a73ec77e TG |
598 | |
599 | return 0; | |
600 | } | |
601 | ||
8bf37d8c TG |
602 | int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, |
603 | unsigned long ctrl) | |
604 | { | |
605 | switch (which) { | |
606 | case PR_SPEC_STORE_BYPASS: | |
607 | return ssb_prctl_set(task, ctrl); | |
608 | default: | |
609 | return -ENODEV; | |
610 | } | |
611 | } | |
612 | ||
613 | #ifdef CONFIG_SECCOMP | |
614 | void arch_seccomp_spec_mitigate(struct task_struct *task) | |
615 | { | |
f21b53b2 KC |
616 | if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) |
617 | ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
8bf37d8c TG |
618 | } |
619 | #endif | |
620 | ||
7bbf1373 | 621 | static int ssb_prctl_get(struct task_struct *task) |
a73ec77e TG |
622 | { |
623 | switch (ssb_mode) { | |
624 | case SPEC_STORE_BYPASS_DISABLE: | |
625 | return PR_SPEC_DISABLE; | |
f21b53b2 | 626 | case SPEC_STORE_BYPASS_SECCOMP: |
a73ec77e | 627 | case SPEC_STORE_BYPASS_PRCTL: |
356e4bff TG |
628 | if (task_spec_ssb_force_disable(task)) |
629 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
630 | if (task_spec_ssb_disable(task)) | |
a73ec77e TG |
631 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; |
632 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
633 | default: | |
634 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
635 | return PR_SPEC_ENABLE; | |
636 | return PR_SPEC_NOT_AFFECTED; | |
637 | } | |
638 | } | |
639 | ||
7bbf1373 | 640 | int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) |
a73ec77e TG |
641 | { |
642 | switch (which) { | |
643 | case PR_SPEC_STORE_BYPASS: | |
7bbf1373 | 644 | return ssb_prctl_get(task); |
a73ec77e TG |
645 | default: |
646 | return -ENODEV; | |
647 | } | |
648 | } | |
649 | ||
77243971 KRW |
650 | void x86_spec_ctrl_setup_ap(void) |
651 | { | |
7eb8956a | 652 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
4b59bdb5 | 653 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
764f3c21 KRW |
654 | |
655 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) | |
9f65fb29 | 656 | x86_amd_ssb_disable(); |
77243971 KRW |
657 | } |
658 | ||
56563f53 KRW |
659 | #undef pr_fmt |
660 | #define pr_fmt(fmt) "L1TF: " fmt | |
72c6d2db TG |
661 | |
662 | #if IS_ENABLED(CONFIG_KVM_INTEL) | |
663 | enum vmx_l1d_flush_state l1tf_vmx_mitigation __ro_after_init = VMENTER_L1D_FLUSH_AUTO; | |
664 | EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation); | |
665 | #endif | |
666 | ||
56563f53 KRW |
667 | static void __init l1tf_select_mitigation(void) |
668 | { | |
669 | u64 half_pa; | |
670 | ||
671 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
672 | return; | |
673 | ||
674 | #if CONFIG_PGTABLE_LEVELS == 2 | |
675 | pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n"); | |
676 | return; | |
677 | #endif | |
678 | ||
679 | /* | |
680 | * This is extremely unlikely to happen because almost all | |
681 | * systems have far more MAX_PA/2 than RAM can be fit into | |
682 | * DIMM slots. | |
683 | */ | |
684 | half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT; | |
685 | if (e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) { | |
686 | pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n"); | |
687 | return; | |
688 | } | |
689 | ||
690 | setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV); | |
691 | } | |
692 | #undef pr_fmt | |
693 | ||
61dc0f55 | 694 | #ifdef CONFIG_SYSFS |
d1059518 | 695 | |
72c6d2db TG |
696 | #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion" |
697 | ||
698 | #if IS_ENABLED(CONFIG_KVM_INTEL) | |
699 | static const char *l1tf_vmx_states[] = { | |
a7b9020b TG |
700 | [VMENTER_L1D_FLUSH_AUTO] = "auto", |
701 | [VMENTER_L1D_FLUSH_NEVER] = "vulnerable", | |
702 | [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes", | |
703 | [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes", | |
704 | [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled", | |
72c6d2db TG |
705 | }; |
706 | ||
707 | static ssize_t l1tf_show_state(char *buf) | |
708 | { | |
709 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) | |
710 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
711 | ||
712 | return sprintf(buf, "%s; VMX: SMT %s, L1D %s\n", L1TF_DEFAULT_MSG, | |
713 | cpu_smt_control == CPU_SMT_ENABLED ? "vulnerable" : "disabled", | |
714 | l1tf_vmx_states[l1tf_vmx_mitigation]); | |
715 | } | |
716 | #else | |
717 | static ssize_t l1tf_show_state(char *buf) | |
718 | { | |
719 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
720 | } | |
721 | #endif | |
722 | ||
7bb4d366 | 723 | static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, |
ffed645e | 724 | char *buf, unsigned int bug) |
61dc0f55 | 725 | { |
d1059518 | 726 | if (!boot_cpu_has_bug(bug)) |
61dc0f55 | 727 | return sprintf(buf, "Not affected\n"); |
d1059518 KRW |
728 | |
729 | switch (bug) { | |
730 | case X86_BUG_CPU_MELTDOWN: | |
731 | if (boot_cpu_has(X86_FEATURE_PTI)) | |
732 | return sprintf(buf, "Mitigation: PTI\n"); | |
733 | ||
734 | break; | |
735 | ||
736 | case X86_BUG_SPECTRE_V1: | |
737 | return sprintf(buf, "Mitigation: __user pointer sanitization\n"); | |
738 | ||
739 | case X86_BUG_SPECTRE_V2: | |
740 | return sprintf(buf, "%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], | |
741 | boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "", | |
742 | boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", | |
743 | spectre_v2_module_string()); | |
744 | ||
24f7fc83 KRW |
745 | case X86_BUG_SPEC_STORE_BYPASS: |
746 | return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); | |
747 | ||
17dbca11 AK |
748 | case X86_BUG_L1TF: |
749 | if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV)) | |
72c6d2db | 750 | return l1tf_show_state(buf); |
17dbca11 | 751 | break; |
d1059518 KRW |
752 | default: |
753 | break; | |
754 | } | |
755 | ||
61dc0f55 TG |
756 | return sprintf(buf, "Vulnerable\n"); |
757 | } | |
758 | ||
d1059518 KRW |
759 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) |
760 | { | |
761 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); | |
762 | } | |
763 | ||
21e433bd | 764 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 765 | { |
d1059518 | 766 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
61dc0f55 TG |
767 | } |
768 | ||
21e433bd | 769 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 770 | { |
d1059518 | 771 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); |
61dc0f55 | 772 | } |
c456442c KRW |
773 | |
774 | ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) | |
775 | { | |
776 | return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); | |
777 | } | |
17dbca11 AK |
778 | |
779 | ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf) | |
780 | { | |
781 | return cpu_show_common(dev, attr, buf, X86_BUG_L1TF); | |
782 | } | |
61dc0f55 | 783 | #endif |