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Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
acb04058 PZ |
2 | |
3 | #include <linux/sched.h> | |
e6017571 | 4 | #include <linux/sched/clock.h> |
edc05e6d | 5 | |
5d510359 | 6 | #include <asm/cpu.h> |
cd4d09ec | 7 | #include <asm/cpufeature.h> |
66441bd3 | 8 | #include <asm/e820/api.h> |
52f4a91a | 9 | #include <asm/mtrr.h> |
48f4c485 | 10 | #include <asm/msr.h> |
edc05e6d | 11 | |
1da177e4 LT |
12 | #include "cpu.h" |
13 | ||
1da177e4 LT |
14 | #define ACE_PRESENT (1 << 6) |
15 | #define ACE_ENABLED (1 << 7) | |
16 | #define ACE_FCR (1 << 28) /* MSR_VIA_FCR */ | |
17 | ||
18 | #define RNG_PRESENT (1 << 2) | |
19 | #define RNG_ENABLED (1 << 3) | |
20 | #define RNG_ENABLE (1 << 6) /* MSR_VIA_RNG */ | |
21 | ||
148f9bb8 | 22 | static void init_c3(struct cpuinfo_x86 *c) |
1da177e4 LT |
23 | { |
24 | u32 lo, hi; | |
25 | ||
26 | /* Test for Centaur Extended Feature Flags presence */ | |
27 | if (cpuid_eax(0xC0000000) >= 0xC0000001) { | |
28 | u32 tmp = cpuid_edx(0xC0000001); | |
29 | ||
30 | /* enable ACE unit, if present and disabled */ | |
31 | if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) { | |
29a9994b | 32 | rdmsr(MSR_VIA_FCR, lo, hi); |
1da177e4 | 33 | lo |= ACE_FCR; /* enable ACE unit */ |
29a9994b | 34 | wrmsr(MSR_VIA_FCR, lo, hi); |
1b74dde7 | 35 | pr_info("CPU: Enabled ACE h/w crypto\n"); |
1da177e4 LT |
36 | } |
37 | ||
38 | /* enable RNG unit, if present and disabled */ | |
39 | if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) { | |
29a9994b | 40 | rdmsr(MSR_VIA_RNG, lo, hi); |
1da177e4 | 41 | lo |= RNG_ENABLE; /* enable RNG unit */ |
29a9994b | 42 | wrmsr(MSR_VIA_RNG, lo, hi); |
1b74dde7 | 43 | pr_info("CPU: Enabled h/w RNG\n"); |
1da177e4 LT |
44 | } |
45 | ||
46 | /* store Centaur Extended Feature Flags as | |
47 | * word 5 of the CPU capability bit array | |
48 | */ | |
39c06df4 | 49 | c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001); |
1da177e4 | 50 | } |
48f4c485 | 51 | #ifdef CONFIG_X86_32 |
27b46d76 | 52 | /* Cyrix III family needs CX8 & PGE explicitly enabled. */ |
cb3f718d | 53 | if (c->x86_model >= 6 && c->x86_model <= 13) { |
29a9994b | 54 | rdmsr(MSR_VIA_FCR, lo, hi); |
1da177e4 | 55 | lo |= (1<<1 | 1<<7); |
29a9994b | 56 | wrmsr(MSR_VIA_FCR, lo, hi); |
e1a94a97 | 57 | set_cpu_cap(c, X86_FEATURE_CX8); |
1da177e4 LT |
58 | } |
59 | ||
60 | /* Before Nehemiah, the C3's had 3dNOW! */ | |
29a9994b | 61 | if (c->x86_model >= 6 && c->x86_model < 9) |
e1a94a97 | 62 | set_cpu_cap(c, X86_FEATURE_3DNOW); |
48f4c485 SAS |
63 | #endif |
64 | if (c->x86 == 0x6 && c->x86_model >= 0xf) { | |
65 | c->x86_cache_alignment = c->x86_clflush_size * 2; | |
66 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); | |
67 | } | |
33b4711d TW |
68 | |
69 | if (c->x86 >= 7) | |
70 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); | |
1da177e4 LT |
71 | } |
72 | ||
edc05e6d IM |
73 | enum { |
74 | ECX8 = 1<<1, | |
75 | EIERRINT = 1<<2, | |
76 | DPM = 1<<3, | |
77 | DMCE = 1<<4, | |
78 | DSTPCLK = 1<<5, | |
79 | ELINEAR = 1<<6, | |
80 | DSMC = 1<<7, | |
81 | DTLOCK = 1<<8, | |
82 | EDCTLB = 1<<8, | |
83 | EMMX = 1<<9, | |
84 | DPDC = 1<<11, | |
85 | EBRPRED = 1<<12, | |
86 | DIC = 1<<13, | |
87 | DDC = 1<<14, | |
88 | DNA = 1<<15, | |
89 | ERETSTK = 1<<16, | |
90 | E2MMX = 1<<19, | |
91 | EAMD3D = 1<<20, | |
92 | }; | |
93 | ||
148f9bb8 | 94 | static void early_init_centaur(struct cpuinfo_x86 *c) |
5fef55fd | 95 | { |
48f4c485 | 96 | #ifdef CONFIG_X86_32 |
8687bdc0 TW |
97 | /* Emulate MTRRs using Centaur's MCR. */ |
98 | if (c->x86 == 5) | |
5fef55fd | 99 | set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR); |
48f4c485 | 100 | #endif |
33b4711d TW |
101 | if ((c->x86 == 6 && c->x86_model >= 0xf) || |
102 | (c->x86 >= 7)) | |
8687bdc0 TW |
103 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); |
104 | ||
48f4c485 SAS |
105 | #ifdef CONFIG_X86_64 |
106 | set_cpu_cap(c, X86_FEATURE_SYSENTER32); | |
107 | #endif | |
fe6daab1 | 108 | if (c->x86_power & (1 << 8)) { |
109 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); | |
110 | set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); | |
111 | } | |
5fef55fd YL |
112 | } |
113 | ||
148f9bb8 | 114 | static void init_centaur(struct cpuinfo_x86 *c) |
1da177e4 | 115 | { |
48f4c485 | 116 | #ifdef CONFIG_X86_32 |
1da177e4 | 117 | char *name; |
29a9994b PC |
118 | u32 fcr_set = 0; |
119 | u32 fcr_clr = 0; | |
120 | u32 lo, hi, newlo; | |
121 | u32 aa, bb, cc, dd; | |
1da177e4 | 122 | |
edc05e6d IM |
123 | /* |
124 | * Bit 31 in normal CPUID used for nonstandard 3DNow ID; | |
125 | * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway | |
126 | */ | |
e1a94a97 | 127 | clear_cpu_cap(c, 0*32+31); |
48f4c485 SAS |
128 | #endif |
129 | early_init_centaur(c); | |
a2aa578f | 130 | init_intel_cacheinfo(c); |
9305bd6c | 131 | detect_num_cpu_cores(c); |
a2aa578f DW |
132 | #ifdef CONFIG_X86_32 |
133 | detect_ht(c); | |
134 | #endif | |
60882cc1 DW |
135 | |
136 | if (c->cpuid_level > 9) { | |
137 | unsigned int eax = cpuid_eax(10); | |
138 | ||
139 | /* | |
140 | * Check for version and the number of counters | |
141 | * Version(eax[7:0]) can't be 0; | |
142 | * Counters(eax[15:8]) should be greater than 1; | |
143 | */ | |
144 | if ((eax & 0xff) && (((eax >> 8) & 0xff) > 1)) | |
145 | set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); | |
146 | } | |
147 | ||
48f4c485 | 148 | #ifdef CONFIG_X86_32 |
8687bdc0 | 149 | if (c->x86 == 5) { |
edc05e6d IM |
150 | switch (c->x86_model) { |
151 | case 4: | |
152 | name = "C6"; | |
153 | fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK; | |
154 | fcr_clr = DPDC; | |
1b74dde7 | 155 | pr_notice("Disabling bugged TSC.\n"); |
e1a94a97 | 156 | clear_cpu_cap(c, X86_FEATURE_TSC); |
edc05e6d IM |
157 | break; |
158 | case 8: | |
b399151c | 159 | switch (c->x86_stepping) { |
edc05e6d IM |
160 | default: |
161 | name = "2"; | |
1da177e4 | 162 | break; |
edc05e6d IM |
163 | case 7 ... 9: |
164 | name = "2A"; | |
165 | break; | |
166 | case 10 ... 15: | |
167 | name = "2B"; | |
168 | break; | |
169 | } | |
170 | fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK| | |
171 | E2MMX|EAMD3D; | |
172 | fcr_clr = DPDC; | |
edc05e6d IM |
173 | break; |
174 | case 9: | |
175 | name = "3"; | |
176 | fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK| | |
177 | E2MMX|EAMD3D; | |
178 | fcr_clr = DPDC; | |
edc05e6d IM |
179 | break; |
180 | default: | |
181 | name = "??"; | |
182 | } | |
1da177e4 | 183 | |
edc05e6d IM |
184 | rdmsr(MSR_IDT_FCR1, lo, hi); |
185 | newlo = (lo|fcr_set) & (~fcr_clr); | |
1da177e4 | 186 | |
edc05e6d | 187 | if (newlo != lo) { |
1b74dde7 | 188 | pr_info("Centaur FCR was 0x%X now 0x%X\n", |
edc05e6d IM |
189 | lo, newlo); |
190 | wrmsr(MSR_IDT_FCR1, newlo, hi); | |
191 | } else { | |
1b74dde7 | 192 | pr_info("Centaur FCR is 0x%X\n", lo); |
edc05e6d IM |
193 | } |
194 | /* Emulate MTRRs using Centaur's MCR. */ | |
e1a94a97 | 195 | set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR); |
edc05e6d | 196 | /* Report CX8 */ |
e1a94a97 | 197 | set_cpu_cap(c, X86_FEATURE_CX8); |
edc05e6d IM |
198 | /* Set 3DNow! on Winchip 2 and above. */ |
199 | if (c->x86_model >= 8) | |
e1a94a97 | 200 | set_cpu_cap(c, X86_FEATURE_3DNOW); |
edc05e6d IM |
201 | /* See if we can find out some more. */ |
202 | if (cpuid_eax(0x80000000) >= 0x80000005) { | |
203 | /* Yes, we can. */ | |
204 | cpuid(0x80000005, &aa, &bb, &cc, &dd); | |
205 | /* Add L1 data and code cache sizes. */ | |
206 | c->x86_cache_size = (cc>>24)+(dd>>24); | |
207 | } | |
208 | sprintf(c->x86_model_id, "WinChip %s", name); | |
8687bdc0 | 209 | } |
48f4c485 | 210 | #endif |
33b4711d | 211 | if (c->x86 == 6 || c->x86 >= 7) |
edc05e6d | 212 | init_c3(c); |
48f4c485 SAS |
213 | #ifdef CONFIG_X86_64 |
214 | set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); | |
215 | #endif | |
60882cc1 | 216 | |
50144490 | 217 | init_ia32_feat_ctl(c); |
1da177e4 LT |
218 | } |
219 | ||
09dc68d9 | 220 | #ifdef CONFIG_X86_32 |
148f9bb8 | 221 | static unsigned int |
edc05e6d | 222 | centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size) |
1da177e4 LT |
223 | { |
224 | /* VIA C3 CPUs (670-68F) need further shifting. */ | |
225 | if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8))) | |
226 | size >>= 8; | |
227 | ||
edc05e6d IM |
228 | /* |
229 | * There's also an erratum in Nehemiah stepping 1, which | |
230 | * returns '65KB' instead of '64KB' | |
231 | * - Note, it seems this may only be in engineering samples. | |
232 | */ | |
233 | if ((c->x86 == 6) && (c->x86_model == 9) && | |
b399151c | 234 | (c->x86_stepping == 1) && (size == 65)) |
29a9994b | 235 | size -= 1; |
1da177e4 LT |
236 | return size; |
237 | } | |
09dc68d9 | 238 | #endif |
1da177e4 | 239 | |
148f9bb8 | 240 | static const struct cpu_dev centaur_cpu_dev = { |
1da177e4 LT |
241 | .c_vendor = "Centaur", |
242 | .c_ident = { "CentaurHauls" }, | |
5fef55fd | 243 | .c_early_init = early_init_centaur, |
1da177e4 | 244 | .c_init = init_centaur, |
09dc68d9 JB |
245 | #ifdef CONFIG_X86_32 |
246 | .legacy_cache_size = centaur_size_cache, | |
247 | #endif | |
10a434fc | 248 | .c_x86_vendor = X86_VENDOR_CENTAUR, |
1da177e4 LT |
249 | }; |
250 | ||
10a434fc | 251 | cpu_dev_register(centaur_cpu_dev); |