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Commit | Line | Data |
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f0fc4aff | 1 | #include <linux/bootmem.h> |
9766cdbc | 2 | #include <linux/linkage.h> |
f0fc4aff | 3 | #include <linux/bitops.h> |
9766cdbc | 4 | #include <linux/kernel.h> |
f0fc4aff | 5 | #include <linux/module.h> |
9766cdbc JSR |
6 | #include <linux/percpu.h> |
7 | #include <linux/string.h> | |
ee098e1a | 8 | #include <linux/ctype.h> |
1da177e4 | 9 | #include <linux/delay.h> |
9766cdbc JSR |
10 | #include <linux/sched.h> |
11 | #include <linux/init.h> | |
0f46efeb | 12 | #include <linux/kprobes.h> |
9766cdbc | 13 | #include <linux/kgdb.h> |
1da177e4 | 14 | #include <linux/smp.h> |
9766cdbc | 15 | #include <linux/io.h> |
b51ef52d | 16 | #include <linux/syscore_ops.h> |
9766cdbc JSR |
17 | |
18 | #include <asm/stackprotector.h> | |
cdd6c482 | 19 | #include <asm/perf_event.h> |
1da177e4 | 20 | #include <asm/mmu_context.h> |
49d859d7 | 21 | #include <asm/archrandom.h> |
9766cdbc JSR |
22 | #include <asm/hypervisor.h> |
23 | #include <asm/processor.h> | |
1e02ce4c | 24 | #include <asm/tlbflush.h> |
f649e938 | 25 | #include <asm/debugreg.h> |
9766cdbc | 26 | #include <asm/sections.h> |
f40c3300 | 27 | #include <asm/vsyscall.h> |
8bdbd962 AC |
28 | #include <linux/topology.h> |
29 | #include <linux/cpumask.h> | |
9766cdbc | 30 | #include <asm/pgtable.h> |
60063497 | 31 | #include <linux/atomic.h> |
9766cdbc JSR |
32 | #include <asm/proto.h> |
33 | #include <asm/setup.h> | |
34 | #include <asm/apic.h> | |
35 | #include <asm/desc.h> | |
78f7f1e5 | 36 | #include <asm/fpu/internal.h> |
27b07da7 | 37 | #include <asm/mtrr.h> |
8bdbd962 | 38 | #include <linux/numa.h> |
9766cdbc JSR |
39 | #include <asm/asm.h> |
40 | #include <asm/cpu.h> | |
a03a3e28 | 41 | #include <asm/mce.h> |
9766cdbc | 42 | #include <asm/msr.h> |
8d4a4300 | 43 | #include <asm/pat.h> |
d288e1cf FY |
44 | #include <asm/microcode.h> |
45 | #include <asm/microcode_intel.h> | |
e641f5f5 IM |
46 | |
47 | #ifdef CONFIG_X86_LOCAL_APIC | |
bdbcdd48 | 48 | #include <asm/uv/uv.h> |
1da177e4 LT |
49 | #endif |
50 | ||
51 | #include "cpu.h" | |
52 | ||
c2d1cec1 | 53 | /* all of these masks are initialized in setup_cpu_local_masks() */ |
c2d1cec1 | 54 | cpumask_var_t cpu_initialized_mask; |
9766cdbc JSR |
55 | cpumask_var_t cpu_callout_mask; |
56 | cpumask_var_t cpu_callin_mask; | |
c2d1cec1 MT |
57 | |
58 | /* representing cpus for which sibling maps can be computed */ | |
59 | cpumask_var_t cpu_sibling_setup_mask; | |
60 | ||
2f2f52ba | 61 | /* correctly size the local cpu masks */ |
4369f1fb | 62 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
63 | { |
64 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
65 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
66 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
67 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
68 | } | |
69 | ||
148f9bb8 | 70 | static void default_init(struct cpuinfo_x86 *c) |
e8055139 OZ |
71 | { |
72 | #ifdef CONFIG_X86_64 | |
27c13ece | 73 | cpu_detect_cache_sizes(c); |
e8055139 OZ |
74 | #else |
75 | /* Not much we can do here... */ | |
76 | /* Check if at least it has cpuid */ | |
77 | if (c->cpuid_level == -1) { | |
78 | /* No cpuid. It must be an ancient CPU */ | |
79 | if (c->x86 == 4) | |
80 | strcpy(c->x86_model_id, "486"); | |
81 | else if (c->x86 == 3) | |
82 | strcpy(c->x86_model_id, "386"); | |
83 | } | |
84 | #endif | |
85 | } | |
86 | ||
148f9bb8 | 87 | static const struct cpu_dev default_cpu = { |
e8055139 OZ |
88 | .c_init = default_init, |
89 | .c_vendor = "Unknown", | |
90 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
91 | }; | |
92 | ||
148f9bb8 | 93 | static const struct cpu_dev *this_cpu = &default_cpu; |
0a488a53 | 94 | |
06deef89 | 95 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 96 | #ifdef CONFIG_X86_64 |
06deef89 BG |
97 | /* |
98 | * We need valid kernel segments for data and code in long mode too | |
99 | * IRET will check the segment types kkeil 2000/10/28 | |
100 | * Also sysret mandates a special GDT layout | |
101 | * | |
9766cdbc | 102 | * TLS descriptors are currently at a different place compared to i386. |
06deef89 BG |
103 | * Hopefully nobody expects them at a fixed place (Wine?) |
104 | */ | |
1e5de182 AM |
105 | [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), |
106 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), | |
107 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), | |
108 | [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), | |
109 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), | |
110 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), | |
950ad7ff | 111 | #else |
1e5de182 AM |
112 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), |
113 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
114 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), | |
115 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), | |
bf504672 RR |
116 | /* |
117 | * Segments used for calling PnP BIOS have byte granularity. | |
118 | * They code segments and data segments have fixed 64k limits, | |
119 | * the transfer segment sizes are set at run time. | |
120 | */ | |
6842ef0e | 121 | /* 32-bit code */ |
1e5de182 | 122 | [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
6842ef0e | 123 | /* 16-bit code */ |
1e5de182 | 124 | [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 125 | /* 16-bit data */ |
1e5de182 | 126 | [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), |
6842ef0e | 127 | /* 16-bit data */ |
1e5de182 | 128 | [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), |
6842ef0e | 129 | /* 16-bit data */ |
1e5de182 | 130 | [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), |
bf504672 RR |
131 | /* |
132 | * The APM segments have byte granularity and their bases | |
133 | * are set at run time. All have 64k limits. | |
134 | */ | |
6842ef0e | 135 | /* 32-bit code */ |
1e5de182 | 136 | [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
bf504672 | 137 | /* 16-bit code */ |
1e5de182 | 138 | [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 139 | /* data */ |
72c4d853 | 140 | [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), |
bf504672 | 141 | |
1e5de182 AM |
142 | [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), |
143 | [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
60a5317f | 144 | GDT_STACK_CANARY_INIT |
950ad7ff | 145 | #endif |
06deef89 | 146 | } }; |
7a61d35d | 147 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 148 | |
8c3641e9 | 149 | static int __init x86_mpx_setup(char *s) |
0c752a93 | 150 | { |
8c3641e9 | 151 | /* require an exact match without trailing characters */ |
2cd3949f DH |
152 | if (strlen(s)) |
153 | return 0; | |
0c752a93 | 154 | |
8c3641e9 DH |
155 | /* do not emit a message if the feature is not present */ |
156 | if (!boot_cpu_has(X86_FEATURE_MPX)) | |
157 | return 1; | |
6bad06b7 | 158 | |
8c3641e9 DH |
159 | setup_clear_cpu_cap(X86_FEATURE_MPX); |
160 | pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); | |
b6f42a4a FY |
161 | return 1; |
162 | } | |
8c3641e9 | 163 | __setup("nompx", x86_mpx_setup); |
b6f42a4a | 164 | |
d12a72b8 AL |
165 | static int __init x86_noinvpcid_setup(char *s) |
166 | { | |
167 | /* noinvpcid doesn't accept parameters */ | |
168 | if (s) | |
169 | return -EINVAL; | |
170 | ||
171 | /* do not emit a message if the feature is not present */ | |
172 | if (!boot_cpu_has(X86_FEATURE_INVPCID)) | |
173 | return 0; | |
174 | ||
175 | setup_clear_cpu_cap(X86_FEATURE_INVPCID); | |
176 | pr_info("noinvpcid: INVPCID feature disabled\n"); | |
177 | return 0; | |
178 | } | |
179 | early_param("noinvpcid", x86_noinvpcid_setup); | |
180 | ||
ba51dced | 181 | #ifdef CONFIG_X86_32 |
148f9bb8 PG |
182 | static int cachesize_override = -1; |
183 | static int disable_x86_serial_nr = 1; | |
1da177e4 | 184 | |
0a488a53 YL |
185 | static int __init cachesize_setup(char *str) |
186 | { | |
187 | get_option(&str, &cachesize_override); | |
188 | return 1; | |
189 | } | |
190 | __setup("cachesize=", cachesize_setup); | |
191 | ||
0a488a53 YL |
192 | static int __init x86_sep_setup(char *s) |
193 | { | |
194 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
195 | return 1; | |
196 | } | |
197 | __setup("nosep", x86_sep_setup); | |
198 | ||
199 | /* Standard macro to see if a specific flag is changeable */ | |
200 | static inline int flag_is_changeable_p(u32 flag) | |
201 | { | |
202 | u32 f1, f2; | |
203 | ||
94f6bac1 KH |
204 | /* |
205 | * Cyrix and IDT cpus allow disabling of CPUID | |
206 | * so the code below may return different results | |
207 | * when it is executed before and after enabling | |
208 | * the CPUID. Add "volatile" to not allow gcc to | |
209 | * optimize the subsequent calls to this function. | |
210 | */ | |
0f3fa48a IM |
211 | asm volatile ("pushfl \n\t" |
212 | "pushfl \n\t" | |
213 | "popl %0 \n\t" | |
214 | "movl %0, %1 \n\t" | |
215 | "xorl %2, %0 \n\t" | |
216 | "pushl %0 \n\t" | |
217 | "popfl \n\t" | |
218 | "pushfl \n\t" | |
219 | "popl %0 \n\t" | |
220 | "popfl \n\t" | |
221 | ||
94f6bac1 KH |
222 | : "=&r" (f1), "=&r" (f2) |
223 | : "ir" (flag)); | |
0a488a53 YL |
224 | |
225 | return ((f1^f2) & flag) != 0; | |
226 | } | |
227 | ||
228 | /* Probe for the CPUID instruction */ | |
148f9bb8 | 229 | int have_cpuid_p(void) |
0a488a53 YL |
230 | { |
231 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
232 | } | |
233 | ||
148f9bb8 | 234 | static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
0a488a53 | 235 | { |
0f3fa48a IM |
236 | unsigned long lo, hi; |
237 | ||
238 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
239 | return; | |
240 | ||
241 | /* Disable processor serial number: */ | |
242 | ||
243 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
244 | lo |= 0x200000; | |
245 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
246 | ||
1b74dde7 | 247 | pr_notice("CPU serial number disabled.\n"); |
0f3fa48a IM |
248 | clear_cpu_cap(c, X86_FEATURE_PN); |
249 | ||
250 | /* Disabling the serial number may affect the cpuid level */ | |
251 | c->cpuid_level = cpuid_eax(0); | |
0a488a53 YL |
252 | } |
253 | ||
254 | static int __init x86_serial_nr_setup(char *s) | |
255 | { | |
256 | disable_x86_serial_nr = 0; | |
257 | return 1; | |
258 | } | |
259 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 260 | #else |
102bbe3a YL |
261 | static inline int flag_is_changeable_p(u32 flag) |
262 | { | |
263 | return 1; | |
264 | } | |
102bbe3a YL |
265 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
266 | { | |
267 | } | |
ba51dced | 268 | #endif |
0a488a53 | 269 | |
de5397ad FY |
270 | static __init int setup_disable_smep(char *arg) |
271 | { | |
b2cc2a07 | 272 | setup_clear_cpu_cap(X86_FEATURE_SMEP); |
de5397ad FY |
273 | return 1; |
274 | } | |
275 | __setup("nosmep", setup_disable_smep); | |
276 | ||
b2cc2a07 | 277 | static __always_inline void setup_smep(struct cpuinfo_x86 *c) |
de5397ad | 278 | { |
b2cc2a07 | 279 | if (cpu_has(c, X86_FEATURE_SMEP)) |
375074cc | 280 | cr4_set_bits(X86_CR4_SMEP); |
de5397ad FY |
281 | } |
282 | ||
52b6179a PA |
283 | static __init int setup_disable_smap(char *arg) |
284 | { | |
b2cc2a07 | 285 | setup_clear_cpu_cap(X86_FEATURE_SMAP); |
52b6179a PA |
286 | return 1; |
287 | } | |
288 | __setup("nosmap", setup_disable_smap); | |
289 | ||
b2cc2a07 PA |
290 | static __always_inline void setup_smap(struct cpuinfo_x86 *c) |
291 | { | |
581b7f15 | 292 | unsigned long eflags = native_save_fl(); |
b2cc2a07 PA |
293 | |
294 | /* This should have been cleared long ago */ | |
b2cc2a07 PA |
295 | BUG_ON(eflags & X86_EFLAGS_AC); |
296 | ||
03bbd596 PA |
297 | if (cpu_has(c, X86_FEATURE_SMAP)) { |
298 | #ifdef CONFIG_X86_SMAP | |
375074cc | 299 | cr4_set_bits(X86_CR4_SMAP); |
03bbd596 | 300 | #else |
375074cc | 301 | cr4_clear_bits(X86_CR4_SMAP); |
03bbd596 PA |
302 | #endif |
303 | } | |
de5397ad FY |
304 | } |
305 | ||
06976945 DH |
306 | /* |
307 | * Protection Keys are not available in 32-bit mode. | |
308 | */ | |
309 | static bool pku_disabled; | |
310 | ||
311 | static __always_inline void setup_pku(struct cpuinfo_x86 *c) | |
312 | { | |
313 | if (!cpu_has(c, X86_FEATURE_PKU)) | |
314 | return; | |
315 | if (pku_disabled) | |
316 | return; | |
317 | ||
318 | cr4_set_bits(X86_CR4_PKE); | |
319 | /* | |
320 | * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE | |
321 | * cpuid bit to be set. We need to ensure that we | |
322 | * update that bit in this CPU's "cpu_info". | |
323 | */ | |
324 | get_cpu_cap(c); | |
325 | } | |
326 | ||
327 | #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS | |
328 | static __init int setup_disable_pku(char *arg) | |
329 | { | |
330 | /* | |
331 | * Do not clear the X86_FEATURE_PKU bit. All of the | |
332 | * runtime checks are against OSPKE so clearing the | |
333 | * bit does nothing. | |
334 | * | |
335 | * This way, we will see "pku" in cpuinfo, but not | |
336 | * "ospke", which is exactly what we want. It shows | |
337 | * that the CPU has PKU, but the OS has not enabled it. | |
338 | * This happens to be exactly how a system would look | |
339 | * if we disabled the config option. | |
340 | */ | |
341 | pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); | |
342 | pku_disabled = true; | |
343 | return 1; | |
344 | } | |
345 | __setup("nopku", setup_disable_pku); | |
346 | #endif /* CONFIG_X86_64 */ | |
347 | ||
b38b0665 PA |
348 | /* |
349 | * Some CPU features depend on higher CPUID levels, which may not always | |
350 | * be available due to CPUID level capping or broken virtualization | |
351 | * software. Add those features to this table to auto-disable them. | |
352 | */ | |
353 | struct cpuid_dependent_feature { | |
354 | u32 feature; | |
355 | u32 level; | |
356 | }; | |
0f3fa48a | 357 | |
148f9bb8 | 358 | static const struct cpuid_dependent_feature |
b38b0665 PA |
359 | cpuid_dependent_features[] = { |
360 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
361 | { X86_FEATURE_DCA, 0x00000009 }, | |
362 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
363 | { 0, 0 } | |
364 | }; | |
365 | ||
148f9bb8 | 366 | static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) |
b38b0665 PA |
367 | { |
368 | const struct cpuid_dependent_feature *df; | |
9766cdbc | 369 | |
b38b0665 | 370 | for (df = cpuid_dependent_features; df->feature; df++) { |
0f3fa48a IM |
371 | |
372 | if (!cpu_has(c, df->feature)) | |
373 | continue; | |
b38b0665 PA |
374 | /* |
375 | * Note: cpuid_level is set to -1 if unavailable, but | |
376 | * extended_extended_level is set to 0 if unavailable | |
377 | * and the legitimate extended levels are all negative | |
378 | * when signed; hence the weird messing around with | |
379 | * signs here... | |
380 | */ | |
0f3fa48a | 381 | if (!((s32)df->level < 0 ? |
f6db44df | 382 | (u32)df->level > (u32)c->extended_cpuid_level : |
0f3fa48a IM |
383 | (s32)df->level > (s32)c->cpuid_level)) |
384 | continue; | |
385 | ||
386 | clear_cpu_cap(c, df->feature); | |
387 | if (!warn) | |
388 | continue; | |
389 | ||
1b74dde7 CY |
390 | pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", |
391 | x86_cap_flag(df->feature), df->level); | |
b38b0665 | 392 | } |
f6db44df | 393 | } |
b38b0665 | 394 | |
102bbe3a YL |
395 | /* |
396 | * Naming convention should be: <Name> [(<Codename>)] | |
397 | * This table only is used unless init_<vendor>() below doesn't set it; | |
0f3fa48a IM |
398 | * in particular, if CPUID levels 0x80000002..4 are supported, this |
399 | * isn't used | |
102bbe3a YL |
400 | */ |
401 | ||
402 | /* Look up CPU names by table lookup. */ | |
148f9bb8 | 403 | static const char *table_lookup_model(struct cpuinfo_x86 *c) |
102bbe3a | 404 | { |
09dc68d9 JB |
405 | #ifdef CONFIG_X86_32 |
406 | const struct legacy_cpu_model_info *info; | |
102bbe3a YL |
407 | |
408 | if (c->x86_model >= 16) | |
409 | return NULL; /* Range check */ | |
410 | ||
411 | if (!this_cpu) | |
412 | return NULL; | |
413 | ||
09dc68d9 | 414 | info = this_cpu->legacy_models; |
102bbe3a | 415 | |
09dc68d9 | 416 | while (info->family) { |
102bbe3a YL |
417 | if (info->family == c->x86) |
418 | return info->model_names[c->x86_model]; | |
419 | info++; | |
420 | } | |
09dc68d9 | 421 | #endif |
102bbe3a YL |
422 | return NULL; /* Not found */ |
423 | } | |
424 | ||
148f9bb8 PG |
425 | __u32 cpu_caps_cleared[NCAPINTS]; |
426 | __u32 cpu_caps_set[NCAPINTS]; | |
7d851c8d | 427 | |
11e3a840 JF |
428 | void load_percpu_segment(int cpu) |
429 | { | |
430 | #ifdef CONFIG_X86_32 | |
431 | loadsegment(fs, __KERNEL_PERCPU); | |
432 | #else | |
45e876f7 | 433 | __loadsegment_simple(gs, 0); |
11e3a840 JF |
434 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); |
435 | #endif | |
60a5317f | 436 | load_stack_canary_segment(); |
11e3a840 JF |
437 | } |
438 | ||
0f3fa48a IM |
439 | /* |
440 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
441 | * it's on the real one. | |
442 | */ | |
552be871 | 443 | void switch_to_new_gdt(int cpu) |
9d31d35b YL |
444 | { |
445 | struct desc_ptr gdt_descr; | |
446 | ||
2697fbd5 | 447 | gdt_descr.address = (long)get_cpu_gdt_table(cpu); |
9d31d35b YL |
448 | gdt_descr.size = GDT_SIZE - 1; |
449 | load_gdt(&gdt_descr); | |
2697fbd5 | 450 | /* Reload the per-cpu base */ |
11e3a840 JF |
451 | |
452 | load_percpu_segment(cpu); | |
9d31d35b YL |
453 | } |
454 | ||
148f9bb8 | 455 | static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 456 | |
148f9bb8 | 457 | static void get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
458 | { |
459 | unsigned int *v; | |
ee098e1a | 460 | char *p, *q, *s; |
1da177e4 | 461 | |
3da99c97 | 462 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 463 | return; |
1da177e4 | 464 | |
0f3fa48a | 465 | v = (unsigned int *)c->x86_model_id; |
1da177e4 LT |
466 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); |
467 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
468 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
469 | c->x86_model_id[48] = 0; | |
470 | ||
ee098e1a BP |
471 | /* Trim whitespace */ |
472 | p = q = s = &c->x86_model_id[0]; | |
473 | ||
474 | while (*p == ' ') | |
475 | p++; | |
476 | ||
477 | while (*p) { | |
478 | /* Note the last non-whitespace index */ | |
479 | if (!isspace(*p)) | |
480 | s = q; | |
481 | ||
482 | *q++ = *p++; | |
483 | } | |
484 | ||
485 | *(s + 1) = '\0'; | |
1da177e4 LT |
486 | } |
487 | ||
148f9bb8 | 488 | void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) |
1da177e4 | 489 | { |
9d31d35b | 490 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 491 | |
3da99c97 | 492 | n = c->extended_cpuid_level; |
1da177e4 LT |
493 | |
494 | if (n >= 0x80000005) { | |
9d31d35b | 495 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
9d31d35b | 496 | c->x86_cache_size = (ecx>>24) + (edx>>24); |
140fc727 YL |
497 | #ifdef CONFIG_X86_64 |
498 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
499 | c->x86_tlbsize = 0; | |
500 | #endif | |
1da177e4 LT |
501 | } |
502 | ||
503 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
504 | return; | |
505 | ||
0a488a53 | 506 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 507 | l2size = ecx >> 16; |
34048c9e | 508 | |
140fc727 YL |
509 | #ifdef CONFIG_X86_64 |
510 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
511 | #else | |
1da177e4 | 512 | /* do processor-specific cache resizing */ |
09dc68d9 JB |
513 | if (this_cpu->legacy_cache_size) |
514 | l2size = this_cpu->legacy_cache_size(c, l2size); | |
1da177e4 LT |
515 | |
516 | /* Allow user to override all this if necessary. */ | |
517 | if (cachesize_override != -1) | |
518 | l2size = cachesize_override; | |
519 | ||
34048c9e | 520 | if (l2size == 0) |
1da177e4 | 521 | return; /* Again, no L2 cache is possible */ |
140fc727 | 522 | #endif |
1da177e4 LT |
523 | |
524 | c->x86_cache_size = l2size; | |
1da177e4 LT |
525 | } |
526 | ||
e0ba94f1 AS |
527 | u16 __read_mostly tlb_lli_4k[NR_INFO]; |
528 | u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
529 | u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
530 | u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
531 | u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
532 | u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
dd360393 | 533 | u16 __read_mostly tlb_lld_1g[NR_INFO]; |
e0ba94f1 | 534 | |
f94fe119 | 535 | static void cpu_detect_tlb(struct cpuinfo_x86 *c) |
e0ba94f1 AS |
536 | { |
537 | if (this_cpu->c_detect_tlb) | |
538 | this_cpu->c_detect_tlb(c); | |
539 | ||
f94fe119 | 540 | pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", |
e0ba94f1 | 541 | tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], |
f94fe119 SH |
542 | tlb_lli_4m[ENTRIES]); |
543 | ||
544 | pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", | |
545 | tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], | |
546 | tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); | |
e0ba94f1 AS |
547 | } |
548 | ||
148f9bb8 | 549 | void detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 550 | { |
c8e56d20 | 551 | #ifdef CONFIG_SMP |
0a488a53 YL |
552 | u32 eax, ebx, ecx, edx; |
553 | int index_msb, core_bits; | |
2eaad1fd | 554 | static bool printed; |
1da177e4 | 555 | |
0a488a53 | 556 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 557 | return; |
1da177e4 | 558 | |
0a488a53 YL |
559 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
560 | goto out; | |
1da177e4 | 561 | |
1cd78776 YL |
562 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
563 | return; | |
1da177e4 | 564 | |
0a488a53 | 565 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 566 | |
9d31d35b YL |
567 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
568 | ||
569 | if (smp_num_siblings == 1) { | |
1b74dde7 | 570 | pr_info_once("CPU0: Hyper-Threading is disabled\n"); |
0f3fa48a IM |
571 | goto out; |
572 | } | |
9d31d35b | 573 | |
0f3fa48a IM |
574 | if (smp_num_siblings <= 1) |
575 | goto out; | |
9d31d35b | 576 | |
0f3fa48a IM |
577 | index_msb = get_count_order(smp_num_siblings); |
578 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
9d31d35b | 579 | |
0f3fa48a | 580 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
9d31d35b | 581 | |
0f3fa48a | 582 | index_msb = get_count_order(smp_num_siblings); |
9d31d35b | 583 | |
0f3fa48a | 584 | core_bits = get_count_order(c->x86_max_cores); |
9d31d35b | 585 | |
0f3fa48a IM |
586 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
587 | ((1 << core_bits) - 1); | |
1da177e4 | 588 | |
0a488a53 | 589 | out: |
2eaad1fd | 590 | if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { |
1b74dde7 CY |
591 | pr_info("CPU: Physical Processor ID: %d\n", |
592 | c->phys_proc_id); | |
593 | pr_info("CPU: Processor Core ID: %d\n", | |
594 | c->cpu_core_id); | |
2eaad1fd | 595 | printed = 1; |
9d31d35b | 596 | } |
9d31d35b | 597 | #endif |
97e4db7c | 598 | } |
1da177e4 | 599 | |
148f9bb8 | 600 | static void get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
601 | { |
602 | char *v = c->x86_vendor_id; | |
0f3fa48a | 603 | int i; |
1da177e4 LT |
604 | |
605 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
606 | if (!cpu_devs[i]) |
607 | break; | |
608 | ||
609 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
610 | (cpu_devs[i]->c_ident[1] && | |
611 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
0f3fa48a | 612 | |
10a434fc YL |
613 | this_cpu = cpu_devs[i]; |
614 | c->x86_vendor = this_cpu->c_x86_vendor; | |
615 | return; | |
1da177e4 LT |
616 | } |
617 | } | |
10a434fc | 618 | |
1b74dde7 CY |
619 | pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ |
620 | "CPU: Your system may be unstable.\n", v); | |
10a434fc | 621 | |
fe38d855 CE |
622 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
623 | this_cpu = &default_cpu; | |
1da177e4 LT |
624 | } |
625 | ||
148f9bb8 | 626 | void cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 627 | { |
1da177e4 | 628 | /* Get vendor name */ |
4a148513 HH |
629 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
630 | (unsigned int *)&c->x86_vendor_id[0], | |
631 | (unsigned int *)&c->x86_vendor_id[8], | |
632 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 633 | |
1da177e4 | 634 | c->x86 = 4; |
9d31d35b | 635 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
636 | if (c->cpuid_level >= 0x00000001) { |
637 | u32 junk, tfms, cap0, misc; | |
0f3fa48a | 638 | |
1da177e4 | 639 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
99f925ce BP |
640 | c->x86 = x86_family(tfms); |
641 | c->x86_model = x86_model(tfms); | |
642 | c->x86_mask = x86_stepping(tfms); | |
0f3fa48a | 643 | |
d4387bd3 | 644 | if (cap0 & (1<<19)) { |
d4387bd3 | 645 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 646 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 647 | } |
1da177e4 | 648 | } |
1da177e4 | 649 | } |
3da99c97 | 650 | |
148f9bb8 | 651 | void get_cpu_cap(struct cpuinfo_x86 *c) |
093af8d7 | 652 | { |
39c06df4 | 653 | u32 eax, ebx, ecx, edx; |
093af8d7 | 654 | |
3da99c97 YL |
655 | /* Intel-defined flags: level 0x00000001 */ |
656 | if (c->cpuid_level >= 0x00000001) { | |
39c06df4 | 657 | cpuid(0x00000001, &eax, &ebx, &ecx, &edx); |
0f3fa48a | 658 | |
39c06df4 BP |
659 | c->x86_capability[CPUID_1_ECX] = ecx; |
660 | c->x86_capability[CPUID_1_EDX] = edx; | |
3da99c97 | 661 | } |
093af8d7 | 662 | |
bdc802dc PA |
663 | /* Additional Intel-defined flags: level 0x00000007 */ |
664 | if (c->cpuid_level >= 0x00000007) { | |
bdc802dc PA |
665 | cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); |
666 | ||
39c06df4 | 667 | c->x86_capability[CPUID_7_0_EBX] = ebx; |
2ccd71f1 | 668 | |
39c06df4 | 669 | c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); |
dfb4a70f | 670 | c->x86_capability[CPUID_7_ECX] = ecx; |
bdc802dc PA |
671 | } |
672 | ||
6229ad27 FY |
673 | /* Extended state features: level 0x0000000d */ |
674 | if (c->cpuid_level >= 0x0000000d) { | |
6229ad27 FY |
675 | cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); |
676 | ||
39c06df4 | 677 | c->x86_capability[CPUID_D_1_EAX] = eax; |
6229ad27 FY |
678 | } |
679 | ||
cbc82b17 PWJ |
680 | /* Additional Intel-defined flags: level 0x0000000F */ |
681 | if (c->cpuid_level >= 0x0000000F) { | |
cbc82b17 PWJ |
682 | |
683 | /* QoS sub-leaf, EAX=0Fh, ECX=0 */ | |
684 | cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx); | |
39c06df4 BP |
685 | c->x86_capability[CPUID_F_0_EDX] = edx; |
686 | ||
cbc82b17 PWJ |
687 | if (cpu_has(c, X86_FEATURE_CQM_LLC)) { |
688 | /* will be overridden if occupancy monitoring exists */ | |
689 | c->x86_cache_max_rmid = ebx; | |
690 | ||
691 | /* QoS sub-leaf, EAX=0Fh, ECX=1 */ | |
692 | cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx); | |
39c06df4 BP |
693 | c->x86_capability[CPUID_F_1_EDX] = edx; |
694 | ||
33c3cc7a VS |
695 | if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) || |
696 | ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) || | |
697 | (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) { | |
cbc82b17 PWJ |
698 | c->x86_cache_max_rmid = ecx; |
699 | c->x86_cache_occ_scale = ebx; | |
700 | } | |
701 | } else { | |
702 | c->x86_cache_max_rmid = -1; | |
703 | c->x86_cache_occ_scale = -1; | |
704 | } | |
705 | } | |
706 | ||
3da99c97 | 707 | /* AMD-defined flags: level 0x80000001 */ |
39c06df4 BP |
708 | eax = cpuid_eax(0x80000000); |
709 | c->extended_cpuid_level = eax; | |
710 | ||
711 | if ((eax & 0xffff0000) == 0x80000000) { | |
712 | if (eax >= 0x80000001) { | |
713 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
0f3fa48a | 714 | |
39c06df4 BP |
715 | c->x86_capability[CPUID_8000_0001_ECX] = ecx; |
716 | c->x86_capability[CPUID_8000_0001_EDX] = edx; | |
093af8d7 | 717 | } |
093af8d7 | 718 | } |
093af8d7 | 719 | |
71faad43 YG |
720 | if (c->extended_cpuid_level >= 0x80000007) { |
721 | cpuid(0x80000007, &eax, &ebx, &ecx, &edx); | |
722 | ||
723 | c->x86_capability[CPUID_8000_0007_EBX] = ebx; | |
724 | c->x86_power = edx; | |
725 | } | |
726 | ||
5122c890 | 727 | if (c->extended_cpuid_level >= 0x80000008) { |
39c06df4 | 728 | cpuid(0x80000008, &eax, &ebx, &ecx, &edx); |
5122c890 YL |
729 | |
730 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
731 | c->x86_phys_bits = eax & 0xff; | |
39c06df4 | 732 | c->x86_capability[CPUID_8000_0008_EBX] = ebx; |
093af8d7 | 733 | } |
13c6c532 JB |
734 | #ifdef CONFIG_X86_32 |
735 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
736 | c->x86_phys_bits = 36; | |
5122c890 | 737 | #endif |
e3224234 | 738 | |
2ccd71f1 | 739 | if (c->extended_cpuid_level >= 0x8000000a) |
39c06df4 | 740 | c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); |
093af8d7 | 741 | |
1dedefd1 | 742 | init_scattered_cpuid_features(c); |
093af8d7 | 743 | } |
1da177e4 | 744 | |
148f9bb8 | 745 | static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
aef93c8b YL |
746 | { |
747 | #ifdef CONFIG_X86_32 | |
748 | int i; | |
749 | ||
750 | /* | |
751 | * First of all, decide if this is a 486 or higher | |
752 | * It's a 486 if we can modify the AC flag | |
753 | */ | |
754 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
755 | c->x86 = 4; | |
756 | else | |
757 | c->x86 = 3; | |
758 | ||
759 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
760 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
761 | c->x86_vendor_id[0] = 0; | |
762 | cpu_devs[i]->c_identify(c); | |
763 | if (c->x86_vendor_id[0]) { | |
764 | get_cpu_vendor(c); | |
765 | break; | |
766 | } | |
767 | } | |
768 | #endif | |
769 | } | |
770 | ||
34048c9e PC |
771 | /* |
772 | * Do minimum CPU detection early. | |
773 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
774 | * cache alignment. | |
775 | * The others are not touched to avoid unwanted side effects. | |
776 | * | |
777 | * WARNING: this function is only called on the BP. Don't add code here | |
778 | * that is supposed to run on all CPUs. | |
779 | */ | |
3da99c97 | 780 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 781 | { |
6627d242 YL |
782 | #ifdef CONFIG_X86_64 |
783 | c->x86_clflush_size = 64; | |
13c6c532 JB |
784 | c->x86_phys_bits = 36; |
785 | c->x86_virt_bits = 48; | |
6627d242 | 786 | #else |
d4387bd3 | 787 | c->x86_clflush_size = 32; |
13c6c532 JB |
788 | c->x86_phys_bits = 32; |
789 | c->x86_virt_bits = 32; | |
6627d242 | 790 | #endif |
0a488a53 | 791 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 792 | |
3da99c97 | 793 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 794 | c->extended_cpuid_level = 0; |
d7cd5611 | 795 | |
aef93c8b YL |
796 | if (!have_cpuid_p()) |
797 | identify_cpu_without_cpuid(c); | |
798 | ||
799 | /* cyrix could have cpuid enabled via c_identify()*/ | |
d7cd5611 RR |
800 | if (!have_cpuid_p()) |
801 | return; | |
802 | ||
803 | cpu_detect(c); | |
3da99c97 | 804 | get_cpu_vendor(c); |
3da99c97 | 805 | get_cpu_cap(c); |
12cf105c | 806 | |
10a434fc YL |
807 | if (this_cpu->c_early_init) |
808 | this_cpu->c_early_init(c); | |
093af8d7 | 809 | |
f6e9456c | 810 | c->cpu_index = 0; |
b38b0665 | 811 | filter_cpuid_features(c, false); |
de5397ad | 812 | |
a110b5ec BP |
813 | if (this_cpu->c_bsp_init) |
814 | this_cpu->c_bsp_init(c); | |
c3b83598 BP |
815 | |
816 | setup_force_cpu_cap(X86_FEATURE_ALWAYS); | |
db52ef74 | 817 | fpu__init_system(c); |
d7cd5611 RR |
818 | } |
819 | ||
9d31d35b YL |
820 | void __init early_cpu_init(void) |
821 | { | |
02dde8b4 | 822 | const struct cpu_dev *const *cdev; |
10a434fc YL |
823 | int count = 0; |
824 | ||
ac23f253 | 825 | #ifdef CONFIG_PROCESSOR_SELECT |
1b74dde7 | 826 | pr_info("KERNEL supported cpus:\n"); |
31c997ca IM |
827 | #endif |
828 | ||
10a434fc | 829 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
02dde8b4 | 830 | const struct cpu_dev *cpudev = *cdev; |
9d31d35b | 831 | |
10a434fc YL |
832 | if (count >= X86_VENDOR_NUM) |
833 | break; | |
834 | cpu_devs[count] = cpudev; | |
835 | count++; | |
836 | ||
ac23f253 | 837 | #ifdef CONFIG_PROCESSOR_SELECT |
31c997ca IM |
838 | { |
839 | unsigned int j; | |
840 | ||
841 | for (j = 0; j < 2; j++) { | |
842 | if (!cpudev->c_ident[j]) | |
843 | continue; | |
1b74dde7 | 844 | pr_info(" %s %s\n", cpudev->c_vendor, |
31c997ca IM |
845 | cpudev->c_ident[j]); |
846 | } | |
10a434fc | 847 | } |
0388423d | 848 | #endif |
10a434fc | 849 | } |
9d31d35b | 850 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 851 | } |
093af8d7 | 852 | |
b6734c35 | 853 | /* |
366d4a43 BP |
854 | * The NOPL instruction is supposed to exist on all CPUs of family >= 6; |
855 | * unfortunately, that's not true in practice because of early VIA | |
856 | * chips and (more importantly) broken virtualizers that are not easy | |
857 | * to detect. In the latter case it doesn't even *fail* reliably, so | |
858 | * probing for it doesn't even work. Disable it completely on 32-bit | |
ba0593bf | 859 | * unless we can find a reliable way to detect all the broken cases. |
366d4a43 | 860 | * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). |
b6734c35 | 861 | */ |
148f9bb8 | 862 | static void detect_nopl(struct cpuinfo_x86 *c) |
b6734c35 | 863 | { |
366d4a43 | 864 | #ifdef CONFIG_X86_32 |
b6734c35 | 865 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
366d4a43 BP |
866 | #else |
867 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
58a5aac5 | 868 | #endif |
d7cd5611 | 869 | } |
58a5aac5 | 870 | |
7a5d6704 AL |
871 | static void detect_null_seg_behavior(struct cpuinfo_x86 *c) |
872 | { | |
873 | #ifdef CONFIG_X86_64 | |
58a5aac5 | 874 | /* |
7a5d6704 AL |
875 | * Empirically, writing zero to a segment selector on AMD does |
876 | * not clear the base, whereas writing zero to a segment | |
877 | * selector on Intel does clear the base. Intel's behavior | |
878 | * allows slightly faster context switches in the common case | |
879 | * where GS is unused by the prev and next threads. | |
58a5aac5 | 880 | * |
7a5d6704 AL |
881 | * Since neither vendor documents this anywhere that I can see, |
882 | * detect it directly instead of hardcoding the choice by | |
883 | * vendor. | |
884 | * | |
885 | * I've designated AMD's behavior as the "bug" because it's | |
886 | * counterintuitive and less friendly. | |
58a5aac5 | 887 | */ |
7a5d6704 AL |
888 | |
889 | unsigned long old_base, tmp; | |
890 | rdmsrl(MSR_FS_BASE, old_base); | |
891 | wrmsrl(MSR_FS_BASE, 1); | |
892 | loadsegment(fs, 0); | |
893 | rdmsrl(MSR_FS_BASE, tmp); | |
894 | if (tmp != 0) | |
895 | set_cpu_bug(c, X86_BUG_NULL_SEG); | |
896 | wrmsrl(MSR_FS_BASE, old_base); | |
366d4a43 | 897 | #endif |
d7cd5611 RR |
898 | } |
899 | ||
148f9bb8 | 900 | static void generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 901 | { |
aef93c8b | 902 | c->extended_cpuid_level = 0; |
1da177e4 | 903 | |
3da99c97 | 904 | if (!have_cpuid_p()) |
aef93c8b | 905 | identify_cpu_without_cpuid(c); |
1d67953f | 906 | |
aef93c8b | 907 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 908 | if (!have_cpuid_p()) |
aef93c8b | 909 | return; |
1da177e4 | 910 | |
3da99c97 | 911 | cpu_detect(c); |
1da177e4 | 912 | |
3da99c97 | 913 | get_cpu_vendor(c); |
1da177e4 | 914 | |
3da99c97 | 915 | get_cpu_cap(c); |
1da177e4 | 916 | |
3da99c97 YL |
917 | if (c->cpuid_level >= 0x00000001) { |
918 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e | 919 | #ifdef CONFIG_X86_32 |
c8e56d20 | 920 | # ifdef CONFIG_SMP |
cb8cc442 | 921 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 922 | # else |
3da99c97 | 923 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
924 | # endif |
925 | #endif | |
b89d3b3e | 926 | c->phys_proc_id = c->initial_apicid; |
3da99c97 | 927 | } |
1da177e4 | 928 | |
1b05d60d | 929 | get_model_name(c); /* Default name */ |
1da177e4 | 930 | |
3da99c97 | 931 | detect_nopl(c); |
7a5d6704 AL |
932 | |
933 | detect_null_seg_behavior(c); | |
0230bb03 AL |
934 | |
935 | /* | |
936 | * ESPFIX is a strange bug. All real CPUs have it. Paravirt | |
937 | * systems that run Linux at CPL > 0 may or may not have the | |
938 | * issue, but, even if they have the issue, there's absolutely | |
939 | * nothing we can do about it because we can't use the real IRET | |
940 | * instruction. | |
941 | * | |
942 | * NB: For the time being, only 32-bit kernels support | |
943 | * X86_BUG_ESPFIX as such. 64-bit kernels directly choose | |
944 | * whether to apply espfix using paravirt hooks. If any | |
945 | * non-paravirt system ever shows up that does *not* have the | |
946 | * ESPFIX issue, we can change this. | |
947 | */ | |
948 | #ifdef CONFIG_X86_32 | |
949 | # ifdef CONFIG_PARAVIRT | |
950 | do { | |
951 | extern void native_iret(void); | |
952 | if (pv_cpu_ops.iret == native_iret) | |
953 | set_cpu_bug(c, X86_BUG_ESPFIX); | |
954 | } while (0); | |
955 | # else | |
956 | set_cpu_bug(c, X86_BUG_ESPFIX); | |
957 | # endif | |
958 | #endif | |
1da177e4 | 959 | } |
1da177e4 | 960 | |
cbc82b17 PWJ |
961 | static void x86_init_cache_qos(struct cpuinfo_x86 *c) |
962 | { | |
963 | /* | |
964 | * The heavy lifting of max_rmid and cache_occ_scale are handled | |
965 | * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu | |
966 | * in case CQM bits really aren't there in this CPU. | |
967 | */ | |
968 | if (c != &boot_cpu_data) { | |
969 | boot_cpu_data.x86_cache_max_rmid = | |
970 | min(boot_cpu_data.x86_cache_max_rmid, | |
971 | c->x86_cache_max_rmid); | |
972 | } | |
973 | } | |
974 | ||
1da177e4 LT |
975 | /* |
976 | * This does the hard work of actually picking apart the CPU stuff... | |
977 | */ | |
148f9bb8 | 978 | static void identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
979 | { |
980 | int i; | |
981 | ||
982 | c->loops_per_jiffy = loops_per_jiffy; | |
983 | c->x86_cache_size = -1; | |
984 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
985 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
986 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
987 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 988 | c->x86_max_cores = 1; |
102bbe3a | 989 | c->x86_coreid_bits = 0; |
11fdd252 | 990 | #ifdef CONFIG_X86_64 |
102bbe3a | 991 | c->x86_clflush_size = 64; |
13c6c532 JB |
992 | c->x86_phys_bits = 36; |
993 | c->x86_virt_bits = 48; | |
102bbe3a YL |
994 | #else |
995 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 996 | c->x86_clflush_size = 32; |
13c6c532 JB |
997 | c->x86_phys_bits = 32; |
998 | c->x86_virt_bits = 32; | |
102bbe3a YL |
999 | #endif |
1000 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
1001 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
1002 | ||
1da177e4 LT |
1003 | generic_identify(c); |
1004 | ||
3898534d | 1005 | if (this_cpu->c_identify) |
1da177e4 LT |
1006 | this_cpu->c_identify(c); |
1007 | ||
6a6256f9 | 1008 | /* Clear/Set all flags overridden by options, after probe */ |
2759c328 YL |
1009 | for (i = 0; i < NCAPINTS; i++) { |
1010 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
1011 | c->x86_capability[i] |= cpu_caps_set[i]; | |
1012 | } | |
1013 | ||
102bbe3a | 1014 | #ifdef CONFIG_X86_64 |
cb8cc442 | 1015 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
1016 | #endif |
1017 | ||
1da177e4 LT |
1018 | /* |
1019 | * Vendor-specific initialization. In this section we | |
1020 | * canonicalize the feature flags, meaning if there are | |
1021 | * features a certain CPU supports which CPUID doesn't | |
1022 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
1023 | * we handle them here. | |
1024 | * | |
1025 | * At the end of this section, c->x86_capability better | |
1026 | * indicate the features this CPU genuinely supports! | |
1027 | */ | |
1028 | if (this_cpu->c_init) | |
1029 | this_cpu->c_init(c); | |
1030 | ||
1031 | /* Disable the PN if appropriate */ | |
1032 | squash_the_stupid_serial_number(c); | |
1033 | ||
b2cc2a07 PA |
1034 | /* Set up SMEP/SMAP */ |
1035 | setup_smep(c); | |
1036 | setup_smap(c); | |
1037 | ||
1da177e4 | 1038 | /* |
0f3fa48a IM |
1039 | * The vendor-specific functions might have changed features. |
1040 | * Now we do "generic changes." | |
1da177e4 LT |
1041 | */ |
1042 | ||
b38b0665 PA |
1043 | /* Filter out anything that depends on CPUID levels we don't have */ |
1044 | filter_cpuid_features(c, true); | |
1045 | ||
1da177e4 | 1046 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 1047 | if (!c->x86_model_id[0]) { |
02dde8b4 | 1048 | const char *p; |
1da177e4 | 1049 | p = table_lookup_model(c); |
34048c9e | 1050 | if (p) |
1da177e4 LT |
1051 | strcpy(c->x86_model_id, p); |
1052 | else | |
1053 | /* Last resort... */ | |
1054 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 1055 | c->x86, c->x86_model); |
1da177e4 LT |
1056 | } |
1057 | ||
102bbe3a YL |
1058 | #ifdef CONFIG_X86_64 |
1059 | detect_ht(c); | |
1060 | #endif | |
1061 | ||
88b094fb | 1062 | init_hypervisor(c); |
49d859d7 | 1063 | x86_init_rdrand(c); |
cbc82b17 | 1064 | x86_init_cache_qos(c); |
06976945 | 1065 | setup_pku(c); |
3e0c3737 YL |
1066 | |
1067 | /* | |
6a6256f9 | 1068 | * Clear/Set all flags overridden by options, need do it |
3e0c3737 YL |
1069 | * before following smp all cpus cap AND. |
1070 | */ | |
1071 | for (i = 0; i < NCAPINTS; i++) { | |
1072 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
1073 | c->x86_capability[i] |= cpu_caps_set[i]; | |
1074 | } | |
1075 | ||
1da177e4 LT |
1076 | /* |
1077 | * On SMP, boot_cpu_data holds the common feature set between | |
1078 | * all CPUs; so make sure that we indicate which features are | |
1079 | * common between the CPUs. The first time this routine gets | |
1080 | * executed, c == &boot_cpu_data. | |
1081 | */ | |
34048c9e | 1082 | if (c != &boot_cpu_data) { |
1da177e4 | 1083 | /* AND the already accumulated flags with these */ |
9d31d35b | 1084 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 | 1085 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
65fc985b BP |
1086 | |
1087 | /* OR, i.e. replicate the bug flags */ | |
1088 | for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) | |
1089 | c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; | |
1da177e4 LT |
1090 | } |
1091 | ||
1092 | /* Init Machine Check Exception if available. */ | |
5e09954a | 1093 | mcheck_cpu_init(c); |
30d432df AK |
1094 | |
1095 | select_idle_routine(c); | |
102bbe3a | 1096 | |
de2d9445 | 1097 | #ifdef CONFIG_NUMA |
102bbe3a YL |
1098 | numa_add_cpu(smp_processor_id()); |
1099 | #endif | |
1f12e32f TG |
1100 | /* The boot/hotplug time assigment got cleared, restore it */ |
1101 | c->logical_proc_id = topology_phys_to_logical_pkg(c->phys_proc_id); | |
a6c4e076 | 1102 | } |
31ab269a | 1103 | |
8b6c0ab1 IM |
1104 | /* |
1105 | * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions | |
1106 | * on 32-bit kernels: | |
1107 | */ | |
cfda7bb9 AL |
1108 | #ifdef CONFIG_X86_32 |
1109 | void enable_sep_cpu(void) | |
1110 | { | |
8b6c0ab1 IM |
1111 | struct tss_struct *tss; |
1112 | int cpu; | |
cfda7bb9 | 1113 | |
b3edfda4 BP |
1114 | if (!boot_cpu_has(X86_FEATURE_SEP)) |
1115 | return; | |
1116 | ||
8b6c0ab1 IM |
1117 | cpu = get_cpu(); |
1118 | tss = &per_cpu(cpu_tss, cpu); | |
1119 | ||
8b6c0ab1 | 1120 | /* |
cf9328cc AL |
1121 | * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- |
1122 | * see the big comment in struct x86_hw_tss's definition. | |
8b6c0ab1 | 1123 | */ |
cfda7bb9 AL |
1124 | |
1125 | tss->x86_tss.ss1 = __KERNEL_CS; | |
8b6c0ab1 IM |
1126 | wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); |
1127 | ||
cf9328cc AL |
1128 | wrmsr(MSR_IA32_SYSENTER_ESP, |
1129 | (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack), | |
1130 | 0); | |
8b6c0ab1 | 1131 | |
4c8cd0c5 | 1132 | wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); |
8b6c0ab1 | 1133 | |
cfda7bb9 AL |
1134 | put_cpu(); |
1135 | } | |
e04d645f GC |
1136 | #endif |
1137 | ||
a6c4e076 JF |
1138 | void __init identify_boot_cpu(void) |
1139 | { | |
1140 | identify_cpu(&boot_cpu_data); | |
02c68a02 | 1141 | init_amd_e400_c1e_mask(); |
102bbe3a | 1142 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1143 | sysenter_setup(); |
6fe940d6 | 1144 | enable_sep_cpu(); |
102bbe3a | 1145 | #endif |
5b556332 | 1146 | cpu_detect_tlb(&boot_cpu_data); |
a6c4e076 | 1147 | } |
3b520b23 | 1148 | |
148f9bb8 | 1149 | void identify_secondary_cpu(struct cpuinfo_x86 *c) |
a6c4e076 JF |
1150 | { |
1151 | BUG_ON(c == &boot_cpu_data); | |
1152 | identify_cpu(c); | |
102bbe3a | 1153 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1154 | enable_sep_cpu(); |
102bbe3a | 1155 | #endif |
a6c4e076 | 1156 | mtrr_ap_init(); |
1da177e4 LT |
1157 | } |
1158 | ||
a0854a46 | 1159 | struct msr_range { |
0f3fa48a IM |
1160 | unsigned min; |
1161 | unsigned max; | |
a0854a46 | 1162 | }; |
1da177e4 | 1163 | |
148f9bb8 | 1164 | static const struct msr_range msr_range_array[] = { |
a0854a46 YL |
1165 | { 0x00000000, 0x00000418}, |
1166 | { 0xc0000000, 0xc000040b}, | |
1167 | { 0xc0010000, 0xc0010142}, | |
1168 | { 0xc0011000, 0xc001103b}, | |
1169 | }; | |
1da177e4 | 1170 | |
148f9bb8 | 1171 | static void __print_cpu_msr(void) |
a0854a46 | 1172 | { |
0f3fa48a | 1173 | unsigned index_min, index_max; |
a0854a46 YL |
1174 | unsigned index; |
1175 | u64 val; | |
1176 | int i; | |
a0854a46 YL |
1177 | |
1178 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
1179 | index_min = msr_range_array[i].min; | |
1180 | index_max = msr_range_array[i].max; | |
0f3fa48a | 1181 | |
a0854a46 | 1182 | for (index = index_min; index < index_max; index++) { |
ecd431d9 | 1183 | if (rdmsrl_safe(index, &val)) |
a0854a46 | 1184 | continue; |
1b74dde7 | 1185 | pr_info(" MSR%08x: %016llx\n", index, val); |
1da177e4 | 1186 | } |
a0854a46 YL |
1187 | } |
1188 | } | |
94605eff | 1189 | |
148f9bb8 | 1190 | static int show_msr; |
0f3fa48a | 1191 | |
a0854a46 YL |
1192 | static __init int setup_show_msr(char *arg) |
1193 | { | |
1194 | int num; | |
3dd9d514 | 1195 | |
a0854a46 | 1196 | get_option(&arg, &num); |
3dd9d514 | 1197 | |
a0854a46 YL |
1198 | if (num > 0) |
1199 | show_msr = num; | |
1200 | return 1; | |
1da177e4 | 1201 | } |
a0854a46 | 1202 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 1203 | |
191679fd AK |
1204 | static __init int setup_noclflush(char *arg) |
1205 | { | |
840d2830 | 1206 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); |
da4aaa7d | 1207 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); |
191679fd AK |
1208 | return 1; |
1209 | } | |
1210 | __setup("noclflush", setup_noclflush); | |
1211 | ||
148f9bb8 | 1212 | void print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 | 1213 | { |
02dde8b4 | 1214 | const char *vendor = NULL; |
1da177e4 | 1215 | |
0f3fa48a | 1216 | if (c->x86_vendor < X86_VENDOR_NUM) { |
1da177e4 | 1217 | vendor = this_cpu->c_vendor; |
0f3fa48a IM |
1218 | } else { |
1219 | if (c->cpuid_level >= 0) | |
1220 | vendor = c->x86_vendor_id; | |
1221 | } | |
1da177e4 | 1222 | |
bd32a8cf | 1223 | if (vendor && !strstr(c->x86_model_id, vendor)) |
1b74dde7 | 1224 | pr_cont("%s ", vendor); |
1da177e4 | 1225 | |
9d31d35b | 1226 | if (c->x86_model_id[0]) |
1b74dde7 | 1227 | pr_cont("%s", c->x86_model_id); |
1da177e4 | 1228 | else |
1b74dde7 | 1229 | pr_cont("%d86", c->x86); |
1da177e4 | 1230 | |
1b74dde7 | 1231 | pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); |
924e101a | 1232 | |
34048c9e | 1233 | if (c->x86_mask || c->cpuid_level >= 0) |
1b74dde7 | 1234 | pr_cont(", stepping: 0x%x)\n", c->x86_mask); |
1da177e4 | 1235 | else |
1b74dde7 | 1236 | pr_cont(")\n"); |
a0854a46 | 1237 | |
0b8b8078 | 1238 | print_cpu_msr(c); |
21c3fcf3 YL |
1239 | } |
1240 | ||
148f9bb8 | 1241 | void print_cpu_msr(struct cpuinfo_x86 *c) |
21c3fcf3 | 1242 | { |
a0854a46 | 1243 | if (c->cpu_index < show_msr) |
21c3fcf3 | 1244 | __print_cpu_msr(); |
1da177e4 LT |
1245 | } |
1246 | ||
ac72e788 AK |
1247 | static __init int setup_disablecpuid(char *arg) |
1248 | { | |
1249 | int bit; | |
0f3fa48a | 1250 | |
ac72e788 AK |
1251 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) |
1252 | setup_clear_cpu_cap(bit); | |
1253 | else | |
1254 | return 0; | |
0f3fa48a | 1255 | |
ac72e788 AK |
1256 | return 1; |
1257 | } | |
1258 | __setup("clearcpuid=", setup_disablecpuid); | |
1259 | ||
d5494d4f | 1260 | #ifdef CONFIG_X86_64 |
9ff80942 | 1261 | struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table }; |
629f4f9d SA |
1262 | struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1, |
1263 | (unsigned long) debug_idt_table }; | |
d5494d4f | 1264 | |
947e76cd | 1265 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
277d5b40 | 1266 | irq_stack_union) __aligned(PAGE_SIZE) __visible; |
0f3fa48a | 1267 | |
bdf977b3 | 1268 | /* |
a7fcf28d AL |
1269 | * The following percpu variables are hot. Align current_task to |
1270 | * cacheline size such that they fall in the same cacheline. | |
bdf977b3 TH |
1271 | */ |
1272 | DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = | |
1273 | &init_task; | |
1274 | EXPORT_PER_CPU_SYMBOL(current_task); | |
d5494d4f | 1275 | |
bdf977b3 TH |
1276 | DEFINE_PER_CPU(char *, irq_stack_ptr) = |
1277 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; | |
1278 | ||
277d5b40 | 1279 | DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; |
d5494d4f | 1280 | |
c2daa3be PZ |
1281 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1282 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
1283 | ||
0f3fa48a IM |
1284 | /* |
1285 | * Special IST stacks which the CPU switches to when it calls | |
1286 | * an IST-marked descriptor entry. Up to 7 stacks (hardware | |
1287 | * limit), all of them are 4K, except the debug stack which | |
1288 | * is 8K. | |
1289 | */ | |
1290 | static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { | |
1291 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
1292 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
1293 | }; | |
1294 | ||
92d65b23 | 1295 | static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks |
3e352aa8 | 1296 | [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); |
d5494d4f | 1297 | |
d5494d4f YL |
1298 | /* May not be marked __init: used by software suspend */ |
1299 | void syscall_init(void) | |
1da177e4 | 1300 | { |
d5494d4f YL |
1301 | /* |
1302 | * LSTAR and STAR live in a bit strange symbiosis. | |
1303 | * They both write to the same internal register. STAR allows to | |
1304 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
1305 | */ | |
31ac34ca | 1306 | wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); |
47edb651 | 1307 | wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); |
d56fe4bf IM |
1308 | |
1309 | #ifdef CONFIG_IA32_EMULATION | |
47edb651 | 1310 | wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); |
a76c7f46 | 1311 | /* |
487d1edb DV |
1312 | * This only works on Intel CPUs. |
1313 | * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. | |
1314 | * This does not cause SYSENTER to jump to the wrong location, because | |
1315 | * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). | |
a76c7f46 DV |
1316 | */ |
1317 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); | |
1318 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); | |
4c8cd0c5 | 1319 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); |
d56fe4bf | 1320 | #else |
47edb651 | 1321 | wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); |
6b51311c | 1322 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); |
d56fe4bf IM |
1323 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); |
1324 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); | |
d5494d4f | 1325 | #endif |
03ae5768 | 1326 | |
d5494d4f YL |
1327 | /* Flags to clear on syscall */ |
1328 | wrmsrl(MSR_SYSCALL_MASK, | |
63bcff2a | 1329 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| |
8c7aa698 | 1330 | X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); |
1da177e4 | 1331 | } |
62111195 | 1332 | |
d5494d4f YL |
1333 | /* |
1334 | * Copies of the original ist values from the tss are only accessed during | |
1335 | * debugging, no special alignment required. | |
1336 | */ | |
1337 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
1338 | ||
228bdaa9 | 1339 | static DEFINE_PER_CPU(unsigned long, debug_stack_addr); |
42181186 | 1340 | DEFINE_PER_CPU(int, debug_stack_usage); |
228bdaa9 SR |
1341 | |
1342 | int is_debug_stack(unsigned long addr) | |
1343 | { | |
89cbc767 CL |
1344 | return __this_cpu_read(debug_stack_usage) || |
1345 | (addr <= __this_cpu_read(debug_stack_addr) && | |
1346 | addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); | |
228bdaa9 | 1347 | } |
0f46efeb | 1348 | NOKPROBE_SYMBOL(is_debug_stack); |
228bdaa9 | 1349 | |
629f4f9d | 1350 | DEFINE_PER_CPU(u32, debug_idt_ctr); |
f8988175 | 1351 | |
228bdaa9 SR |
1352 | void debug_stack_set_zero(void) |
1353 | { | |
629f4f9d SA |
1354 | this_cpu_inc(debug_idt_ctr); |
1355 | load_current_idt(); | |
228bdaa9 | 1356 | } |
0f46efeb | 1357 | NOKPROBE_SYMBOL(debug_stack_set_zero); |
228bdaa9 SR |
1358 | |
1359 | void debug_stack_reset(void) | |
1360 | { | |
629f4f9d | 1361 | if (WARN_ON(!this_cpu_read(debug_idt_ctr))) |
f8988175 | 1362 | return; |
629f4f9d SA |
1363 | if (this_cpu_dec_return(debug_idt_ctr) == 0) |
1364 | load_current_idt(); | |
228bdaa9 | 1365 | } |
0f46efeb | 1366 | NOKPROBE_SYMBOL(debug_stack_reset); |
228bdaa9 | 1367 | |
0f3fa48a | 1368 | #else /* CONFIG_X86_64 */ |
d5494d4f | 1369 | |
bdf977b3 TH |
1370 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; |
1371 | EXPORT_PER_CPU_SYMBOL(current_task); | |
c2daa3be PZ |
1372 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1373 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
bdf977b3 | 1374 | |
a7fcf28d AL |
1375 | /* |
1376 | * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find | |
1377 | * the top of the kernel stack. Use an extra percpu variable to track the | |
1378 | * top of the kernel stack directly. | |
1379 | */ | |
1380 | DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = | |
1381 | (unsigned long)&init_thread_union + THREAD_SIZE; | |
1382 | EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); | |
1383 | ||
60a5317f | 1384 | #ifdef CONFIG_CC_STACKPROTECTOR |
53f82452 | 1385 | DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
60a5317f | 1386 | #endif |
d5494d4f | 1387 | |
0f3fa48a | 1388 | #endif /* CONFIG_X86_64 */ |
c5413fbe | 1389 | |
9766cdbc JSR |
1390 | /* |
1391 | * Clear all 6 debug registers: | |
1392 | */ | |
1393 | static void clear_all_debug_regs(void) | |
1394 | { | |
1395 | int i; | |
1396 | ||
1397 | for (i = 0; i < 8; i++) { | |
1398 | /* Ignore db4, db5 */ | |
1399 | if ((i == 4) || (i == 5)) | |
1400 | continue; | |
1401 | ||
1402 | set_debugreg(0, i); | |
1403 | } | |
1404 | } | |
c5413fbe | 1405 | |
0bb9fef9 JW |
1406 | #ifdef CONFIG_KGDB |
1407 | /* | |
1408 | * Restore debug regs if using kgdbwait and you have a kernel debugger | |
1409 | * connection established. | |
1410 | */ | |
1411 | static void dbg_restore_debug_regs(void) | |
1412 | { | |
1413 | if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) | |
1414 | arch_kgdb_ops.correct_hw_break(); | |
1415 | } | |
1416 | #else /* ! CONFIG_KGDB */ | |
1417 | #define dbg_restore_debug_regs() | |
1418 | #endif /* ! CONFIG_KGDB */ | |
1419 | ||
ce4b1b16 IM |
1420 | static void wait_for_master_cpu(int cpu) |
1421 | { | |
1422 | #ifdef CONFIG_SMP | |
1423 | /* | |
1424 | * wait for ACK from master CPU before continuing | |
1425 | * with AP initialization | |
1426 | */ | |
1427 | WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); | |
1428 | while (!cpumask_test_cpu(cpu, cpu_callout_mask)) | |
1429 | cpu_relax(); | |
1430 | #endif | |
1431 | } | |
1432 | ||
d2cbcc49 RR |
1433 | /* |
1434 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1435 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1436 | * and IDT. We reload them nevertheless, this function acts as a | |
1437 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 1438 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 1439 | */ |
1ba76586 | 1440 | #ifdef CONFIG_X86_64 |
0f3fa48a | 1441 | |
148f9bb8 | 1442 | void cpu_init(void) |
1ba76586 | 1443 | { |
0fe1e009 | 1444 | struct orig_ist *oist; |
1ba76586 | 1445 | struct task_struct *me; |
0f3fa48a IM |
1446 | struct tss_struct *t; |
1447 | unsigned long v; | |
ce4b1b16 | 1448 | int cpu = stack_smp_processor_id(); |
1ba76586 YL |
1449 | int i; |
1450 | ||
ce4b1b16 IM |
1451 | wait_for_master_cpu(cpu); |
1452 | ||
1e02ce4c AL |
1453 | /* |
1454 | * Initialize the CR4 shadow before doing anything that could | |
1455 | * try to read it. | |
1456 | */ | |
1457 | cr4_init_shadow(); | |
1458 | ||
e6ebf5de FY |
1459 | /* |
1460 | * Load microcode on this cpu if a valid microcode is available. | |
1461 | * This is early microcode loading procedure. | |
1462 | */ | |
1463 | load_ucode_ap(); | |
1464 | ||
24933b82 | 1465 | t = &per_cpu(cpu_tss, cpu); |
0fe1e009 | 1466 | oist = &per_cpu(orig_ist, cpu); |
0f3fa48a | 1467 | |
e7a22c1e | 1468 | #ifdef CONFIG_NUMA |
27fd185f | 1469 | if (this_cpu_read(numa_node) == 0 && |
e534c7c5 LS |
1470 | early_cpu_to_node(cpu) != NUMA_NO_NODE) |
1471 | set_numa_node(early_cpu_to_node(cpu)); | |
e7a22c1e | 1472 | #endif |
1ba76586 YL |
1473 | |
1474 | me = current; | |
1475 | ||
2eaad1fd | 1476 | pr_debug("Initializing CPU#%d\n", cpu); |
1ba76586 | 1477 | |
375074cc | 1478 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); |
1ba76586 YL |
1479 | |
1480 | /* | |
1481 | * Initialize the per-CPU GDT with the boot GDT, | |
1482 | * and set up the GDT descriptor: | |
1483 | */ | |
1484 | ||
552be871 | 1485 | switch_to_new_gdt(cpu); |
2697fbd5 BG |
1486 | loadsegment(fs, 0); |
1487 | ||
cf910e83 | 1488 | load_current_idt(); |
1ba76586 YL |
1489 | |
1490 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1491 | syscall_init(); | |
1492 | ||
1493 | wrmsrl(MSR_FS_BASE, 0); | |
1494 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1495 | barrier(); | |
1496 | ||
4763ed4d | 1497 | x86_configure_nx(); |
659006bf | 1498 | x2apic_setup(); |
1ba76586 YL |
1499 | |
1500 | /* | |
1501 | * set up and load the per-CPU TSS | |
1502 | */ | |
0fe1e009 | 1503 | if (!oist->ist[0]) { |
92d65b23 | 1504 | char *estacks = per_cpu(exception_stacks, cpu); |
0f3fa48a | 1505 | |
1ba76586 | 1506 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
0f3fa48a | 1507 | estacks += exception_stack_sizes[v]; |
0fe1e009 | 1508 | oist->ist[v] = t->x86_tss.ist[v] = |
1ba76586 | 1509 | (unsigned long)estacks; |
228bdaa9 SR |
1510 | if (v == DEBUG_STACK-1) |
1511 | per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; | |
1ba76586 YL |
1512 | } |
1513 | } | |
1514 | ||
1515 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
0f3fa48a | 1516 | |
1ba76586 YL |
1517 | /* |
1518 | * <= is required because the CPU will access up to | |
1519 | * 8 bits beyond the end of the IO permission bitmap. | |
1520 | */ | |
1521 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1522 | t->io_bitmap[i] = ~0UL; | |
1523 | ||
1524 | atomic_inc(&init_mm.mm_count); | |
1525 | me->active_mm = &init_mm; | |
8c5dfd25 | 1526 | BUG_ON(me->mm); |
1ba76586 YL |
1527 | enter_lazy_tlb(&init_mm, me); |
1528 | ||
1529 | load_sp0(t, ¤t->thread); | |
1530 | set_tss_desc(cpu, t); | |
1531 | load_TR_desc(); | |
37868fe1 | 1532 | load_mm_ldt(&init_mm); |
1ba76586 | 1533 | |
0bb9fef9 JW |
1534 | clear_all_debug_regs(); |
1535 | dbg_restore_debug_regs(); | |
1ba76586 | 1536 | |
21c4cd10 | 1537 | fpu__init_cpu(); |
1ba76586 | 1538 | |
1ba76586 YL |
1539 | if (is_uv_system()) |
1540 | uv_cpu_init(); | |
1541 | } | |
1542 | ||
1543 | #else | |
1544 | ||
148f9bb8 | 1545 | void cpu_init(void) |
9ee79a3d | 1546 | { |
d2cbcc49 RR |
1547 | int cpu = smp_processor_id(); |
1548 | struct task_struct *curr = current; | |
24933b82 | 1549 | struct tss_struct *t = &per_cpu(cpu_tss, cpu); |
9ee79a3d | 1550 | struct thread_struct *thread = &curr->thread; |
62111195 | 1551 | |
ce4b1b16 | 1552 | wait_for_master_cpu(cpu); |
e6ebf5de | 1553 | |
5b2bdbc8 SR |
1554 | /* |
1555 | * Initialize the CR4 shadow before doing anything that could | |
1556 | * try to read it. | |
1557 | */ | |
1558 | cr4_init_shadow(); | |
1559 | ||
ce4b1b16 | 1560 | show_ucode_info_early(); |
62111195 | 1561 | |
1b74dde7 | 1562 | pr_info("Initializing CPU#%d\n", cpu); |
62111195 | 1563 | |
362f924b | 1564 | if (cpu_feature_enabled(X86_FEATURE_VME) || |
59e21e3d | 1565 | boot_cpu_has(X86_FEATURE_TSC) || |
362f924b | 1566 | boot_cpu_has(X86_FEATURE_DE)) |
375074cc | 1567 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); |
62111195 | 1568 | |
cf910e83 | 1569 | load_current_idt(); |
552be871 | 1570 | switch_to_new_gdt(cpu); |
1da177e4 | 1571 | |
1da177e4 LT |
1572 | /* |
1573 | * Set up and load the per-CPU TSS and LDT | |
1574 | */ | |
1575 | atomic_inc(&init_mm.mm_count); | |
62111195 | 1576 | curr->active_mm = &init_mm; |
8c5dfd25 | 1577 | BUG_ON(curr->mm); |
62111195 | 1578 | enter_lazy_tlb(&init_mm, curr); |
1da177e4 | 1579 | |
faca6227 | 1580 | load_sp0(t, thread); |
34048c9e | 1581 | set_tss_desc(cpu, t); |
1da177e4 | 1582 | load_TR_desc(); |
37868fe1 | 1583 | load_mm_ldt(&init_mm); |
1da177e4 | 1584 | |
f9a196b8 TG |
1585 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); |
1586 | ||
22c4e308 | 1587 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1588 | /* Set up doublefault TSS pointer in the GDT */ |
1589 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1590 | #endif |
1da177e4 | 1591 | |
9766cdbc | 1592 | clear_all_debug_regs(); |
0bb9fef9 | 1593 | dbg_restore_debug_regs(); |
1da177e4 | 1594 | |
21c4cd10 | 1595 | fpu__init_cpu(); |
1da177e4 | 1596 | } |
1ba76586 | 1597 | #endif |
5700f743 | 1598 | |
b51ef52d LA |
1599 | static void bsp_resume(void) |
1600 | { | |
1601 | if (this_cpu->c_bsp_resume) | |
1602 | this_cpu->c_bsp_resume(&boot_cpu_data); | |
1603 | } | |
1604 | ||
1605 | static struct syscore_ops cpu_syscore_ops = { | |
1606 | .resume = bsp_resume, | |
1607 | }; | |
1608 | ||
1609 | static int __init init_cpu_syscore(void) | |
1610 | { | |
1611 | register_syscore_ops(&cpu_syscore_ops); | |
1612 | return 0; | |
1613 | } | |
1614 | core_initcall(init_cpu_syscore); |