[mirror_ubuntu-zesty-kernel.git] / arch / x86 / kernel / cpu / intel.c

#include <linux/init.h>
#include <linux/kernel.h>

#include <linux/string.h>
#include <linux/bitops.h>
#include <linux/smp.h>
#include <linux/thread_info.h>
#include <linux/module.h>

#include <asm/processor.h>
#include <asm/pgtable.h>
#include <asm/msr.h>
#include <asm/uaccess.h>
#include <asm/ds.h>
#include <asm/bugs.h>

#ifdef CONFIG_X86_64
#include <asm/topology.h>
#include <asm/numa_64.h>
#endif

#include "cpu.h"

#ifdef CONFIG_X86_LOCAL_APIC
#include <asm/mpspec.h>
#include <asm/apic.h>
#include <asm/genapic.h>
#endif

static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
{
	/* Unmask CPUID levels if masked: */
	if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
		u64 misc_enable;

		rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);

		if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
			misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
			wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
			c->cpuid_level = cpuid_eax(0);
		}
	}

	if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
		(c->x86 == 0x6 && c->x86_model >= 0x0e))
		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);

#ifdef CONFIG_X86_64
	set_cpu_cap(c, X86_FEATURE_SYSENTER32);
#else
	/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
	if (c->x86 == 15 && c->x86_cache_alignment == 64)
		c->x86_cache_alignment = 128;
#endif

	/*
	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
	 * with P/T states and does not stop in deep C-states
	 */
	if (c->x86_power & (1 << 8)) {
		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
	}

	/*
	 * There is a known erratum on Pentium III and Core Solo
	 * and Core Duo CPUs.
	 * " Page with PAT set to WC while associated MTRR is UC
	 *   may consolidate to UC "
	 * Because of this erratum, it is better to stick with
	 * setting WC in MTRR rather than using PAT on these CPUs.
	 *
	 * Enable PAT WC only on P4, Core 2 or later CPUs.
	 */
	if (c->x86 == 6 && c->x86_model < 15)
		clear_cpu_cap(c, X86_FEATURE_PAT);
}

#ifdef CONFIG_X86_32
/*
 *	Early probe support logic for ppro memory erratum #50
 *
 *	This is called before we do cpu ident work
 */

int __cpuinit ppro_with_ram_bug(void)
{
	/* Uses data from early_cpu_detect now */
	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
	    boot_cpu_data.x86 == 6 &&
	    boot_cpu_data.x86_model == 1 &&
	    boot_cpu_data.x86_mask < 8) {
		printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
		return 1;
	}
	return 0;
}

#ifdef CONFIG_X86_F00F_BUG
static void __cpuinit trap_init_f00f_bug(void)
{
	__set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);

	/*
	 * Update the IDT descriptor and reload the IDT so that
	 * it uses the read-only mapped virtual address.
	 */
	idt_descr.address = fix_to_virt(FIX_F00F_IDT);
	load_idt(&idt_descr);
}
#endif

static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
{
	unsigned long lo, hi;

#ifdef CONFIG_X86_F00F_BUG
	/*
	 * All current models of Pentium and Pentium with MMX technology CPUs
	 * have the F0 0F bug, which lets nonprivileged users lock up the system.
	 * Note that the workaround only should be initialized once...
	 */
	c->f00f_bug = 0;
	if (!paravirt_enabled() && c->x86 == 5) {
		static int f00f_workaround_enabled;

		c->f00f_bug = 1;
		if (!f00f_workaround_enabled) {
			trap_init_f00f_bug();
			printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
			f00f_workaround_enabled = 1;
		}
	}
#endif

	/*
	 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
	 * model 3 mask 3
	 */
	if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
		clear_cpu_cap(c, X86_FEATURE_SEP);

	/*
	 * P4 Xeon errata 037 workaround.
	 * Hardware prefetcher may cause stale data to be loaded into the cache.
	 */
	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
		rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
		if ((lo & (1<<9)) == 0) {
			printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
			printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
			lo |= (1<<9);	/* Disable hw prefetching */
			wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
		}
	}

	/*
	 * See if we have a good local APIC by checking for buggy Pentia,
	 * i.e. all B steppings and the C2 stepping of P54C when using their
	 * integrated APIC (see 11AP erratum in "Pentium Processor
	 * Specification Update").
	 */
	if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
	    (c->x86_mask < 0x6 || c->x86_mask == 0xb))
		set_cpu_cap(c, X86_FEATURE_11AP);


#ifdef CONFIG_X86_INTEL_USERCOPY
	/*
	 * Set up the preferred alignment for movsl bulk memory moves
	 */
	switch (c->x86) {
	case 4:		/* 486: untested */
		break;
	case 5:		/* Old Pentia: untested */
		break;
	case 6:		/* PII/PIII only like movsl with 8-byte alignment */
		movsl_mask.mask = 7;
		break;
	case 15:	/* P4 is OK down to 8-byte alignment */
		movsl_mask.mask = 7;
		break;
	}
#endif

#ifdef CONFIG_X86_NUMAQ
	numaq_tsc_disable();
#endif
}
#else
static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
{
}
#endif

static void __cpuinit srat_detect_node(void)
{
#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
	unsigned node;
	int cpu = smp_processor_id();
	int apicid = hard_smp_processor_id();

	/* Don't do the funky fallback heuristics the AMD version employs
	   for now. */
	node = apicid_to_node[apicid];
	if (node == NUMA_NO_NODE || !node_online(node))
		node = first_node(node_online_map);
	numa_set_node(cpu, node);

	printk(KERN_INFO "CPU %d/0x%x -> Node %d\n", cpu, apicid, node);
#endif
}

/*
 * find out the number of processor cores on the die
 */
static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
{
	unsigned int eax, ebx, ecx, edx;

	if (c->cpuid_level < 4)
		return 1;

	/* Intel has a non-standard dependency on %ecx for this CPUID level. */
	cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
	if (eax & 0x1f)
		return ((eax >> 26) + 1);
	else
		return 1;
}

static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
{
	/* Intel VMX MSR indicated features */
#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW	0x00200000
#define X86_VMX_FEATURE_PROC_CTLS_VNMI		0x00400000
#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS	0x80000000
#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC	0x00000001
#define X86_VMX_FEATURE_PROC_CTLS2_EPT		0x00000002
#define X86_VMX_FEATURE_PROC_CTLS2_VPID		0x00000020

	u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;

	clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
	clear_cpu_cap(c, X86_FEATURE_VNMI);
	clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
	clear_cpu_cap(c, X86_FEATURE_EPT);
	clear_cpu_cap(c, X86_FEATURE_VPID);

	rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
	msr_ctl = vmx_msr_high | vmx_msr_low;
	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
		set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
		set_cpu_cap(c, X86_FEATURE_VNMI);
	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
		rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
		      vmx_msr_low, vmx_msr_high);
		msr_ctl2 = vmx_msr_high | vmx_msr_low;
		if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
		    (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
			set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
		if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
			set_cpu_cap(c, X86_FEATURE_EPT);
		if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
			set_cpu_cap(c, X86_FEATURE_VPID);
	}
}

static void __cpuinit init_intel(struct cpuinfo_x86 *c)
{
	unsigned int l2 = 0;

	early_init_intel(c);

	intel_workarounds(c);

	/*
	 * Detect the extended topology information if available. This
	 * will reinitialise the initial_apicid which will be used
	 * in init_intel_cacheinfo()
	 */
	detect_extended_topology(c);

	l2 = init_intel_cacheinfo(c);
	if (c->cpuid_level > 9) {
		unsigned eax = cpuid_eax(10);
		/* Check for version and the number of counters */
		if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
			set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
	}

	if (cpu_has_xmm2)
		set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
	if (cpu_has_ds) {
		unsigned int l1;
		rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
		if (!(l1 & (1<<11)))
			set_cpu_cap(c, X86_FEATURE_BTS);
		if (!(l1 & (1<<12)))
			set_cpu_cap(c, X86_FEATURE_PEBS);
		ds_init_intel(c);
	}

	if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush)
		set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);

#ifdef CONFIG_X86_64
	if (c->x86 == 15)
		c->x86_cache_alignment = c->x86_clflush_size * 2;
	if (c->x86 == 6)
		set_cpu_cap(c, X86_FEATURE_REP_GOOD);
#else
	/*
	 * Names for the Pentium II/Celeron processors
	 * detectable only by also checking the cache size.
	 * Dixon is NOT a Celeron.
	 */
	if (c->x86 == 6) {
		char *p = NULL;

		switch (c->x86_model) {
		case 5:
			if (c->x86_mask == 0) {
				if (l2 == 0)
					p = "Celeron (Covington)";
				else if (l2 == 256)
					p = "Mobile Pentium II (Dixon)";
			}
			break;

		case 6:
			if (l2 == 128)
				p = "Celeron (Mendocino)";
			else if (c->x86_mask == 0 || c->x86_mask == 5)
				p = "Celeron-A";
			break;

		case 8:
			if (l2 == 128)
				p = "Celeron (Coppermine)";
			break;
		}

		if (p)
			strcpy(c->x86_model_id, p);
	}

	if (c->x86 == 15)
		set_cpu_cap(c, X86_FEATURE_P4);
	if (c->x86 == 6)
		set_cpu_cap(c, X86_FEATURE_P3);
#endif

	if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
		/*
		 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
		 * detection.
		 */
		c->x86_max_cores = intel_num_cpu_cores(c);
#ifdef CONFIG_X86_32
		detect_ht(c);
#endif
	}

	/* Work around errata */
	srat_detect_node();

	if (cpu_has(c, X86_FEATURE_VMX))
		detect_vmx_virtcap(c);
}

#ifdef CONFIG_X86_32
static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
{
	/*
	 * Intel PIII Tualatin. This comes in two flavours.
	 * One has 256kb of cache, the other 512. We have no way
	 * to determine which, so we use a boottime override
	 * for the 512kb model, and assume 256 otherwise.
	 */
	if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
		size = 256;
	return size;
}
#endif

static struct cpu_dev intel_cpu_dev __cpuinitdata = {
	.c_vendor	= "Intel",
	.c_ident	= { "GenuineIntel" },
#ifdef CONFIG_X86_32
	.c_models = {
		{ .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
		  {
			  [0] = "486 DX-25/33",
			  [1] = "486 DX-50",
			  [2] = "486 SX",
			  [3] = "486 DX/2",
			  [4] = "486 SL",
			  [5] = "486 SX/2",
			  [7] = "486 DX/2-WB",
			  [8] = "486 DX/4",
			  [9] = "486 DX/4-WB"
		  }
		},
		{ .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
		  {
			  [0] = "Pentium 60/66 A-step",
			  [1] = "Pentium 60/66",
			  [2] = "Pentium 75 - 200",
			  [3] = "OverDrive PODP5V83",
			  [4] = "Pentium MMX",
			  [7] = "Mobile Pentium 75 - 200",
			  [8] = "Mobile Pentium MMX"
		  }
		},
		{ .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
		  {
			  [0] = "Pentium Pro A-step",
			  [1] = "Pentium Pro",
			  [3] = "Pentium II (Klamath)",
			  [4] = "Pentium II (Deschutes)",
			  [5] = "Pentium II (Deschutes)",
			  [6] = "Mobile Pentium II",
			  [7] = "Pentium III (Katmai)",
			  [8] = "Pentium III (Coppermine)",
			  [10] = "Pentium III (Cascades)",
			  [11] = "Pentium III (Tualatin)",
		  }
		},
		{ .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
		  {
			  [0] = "Pentium 4 (Unknown)",
			  [1] = "Pentium 4 (Willamette)",
			  [2] = "Pentium 4 (Northwood)",
			  [4] = "Pentium 4 (Foster)",
			  [5] = "Pentium 4 (Foster)",
		  }
		},
	},
	.c_size_cache	= intel_size_cache,
#endif
	.c_early_init   = early_init_intel,
	.c_init		= init_intel,
	.c_x86_vendor	= X86_VENDOR_INTEL,
};

cpu_dev_register(intel_cpu_dev);
Commit	Line	Data
1da177e4 LT	1	#include <linux/init.h>
	2	#include <linux/kernel.h>
	3
	4	#include <linux/string.h>
	5	#include <linux/bitops.h>
	6	#include <linux/smp.h>
	7	#include <linux/thread_info.h>
53e86b91	8	#include <linux/module.h>
1da177e4 LT	9
1da177e4 LT	10	#include <asm/processor.h>
d72b1b4f	11	#include <asm/pgtable.h>
1da177e4 LT	12	#include <asm/msr.h>
1da177e4 LT	13	#include <asm/uaccess.h>
eee3af4a	14	#include <asm/ds.h>
73bdb73f	15	#include <asm/bugs.h>
1da177e4	16
185f3b9d YL	17	#ifdef CONFIG_X86_64
	18	#include <asm/topology.h>
	19	#include <asm/numa_64.h>
	20	#endif
	21
1da177e4 LT	22	#include "cpu.h"
	23
	24	#ifdef CONFIG_X86_LOCAL_APIC
	25	#include <asm/mpspec.h>
	26	#include <asm/apic.h>
1dcdd3d1	27	#include <asm/genapic.h>
1da177e4 LT	28	#endif
1da177e4 LT	29
03ae5768	30	static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
1da177e4	31	{
99fb4d34	32	/* Unmask CPUID levels if masked: */
30a0fb94	33	if (c->x86 > 6 \|\| (c->x86 == 6 && c->x86_model >= 0xd)) {
99fb4d34	34	u64 misc_enable;
066941bd	35
99fb4d34 IM	36	rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
	37
	38	if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
	39	misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
	40	wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
	41	c->cpuid_level = cpuid_eax(0);
	42	}
066941bd PA	43	}
066941bd PA	44
2b16a235 AK	45	if ((c->x86 == 0xf && c->x86_model >= 0x03) \|\|
	46	(c->x86 == 0x6 && c->x86_model >= 0x0e))
	47	set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
185f3b9d YL	48
	49	#ifdef CONFIG_X86_64
	50	set_cpu_cap(c, X86_FEATURE_SYSENTER32);
	51	#else
	52	/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
	53	if (c->x86 == 15 && c->x86_cache_alignment == 64)
	54	c->x86_cache_alignment = 128;
	55	#endif
40fb1715 VP	56
	57	/*
	58	* c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
	59	* with P/T states and does not stop in deep C-states
	60	*/
	61	if (c->x86_power & (1 << 8)) {
	62	set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
	63	set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
	64	}
	65
75a04811 PA	66	/*
	67	* There is a known erratum on Pentium III and Core Solo
	68	* and Core Duo CPUs.
	69	* " Page with PAT set to WC while associated MTRR is UC
	70	* may consolidate to UC "
	71	* Because of this erratum, it is better to stick with
	72	* setting WC in MTRR rather than using PAT on these CPUs.
	73	*
	74	* Enable PAT WC only on P4, Core 2 or later CPUs.
	75	*/
	76	if (c->x86 == 6 && c->x86_model < 15)
	77	clear_cpu_cap(c, X86_FEATURE_PAT);
1da177e4 LT	78	}
1da177e4 LT	79
185f3b9d	80	#ifdef CONFIG_X86_32
1da177e4 LT	81	/*
	82	* Early probe support logic for ppro memory erratum #50
	83	*
	84	* This is called before we do cpu ident work
	85	*/
65eb6b43	86
3bc9b76b	87	int __cpuinit ppro_with_ram_bug(void)
1da177e4 LT	88	{
	89	/* Uses data from early_cpu_detect now */
	90	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
	91	boot_cpu_data.x86 == 6 &&
	92	boot_cpu_data.x86_model == 1 &&
	93	boot_cpu_data.x86_mask < 8) {
	94	printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
	95	return 1;
	96	}
	97	return 0;
	98	}
65eb6b43	99
4052704d YL	100	#ifdef CONFIG_X86_F00F_BUG
	101	static void __cpuinit trap_init_f00f_bug(void)
	102	{
	103	__set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
1da177e4	104
4052704d YL	105	/*
	106	* Update the IDT descriptor and reload the IDT so that
	107	* it uses the read-only mapped virtual address.
	108	*/
	109	idt_descr.address = fix_to_virt(FIX_F00F_IDT);
	110	load_idt(&idt_descr);
	111	}
	112	#endif
	113
	114	static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
1da177e4 LT	115	{
	116	unsigned long lo, hi;
	117
4052704d YL	118	#ifdef CONFIG_X86_F00F_BUG
	119	/*
	120	* All current models of Pentium and Pentium with MMX technology CPUs
	121	* have the F0 0F bug, which lets nonprivileged users lock up the system.
	122	* Note that the workaround only should be initialized once...
	123	*/
	124	c->f00f_bug = 0;
	125	if (!paravirt_enabled() && c->x86 == 5) {
	126	static int f00f_workaround_enabled;
	127
	128	c->f00f_bug = 1;
	129	if (!f00f_workaround_enabled) {
	130	trap_init_f00f_bug();
	131	printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
	132	f00f_workaround_enabled = 1;
	133	}
	134	}
	135	#endif
	136
	137	/*
	138	* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
	139	* model 3 mask 3
	140	*/
	141	if ((c->x86<<8 \| c->x86_model<<4 \| c->x86_mask) < 0x633)
	142	clear_cpu_cap(c, X86_FEATURE_SEP);
	143
	144	/*
	145	* P4 Xeon errata 037 workaround.
	146	* Hardware prefetcher may cause stale data to be loaded into the cache.
	147	*/
1da177e4	148	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
65eb6b43	149	rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
1da177e4 LT	150	if ((lo & (1<<9)) == 0) {
	151	printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
	152	printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
	153	lo \|= (1<<9); /* Disable hw prefetching */
	154	wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
	155	}
	156	}
1da177e4	157
4052704d YL	158	/*
	159	* See if we have a good local APIC by checking for buggy Pentia,
	160	* i.e. all B steppings and the C2 stepping of P54C when using their
	161	* integrated APIC (see 11AP erratum in "Pentium Processor
	162	* Specification Update").
	163	*/
	164	if (cpu_has_apic && (c->x86<<8 \| c->x86_model<<4) == 0x520 &&
	165	(c->x86_mask < 0x6 \|\| c->x86_mask == 0xb))
	166	set_cpu_cap(c, X86_FEATURE_11AP);
185f3b9d	167
185f3b9d	168
4052704d	169	#ifdef CONFIG_X86_INTEL_USERCOPY
185f3b9d	170	/*
4052704d	171	* Set up the preferred alignment for movsl bulk memory moves
185f3b9d	172	*/
4052704d YL	173	switch (c->x86) {
	174	case 4: /* 486: untested */
	175	break;
	176	case 5: /* Old Pentia: untested */
	177	break;
	178	case 6: /* PII/PIII only like movsl with 8-byte alignment */
	179	movsl_mask.mask = 7;
	180	break;
	181	case 15: /* P4 is OK down to 8-byte alignment */
	182	movsl_mask.mask = 7;
	183	break;
	184	}
185f3b9d	185	#endif
4052704d YL	186
	187	#ifdef CONFIG_X86_NUMAQ
	188	numaq_tsc_disable();
	189	#endif
	190	}
	191	#else
	192	static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
	193	{
	194	}
185f3b9d YL	195	#endif
	196
	197	static void __cpuinit srat_detect_node(void)
	198	{
	199	#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
	200	unsigned node;
	201	int cpu = smp_processor_id();
	202	int apicid = hard_smp_processor_id();
	203
	204	/* Don't do the funky fallback heuristics the AMD version employs
	205	for now. */
	206	node = apicid_to_node[apicid];
	207	if (node == NUMA_NO_NODE \|\| !node_online(node))
	208	node = first_node(node_online_map);
	209	numa_set_node(cpu, node);
	210
823b259b	211	printk(KERN_INFO "CPU %d/0x%x -> Node %d\n", cpu, apicid, node);
185f3b9d YL	212	#endif
	213	}
	214
3dd9d514 AK	215	/*
	216	* find out the number of processor cores on the die
	217	*/
f69feff7	218	static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
3dd9d514	219	{
f2ab4461	220	unsigned int eax, ebx, ecx, edx;
3dd9d514 AK	221
	222	if (c->cpuid_level < 4)
	223	return 1;
	224
f2ab4461 ZA	225	/* Intel has a non-standard dependency on %ecx for this CPUID level. */
f2ab4461 ZA	226	cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
3dd9d514 AK	227	if (eax & 0x1f)
	228	return ((eax >> 26) + 1);
	229	else
	230	return 1;
	231	}
	232
e38e05a8 SY	233	static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
	234	{
	235	/* Intel VMX MSR indicated features */
	236	#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
	237	#define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
	238	#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
	239	#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
	240	#define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
	241	#define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
	242
	243	u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
	244
	245	clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
	246	clear_cpu_cap(c, X86_FEATURE_VNMI);
	247	clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
	248	clear_cpu_cap(c, X86_FEATURE_EPT);
	249	clear_cpu_cap(c, X86_FEATURE_VPID);
	250
	251	rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
	252	msr_ctl = vmx_msr_high \| vmx_msr_low;
	253	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
	254	set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
	255	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
	256	set_cpu_cap(c, X86_FEATURE_VNMI);
	257	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
	258	rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
	259	vmx_msr_low, vmx_msr_high);
	260	msr_ctl2 = vmx_msr_high \| vmx_msr_low;
	261	if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
	262	(msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
	263	set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
	264	if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
	265	set_cpu_cap(c, X86_FEATURE_EPT);
	266	if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
	267	set_cpu_cap(c, X86_FEATURE_VPID);
	268	}
	269	}
	270
3bc9b76b	271	static void __cpuinit init_intel(struct cpuinfo_x86 *c)
1da177e4 LT	272	{
1da177e4 LT	273	unsigned int l2 = 0;
1da177e4	274
2b16a235 AK	275	early_init_intel(c);
2b16a235 AK	276
4052704d	277	intel_workarounds(c);
1da177e4	278
345077cd SS	279	/*
	280	* Detect the extended topology information if available. This
	281	* will reinitialise the initial_apicid which will be used
	282	* in init_intel_cacheinfo()
	283	*/
	284	detect_extended_topology(c);
	285
1da177e4	286	l2 = init_intel_cacheinfo(c);
65eb6b43	287	if (c->cpuid_level > 9) {
0080e667 VP	288	unsigned eax = cpuid_eax(10);
	289	/* Check for version and the number of counters */
	290	if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
d0e95ebd	291	set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
0080e667	292	}
1da177e4	293
4052704d YL	294	if (cpu_has_xmm2)
	295	set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
	296	if (cpu_has_ds) {
	297	unsigned int l1;
	298	rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
	299	if (!(l1 & (1<<11)))
	300	set_cpu_cap(c, X86_FEATURE_BTS);
	301	if (!(l1 & (1<<12)))
	302	set_cpu_cap(c, X86_FEATURE_PEBS);
	303	ds_init_intel(c);
	304	}
1da177e4	305
e736ad54 PV	306	if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush)
	307	set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);
	308
4052704d YL	309	#ifdef CONFIG_X86_64
	310	if (c->x86 == 15)
	311	c->x86_cache_alignment = c->x86_clflush_size * 2;
	312	if (c->x86 == 6)
	313	set_cpu_cap(c, X86_FEATURE_REP_GOOD);
	314	#else
65eb6b43 PC	315	/*
	316	* Names for the Pentium II/Celeron processors
	317	* detectable only by also checking the cache size.
	318	* Dixon is NOT a Celeron.
	319	*/
1da177e4	320	if (c->x86 == 6) {
4052704d YL	321	char *p = NULL;
4052704d YL	322
1da177e4 LT	323	switch (c->x86_model) {
	324	case 5:
	325	if (c->x86_mask == 0) {
	326	if (l2 == 0)
	327	p = "Celeron (Covington)";
	328	else if (l2 == 256)
	329	p = "Mobile Pentium II (Dixon)";
	330	}
	331	break;
65eb6b43	332
1da177e4 LT	333	case 6:
	334	if (l2 == 128)
	335	p = "Celeron (Mendocino)";
	336	else if (c->x86_mask == 0 \|\| c->x86_mask == 5)
	337	p = "Celeron-A";
	338	break;
65eb6b43	339
1da177e4 LT	340	case 8:
	341	if (l2 == 128)
	342	p = "Celeron (Coppermine)";
	343	break;
	344	}
1da177e4	345
4052704d YL	346	if (p)
4052704d YL	347	strcpy(c->x86_model_id, p);
1da177e4	348	}
1da177e4	349
185f3b9d YL	350	if (c->x86 == 15)
	351	set_cpu_cap(c, X86_FEATURE_P4);
	352	if (c->x86 == 6)
	353	set_cpu_cap(c, X86_FEATURE_P3);
f4166c54	354	#endif
185f3b9d	355
185f3b9d YL	356	if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
	357	/*
	358	* let's use the legacy cpuid vector 0x1 and 0x4 for topology
	359	* detection.
	360	*/
	361	c->x86_max_cores = intel_num_cpu_cores(c);
	362	#ifdef CONFIG_X86_32
	363	detect_ht(c);
	364	#endif
	365	}
	366
	367	/* Work around errata */
	368	srat_detect_node();
e38e05a8 SY	369
	370	if (cpu_has(c, X86_FEATURE_VMX))
	371	detect_vmx_virtcap(c);
42ed458a	372	}
1da177e4	373
185f3b9d	374	#ifdef CONFIG_X86_32
65eb6b43	375	static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
1da177e4	376	{
65eb6b43 PC	377	/*
65eb6b43 PC	378	* Intel PIII Tualatin. This comes in two flavours.
1da177e4 LT	379	* One has 256kb of cache, the other 512. We have no way
	380	* to determine which, so we use a boottime override
	381	* for the 512kb model, and assume 256 otherwise.
	382	*/
	383	if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
	384	size = 256;
	385	return size;
	386	}
185f3b9d	387	#endif
1da177e4	388
3bc9b76b	389	static struct cpu_dev intel_cpu_dev __cpuinitdata = {
1da177e4	390	.c_vendor = "Intel",
65eb6b43	391	.c_ident = { "GenuineIntel" },
185f3b9d	392	#ifdef CONFIG_X86_32
1da177e4	393	.c_models = {
65eb6b43 PC	394	{ .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
	395	{
	396	[0] = "486 DX-25/33",
	397	[1] = "486 DX-50",
	398	[2] = "486 SX",
	399	[3] = "486 DX/2",
	400	[4] = "486 SL",
	401	[5] = "486 SX/2",
	402	[7] = "486 DX/2-WB",
	403	[8] = "486 DX/4",
1da177e4 LT	404	[9] = "486 DX/4-WB"
	405	}
	406	},
	407	{ .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
65eb6b43 PC	408	{
	409	[0] = "Pentium 60/66 A-step",
	410	[1] = "Pentium 60/66",
1da177e4	411	[2] = "Pentium 75 - 200",
65eb6b43	412	[3] = "OverDrive PODP5V83",
1da177e4	413	[4] = "Pentium MMX",
65eb6b43	414	[7] = "Mobile Pentium 75 - 200",
1da177e4 LT	415	[8] = "Mobile Pentium MMX"
	416	}
	417	},
	418	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
65eb6b43	419	{
1da177e4	420	[0] = "Pentium Pro A-step",
65eb6b43 PC	421	[1] = "Pentium Pro",
	422	[3] = "Pentium II (Klamath)",
	423	[4] = "Pentium II (Deschutes)",
	424	[5] = "Pentium II (Deschutes)",
1da177e4	425	[6] = "Mobile Pentium II",
65eb6b43 PC	426	[7] = "Pentium III (Katmai)",
65eb6b43 PC	427	[8] = "Pentium III (Coppermine)",
1da177e4 LT	428	[10] = "Pentium III (Cascades)",
	429	[11] = "Pentium III (Tualatin)",
	430	}
	431	},
	432	{ .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
	433	{
	434	[0] = "Pentium 4 (Unknown)",
	435	[1] = "Pentium 4 (Willamette)",
	436	[2] = "Pentium 4 (Northwood)",
	437	[4] = "Pentium 4 (Foster)",
	438	[5] = "Pentium 4 (Foster)",
	439	}
	440	},
	441	},
185f3b9d YL	442	.c_size_cache = intel_size_cache,
185f3b9d YL	443	#endif
03ae5768	444	.c_early_init = early_init_intel,
1da177e4	445	.c_init = init_intel,
10a434fc	446	.c_x86_vendor = X86_VENDOR_INTEL,
1da177e4 LT	447	};
1da177e4 LT	448
10a434fc	449	cpu_dev_register(intel_cpu_dev);
1da177e4	450