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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
c767a54b JP |
10 | |
11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
12 | ||
e9eee03e IM |
13 | #include <linux/thread_info.h> |
14 | #include <linux/capability.h> | |
15 | #include <linux/miscdevice.h> | |
16 | #include <linux/ratelimit.h> | |
17 | #include <linux/kallsyms.h> | |
18 | #include <linux/rcupdate.h> | |
e9eee03e | 19 | #include <linux/kobject.h> |
14a02530 | 20 | #include <linux/uaccess.h> |
e9eee03e IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/kernel.h> | |
23 | #include <linux/percpu.h> | |
1da177e4 | 24 | #include <linux/string.h> |
8a25a2fd | 25 | #include <linux/device.h> |
f3c6ea1b | 26 | #include <linux/syscore_ops.h> |
3c079792 | 27 | #include <linux/delay.h> |
8c566ef5 | 28 | #include <linux/ctype.h> |
e9eee03e | 29 | #include <linux/sched.h> |
0d7482e3 | 30 | #include <linux/sysfs.h> |
e9eee03e | 31 | #include <linux/types.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
e9eee03e IM |
33 | #include <linux/init.h> |
34 | #include <linux/kmod.h> | |
35 | #include <linux/poll.h> | |
3c079792 | 36 | #include <linux/nmi.h> |
e9eee03e | 37 | #include <linux/cpu.h> |
011d8261 | 38 | #include <linux/ras.h> |
14a02530 | 39 | #include <linux/smp.h> |
e9eee03e | 40 | #include <linux/fs.h> |
9b1beaf2 | 41 | #include <linux/mm.h> |
5be9ed25 | 42 | #include <linux/debugfs.h> |
b77e70bf | 43 | #include <linux/irq_work.h> |
69c60c88 | 44 | #include <linux/export.h> |
3637efb0 | 45 | #include <linux/jump_label.h> |
e9eee03e | 46 | |
3f5a7896 | 47 | #include <asm/intel-family.h> |
d88203d1 | 48 | #include <asm/processor.h> |
95927475 | 49 | #include <asm/traps.h> |
375074cc | 50 | #include <asm/tlbflush.h> |
e9eee03e IM |
51 | #include <asm/mce.h> |
52 | #include <asm/msr.h> | |
5bc32950 | 53 | #include <asm/reboot.h> |
1da177e4 | 54 | |
bd19a5e6 | 55 | #include "mce-internal.h" |
711c2e48 | 56 | |
5de97c9f | 57 | static DEFINE_MUTEX(mce_log_mutex); |
f56e8a07 | 58 | |
8968f9d3 HS |
59 | #define CREATE_TRACE_POINTS |
60 | #include <trace/events/mce.h> | |
61 | ||
3f2f0680 | 62 | #define SPINUNIT 100 /* 100ns */ |
3c079792 | 63 | |
01ca79f1 AK |
64 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
65 | ||
1462594b | 66 | struct mce_bank *mce_banks __read_mostly; |
bf80bbd7 | 67 | struct mce_vendor_flags mce_flags __read_mostly; |
cebe1820 | 68 | |
d203f0b8 | 69 | struct mca_config mca_cfg __read_mostly = { |
84c2559d | 70 | .bootlog = -1, |
d203f0b8 BP |
71 | /* |
72 | * Tolerant levels: | |
73 | * 0: always panic on uncorrected errors, log corrected errors | |
74 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
75 | * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors | |
76 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
77 | */ | |
84c2559d BP |
78 | .tolerant = 1, |
79 | .monarch_timeout = -1 | |
d203f0b8 BP |
80 | }; |
81 | ||
3c079792 | 82 | static DEFINE_PER_CPU(struct mce, mces_seen); |
5de97c9f TL |
83 | static unsigned long mce_need_notify; |
84 | static int cpu_missing; | |
3c079792 | 85 | |
0644414e NR |
86 | /* |
87 | * MCA banks polled by the period polling timer for corrected events. | |
88 | * With Intel CMCI, this only has MCA banks which do not support CMCI (if any). | |
89 | */ | |
ee031c31 AK |
90 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { |
91 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
92 | }; | |
93 | ||
c3d1fb56 NR |
94 | /* |
95 | * MCA banks controlled through firmware first for corrected errors. | |
96 | * This is a global list of banks for which we won't enable CMCI and we | |
97 | * won't poll. Firmware controls these banks and is responsible for | |
98 | * reporting corrected errors through GHES. Uncorrected/recoverable | |
99 | * errors are still notified through a machine check. | |
100 | */ | |
101 | mce_banks_t mce_banks_ce_disabled; | |
102 | ||
061120ae CG |
103 | static struct work_struct mce_work; |
104 | static struct irq_work mce_irq_work; | |
9b1beaf2 | 105 | |
61b0fccd TL |
106 | static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs); |
107 | ||
3653ada5 BP |
108 | /* |
109 | * CPU/chipset specific EDAC code can register a notifier call here to print | |
110 | * MCE errors in a human-readable form. | |
111 | */ | |
0dc9c639 | 112 | BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain); |
3653ada5 | 113 | |
b5f2fa4e AK |
114 | /* Do initial initialization of a struct mce */ |
115 | void mce_setup(struct mce *m) | |
116 | { | |
117 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 118 | m->cpu = m->extcpu = smp_processor_id(); |
8ee08347 AK |
119 | /* We hope get_seconds stays lockless */ |
120 | m->time = get_seconds(); | |
121 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
122 | m->cpuid = cpuid_eax(1); | |
8ee08347 | 123 | m->socketid = cpu_data(m->extcpu).phys_proc_id; |
8ee08347 AK |
124 | m->apicid = cpu_data(m->extcpu).initial_apicid; |
125 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
3f5a7896 TL |
126 | |
127 | if (this_cpu_has(X86_FEATURE_INTEL_PPIN)) | |
128 | rdmsrl(MSR_PPIN, m->ppin); | |
b5f2fa4e AK |
129 | } |
130 | ||
ea149b36 AK |
131 | DEFINE_PER_CPU(struct mce, injectm); |
132 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
133 | ||
fe3ed20f | 134 | void mce_log(struct mce *m) |
1da177e4 | 135 | { |
fe3ed20f | 136 | if (!mce_gen_pool_add(m)) |
f29a7aff | 137 | irq_work_queue(&mce_irq_work); |
1da177e4 LT |
138 | } |
139 | ||
a79da384 | 140 | void mce_inject_log(struct mce *m) |
09371957 | 141 | { |
5de97c9f | 142 | mutex_lock(&mce_log_mutex); |
a79da384 | 143 | mce_log(m); |
5de97c9f | 144 | mutex_unlock(&mce_log_mutex); |
09371957 | 145 | } |
a79da384 | 146 | EXPORT_SYMBOL_GPL(mce_inject_log); |
09371957 | 147 | |
fd4cf79f | 148 | static struct notifier_block mce_srao_nb; |
09371957 | 149 | |
011d8261 BP |
150 | /* |
151 | * We run the default notifier if we have only the SRAO, the first and the | |
152 | * default notifier registered. I.e., the mandatory NUM_DEFAULT_NOTIFIERS | |
153 | * notifiers registered on the chain. | |
154 | */ | |
155 | #define NUM_DEFAULT_NOTIFIERS 3 | |
cd9c57ca BP |
156 | static atomic_t num_notifiers; |
157 | ||
3653ada5 BP |
158 | void mce_register_decode_chain(struct notifier_block *nb) |
159 | { | |
415601b1 | 160 | if (WARN_ON(nb->priority > MCE_PRIO_MCELOG && nb->priority < MCE_PRIO_EDAC)) |
32b40a82 | 161 | return; |
cd9c57ca | 162 | |
32b40a82 | 163 | atomic_inc(&num_notifiers); |
fd4cf79f | 164 | |
0dc9c639 | 165 | blocking_notifier_chain_register(&x86_mce_decoder_chain, nb); |
3653ada5 BP |
166 | } |
167 | EXPORT_SYMBOL_GPL(mce_register_decode_chain); | |
168 | ||
169 | void mce_unregister_decode_chain(struct notifier_block *nb) | |
170 | { | |
cd9c57ca BP |
171 | atomic_dec(&num_notifiers); |
172 | ||
0dc9c639 | 173 | blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb); |
3653ada5 BP |
174 | } |
175 | EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); | |
176 | ||
a9750a31 YG |
177 | static inline u32 ctl_reg(int bank) |
178 | { | |
179 | return MSR_IA32_MCx_CTL(bank); | |
180 | } | |
181 | ||
182 | static inline u32 status_reg(int bank) | |
183 | { | |
184 | return MSR_IA32_MCx_STATUS(bank); | |
185 | } | |
186 | ||
187 | static inline u32 addr_reg(int bank) | |
188 | { | |
189 | return MSR_IA32_MCx_ADDR(bank); | |
190 | } | |
191 | ||
192 | static inline u32 misc_reg(int bank) | |
193 | { | |
194 | return MSR_IA32_MCx_MISC(bank); | |
195 | } | |
196 | ||
197 | static inline u32 smca_ctl_reg(int bank) | |
198 | { | |
199 | return MSR_AMD64_SMCA_MCx_CTL(bank); | |
200 | } | |
201 | ||
202 | static inline u32 smca_status_reg(int bank) | |
203 | { | |
204 | return MSR_AMD64_SMCA_MCx_STATUS(bank); | |
205 | } | |
206 | ||
207 | static inline u32 smca_addr_reg(int bank) | |
208 | { | |
209 | return MSR_AMD64_SMCA_MCx_ADDR(bank); | |
210 | } | |
211 | ||
212 | static inline u32 smca_misc_reg(int bank) | |
213 | { | |
214 | return MSR_AMD64_SMCA_MCx_MISC(bank); | |
215 | } | |
216 | ||
217 | struct mca_msr_regs msr_ops = { | |
218 | .ctl = ctl_reg, | |
219 | .status = status_reg, | |
220 | .addr = addr_reg, | |
221 | .misc = misc_reg | |
222 | }; | |
223 | ||
cd9c57ca | 224 | static void __print_mce(struct mce *m) |
1da177e4 | 225 | { |
cd9c57ca BP |
226 | pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n", |
227 | m->extcpu, | |
228 | (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""), | |
229 | m->mcgstatus, m->bank, m->status); | |
f436f8bb | 230 | |
65ea5b03 | 231 | if (m->ip) { |
a2d7b0d4 | 232 | pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", |
f436f8bb | 233 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
cd9c57ca | 234 | m->cs, m->ip); |
f436f8bb | 235 | |
1da177e4 | 236 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 237 | print_symbol("{%s}", m->ip); |
f436f8bb | 238 | pr_cont("\n"); |
1da177e4 | 239 | } |
f436f8bb | 240 | |
a2d7b0d4 | 241 | pr_emerg(HW_ERR "TSC %llx ", m->tsc); |
1da177e4 | 242 | if (m->addr) |
f436f8bb | 243 | pr_cont("ADDR %llx ", m->addr); |
1da177e4 | 244 | if (m->misc) |
f436f8bb | 245 | pr_cont("MISC %llx ", m->misc); |
549d042d | 246 | |
4b711f92 YG |
247 | if (mce_flags.smca) { |
248 | if (m->synd) | |
249 | pr_cont("SYND %llx ", m->synd); | |
250 | if (m->ipid) | |
251 | pr_cont("IPID %llx ", m->ipid); | |
252 | } | |
253 | ||
f436f8bb | 254 | pr_cont("\n"); |
506ed6b5 AK |
255 | /* |
256 | * Note this output is parsed by external tools and old fields | |
257 | * should not be changed. | |
258 | */ | |
881e23e5 | 259 | pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", |
506ed6b5 AK |
260 | m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, |
261 | cpu_data(m->extcpu).microcode); | |
cd9c57ca BP |
262 | } |
263 | ||
264 | static void print_mce(struct mce *m) | |
265 | { | |
cd9c57ca | 266 | __print_mce(m); |
dffa4b2f | 267 | pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); |
86503560 AK |
268 | } |
269 | ||
f94b61c2 AK |
270 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
271 | ||
c7c9b392 | 272 | static atomic_t mce_panicked; |
f94b61c2 | 273 | |
bf783f9f | 274 | static int fake_panic; |
c7c9b392 | 275 | static atomic_t mce_fake_panicked; |
bf783f9f | 276 | |
f94b61c2 AK |
277 | /* Panic in progress. Enable interrupts and wait for final IPI */ |
278 | static void wait_for_panic(void) | |
279 | { | |
280 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; | |
f436f8bb | 281 | |
f94b61c2 AK |
282 | preempt_disable(); |
283 | local_irq_enable(); | |
284 | while (timeout-- > 0) | |
285 | udelay(1); | |
29b0f591 | 286 | if (panic_timeout == 0) |
7af19e4a | 287 | panic_timeout = mca_cfg.panic_timeout; |
f94b61c2 AK |
288 | panic("Panicing machine check CPU died"); |
289 | } | |
290 | ||
6c80f87e | 291 | static void mce_panic(const char *msg, struct mce *final, char *exp) |
d88203d1 | 292 | { |
5541c93c TL |
293 | int apei_err = 0; |
294 | struct llist_node *pending; | |
295 | struct mce_evt_llist *l; | |
e02e68d3 | 296 | |
bf783f9f HY |
297 | if (!fake_panic) { |
298 | /* | |
299 | * Make sure only one CPU runs in machine check panic | |
300 | */ | |
c7c9b392 | 301 | if (atomic_inc_return(&mce_panicked) > 1) |
bf783f9f HY |
302 | wait_for_panic(); |
303 | barrier(); | |
f94b61c2 | 304 | |
bf783f9f HY |
305 | bust_spinlocks(1); |
306 | console_verbose(); | |
307 | } else { | |
308 | /* Don't log too much for fake panic */ | |
c7c9b392 | 309 | if (atomic_inc_return(&mce_fake_panicked) > 1) |
bf783f9f HY |
310 | return; |
311 | } | |
5541c93c | 312 | pending = mce_gen_pool_prepare_records(); |
a0189c70 | 313 | /* First print corrected ones that are still unlogged */ |
5541c93c TL |
314 | llist_for_each_entry(l, pending, llnode) { |
315 | struct mce *m = &l->mce; | |
482908b4 | 316 | if (!(m->status & MCI_STATUS_UC)) { |
77e26cca | 317 | print_mce(m); |
482908b4 HY |
318 | if (!apei_err) |
319 | apei_err = apei_write_mce(m); | |
320 | } | |
a0189c70 AK |
321 | } |
322 | /* Now print uncorrected but with the final one last */ | |
5541c93c TL |
323 | llist_for_each_entry(l, pending, llnode) { |
324 | struct mce *m = &l->mce; | |
77e26cca HS |
325 | if (!(m->status & MCI_STATUS_UC)) |
326 | continue; | |
5541c93c | 327 | if (!final || mce_cmp(m, final)) { |
77e26cca | 328 | print_mce(m); |
482908b4 HY |
329 | if (!apei_err) |
330 | apei_err = apei_write_mce(m); | |
331 | } | |
1da177e4 | 332 | } |
482908b4 | 333 | if (final) { |
77e26cca | 334 | print_mce(final); |
482908b4 HY |
335 | if (!apei_err) |
336 | apei_err = apei_write_mce(final); | |
337 | } | |
3c079792 | 338 | if (cpu_missing) |
a2d7b0d4 | 339 | pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n"); |
bd19a5e6 | 340 | if (exp) |
a2d7b0d4 | 341 | pr_emerg(HW_ERR "Machine check: %s\n", exp); |
bf783f9f HY |
342 | if (!fake_panic) { |
343 | if (panic_timeout == 0) | |
7af19e4a | 344 | panic_timeout = mca_cfg.panic_timeout; |
bf783f9f HY |
345 | panic(msg); |
346 | } else | |
a2d7b0d4 | 347 | pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); |
d88203d1 | 348 | } |
1da177e4 | 349 | |
ea149b36 AK |
350 | /* Support code for software error injection */ |
351 | ||
352 | static int msr_to_offset(u32 msr) | |
353 | { | |
0a3aee0d | 354 | unsigned bank = __this_cpu_read(injectm.bank); |
f436f8bb | 355 | |
84c2559d | 356 | if (msr == mca_cfg.rip_msr) |
ea149b36 | 357 | return offsetof(struct mce, ip); |
d9d73fcc | 358 | if (msr == msr_ops.status(bank)) |
ea149b36 | 359 | return offsetof(struct mce, status); |
d9d73fcc | 360 | if (msr == msr_ops.addr(bank)) |
ea149b36 | 361 | return offsetof(struct mce, addr); |
d9d73fcc | 362 | if (msr == msr_ops.misc(bank)) |
ea149b36 AK |
363 | return offsetof(struct mce, misc); |
364 | if (msr == MSR_IA32_MCG_STATUS) | |
365 | return offsetof(struct mce, mcgstatus); | |
366 | return -1; | |
367 | } | |
368 | ||
5f8c1a54 AK |
369 | /* MSR access wrappers used for error injection */ |
370 | static u64 mce_rdmsrl(u32 msr) | |
371 | { | |
372 | u64 v; | |
11868a2d | 373 | |
0a3aee0d | 374 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 375 | int offset = msr_to_offset(msr); |
11868a2d | 376 | |
ea149b36 AK |
377 | if (offset < 0) |
378 | return 0; | |
89cbc767 | 379 | return *(u64 *)((char *)this_cpu_ptr(&injectm) + offset); |
ea149b36 | 380 | } |
11868a2d IM |
381 | |
382 | if (rdmsrl_safe(msr, &v)) { | |
38c54ccb | 383 | WARN_ONCE(1, "mce: Unable to read MSR 0x%x!\n", msr); |
11868a2d IM |
384 | /* |
385 | * Return zero in case the access faulted. This should | |
386 | * not happen normally but can happen if the CPU does | |
387 | * something weird, or if the code is buggy. | |
388 | */ | |
389 | v = 0; | |
390 | } | |
391 | ||
5f8c1a54 AK |
392 | return v; |
393 | } | |
394 | ||
395 | static void mce_wrmsrl(u32 msr, u64 v) | |
396 | { | |
0a3aee0d | 397 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 398 | int offset = msr_to_offset(msr); |
11868a2d | 399 | |
ea149b36 | 400 | if (offset >= 0) |
89cbc767 | 401 | *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v; |
ea149b36 AK |
402 | return; |
403 | } | |
5f8c1a54 AK |
404 | wrmsrl(msr, v); |
405 | } | |
406 | ||
b8325c5b HS |
407 | /* |
408 | * Collect all global (w.r.t. this processor) status about this machine | |
409 | * check into our "mce" struct so that we can use it later to assess | |
410 | * the severity of the problem as we read per-bank specific details. | |
411 | */ | |
412 | static inline void mce_gather_info(struct mce *m, struct pt_regs *regs) | |
413 | { | |
414 | mce_setup(m); | |
415 | ||
416 | m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); | |
417 | if (regs) { | |
418 | /* | |
419 | * Get the address of the instruction at the time of | |
420 | * the machine check error. | |
421 | */ | |
422 | if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { | |
423 | m->ip = regs->ip; | |
424 | m->cs = regs->cs; | |
a129a7c8 AK |
425 | |
426 | /* | |
427 | * When in VM86 mode make the cs look like ring 3 | |
428 | * always. This is a lie, but it's better than passing | |
429 | * the additional vm86 bit around everywhere. | |
430 | */ | |
431 | if (v8086_mode(regs)) | |
432 | m->cs |= 3; | |
b8325c5b HS |
433 | } |
434 | /* Use accurate RIP reporting if available. */ | |
84c2559d BP |
435 | if (mca_cfg.rip_msr) |
436 | m->ip = mce_rdmsrl(mca_cfg.rip_msr); | |
b8325c5b HS |
437 | } |
438 | } | |
439 | ||
88ccbedd | 440 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 441 | { |
1462594b | 442 | if (mca_cfg.disabled) |
5b4408fd | 443 | return 0; |
3d1712c9 | 444 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
445 | } |
446 | ||
9b1beaf2 AK |
447 | static void mce_schedule_work(void) |
448 | { | |
a2c2727d | 449 | if (!mce_gen_pool_empty()) |
061120ae | 450 | schedule_work(&mce_work); |
9b1beaf2 AK |
451 | } |
452 | ||
b77e70bf | 453 | static void mce_irq_work_cb(struct irq_work *entry) |
ccc3c319 | 454 | { |
9b1beaf2 | 455 | mce_schedule_work(); |
ccc3c319 | 456 | } |
ccc3c319 AK |
457 | |
458 | static void mce_report_event(struct pt_regs *regs) | |
459 | { | |
460 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
9ff36ee9 | 461 | mce_notify_irq(); |
9b1beaf2 AK |
462 | /* |
463 | * Triggering the work queue here is just an insurance | |
464 | * policy in case the syscall exit notify handler | |
465 | * doesn't run soon enough or ends up running on the | |
466 | * wrong CPU (can happen when audit sleeps) | |
467 | */ | |
468 | mce_schedule_work(); | |
ccc3c319 AK |
469 | return; |
470 | } | |
471 | ||
061120ae | 472 | irq_work_queue(&mce_irq_work); |
ccc3c319 AK |
473 | } |
474 | ||
feab21f8 BP |
475 | /* |
476 | * Check if the address reported by the CPU is in a format we can parse. | |
477 | * It would be possible to add code for most other cases, but all would | |
478 | * be somewhat complicated (e.g. segment offset would require an instruction | |
479 | * parser). So only support physical addresses up to page granuality for now. | |
480 | */ | |
481 | static int mce_usable_address(struct mce *m) | |
482 | { | |
c6a9583f | 483 | if (!(m->status & MCI_STATUS_ADDRV)) |
feab21f8 BP |
484 | return 0; |
485 | ||
486 | /* Checks after this one are Intel-specific: */ | |
487 | if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) | |
488 | return 1; | |
489 | ||
c6a9583f BP |
490 | if (!(m->status & MCI_STATUS_MISCV)) |
491 | return 0; | |
492 | ||
feab21f8 BP |
493 | if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) |
494 | return 0; | |
c6a9583f | 495 | |
feab21f8 BP |
496 | if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) |
497 | return 0; | |
c6a9583f | 498 | |
feab21f8 BP |
499 | return 1; |
500 | } | |
501 | ||
2d1f4061 | 502 | bool mce_is_memory_error(struct mce *m) |
011d8261 | 503 | { |
2d1f4061 | 504 | if (m->cpuvendor == X86_VENDOR_AMD) { |
011d8261 BP |
505 | /* ErrCodeExt[20:16] */ |
506 | u8 xec = (m->status >> 16) & 0x1f; | |
507 | ||
508 | return (xec == 0x0 || xec == 0x8); | |
2d1f4061 | 509 | } else if (m->cpuvendor == X86_VENDOR_INTEL) { |
011d8261 BP |
510 | /* |
511 | * Intel SDM Volume 3B - 15.9.2 Compound Error Codes | |
512 | * | |
513 | * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for | |
514 | * indicating a memory error. Bit 8 is used for indicating a | |
515 | * cache hierarchy error. The combination of bit 2 and bit 3 | |
516 | * is used for indicating a `generic' cache hierarchy error | |
517 | * But we can't just blindly check the above bits, because if | |
518 | * bit 11 is set, then it is a bus/interconnect error - and | |
519 | * either way the above bits just gives more detail on what | |
520 | * bus/interconnect error happened. Note that bit 12 can be | |
521 | * ignored, as it's the "filter" bit. | |
522 | */ | |
523 | return (m->status & 0xef80) == BIT(7) || | |
524 | (m->status & 0xef00) == BIT(8) || | |
525 | (m->status & 0xeffc) == 0xc; | |
526 | } | |
527 | ||
528 | return false; | |
529 | } | |
2d1f4061 | 530 | EXPORT_SYMBOL_GPL(mce_is_memory_error); |
011d8261 BP |
531 | |
532 | static bool cec_add_mce(struct mce *m) | |
533 | { | |
534 | if (!m) | |
535 | return false; | |
536 | ||
537 | /* We eat only correctable DRAM errors with usable addresses. */ | |
2d1f4061 | 538 | if (mce_is_memory_error(m) && |
011d8261 BP |
539 | !(m->status & MCI_STATUS_UC) && |
540 | mce_usable_address(m)) | |
541 | if (!cec_add_elem(m->addr >> PAGE_SHIFT)) | |
542 | return true; | |
543 | ||
544 | return false; | |
545 | } | |
546 | ||
547 | static int mce_first_notifier(struct notifier_block *nb, unsigned long val, | |
548 | void *data) | |
549 | { | |
550 | struct mce *m = (struct mce *)data; | |
011d8261 BP |
551 | |
552 | if (!m) | |
553 | return NOTIFY_DONE; | |
554 | ||
555 | if (cec_add_mce(m)) | |
556 | return NOTIFY_STOP; | |
557 | ||
558 | /* Emit the trace record: */ | |
559 | trace_mce_record(m); | |
560 | ||
011d8261 BP |
561 | set_bit(0, &mce_need_notify); |
562 | ||
563 | mce_notify_irq(); | |
564 | ||
565 | return NOTIFY_DONE; | |
566 | } | |
567 | ||
568 | static struct notifier_block first_nb = { | |
569 | .notifier_call = mce_first_notifier, | |
570 | .priority = MCE_PRIO_FIRST, | |
571 | }; | |
572 | ||
fd4cf79f CG |
573 | static int srao_decode_notifier(struct notifier_block *nb, unsigned long val, |
574 | void *data) | |
575 | { | |
576 | struct mce *mce = (struct mce *)data; | |
577 | unsigned long pfn; | |
578 | ||
579 | if (!mce) | |
580 | return NOTIFY_DONE; | |
581 | ||
c0ec382e | 582 | if (mce_usable_address(mce) && (mce->severity == MCE_AO_SEVERITY)) { |
fd4cf79f CG |
583 | pfn = mce->addr >> PAGE_SHIFT; |
584 | memory_failure(pfn, MCE_VECTOR, 0); | |
585 | } | |
586 | ||
587 | return NOTIFY_OK; | |
ccc3c319 | 588 | } |
fd4cf79f CG |
589 | static struct notifier_block mce_srao_nb = { |
590 | .notifier_call = srao_decode_notifier, | |
9026cc82 | 591 | .priority = MCE_PRIO_SRAO, |
fd4cf79f | 592 | }; |
ccc3c319 | 593 | |
cd9c57ca BP |
594 | static int mce_default_notifier(struct notifier_block *nb, unsigned long val, |
595 | void *data) | |
596 | { | |
597 | struct mce *m = (struct mce *)data; | |
598 | ||
599 | if (!m) | |
600 | return NOTIFY_DONE; | |
601 | ||
011d8261 | 602 | if (atomic_read(&num_notifiers) > NUM_DEFAULT_NOTIFIERS) |
cc66afea AK |
603 | return NOTIFY_DONE; |
604 | ||
cd9c57ca BP |
605 | __print_mce(m); |
606 | ||
607 | return NOTIFY_DONE; | |
608 | } | |
609 | ||
610 | static struct notifier_block mce_default_nb = { | |
611 | .notifier_call = mce_default_notifier, | |
612 | /* lowest prio, we want it to run last. */ | |
9026cc82 | 613 | .priority = MCE_PRIO_LOWEST, |
cd9c57ca BP |
614 | }; |
615 | ||
85f92694 TL |
616 | /* |
617 | * Read ADDR and MISC registers. | |
618 | */ | |
619 | static void mce_read_aux(struct mce *m, int i) | |
620 | { | |
621 | if (m->status & MCI_STATUS_MISCV) | |
d9d73fcc | 622 | m->misc = mce_rdmsrl(msr_ops.misc(i)); |
db819d60 | 623 | |
85f92694 | 624 | if (m->status & MCI_STATUS_ADDRV) { |
d9d73fcc | 625 | m->addr = mce_rdmsrl(msr_ops.addr(i)); |
85f92694 TL |
626 | |
627 | /* | |
628 | * Mask the reported address by the reported granularity. | |
629 | */ | |
1462594b | 630 | if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) { |
85f92694 TL |
631 | u8 shift = MCI_MISC_ADDR_LSB(m->misc); |
632 | m->addr >>= shift; | |
633 | m->addr <<= shift; | |
634 | } | |
4f29b73b YG |
635 | |
636 | /* | |
637 | * Extract [55:<lsb>] where lsb is the least significant | |
638 | * *valid* bit of the address bits. | |
639 | */ | |
640 | if (mce_flags.smca) { | |
641 | u8 lsb = (m->addr >> 56) & 0x3f; | |
642 | ||
643 | m->addr &= GENMASK_ULL(55, lsb); | |
644 | } | |
85f92694 | 645 | } |
db819d60 | 646 | |
5828c46f YG |
647 | if (mce_flags.smca) { |
648 | m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i)); | |
649 | ||
650 | if (m->status & MCI_STATUS_SYNDV) | |
651 | m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i)); | |
652 | } | |
85f92694 TL |
653 | } |
654 | ||
ca84f696 AK |
655 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
656 | ||
d88203d1 | 657 | /* |
b79109c3 AK |
658 | * Poll for corrected events or events that happened before reset. |
659 | * Those are just logged through /dev/mcelog. | |
660 | * | |
661 | * This is executed in standard interrupt context. | |
ed7290d0 AK |
662 | * |
663 | * Note: spec recommends to panic for fatal unsignalled | |
664 | * errors here. However this would be quite problematic -- | |
665 | * we would need to reimplement the Monarch handling and | |
666 | * it would mess up the exclusion between exception handler | |
667 | * and poll hander -- * so we skip this for now. | |
668 | * These cases should not happen anyways, or only when the CPU | |
669 | * is already totally * confused. In this case it's likely it will | |
670 | * not fully execute the machine check handler either. | |
b79109c3 | 671 | */ |
3f2f0680 | 672 | bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 | 673 | { |
8b38937b | 674 | bool error_seen = false; |
b79109c3 | 675 | struct mce m; |
fa92c586 | 676 | int severity; |
b79109c3 AK |
677 | int i; |
678 | ||
c6ae41e7 | 679 | this_cpu_inc(mce_poll_count); |
ca84f696 | 680 | |
b8325c5b | 681 | mce_gather_info(&m, NULL); |
b79109c3 | 682 | |
669c00f0 BP |
683 | if (flags & MCP_TIMESTAMP) |
684 | m.tsc = rdtsc(); | |
54467353 | 685 | |
d203f0b8 | 686 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 687 | if (!mce_banks[i].ctl || !test_bit(i, *b)) |
b79109c3 AK |
688 | continue; |
689 | ||
690 | m.misc = 0; | |
691 | m.addr = 0; | |
692 | m.bank = i; | |
b79109c3 AK |
693 | |
694 | barrier(); | |
d9d73fcc | 695 | m.status = mce_rdmsrl(msr_ops.status(i)); |
b79109c3 AK |
696 | if (!(m.status & MCI_STATUS_VAL)) |
697 | continue; | |
698 | ||
699 | /* | |
ed7290d0 AK |
700 | * Uncorrected or signalled events are handled by the exception |
701 | * handler when it is enabled, so don't process those here. | |
b79109c3 AK |
702 | * |
703 | * TBD do the same check for MCI_STATUS_EN here? | |
704 | */ | |
ed7290d0 | 705 | if (!(flags & MCP_UC) && |
1462594b | 706 | (m.status & (mca_cfg.ser ? MCI_STATUS_S : MCI_STATUS_UC))) |
b79109c3 AK |
707 | continue; |
708 | ||
8b38937b TL |
709 | error_seen = true; |
710 | ||
85f92694 | 711 | mce_read_aux(&m, i); |
b79109c3 | 712 | |
fa92c586 CY |
713 | severity = mce_severity(&m, mca_cfg.tolerant, NULL, false); |
714 | ||
2d1f4061 | 715 | if (severity == MCE_DEFERRED_SEVERITY && mce_is_memory_error(&m)) |
c0ec382e | 716 | if (m.status & MCI_STATUS_ADDRV) |
fd4cf79f | 717 | m.severity = severity; |
fa92c586 | 718 | |
b79109c3 AK |
719 | /* |
720 | * Don't get the IP here because it's unlikely to | |
721 | * have anything to do with the actual error location. | |
722 | */ | |
8b38937b | 723 | if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce) |
5679af4c | 724 | mce_log(&m); |
c0ec382e | 725 | else if (mce_usable_address(&m)) { |
8b38937b TL |
726 | /* |
727 | * Although we skipped logging this, we still want | |
728 | * to take action. Add to the pool so the registered | |
729 | * notifiers will see it. | |
730 | */ | |
731 | if (!mce_gen_pool_add(&m)) | |
732 | mce_schedule_work(); | |
3f2f0680 | 733 | } |
b79109c3 AK |
734 | |
735 | /* | |
736 | * Clear state for this bank. | |
737 | */ | |
d9d73fcc | 738 | mce_wrmsrl(msr_ops.status(i), 0); |
b79109c3 AK |
739 | } |
740 | ||
741 | /* | |
742 | * Don't clear MCG_STATUS here because it's only defined for | |
743 | * exceptions. | |
744 | */ | |
88921be3 AK |
745 | |
746 | sync_core(); | |
3f2f0680 | 747 | |
8b38937b | 748 | return error_seen; |
b79109c3 | 749 | } |
ea149b36 | 750 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 751 | |
bd19a5e6 AK |
752 | /* |
753 | * Do a quick check if any of the events requires a panic. | |
754 | * This decides if we keep the events around or clear them. | |
755 | */ | |
61b0fccd TL |
756 | static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp, |
757 | struct pt_regs *regs) | |
bd19a5e6 | 758 | { |
95022b8c | 759 | int i, ret = 0; |
17fea54b | 760 | char *tmp; |
bd19a5e6 | 761 | |
d203f0b8 | 762 | for (i = 0; i < mca_cfg.banks; i++) { |
d9d73fcc | 763 | m->status = mce_rdmsrl(msr_ops.status(i)); |
61b0fccd | 764 | if (m->status & MCI_STATUS_VAL) { |
95022b8c | 765 | __set_bit(i, validp); |
61b0fccd TL |
766 | if (quirk_no_way_out) |
767 | quirk_no_way_out(i, m, regs); | |
768 | } | |
17fea54b BP |
769 | |
770 | if (mce_severity(m, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) { | |
771 | *msg = tmp; | |
95022b8c | 772 | ret = 1; |
17fea54b | 773 | } |
bd19a5e6 | 774 | } |
95022b8c | 775 | return ret; |
bd19a5e6 AK |
776 | } |
777 | ||
3c079792 AK |
778 | /* |
779 | * Variable to establish order between CPUs while scanning. | |
780 | * Each CPU spins initially until executing is equal its number. | |
781 | */ | |
782 | static atomic_t mce_executing; | |
783 | ||
784 | /* | |
785 | * Defines order of CPUs on entry. First CPU becomes Monarch. | |
786 | */ | |
787 | static atomic_t mce_callin; | |
788 | ||
789 | /* | |
790 | * Check if a timeout waiting for other CPUs happened. | |
791 | */ | |
6c80f87e | 792 | static int mce_timed_out(u64 *t, const char *msg) |
3c079792 AK |
793 | { |
794 | /* | |
795 | * The others already did panic for some reason. | |
796 | * Bail out like in a timeout. | |
797 | * rmb() to tell the compiler that system_state | |
798 | * might have been modified by someone else. | |
799 | */ | |
800 | rmb(); | |
c7c9b392 | 801 | if (atomic_read(&mce_panicked)) |
3c079792 | 802 | wait_for_panic(); |
84c2559d | 803 | if (!mca_cfg.monarch_timeout) |
3c079792 AK |
804 | goto out; |
805 | if ((s64)*t < SPINUNIT) { | |
716079f6 | 806 | if (mca_cfg.tolerant <= 1) |
6c80f87e | 807 | mce_panic(msg, NULL, NULL); |
3c079792 AK |
808 | cpu_missing = 1; |
809 | return 1; | |
810 | } | |
811 | *t -= SPINUNIT; | |
812 | out: | |
813 | touch_nmi_watchdog(); | |
814 | return 0; | |
815 | } | |
816 | ||
817 | /* | |
818 | * The Monarch's reign. The Monarch is the CPU who entered | |
819 | * the machine check handler first. It waits for the others to | |
820 | * raise the exception too and then grades them. When any | |
821 | * error is fatal panic. Only then let the others continue. | |
822 | * | |
823 | * The other CPUs entering the MCE handler will be controlled by the | |
824 | * Monarch. They are called Subjects. | |
825 | * | |
826 | * This way we prevent any potential data corruption in a unrecoverable case | |
827 | * and also makes sure always all CPU's errors are examined. | |
828 | * | |
680b6cfd | 829 | * Also this detects the case of a machine check event coming from outer |
3c079792 AK |
830 | * space (not detected by any CPUs) In this case some external agent wants |
831 | * us to shut down, so panic too. | |
832 | * | |
833 | * The other CPUs might still decide to panic if the handler happens | |
834 | * in a unrecoverable place, but in this case the system is in a semi-stable | |
835 | * state and won't corrupt anything by itself. It's ok to let the others | |
836 | * continue for a bit first. | |
837 | * | |
838 | * All the spin loops have timeouts; when a timeout happens a CPU | |
839 | * typically elects itself to be Monarch. | |
840 | */ | |
841 | static void mce_reign(void) | |
842 | { | |
843 | int cpu; | |
844 | struct mce *m = NULL; | |
845 | int global_worst = 0; | |
846 | char *msg = NULL; | |
847 | char *nmsg = NULL; | |
848 | ||
849 | /* | |
850 | * This CPU is the Monarch and the other CPUs have run | |
851 | * through their handlers. | |
852 | * Grade the severity of the errors of all the CPUs. | |
853 | */ | |
854 | for_each_possible_cpu(cpu) { | |
d203f0b8 BP |
855 | int severity = mce_severity(&per_cpu(mces_seen, cpu), |
856 | mca_cfg.tolerant, | |
e3480271 | 857 | &nmsg, true); |
3c079792 AK |
858 | if (severity > global_worst) { |
859 | msg = nmsg; | |
860 | global_worst = severity; | |
861 | m = &per_cpu(mces_seen, cpu); | |
862 | } | |
863 | } | |
864 | ||
865 | /* | |
866 | * Cannot recover? Panic here then. | |
867 | * This dumps all the mces in the log buffer and stops the | |
868 | * other CPUs. | |
869 | */ | |
d203f0b8 | 870 | if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) |
8af7043a | 871 | mce_panic("Fatal machine check", m, msg); |
3c079792 AK |
872 | |
873 | /* | |
874 | * For UC somewhere we let the CPU who detects it handle it. | |
875 | * Also must let continue the others, otherwise the handling | |
876 | * CPU could deadlock on a lock. | |
877 | */ | |
878 | ||
879 | /* | |
880 | * No machine check event found. Must be some external | |
881 | * source or one CPU is hung. Panic. | |
882 | */ | |
d203f0b8 | 883 | if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3) |
8af7043a | 884 | mce_panic("Fatal machine check from unknown source", NULL, NULL); |
3c079792 AK |
885 | |
886 | /* | |
887 | * Now clear all the mces_seen so that they don't reappear on | |
888 | * the next mce. | |
889 | */ | |
890 | for_each_possible_cpu(cpu) | |
891 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); | |
892 | } | |
893 | ||
894 | static atomic_t global_nwo; | |
895 | ||
896 | /* | |
897 | * Start of Monarch synchronization. This waits until all CPUs have | |
898 | * entered the exception handler and then determines if any of them | |
899 | * saw a fatal event that requires panic. Then it executes them | |
900 | * in the entry order. | |
901 | * TBD double check parallel CPU hotunplug | |
902 | */ | |
7fb06fc9 | 903 | static int mce_start(int *no_way_out) |
3c079792 | 904 | { |
7fb06fc9 | 905 | int order; |
3c079792 | 906 | int cpus = num_online_cpus(); |
84c2559d | 907 | u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; |
3c079792 | 908 | |
7fb06fc9 HS |
909 | if (!timeout) |
910 | return -1; | |
3c079792 | 911 | |
7fb06fc9 | 912 | atomic_add(*no_way_out, &global_nwo); |
184e1fdf | 913 | /* |
bf92b1fe DB |
914 | * Rely on the implied barrier below, such that global_nwo |
915 | * is updated before mce_callin. | |
184e1fdf | 916 | */ |
a95436e4 | 917 | order = atomic_inc_return(&mce_callin); |
3c079792 AK |
918 | |
919 | /* | |
920 | * Wait for everyone. | |
921 | */ | |
922 | while (atomic_read(&mce_callin) != cpus) { | |
6c80f87e AL |
923 | if (mce_timed_out(&timeout, |
924 | "Timeout: Not all CPUs entered broadcast exception handler")) { | |
3c079792 | 925 | atomic_set(&global_nwo, 0); |
7fb06fc9 | 926 | return -1; |
3c079792 AK |
927 | } |
928 | ndelay(SPINUNIT); | |
929 | } | |
930 | ||
184e1fdf HY |
931 | /* |
932 | * mce_callin should be read before global_nwo | |
933 | */ | |
934 | smp_rmb(); | |
3c079792 | 935 | |
7fb06fc9 HS |
936 | if (order == 1) { |
937 | /* | |
938 | * Monarch: Starts executing now, the others wait. | |
939 | */ | |
3c079792 | 940 | atomic_set(&mce_executing, 1); |
7fb06fc9 HS |
941 | } else { |
942 | /* | |
943 | * Subject: Now start the scanning loop one by one in | |
944 | * the original callin order. | |
945 | * This way when there are any shared banks it will be | |
946 | * only seen by one CPU before cleared, avoiding duplicates. | |
947 | */ | |
948 | while (atomic_read(&mce_executing) < order) { | |
6c80f87e AL |
949 | if (mce_timed_out(&timeout, |
950 | "Timeout: Subject CPUs unable to finish machine check processing")) { | |
7fb06fc9 HS |
951 | atomic_set(&global_nwo, 0); |
952 | return -1; | |
953 | } | |
954 | ndelay(SPINUNIT); | |
955 | } | |
3c079792 AK |
956 | } |
957 | ||
958 | /* | |
7fb06fc9 | 959 | * Cache the global no_way_out state. |
3c079792 | 960 | */ |
7fb06fc9 HS |
961 | *no_way_out = atomic_read(&global_nwo); |
962 | ||
963 | return order; | |
3c079792 AK |
964 | } |
965 | ||
966 | /* | |
967 | * Synchronize between CPUs after main scanning loop. | |
968 | * This invokes the bulk of the Monarch processing. | |
969 | */ | |
970 | static int mce_end(int order) | |
971 | { | |
972 | int ret = -1; | |
84c2559d | 973 | u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; |
3c079792 AK |
974 | |
975 | if (!timeout) | |
976 | goto reset; | |
977 | if (order < 0) | |
978 | goto reset; | |
979 | ||
980 | /* | |
981 | * Allow others to run. | |
982 | */ | |
983 | atomic_inc(&mce_executing); | |
984 | ||
985 | if (order == 1) { | |
986 | /* CHECKME: Can this race with a parallel hotplug? */ | |
987 | int cpus = num_online_cpus(); | |
988 | ||
989 | /* | |
990 | * Monarch: Wait for everyone to go through their scanning | |
991 | * loops. | |
992 | */ | |
993 | while (atomic_read(&mce_executing) <= cpus) { | |
6c80f87e AL |
994 | if (mce_timed_out(&timeout, |
995 | "Timeout: Monarch CPU unable to finish machine check processing")) | |
3c079792 AK |
996 | goto reset; |
997 | ndelay(SPINUNIT); | |
998 | } | |
999 | ||
1000 | mce_reign(); | |
1001 | barrier(); | |
1002 | ret = 0; | |
1003 | } else { | |
1004 | /* | |
1005 | * Subject: Wait for Monarch to finish. | |
1006 | */ | |
1007 | while (atomic_read(&mce_executing) != 0) { | |
6c80f87e AL |
1008 | if (mce_timed_out(&timeout, |
1009 | "Timeout: Monarch CPU did not finish machine check processing")) | |
3c079792 AK |
1010 | goto reset; |
1011 | ndelay(SPINUNIT); | |
1012 | } | |
1013 | ||
1014 | /* | |
1015 | * Don't reset anything. That's done by the Monarch. | |
1016 | */ | |
1017 | return 0; | |
1018 | } | |
1019 | ||
1020 | /* | |
1021 | * Reset all global state. | |
1022 | */ | |
1023 | reset: | |
1024 | atomic_set(&global_nwo, 0); | |
1025 | atomic_set(&mce_callin, 0); | |
1026 | barrier(); | |
1027 | ||
1028 | /* | |
1029 | * Let others run again. | |
1030 | */ | |
1031 | atomic_set(&mce_executing, 0); | |
1032 | return ret; | |
1033 | } | |
1034 | ||
1035 | static void mce_clear_state(unsigned long *toclear) | |
1036 | { | |
1037 | int i; | |
1038 | ||
d203f0b8 | 1039 | for (i = 0; i < mca_cfg.banks; i++) { |
3c079792 | 1040 | if (test_bit(i, toclear)) |
d9d73fcc | 1041 | mce_wrmsrl(msr_ops.status(i), 0); |
3c079792 AK |
1042 | } |
1043 | } | |
1044 | ||
b2f9d678 TL |
1045 | static int do_memory_failure(struct mce *m) |
1046 | { | |
1047 | int flags = MF_ACTION_REQUIRED; | |
1048 | int ret; | |
1049 | ||
1050 | pr_err("Uncorrected hardware memory error in user-access at %llx", m->addr); | |
1051 | if (!(m->mcgstatus & MCG_STATUS_RIPV)) | |
1052 | flags |= MF_MUST_KILL; | |
1053 | ret = memory_failure(m->addr >> PAGE_SHIFT, MCE_VECTOR, flags); | |
1054 | if (ret) | |
1055 | pr_err("Memory error not recovered"); | |
1056 | return ret; | |
1057 | } | |
1058 | ||
b79109c3 AK |
1059 | /* |
1060 | * The actual machine check handler. This only handles real | |
1061 | * exceptions when something got corrupted coming in through int 18. | |
1062 | * | |
1063 | * This is executed in NMI context not subject to normal locking rules. This | |
1064 | * implies that most kernel services cannot be safely used. Don't even | |
1065 | * think about putting a printk in there! | |
3c079792 AK |
1066 | * |
1067 | * On Intel systems this is entered on all CPUs in parallel through | |
1068 | * MCE broadcast. However some CPUs might be broken beyond repair, | |
1069 | * so be always careful when synchronizing with others. | |
1da177e4 | 1070 | */ |
e9eee03e | 1071 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 1072 | { |
1462594b | 1073 | struct mca_config *cfg = &mca_cfg; |
3c079792 | 1074 | struct mce m, *final; |
1da177e4 | 1075 | int i; |
3c079792 AK |
1076 | int worst = 0; |
1077 | int severity; | |
fead35c6 | 1078 | |
3c079792 AK |
1079 | /* |
1080 | * Establish sequential order between the CPUs entering the machine | |
1081 | * check handler. | |
1082 | */ | |
fead35c6 | 1083 | int order = -1; |
bd78432c TH |
1084 | /* |
1085 | * If no_way_out gets set, there is no safe way to recover from this | |
d203f0b8 | 1086 | * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway. |
bd78432c TH |
1087 | */ |
1088 | int no_way_out = 0; | |
1089 | /* | |
1090 | * If kill_it gets set, there might be a way to recover from this | |
1091 | * error. | |
1092 | */ | |
1093 | int kill_it = 0; | |
b79109c3 | 1094 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
95022b8c | 1095 | DECLARE_BITMAP(valid_banks, MAX_NR_BANKS); |
bd19a5e6 | 1096 | char *msg = "Unknown"; |
fead35c6 YG |
1097 | |
1098 | /* | |
1099 | * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES | |
1100 | * on Intel. | |
1101 | */ | |
1102 | int lmce = 1; | |
5bc32950 | 1103 | int cpu = smp_processor_id(); |
1da177e4 | 1104 | |
5bc32950 XP |
1105 | /* |
1106 | * Cases where we avoid rendezvous handler timeout: | |
1107 | * 1) If this CPU is offline. | |
1108 | * | |
1109 | * 2) If crashing_cpu was set, e.g. we're entering kdump and we need to | |
1110 | * skip those CPUs which remain looping in the 1st kernel - see | |
1111 | * crash_nmi_callback(). | |
1112 | * | |
1113 | * Note: there still is a small window between kexec-ing and the new, | |
1114 | * kdump kernel establishing a new #MC handler where a broadcasted MCE | |
1115 | * might not get handled properly. | |
1116 | */ | |
1117 | if (cpu_is_offline(cpu) || | |
1118 | (crashing_cpu != -1 && crashing_cpu != cpu)) { | |
d90167a9 AR |
1119 | u64 mcgstatus; |
1120 | ||
1121 | mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); | |
1122 | if (mcgstatus & MCG_STATUS_RIPV) { | |
1123 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); | |
1124 | return; | |
1125 | } | |
1126 | } | |
1127 | ||
8c84014f | 1128 | ist_enter(regs); |
95927475 | 1129 | |
c6ae41e7 | 1130 | this_cpu_inc(mce_exception_count); |
01ca79f1 | 1131 | |
1462594b | 1132 | if (!cfg->banks) |
32561696 | 1133 | goto out; |
1da177e4 | 1134 | |
b8325c5b | 1135 | mce_gather_info(&m, regs); |
669c00f0 | 1136 | m.tsc = rdtsc(); |
b5f2fa4e | 1137 | |
89cbc767 | 1138 | final = this_cpu_ptr(&mces_seen); |
3c079792 AK |
1139 | *final = m; |
1140 | ||
95022b8c | 1141 | memset(valid_banks, 0, sizeof(valid_banks)); |
61b0fccd | 1142 | no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs); |
680b6cfd | 1143 | |
1da177e4 LT |
1144 | barrier(); |
1145 | ||
ed7290d0 | 1146 | /* |
a8c321fb TL |
1147 | * When no restart IP might need to kill or panic. |
1148 | * Assume the worst for now, but if we find the | |
1149 | * severity is MCE_AR_SEVERITY we have other options. | |
ed7290d0 AK |
1150 | */ |
1151 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
1152 | kill_it = 1; | |
1153 | ||
3c079792 | 1154 | /* |
fead35c6 YG |
1155 | * Check if this MCE is signaled to only this logical processor, |
1156 | * on Intel only. | |
3c079792 | 1157 | */ |
fead35c6 YG |
1158 | if (m.cpuvendor == X86_VENDOR_INTEL) |
1159 | lmce = m.mcgstatus & MCG_STATUS_LMCES; | |
1160 | ||
1161 | /* | |
1162 | * Go through all banks in exclusion of the other CPUs. This way we | |
1163 | * don't report duplicated events on shared banks because the first one | |
1164 | * to see it will clear it. If this is a Local MCE, then no need to | |
1165 | * perform rendezvous. | |
1166 | */ | |
1167 | if (!lmce) | |
243d657e | 1168 | order = mce_start(&no_way_out); |
243d657e | 1169 | |
1462594b | 1170 | for (i = 0; i < cfg->banks; i++) { |
b79109c3 | 1171 | __clear_bit(i, toclear); |
95022b8c TL |
1172 | if (!test_bit(i, valid_banks)) |
1173 | continue; | |
cebe1820 | 1174 | if (!mce_banks[i].ctl) |
1da177e4 | 1175 | continue; |
d88203d1 TG |
1176 | |
1177 | m.misc = 0; | |
1da177e4 LT |
1178 | m.addr = 0; |
1179 | m.bank = i; | |
1da177e4 | 1180 | |
d9d73fcc | 1181 | m.status = mce_rdmsrl(msr_ops.status(i)); |
1da177e4 LT |
1182 | if ((m.status & MCI_STATUS_VAL) == 0) |
1183 | continue; | |
1184 | ||
b79109c3 | 1185 | /* |
ed7290d0 AK |
1186 | * Non uncorrected or non signaled errors are handled by |
1187 | * machine_check_poll. Leave them alone, unless this panics. | |
b79109c3 | 1188 | */ |
1462594b | 1189 | if (!(m.status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) && |
ed7290d0 | 1190 | !no_way_out) |
b79109c3 AK |
1191 | continue; |
1192 | ||
1193 | /* | |
1194 | * Set taint even when machine check was not enabled. | |
1195 | */ | |
373d4d09 | 1196 | add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); |
b79109c3 | 1197 | |
e3480271 | 1198 | severity = mce_severity(&m, cfg->tolerant, NULL, true); |
b79109c3 | 1199 | |
ed7290d0 | 1200 | /* |
e3480271 CY |
1201 | * When machine check was for corrected/deferred handler don't |
1202 | * touch, unless we're panicing. | |
ed7290d0 | 1203 | */ |
e3480271 CY |
1204 | if ((severity == MCE_KEEP_SEVERITY || |
1205 | severity == MCE_UCNA_SEVERITY) && !no_way_out) | |
ed7290d0 AK |
1206 | continue; |
1207 | __set_bit(i, toclear); | |
1208 | if (severity == MCE_NO_SEVERITY) { | |
b79109c3 AK |
1209 | /* |
1210 | * Machine check event was not enabled. Clear, but | |
1211 | * ignore. | |
1212 | */ | |
1213 | continue; | |
1da177e4 LT |
1214 | } |
1215 | ||
85f92694 | 1216 | mce_read_aux(&m, i); |
1da177e4 | 1217 | |
fd4cf79f CG |
1218 | /* assuming valid severity level != 0 */ |
1219 | m.severity = severity; | |
9b1beaf2 | 1220 | |
b79109c3 | 1221 | mce_log(&m); |
1da177e4 | 1222 | |
3c079792 AK |
1223 | if (severity > worst) { |
1224 | *final = m; | |
1225 | worst = severity; | |
1da177e4 | 1226 | } |
1da177e4 LT |
1227 | } |
1228 | ||
a8c321fb TL |
1229 | /* mce_clear_state will clear *final, save locally for use later */ |
1230 | m = *final; | |
1231 | ||
3c079792 AK |
1232 | if (!no_way_out) |
1233 | mce_clear_state(toclear); | |
1234 | ||
e9eee03e | 1235 | /* |
3c079792 AK |
1236 | * Do most of the synchronization with other CPUs. |
1237 | * When there's any problem use only local no_way_out state. | |
e9eee03e | 1238 | */ |
243d657e AR |
1239 | if (!lmce) { |
1240 | if (mce_end(order) < 0) | |
1241 | no_way_out = worst >= MCE_PANIC_SEVERITY; | |
1242 | } else { | |
1243 | /* | |
1244 | * Local MCE skipped calling mce_reign() | |
1245 | * If we found a fatal error, we need to panic here. | |
1246 | */ | |
1247 | if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) | |
1248 | mce_panic("Machine check from unknown source", | |
1249 | NULL, NULL); | |
1250 | } | |
bd78432c TH |
1251 | |
1252 | /* | |
b2f9d678 TL |
1253 | * If tolerant is at an insane level we drop requests to kill |
1254 | * processes and continue even when there is no way out. | |
bd78432c | 1255 | */ |
b2f9d678 TL |
1256 | if (cfg->tolerant == 3) |
1257 | kill_it = 0; | |
1258 | else if (no_way_out) | |
1259 | mce_panic("Fatal machine check on current CPU", &m, msg); | |
e02e68d3 | 1260 | |
3c079792 AK |
1261 | if (worst > 0) |
1262 | mce_report_event(regs); | |
5f8c1a54 | 1263 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 1264 | out: |
88921be3 | 1265 | sync_core(); |
d4812e16 | 1266 | |
b2f9d678 TL |
1267 | if (worst != MCE_AR_SEVERITY && !kill_it) |
1268 | goto out_ist; | |
d4812e16 | 1269 | |
b2f9d678 TL |
1270 | /* Fault was in user mode and we need to take some action */ |
1271 | if ((m.cs & 3) == 3) { | |
1272 | ist_begin_non_atomic(regs); | |
1273 | local_irq_enable(); | |
1274 | ||
1275 | if (kill_it || do_memory_failure(&m)) | |
1276 | force_sig(SIGBUS, current); | |
1277 | local_irq_disable(); | |
1278 | ist_end_non_atomic(); | |
1279 | } else { | |
1280 | if (!fixup_exception(regs, X86_TRAP_MC)) | |
1281 | mce_panic("Failed kernel mode recovery", &m, NULL); | |
d4812e16 | 1282 | } |
b2f9d678 TL |
1283 | |
1284 | out_ist: | |
8c84014f | 1285 | ist_exit(regs); |
1da177e4 | 1286 | } |
ea149b36 | 1287 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 1288 | |
cd42f4a3 TL |
1289 | #ifndef CONFIG_MEMORY_FAILURE |
1290 | int memory_failure(unsigned long pfn, int vector, int flags) | |
9b1beaf2 | 1291 | { |
a8c321fb TL |
1292 | /* mce_severity() should not hand us an ACTION_REQUIRED error */ |
1293 | BUG_ON(flags & MF_ACTION_REQUIRED); | |
c767a54b JP |
1294 | pr_err("Uncorrected memory error in page 0x%lx ignored\n" |
1295 | "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", | |
1296 | pfn); | |
cd42f4a3 TL |
1297 | |
1298 | return 0; | |
9b1beaf2 | 1299 | } |
cd42f4a3 | 1300 | #endif |
9b1beaf2 | 1301 | |
1da177e4 | 1302 | /* |
8a336b0a TH |
1303 | * Periodic polling timer for "silent" machine check errors. If the |
1304 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
1305 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 1306 | */ |
3f2f0680 | 1307 | static unsigned long check_interval = INITIAL_CHECK_INTERVAL; |
e9eee03e | 1308 | |
82f7af09 | 1309 | static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */ |
52d168e2 | 1310 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 1311 | |
55babd8f CG |
1312 | static unsigned long mce_adjust_timer_default(unsigned long interval) |
1313 | { | |
1314 | return interval; | |
1315 | } | |
1316 | ||
3f2f0680 | 1317 | static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default; |
55babd8f | 1318 | |
0becc0ae | 1319 | static void __start_timer(struct timer_list *t, unsigned long interval) |
27f6c573 | 1320 | { |
3f2f0680 BP |
1321 | unsigned long when = jiffies + interval; |
1322 | unsigned long flags; | |
27f6c573 | 1323 | |
3f2f0680 | 1324 | local_irq_save(flags); |
27f6c573 | 1325 | |
0becc0ae TG |
1326 | if (!timer_pending(t) || time_before(when, t->expires)) |
1327 | mod_timer(t, round_jiffies(when)); | |
3f2f0680 BP |
1328 | |
1329 | local_irq_restore(flags); | |
27f6c573 CG |
1330 | } |
1331 | ||
82f7af09 | 1332 | static void mce_timer_fn(unsigned long data) |
1da177e4 | 1333 | { |
89cbc767 | 1334 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
3f2f0680 | 1335 | int cpu = smp_processor_id(); |
82f7af09 | 1336 | unsigned long iv; |
52d168e2 | 1337 | |
3f2f0680 BP |
1338 | WARN_ON(cpu != data); |
1339 | ||
1340 | iv = __this_cpu_read(mce_next_interval); | |
52d168e2 | 1341 | |
89cbc767 | 1342 | if (mce_available(this_cpu_ptr(&cpu_info))) { |
54467353 | 1343 | machine_check_poll(0, this_cpu_ptr(&mce_poll_banks)); |
3f2f0680 BP |
1344 | |
1345 | if (mce_intel_cmci_poll()) { | |
1346 | iv = mce_adjust_timer(iv); | |
1347 | goto done; | |
1348 | } | |
e9eee03e | 1349 | } |
1da177e4 LT |
1350 | |
1351 | /* | |
3f2f0680 BP |
1352 | * Alert userspace if needed. If we logged an MCE, reduce the polling |
1353 | * interval, otherwise increase the polling interval. | |
1da177e4 | 1354 | */ |
3f2f0680 | 1355 | if (mce_notify_irq()) |
958fb3c5 | 1356 | iv = max(iv / 2, (unsigned long) HZ/100); |
3f2f0680 | 1357 | else |
82f7af09 | 1358 | iv = min(iv * 2, round_jiffies_relative(check_interval * HZ)); |
3f2f0680 BP |
1359 | |
1360 | done: | |
82f7af09 | 1361 | __this_cpu_write(mce_next_interval, iv); |
0becc0ae | 1362 | __start_timer(t, iv); |
55babd8f | 1363 | } |
e02e68d3 | 1364 | |
55babd8f CG |
1365 | /* |
1366 | * Ensure that the timer is firing in @interval from now. | |
1367 | */ | |
1368 | void mce_timer_kick(unsigned long interval) | |
1369 | { | |
89cbc767 | 1370 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
55babd8f CG |
1371 | unsigned long iv = __this_cpu_read(mce_next_interval); |
1372 | ||
0becc0ae | 1373 | __start_timer(t, interval); |
3f2f0680 | 1374 | |
55babd8f CG |
1375 | if (interval < iv) |
1376 | __this_cpu_write(mce_next_interval, interval); | |
e02e68d3 TH |
1377 | } |
1378 | ||
9aaef96f HS |
1379 | /* Must not be called in IRQ context where del_timer_sync() can deadlock */ |
1380 | static void mce_timer_delete_all(void) | |
1381 | { | |
1382 | int cpu; | |
1383 | ||
1384 | for_each_online_cpu(cpu) | |
1385 | del_timer_sync(&per_cpu(mce_timer, cpu)); | |
1386 | } | |
1387 | ||
e02e68d3 | 1388 | /* |
9bd98405 AK |
1389 | * Notify the user(s) about new machine check events. |
1390 | * Can be called from interrupt context, but not from machine check/NMI | |
1391 | * context. | |
e02e68d3 | 1392 | */ |
9ff36ee9 | 1393 | int mce_notify_irq(void) |
e02e68d3 | 1394 | { |
8457c84d AK |
1395 | /* Not more than two messages every minute */ |
1396 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
1397 | ||
1020bcbc | 1398 | if (test_and_clear_bit(0, &mce_need_notify)) { |
5de97c9f | 1399 | mce_work_trigger(); |
e02e68d3 | 1400 | |
8457c84d | 1401 | if (__ratelimit(&ratelimit)) |
a2d7b0d4 | 1402 | pr_info(HW_ERR "Machine check events logged\n"); |
e02e68d3 TH |
1403 | |
1404 | return 1; | |
1da177e4 | 1405 | } |
e02e68d3 TH |
1406 | return 0; |
1407 | } | |
9ff36ee9 | 1408 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
8a336b0a | 1409 | |
148f9bb8 | 1410 | static int __mcheck_cpu_mce_banks_init(void) |
cebe1820 AK |
1411 | { |
1412 | int i; | |
d203f0b8 | 1413 | u8 num_banks = mca_cfg.banks; |
cebe1820 | 1414 | |
d203f0b8 | 1415 | mce_banks = kzalloc(num_banks * sizeof(struct mce_bank), GFP_KERNEL); |
cebe1820 AK |
1416 | if (!mce_banks) |
1417 | return -ENOMEM; | |
d203f0b8 BP |
1418 | |
1419 | for (i = 0; i < num_banks; i++) { | |
cebe1820 | 1420 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1421 | |
cebe1820 AK |
1422 | b->ctl = -1ULL; |
1423 | b->init = 1; | |
1424 | } | |
1425 | return 0; | |
1426 | } | |
1427 | ||
d88203d1 | 1428 | /* |
1da177e4 LT |
1429 | * Initialize Machine Checks for a CPU. |
1430 | */ | |
148f9bb8 | 1431 | static int __mcheck_cpu_cap_init(void) |
1da177e4 | 1432 | { |
0d7482e3 | 1433 | unsigned b; |
e9eee03e | 1434 | u64 cap; |
1da177e4 LT |
1435 | |
1436 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
1437 | |
1438 | b = cap & MCG_BANKCNT_MASK; | |
d203f0b8 | 1439 | if (!mca_cfg.banks) |
c767a54b | 1440 | pr_info("CPU supports %d MCE banks\n", b); |
b659294b | 1441 | |
0d7482e3 | 1442 | if (b > MAX_NR_BANKS) { |
c767a54b | 1443 | pr_warn("Using only %u machine check banks out of %u\n", |
0d7482e3 AK |
1444 | MAX_NR_BANKS, b); |
1445 | b = MAX_NR_BANKS; | |
1446 | } | |
1447 | ||
1448 | /* Don't support asymmetric configurations today */ | |
d203f0b8 BP |
1449 | WARN_ON(mca_cfg.banks != 0 && b != mca_cfg.banks); |
1450 | mca_cfg.banks = b; | |
1451 | ||
cebe1820 | 1452 | if (!mce_banks) { |
cffd377e | 1453 | int err = __mcheck_cpu_mce_banks_init(); |
11868a2d | 1454 | |
cebe1820 AK |
1455 | if (err) |
1456 | return err; | |
1da177e4 | 1457 | } |
0d7482e3 | 1458 | |
94ad8474 | 1459 | /* Use accurate RIP reporting if available. */ |
01c6680a | 1460 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
84c2559d | 1461 | mca_cfg.rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 1462 | |
ed7290d0 | 1463 | if (cap & MCG_SER_P) |
1462594b | 1464 | mca_cfg.ser = true; |
ed7290d0 | 1465 | |
0d7482e3 AK |
1466 | return 0; |
1467 | } | |
1468 | ||
5e09954a | 1469 | static void __mcheck_cpu_init_generic(void) |
0d7482e3 | 1470 | { |
84c2559d | 1471 | enum mcp_flags m_fl = 0; |
e9eee03e | 1472 | mce_banks_t all_banks; |
0d7482e3 | 1473 | u64 cap; |
0d7482e3 | 1474 | |
84c2559d BP |
1475 | if (!mca_cfg.bootlog) |
1476 | m_fl = MCP_DONTLOG; | |
1477 | ||
b79109c3 AK |
1478 | /* |
1479 | * Log the machine checks left over from the previous reset. | |
1480 | */ | |
ee031c31 | 1481 | bitmap_fill(all_banks, MAX_NR_BANKS); |
84c2559d | 1482 | machine_check_poll(MCP_UC | m_fl, &all_banks); |
1da177e4 | 1483 | |
375074cc | 1484 | cr4_set_bits(X86_CR4_MCE); |
1da177e4 | 1485 | |
0d7482e3 | 1486 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
1487 | if (cap & MCG_CTL_P) |
1488 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
bb91f8c0 AG |
1489 | } |
1490 | ||
1491 | static void __mcheck_cpu_init_clear_banks(void) | |
1492 | { | |
1493 | int i; | |
1da177e4 | 1494 | |
d203f0b8 | 1495 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 1496 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1497 | |
cebe1820 | 1498 | if (!b->init) |
06b7a7a5 | 1499 | continue; |
d9d73fcc YG |
1500 | wrmsrl(msr_ops.ctl(i), b->ctl); |
1501 | wrmsrl(msr_ops.status(i), 0); | |
d88203d1 | 1502 | } |
1da177e4 LT |
1503 | } |
1504 | ||
61b0fccd TL |
1505 | /* |
1506 | * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and | |
1507 | * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM | |
1508 | * Vol 3B Table 15-20). But this confuses both the code that determines | |
1509 | * whether the machine check occurred in kernel or user mode, and also | |
1510 | * the severity assessment code. Pretend that EIPV was set, and take the | |
1511 | * ip/cs values from the pt_regs that mce_gather_info() ignored earlier. | |
1512 | */ | |
1513 | static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs) | |
1514 | { | |
1515 | if (bank != 0) | |
1516 | return; | |
1517 | if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0) | |
1518 | return; | |
1519 | if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC| | |
1520 | MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV| | |
1521 | MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR| | |
1522 | MCACOD)) != | |
1523 | (MCI_STATUS_UC|MCI_STATUS_EN| | |
1524 | MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S| | |
1525 | MCI_STATUS_AR|MCACOD_INSTR)) | |
1526 | return; | |
1527 | ||
1528 | m->mcgstatus |= MCG_STATUS_EIPV; | |
1529 | m->ip = regs->ip; | |
1530 | m->cs = regs->cs; | |
1531 | } | |
1532 | ||
1da177e4 | 1533 | /* Add per CPU specific workarounds here */ |
148f9bb8 | 1534 | static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 1535 | { |
d203f0b8 BP |
1536 | struct mca_config *cfg = &mca_cfg; |
1537 | ||
e412cd25 | 1538 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
c767a54b | 1539 | pr_info("unknown CPU type - not enabling MCE support\n"); |
e412cd25 IM |
1540 | return -EOPNOTSUPP; |
1541 | } | |
1542 | ||
1da177e4 | 1543 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 1544 | if (c->x86_vendor == X86_VENDOR_AMD) { |
d203f0b8 | 1545 | if (c->x86 == 15 && cfg->banks > 4) { |
e9eee03e IM |
1546 | /* |
1547 | * disable GART TBL walk error reporting, which | |
1548 | * trips off incorrectly with the IOMMU & 3ware | |
1549 | * & Cerberus: | |
1550 | */ | |
cebe1820 | 1551 | clear_bit(10, (unsigned long *)&mce_banks[4].ctl); |
e9eee03e | 1552 | } |
10001d91 | 1553 | if (c->x86 < 17 && cfg->bootlog < 0) { |
e9eee03e IM |
1554 | /* |
1555 | * Lots of broken BIOS around that don't clear them | |
1556 | * by default and leave crap in there. Don't log: | |
1557 | */ | |
84c2559d | 1558 | cfg->bootlog = 0; |
e9eee03e | 1559 | } |
2e6f694f AK |
1560 | /* |
1561 | * Various K7s with broken bank 0 around. Always disable | |
1562 | * by default. | |
1563 | */ | |
c9ce8712 | 1564 | if (c->x86 == 6 && cfg->banks > 0) |
cebe1820 | 1565 | mce_banks[0].ctl = 0; |
575203b4 | 1566 | |
bf80bbd7 AG |
1567 | /* |
1568 | * overflow_recov is supported for F15h Models 00h-0fh | |
1569 | * even though we don't have a CPUID bit for it. | |
1570 | */ | |
1571 | if (c->x86 == 0x15 && c->x86_model <= 0xf) | |
1572 | mce_flags.overflow_recov = 1; | |
1573 | ||
c9ce8712 BP |
1574 | /* |
1575 | * Turn off MC4_MISC thresholding banks on those models since | |
1576 | * they're not supported there. | |
1577 | */ | |
1578 | if (c->x86 == 0x15 && | |
1579 | (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) { | |
1580 | int i; | |
1581 | u64 hwcr; | |
1582 | bool need_toggle; | |
1583 | u32 msrs[] = { | |
575203b4 BP |
1584 | 0x00000413, /* MC4_MISC0 */ |
1585 | 0xc0000408, /* MC4_MISC1 */ | |
c9ce8712 | 1586 | }; |
575203b4 | 1587 | |
c9ce8712 | 1588 | rdmsrl(MSR_K7_HWCR, hwcr); |
575203b4 | 1589 | |
c9ce8712 BP |
1590 | /* McStatusWrEn has to be set */ |
1591 | need_toggle = !(hwcr & BIT(18)); | |
575203b4 | 1592 | |
c9ce8712 BP |
1593 | if (need_toggle) |
1594 | wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); | |
575203b4 | 1595 | |
c9ce8712 BP |
1596 | /* Clear CntP bit safely */ |
1597 | for (i = 0; i < ARRAY_SIZE(msrs); i++) | |
1598 | msr_clear_bit(msrs[i], 62); | |
575203b4 | 1599 | |
c9ce8712 BP |
1600 | /* restore old settings */ |
1601 | if (need_toggle) | |
1602 | wrmsrl(MSR_K7_HWCR, hwcr); | |
1603 | } | |
1da177e4 | 1604 | } |
e583538f | 1605 | |
06b7a7a5 AK |
1606 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
1607 | /* | |
1608 | * SDM documents that on family 6 bank 0 should not be written | |
1609 | * because it aliases to another special BIOS controlled | |
1610 | * register. | |
1611 | * But it's not aliased anymore on model 0x1a+ | |
1612 | * Don't ignore bank 0 completely because there could be a | |
1613 | * valid event later, merely don't write CTL0. | |
1614 | */ | |
1615 | ||
d203f0b8 | 1616 | if (c->x86 == 6 && c->x86_model < 0x1A && cfg->banks > 0) |
cebe1820 | 1617 | mce_banks[0].init = 0; |
3c079792 AK |
1618 | |
1619 | /* | |
1620 | * All newer Intel systems support MCE broadcasting. Enable | |
1621 | * synchronization with a one second timeout. | |
1622 | */ | |
1623 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | |
84c2559d BP |
1624 | cfg->monarch_timeout < 0) |
1625 | cfg->monarch_timeout = USEC_PER_SEC; | |
c7f6fa44 | 1626 | |
e412cd25 IM |
1627 | /* |
1628 | * There are also broken BIOSes on some Pentium M and | |
1629 | * earlier systems: | |
1630 | */ | |
84c2559d BP |
1631 | if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0) |
1632 | cfg->bootlog = 0; | |
61b0fccd TL |
1633 | |
1634 | if (c->x86 == 6 && c->x86_model == 45) | |
1635 | quirk_no_way_out = quirk_sandybridge_ifu; | |
06b7a7a5 | 1636 | } |
84c2559d BP |
1637 | if (cfg->monarch_timeout < 0) |
1638 | cfg->monarch_timeout = 0; | |
1639 | if (cfg->bootlog != 0) | |
7af19e4a | 1640 | cfg->panic_timeout = 30; |
e412cd25 IM |
1641 | |
1642 | return 0; | |
d88203d1 | 1643 | } |
1da177e4 | 1644 | |
148f9bb8 | 1645 | static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) |
4efc0670 AK |
1646 | { |
1647 | if (c->x86 != 5) | |
3a97fc34 HS |
1648 | return 0; |
1649 | ||
4efc0670 AK |
1650 | switch (c->x86_vendor) { |
1651 | case X86_VENDOR_INTEL: | |
c6978369 | 1652 | intel_p5_mcheck_init(c); |
3a97fc34 | 1653 | return 1; |
4efc0670 AK |
1654 | break; |
1655 | case X86_VENDOR_CENTAUR: | |
1656 | winchip_mcheck_init(c); | |
3a97fc34 | 1657 | return 1; |
4efc0670 | 1658 | break; |
dc34bdd2 BP |
1659 | default: |
1660 | return 0; | |
4efc0670 | 1661 | } |
3a97fc34 HS |
1662 | |
1663 | return 0; | |
4efc0670 AK |
1664 | } |
1665 | ||
5204bf17 YG |
1666 | /* |
1667 | * Init basic CPU features needed for early decoding of MCEs. | |
1668 | */ | |
1669 | static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c) | |
1da177e4 | 1670 | { |
5204bf17 | 1671 | if (c->x86_vendor == X86_VENDOR_AMD) { |
14cddfd5 YG |
1672 | mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV); |
1673 | mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR); | |
1674 | mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA); | |
d9d73fcc | 1675 | |
d9d73fcc YG |
1676 | if (mce_flags.smca) { |
1677 | msr_ops.ctl = smca_ctl_reg; | |
1678 | msr_ops.status = smca_status_reg; | |
1679 | msr_ops.addr = smca_addr_reg; | |
1680 | msr_ops.misc = smca_misc_reg; | |
1681 | } | |
5204bf17 YG |
1682 | } |
1683 | } | |
c7f54d21 | 1684 | |
5204bf17 YG |
1685 | static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) |
1686 | { | |
1687 | switch (c->x86_vendor) { | |
1688 | case X86_VENDOR_INTEL: | |
1689 | mce_intel_feature_init(c); | |
1690 | mce_adjust_timer = cmci_intel_adjust_timer; | |
1691 | break; | |
c7f54d21 | 1692 | |
5204bf17 YG |
1693 | case X86_VENDOR_AMD: { |
1694 | mce_amd_feature_init(c); | |
89b831ef | 1695 | break; |
7559e13f AG |
1696 | } |
1697 | ||
1da177e4 LT |
1698 | default: |
1699 | break; | |
1700 | } | |
1701 | } | |
1702 | ||
8838eb6c AR |
1703 | static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c) |
1704 | { | |
1705 | switch (c->x86_vendor) { | |
1706 | case X86_VENDOR_INTEL: | |
1707 | mce_intel_feature_clear(c); | |
1708 | break; | |
1709 | default: | |
1710 | break; | |
1711 | } | |
1712 | } | |
1713 | ||
0becc0ae | 1714 | static void mce_start_timer(struct timer_list *t) |
52d168e2 | 1715 | { |
4f75d841 | 1716 | unsigned long iv = check_interval * HZ; |
bc09effa | 1717 | |
7af19e4a | 1718 | if (mca_cfg.ignore_ce || !iv) |
62fdac59 HS |
1719 | return; |
1720 | ||
0becc0ae TG |
1721 | this_cpu_write(mce_next_interval, iv); |
1722 | __start_timer(t, iv); | |
52d168e2 AK |
1723 | } |
1724 | ||
39f152ff SAS |
1725 | static void __mcheck_cpu_setup_timer(void) |
1726 | { | |
1727 | struct timer_list *t = this_cpu_ptr(&mce_timer); | |
1728 | unsigned int cpu = smp_processor_id(); | |
1729 | ||
1730 | setup_pinned_timer(t, mce_timer_fn, cpu); | |
1731 | } | |
1732 | ||
26c3c283 TG |
1733 | static void __mcheck_cpu_init_timer(void) |
1734 | { | |
89cbc767 | 1735 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
26c3c283 TG |
1736 | unsigned int cpu = smp_processor_id(); |
1737 | ||
f9c287ba | 1738 | setup_pinned_timer(t, mce_timer_fn, cpu); |
0becc0ae | 1739 | mce_start_timer(t); |
26c3c283 TG |
1740 | } |
1741 | ||
9eda8cb3 AK |
1742 | /* Handle unconfigured int18 (should never happen) */ |
1743 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
1744 | { | |
c767a54b | 1745 | pr_err("CPU#%d: Unexpected int18 (Machine Check)\n", |
9eda8cb3 AK |
1746 | smp_processor_id()); |
1747 | } | |
1748 | ||
1749 | /* Call the installed machine check handler for this CPU setup. */ | |
1750 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
1751 | unexpected_machine_check; | |
1752 | ||
d88203d1 | 1753 | /* |
1da177e4 | 1754 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 1755 | * Must be called with preempt off: |
1da177e4 | 1756 | */ |
148f9bb8 | 1757 | void mcheck_cpu_init(struct cpuinfo_x86 *c) |
1da177e4 | 1758 | { |
1462594b | 1759 | if (mca_cfg.disabled) |
4efc0670 AK |
1760 | return; |
1761 | ||
3a97fc34 HS |
1762 | if (__mcheck_cpu_ancient_init(c)) |
1763 | return; | |
4efc0670 | 1764 | |
5b4408fd | 1765 | if (!mce_available(c)) |
1da177e4 LT |
1766 | return; |
1767 | ||
5e09954a | 1768 | if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) { |
1462594b | 1769 | mca_cfg.disabled = true; |
0d7482e3 AK |
1770 | return; |
1771 | } | |
0d7482e3 | 1772 | |
648ed940 CG |
1773 | if (mce_gen_pool_init()) { |
1774 | mca_cfg.disabled = true; | |
1775 | pr_emerg("Couldn't allocate MCE records pool!\n"); | |
1776 | return; | |
1777 | } | |
1778 | ||
5d727926 AK |
1779 | machine_check_vector = do_machine_check; |
1780 | ||
5204bf17 | 1781 | __mcheck_cpu_init_early(c); |
5e09954a BP |
1782 | __mcheck_cpu_init_generic(); |
1783 | __mcheck_cpu_init_vendor(c); | |
bb91f8c0 | 1784 | __mcheck_cpu_init_clear_banks(); |
39f152ff | 1785 | __mcheck_cpu_setup_timer(); |
1da177e4 LT |
1786 | } |
1787 | ||
8838eb6c AR |
1788 | /* |
1789 | * Called for each booted CPU to clear some machine checks opt-ins | |
1790 | */ | |
1791 | void mcheck_cpu_clear(struct cpuinfo_x86 *c) | |
1792 | { | |
1793 | if (mca_cfg.disabled) | |
1794 | return; | |
1795 | ||
1796 | if (!mce_available(c)) | |
1797 | return; | |
1798 | ||
1799 | /* | |
1800 | * Possibly to clear general settings generic to x86 | |
1801 | * __mcheck_cpu_clear_generic(c); | |
1802 | */ | |
1803 | __mcheck_cpu_clear_vendor(c); | |
1804 | ||
1da177e4 LT |
1805 | } |
1806 | ||
c3d1fb56 NR |
1807 | static void __mce_disable_bank(void *arg) |
1808 | { | |
1809 | int bank = *((int *)arg); | |
89cbc767 | 1810 | __clear_bit(bank, this_cpu_ptr(mce_poll_banks)); |
c3d1fb56 NR |
1811 | cmci_disable_bank(bank); |
1812 | } | |
1813 | ||
1814 | void mce_disable_bank(int bank) | |
1815 | { | |
1816 | if (bank >= mca_cfg.banks) { | |
1817 | pr_warn(FW_BUG | |
1818 | "Ignoring request to disable invalid MCA bank %d.\n", | |
1819 | bank); | |
1820 | return; | |
1821 | } | |
1822 | set_bit(bank, mce_banks_ce_disabled); | |
1823 | on_each_cpu(__mce_disable_bank, &bank, 1); | |
1824 | } | |
1825 | ||
13503fa9 | 1826 | /* |
62fdac59 HS |
1827 | * mce=off Disables machine check |
1828 | * mce=no_cmci Disables CMCI | |
88d53867 | 1829 | * mce=no_lmce Disables LMCE |
62fdac59 HS |
1830 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. |
1831 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. | |
3c079792 AK |
1832 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
1833 | * monarchtimeout is how long to wait for other CPUs on machine | |
1834 | * check, or 0 to not wait | |
13503fa9 HS |
1835 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
1836 | * mce=nobootlog Don't log MCEs from before booting. | |
450cc201 | 1837 | * mce=bios_cmci_threshold Don't program the CMCI threshold |
3637efb0 | 1838 | * mce=recovery force enable memcpy_mcsafe() |
13503fa9 | 1839 | */ |
1da177e4 LT |
1840 | static int __init mcheck_enable(char *str) |
1841 | { | |
d203f0b8 BP |
1842 | struct mca_config *cfg = &mca_cfg; |
1843 | ||
e3346fc4 | 1844 | if (*str == 0) { |
4efc0670 | 1845 | enable_p5_mce(); |
e3346fc4 BZ |
1846 | return 1; |
1847 | } | |
4efc0670 AK |
1848 | if (*str == '=') |
1849 | str++; | |
1da177e4 | 1850 | if (!strcmp(str, "off")) |
1462594b | 1851 | cfg->disabled = true; |
62fdac59 | 1852 | else if (!strcmp(str, "no_cmci")) |
7af19e4a | 1853 | cfg->cmci_disabled = true; |
88d53867 AR |
1854 | else if (!strcmp(str, "no_lmce")) |
1855 | cfg->lmce_disabled = true; | |
62fdac59 | 1856 | else if (!strcmp(str, "dont_log_ce")) |
d203f0b8 | 1857 | cfg->dont_log_ce = true; |
62fdac59 | 1858 | else if (!strcmp(str, "ignore_ce")) |
7af19e4a | 1859 | cfg->ignore_ce = true; |
13503fa9 | 1860 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
84c2559d | 1861 | cfg->bootlog = (str[0] == 'b'); |
450cc201 | 1862 | else if (!strcmp(str, "bios_cmci_threshold")) |
1462594b | 1863 | cfg->bios_cmci_threshold = true; |
0f68c088 TL |
1864 | else if (!strcmp(str, "recovery")) |
1865 | cfg->recovery = true; | |
3c079792 | 1866 | else if (isdigit(str[0])) { |
5c31b280 | 1867 | if (get_option(&str, &cfg->tolerant) == 2) |
84c2559d | 1868 | get_option(&str, &(cfg->monarch_timeout)); |
3c079792 | 1869 | } else { |
c767a54b | 1870 | pr_info("mce argument %s ignored. Please use /sys\n", str); |
13503fa9 HS |
1871 | return 0; |
1872 | } | |
9b41046c | 1873 | return 1; |
1da177e4 | 1874 | } |
4efc0670 | 1875 | __setup("mce", mcheck_enable); |
1da177e4 | 1876 | |
a2202aa2 | 1877 | int __init mcheck_init(void) |
b33a6363 | 1878 | { |
a2202aa2 | 1879 | mcheck_intel_therm_init(); |
011d8261 | 1880 | mce_register_decode_chain(&first_nb); |
eef4dfa0 | 1881 | mce_register_decode_chain(&mce_srao_nb); |
cd9c57ca | 1882 | mce_register_decode_chain(&mce_default_nb); |
43eaa2a1 | 1883 | mcheck_vendor_init_severity(); |
a2202aa2 | 1884 | |
cff4c039 | 1885 | INIT_WORK(&mce_work, mce_gen_pool_process); |
061120ae CG |
1886 | init_irq_work(&mce_irq_work, mce_irq_work_cb); |
1887 | ||
b33a6363 BP |
1888 | return 0; |
1889 | } | |
b33a6363 | 1890 | |
d88203d1 | 1891 | /* |
c7cece89 | 1892 | * mce_syscore: PM support |
d88203d1 | 1893 | */ |
1da177e4 | 1894 | |
973a2dd1 AK |
1895 | /* |
1896 | * Disable machine checks on suspend and shutdown. We can't really handle | |
1897 | * them later. | |
1898 | */ | |
6e06780a | 1899 | static void mce_disable_error_reporting(void) |
973a2dd1 AK |
1900 | { |
1901 | int i; | |
1902 | ||
d203f0b8 | 1903 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 1904 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1905 | |
cebe1820 | 1906 | if (b->init) |
d9d73fcc | 1907 | wrmsrl(msr_ops.ctl(i), 0); |
06b7a7a5 | 1908 | } |
6e06780a AR |
1909 | return; |
1910 | } | |
1911 | ||
1912 | static void vendor_disable_error_reporting(void) | |
1913 | { | |
1914 | /* | |
1915 | * Don't clear on Intel CPUs. Some of these MSRs are socket-wide. | |
1916 | * Disabling them for just a single offlined CPU is bad, since it will | |
1917 | * inhibit reporting for all shared resources on the socket like the | |
1918 | * last level cache (LLC), the integrated memory controller (iMC), etc. | |
1919 | */ | |
1920 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) | |
1921 | return; | |
1922 | ||
1923 | mce_disable_error_reporting(); | |
973a2dd1 AK |
1924 | } |
1925 | ||
c7cece89 | 1926 | static int mce_syscore_suspend(void) |
973a2dd1 | 1927 | { |
6e06780a AR |
1928 | vendor_disable_error_reporting(); |
1929 | return 0; | |
973a2dd1 AK |
1930 | } |
1931 | ||
c7cece89 | 1932 | static void mce_syscore_shutdown(void) |
973a2dd1 | 1933 | { |
6e06780a | 1934 | vendor_disable_error_reporting(); |
973a2dd1 AK |
1935 | } |
1936 | ||
e9eee03e IM |
1937 | /* |
1938 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
1939 | * Only one CPU is active at this time, the others get re-added later using | |
1940 | * CPU hotplug: | |
1941 | */ | |
c7cece89 | 1942 | static void mce_syscore_resume(void) |
1da177e4 | 1943 | { |
5e09954a | 1944 | __mcheck_cpu_init_generic(); |
89cbc767 | 1945 | __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); |
bb91f8c0 | 1946 | __mcheck_cpu_init_clear_banks(); |
1da177e4 LT |
1947 | } |
1948 | ||
f3c6ea1b | 1949 | static struct syscore_ops mce_syscore_ops = { |
c7cece89 HS |
1950 | .suspend = mce_syscore_suspend, |
1951 | .shutdown = mce_syscore_shutdown, | |
1952 | .resume = mce_syscore_resume, | |
f3c6ea1b RW |
1953 | }; |
1954 | ||
c7cece89 | 1955 | /* |
8a25a2fd | 1956 | * mce_device: Sysfs support |
c7cece89 HS |
1957 | */ |
1958 | ||
52d168e2 AK |
1959 | static void mce_cpu_restart(void *data) |
1960 | { | |
89cbc767 | 1961 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
33edbf02 | 1962 | return; |
5e09954a | 1963 | __mcheck_cpu_init_generic(); |
bb91f8c0 | 1964 | __mcheck_cpu_init_clear_banks(); |
5e09954a | 1965 | __mcheck_cpu_init_timer(); |
52d168e2 AK |
1966 | } |
1967 | ||
1da177e4 | 1968 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
1969 | static void mce_restart(void) |
1970 | { | |
9aaef96f | 1971 | mce_timer_delete_all(); |
52d168e2 | 1972 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
1973 | } |
1974 | ||
9af43b54 | 1975 | /* Toggle features for corrected errors */ |
9aaef96f | 1976 | static void mce_disable_cmci(void *data) |
9af43b54 | 1977 | { |
89cbc767 | 1978 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
9af43b54 | 1979 | return; |
9af43b54 HS |
1980 | cmci_clear(); |
1981 | } | |
1982 | ||
1983 | static void mce_enable_ce(void *all) | |
1984 | { | |
89cbc767 | 1985 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
9af43b54 HS |
1986 | return; |
1987 | cmci_reenable(); | |
1988 | cmci_recheck(); | |
1989 | if (all) | |
5e09954a | 1990 | __mcheck_cpu_init_timer(); |
9af43b54 HS |
1991 | } |
1992 | ||
8a25a2fd | 1993 | static struct bus_type mce_subsys = { |
e9eee03e | 1994 | .name = "machinecheck", |
8a25a2fd | 1995 | .dev_name = "machinecheck", |
1da177e4 LT |
1996 | }; |
1997 | ||
d6126ef5 | 1998 | DEFINE_PER_CPU(struct device *, mce_device); |
e9eee03e | 1999 | |
8a25a2fd | 2000 | static inline struct mce_bank *attr_to_bank(struct device_attribute *attr) |
cebe1820 AK |
2001 | { |
2002 | return container_of(attr, struct mce_bank, attr); | |
2003 | } | |
0d7482e3 | 2004 | |
8a25a2fd | 2005 | static ssize_t show_bank(struct device *s, struct device_attribute *attr, |
0d7482e3 AK |
2006 | char *buf) |
2007 | { | |
cebe1820 | 2008 | return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); |
0d7482e3 AK |
2009 | } |
2010 | ||
8a25a2fd | 2011 | static ssize_t set_bank(struct device *s, struct device_attribute *attr, |
9319cec8 | 2012 | const char *buf, size_t size) |
0d7482e3 | 2013 | { |
9319cec8 | 2014 | u64 new; |
e9eee03e | 2015 | |
164109e3 | 2016 | if (kstrtou64(buf, 0, &new) < 0) |
0d7482e3 | 2017 | return -EINVAL; |
e9eee03e | 2018 | |
cebe1820 | 2019 | attr_to_bank(attr)->ctl = new; |
0d7482e3 | 2020 | mce_restart(); |
e9eee03e | 2021 | |
9319cec8 | 2022 | return size; |
0d7482e3 | 2023 | } |
a98f0dd3 | 2024 | |
8a25a2fd KS |
2025 | static ssize_t set_ignore_ce(struct device *s, |
2026 | struct device_attribute *attr, | |
9af43b54 HS |
2027 | const char *buf, size_t size) |
2028 | { | |
2029 | u64 new; | |
2030 | ||
164109e3 | 2031 | if (kstrtou64(buf, 0, &new) < 0) |
9af43b54 HS |
2032 | return -EINVAL; |
2033 | ||
7af19e4a | 2034 | if (mca_cfg.ignore_ce ^ !!new) { |
9af43b54 HS |
2035 | if (new) { |
2036 | /* disable ce features */ | |
9aaef96f HS |
2037 | mce_timer_delete_all(); |
2038 | on_each_cpu(mce_disable_cmci, NULL, 1); | |
7af19e4a | 2039 | mca_cfg.ignore_ce = true; |
9af43b54 HS |
2040 | } else { |
2041 | /* enable ce features */ | |
7af19e4a | 2042 | mca_cfg.ignore_ce = false; |
9af43b54 HS |
2043 | on_each_cpu(mce_enable_ce, (void *)1, 1); |
2044 | } | |
2045 | } | |
2046 | return size; | |
2047 | } | |
2048 | ||
8a25a2fd KS |
2049 | static ssize_t set_cmci_disabled(struct device *s, |
2050 | struct device_attribute *attr, | |
9af43b54 HS |
2051 | const char *buf, size_t size) |
2052 | { | |
2053 | u64 new; | |
2054 | ||
164109e3 | 2055 | if (kstrtou64(buf, 0, &new) < 0) |
9af43b54 HS |
2056 | return -EINVAL; |
2057 | ||
7af19e4a | 2058 | if (mca_cfg.cmci_disabled ^ !!new) { |
9af43b54 HS |
2059 | if (new) { |
2060 | /* disable cmci */ | |
9aaef96f | 2061 | on_each_cpu(mce_disable_cmci, NULL, 1); |
7af19e4a | 2062 | mca_cfg.cmci_disabled = true; |
9af43b54 HS |
2063 | } else { |
2064 | /* enable cmci */ | |
7af19e4a | 2065 | mca_cfg.cmci_disabled = false; |
9af43b54 HS |
2066 | on_each_cpu(mce_enable_ce, NULL, 1); |
2067 | } | |
2068 | } | |
2069 | return size; | |
2070 | } | |
2071 | ||
8a25a2fd KS |
2072 | static ssize_t store_int_with_restart(struct device *s, |
2073 | struct device_attribute *attr, | |
b56f642d AK |
2074 | const char *buf, size_t size) |
2075 | { | |
8a25a2fd | 2076 | ssize_t ret = device_store_int(s, attr, buf, size); |
b56f642d AK |
2077 | mce_restart(); |
2078 | return ret; | |
2079 | } | |
2080 | ||
d203f0b8 | 2081 | static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant); |
84c2559d | 2082 | static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout); |
d203f0b8 | 2083 | static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce); |
e9eee03e | 2084 | |
8a25a2fd KS |
2085 | static struct dev_ext_attribute dev_attr_check_interval = { |
2086 | __ATTR(check_interval, 0644, device_show_int, store_int_with_restart), | |
b56f642d AK |
2087 | &check_interval |
2088 | }; | |
e9eee03e | 2089 | |
8a25a2fd | 2090 | static struct dev_ext_attribute dev_attr_ignore_ce = { |
7af19e4a BP |
2091 | __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce), |
2092 | &mca_cfg.ignore_ce | |
9af43b54 HS |
2093 | }; |
2094 | ||
8a25a2fd | 2095 | static struct dev_ext_attribute dev_attr_cmci_disabled = { |
7af19e4a BP |
2096 | __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled), |
2097 | &mca_cfg.cmci_disabled | |
9af43b54 HS |
2098 | }; |
2099 | ||
8a25a2fd KS |
2100 | static struct device_attribute *mce_device_attrs[] = { |
2101 | &dev_attr_tolerant.attr, | |
2102 | &dev_attr_check_interval.attr, | |
5de97c9f | 2103 | #ifdef CONFIG_X86_MCELOG_LEGACY |
8a25a2fd | 2104 | &dev_attr_trigger, |
5de97c9f | 2105 | #endif |
8a25a2fd KS |
2106 | &dev_attr_monarch_timeout.attr, |
2107 | &dev_attr_dont_log_ce.attr, | |
2108 | &dev_attr_ignore_ce.attr, | |
2109 | &dev_attr_cmci_disabled.attr, | |
a98f0dd3 AK |
2110 | NULL |
2111 | }; | |
1da177e4 | 2112 | |
8a25a2fd | 2113 | static cpumask_var_t mce_device_initialized; |
bae19fe0 | 2114 | |
e032d807 GKH |
2115 | static void mce_device_release(struct device *dev) |
2116 | { | |
2117 | kfree(dev); | |
2118 | } | |
2119 | ||
8a25a2fd | 2120 | /* Per cpu device init. All of the cpus still share the same ctrl bank: */ |
148f9bb8 | 2121 | static int mce_device_create(unsigned int cpu) |
1da177e4 | 2122 | { |
e032d807 | 2123 | struct device *dev; |
1da177e4 | 2124 | int err; |
b1f49f95 | 2125 | int i, j; |
92cb7612 | 2126 | |
90367556 | 2127 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
2128 | return -EIO; |
2129 | ||
7f34b935 SAS |
2130 | dev = per_cpu(mce_device, cpu); |
2131 | if (dev) | |
2132 | return 0; | |
2133 | ||
e032d807 GKH |
2134 | dev = kzalloc(sizeof *dev, GFP_KERNEL); |
2135 | if (!dev) | |
2136 | return -ENOMEM; | |
8a25a2fd KS |
2137 | dev->id = cpu; |
2138 | dev->bus = &mce_subsys; | |
e032d807 | 2139 | dev->release = &mce_device_release; |
91c6d400 | 2140 | |
8a25a2fd | 2141 | err = device_register(dev); |
853d9b18 LK |
2142 | if (err) { |
2143 | put_device(dev); | |
d435d862 | 2144 | return err; |
853d9b18 | 2145 | } |
d435d862 | 2146 | |
8a25a2fd KS |
2147 | for (i = 0; mce_device_attrs[i]; i++) { |
2148 | err = device_create_file(dev, mce_device_attrs[i]); | |
d435d862 AM |
2149 | if (err) |
2150 | goto error; | |
2151 | } | |
d203f0b8 | 2152 | for (j = 0; j < mca_cfg.banks; j++) { |
8a25a2fd | 2153 | err = device_create_file(dev, &mce_banks[j].attr); |
0d7482e3 AK |
2154 | if (err) |
2155 | goto error2; | |
2156 | } | |
8a25a2fd | 2157 | cpumask_set_cpu(cpu, mce_device_initialized); |
d6126ef5 | 2158 | per_cpu(mce_device, cpu) = dev; |
91c6d400 | 2159 | |
d435d862 | 2160 | return 0; |
0d7482e3 | 2161 | error2: |
b1f49f95 | 2162 | while (--j >= 0) |
8a25a2fd | 2163 | device_remove_file(dev, &mce_banks[j].attr); |
d435d862 | 2164 | error: |
cb491fca | 2165 | while (--i >= 0) |
8a25a2fd | 2166 | device_remove_file(dev, mce_device_attrs[i]); |
cb491fca | 2167 | |
8a25a2fd | 2168 | device_unregister(dev); |
d435d862 | 2169 | |
91c6d400 AK |
2170 | return err; |
2171 | } | |
2172 | ||
148f9bb8 | 2173 | static void mce_device_remove(unsigned int cpu) |
91c6d400 | 2174 | { |
d6126ef5 | 2175 | struct device *dev = per_cpu(mce_device, cpu); |
73ca5358 SL |
2176 | int i; |
2177 | ||
8a25a2fd | 2178 | if (!cpumask_test_cpu(cpu, mce_device_initialized)) |
bae19fe0 AH |
2179 | return; |
2180 | ||
8a25a2fd KS |
2181 | for (i = 0; mce_device_attrs[i]; i++) |
2182 | device_remove_file(dev, mce_device_attrs[i]); | |
cb491fca | 2183 | |
d203f0b8 | 2184 | for (i = 0; i < mca_cfg.banks; i++) |
8a25a2fd | 2185 | device_remove_file(dev, &mce_banks[i].attr); |
cb491fca | 2186 | |
8a25a2fd KS |
2187 | device_unregister(dev); |
2188 | cpumask_clear_cpu(cpu, mce_device_initialized); | |
d6126ef5 | 2189 | per_cpu(mce_device, cpu) = NULL; |
91c6d400 | 2190 | } |
91c6d400 | 2191 | |
d6b75584 | 2192 | /* Make sure there are no machine checks on offlined CPUs. */ |
39f152ff | 2193 | static void mce_disable_cpu(void) |
d6b75584 | 2194 | { |
89cbc767 | 2195 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
d6b75584 | 2196 | return; |
767df1bd | 2197 | |
39f152ff | 2198 | if (!cpuhp_tasks_frozen) |
88ccbedd | 2199 | cmci_clear(); |
11868a2d | 2200 | |
6e06780a | 2201 | vendor_disable_error_reporting(); |
d6b75584 AK |
2202 | } |
2203 | ||
39f152ff | 2204 | static void mce_reenable_cpu(void) |
d6b75584 | 2205 | { |
e9eee03e | 2206 | int i; |
d6b75584 | 2207 | |
89cbc767 | 2208 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
d6b75584 | 2209 | return; |
e9eee03e | 2210 | |
39f152ff | 2211 | if (!cpuhp_tasks_frozen) |
88ccbedd | 2212 | cmci_reenable(); |
d203f0b8 | 2213 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2214 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2215 | |
cebe1820 | 2216 | if (b->init) |
d9d73fcc | 2217 | wrmsrl(msr_ops.ctl(i), b->ctl); |
06b7a7a5 | 2218 | } |
d6b75584 AK |
2219 | } |
2220 | ||
0e285d36 | 2221 | static int mce_cpu_dead(unsigned int cpu) |
91c6d400 | 2222 | { |
0e285d36 | 2223 | mce_intel_hcpu_update(cpu); |
91c6d400 | 2224 | |
0e285d36 SAS |
2225 | /* intentionally ignoring frozen here */ |
2226 | if (!cpuhp_tasks_frozen) | |
2227 | cmci_rediscover(); | |
2228 | return 0; | |
91c6d400 AK |
2229 | } |
2230 | ||
8c0eeac8 | 2231 | static int mce_cpu_online(unsigned int cpu) |
91c6d400 | 2232 | { |
0becc0ae | 2233 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
8c0eeac8 | 2234 | int ret; |
91c6d400 | 2235 | |
8c0eeac8 | 2236 | mce_device_create(cpu); |
38356c1f | 2237 | |
8c0eeac8 SAS |
2238 | ret = mce_threshold_create_device(cpu); |
2239 | if (ret) { | |
2240 | mce_device_remove(cpu); | |
2241 | return ret; | |
1a65f970 | 2242 | } |
8c0eeac8 | 2243 | mce_reenable_cpu(); |
0becc0ae | 2244 | mce_start_timer(t); |
8c0eeac8 | 2245 | return 0; |
91c6d400 AK |
2246 | } |
2247 | ||
8c0eeac8 SAS |
2248 | static int mce_cpu_pre_down(unsigned int cpu) |
2249 | { | |
0becc0ae | 2250 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
8c0eeac8 SAS |
2251 | |
2252 | mce_disable_cpu(); | |
2253 | del_timer_sync(t); | |
2254 | mce_threshold_remove_device(cpu); | |
2255 | mce_device_remove(cpu); | |
2256 | return 0; | |
2257 | } | |
91c6d400 | 2258 | |
cebe1820 | 2259 | static __init void mce_init_banks(void) |
0d7482e3 AK |
2260 | { |
2261 | int i; | |
2262 | ||
d203f0b8 | 2263 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2264 | struct mce_bank *b = &mce_banks[i]; |
8a25a2fd | 2265 | struct device_attribute *a = &b->attr; |
e9eee03e | 2266 | |
a07e4156 | 2267 | sysfs_attr_init(&a->attr); |
cebe1820 AK |
2268 | a->attr.name = b->attrname; |
2269 | snprintf(b->attrname, ATTR_LEN, "bank%d", i); | |
e9eee03e IM |
2270 | |
2271 | a->attr.mode = 0644; | |
2272 | a->show = show_bank; | |
2273 | a->store = set_bank; | |
0d7482e3 | 2274 | } |
0d7482e3 AK |
2275 | } |
2276 | ||
5e09954a | 2277 | static __init int mcheck_init_device(void) |
91c6d400 AK |
2278 | { |
2279 | int err; | |
91c6d400 | 2280 | |
9c15a24b MS |
2281 | if (!mce_available(&boot_cpu_data)) { |
2282 | err = -EIO; | |
2283 | goto err_out; | |
2284 | } | |
0d7482e3 | 2285 | |
9c15a24b MS |
2286 | if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) { |
2287 | err = -ENOMEM; | |
2288 | goto err_out; | |
2289 | } | |
996867d0 | 2290 | |
cebe1820 | 2291 | mce_init_banks(); |
0d7482e3 | 2292 | |
8a25a2fd | 2293 | err = subsys_system_register(&mce_subsys, NULL); |
d435d862 | 2294 | if (err) |
9c15a24b | 2295 | goto err_out_mem; |
91c6d400 | 2296 | |
0e285d36 SAS |
2297 | err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL, |
2298 | mce_cpu_dead); | |
2299 | if (err) | |
2300 | goto err_out_mem; | |
91c6d400 | 2301 | |
8c0eeac8 SAS |
2302 | err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online", |
2303 | mce_cpu_online, mce_cpu_pre_down); | |
2304 | if (err < 0) | |
0e285d36 | 2305 | goto err_out_online; |
93b62c3c | 2306 | |
9c15a24b MS |
2307 | register_syscore_ops(&mce_syscore_ops); |
2308 | ||
9c15a24b MS |
2309 | return 0; |
2310 | ||
0e285d36 SAS |
2311 | err_out_online: |
2312 | cpuhp_remove_state(CPUHP_X86_MCE_DEAD); | |
9c15a24b MS |
2313 | |
2314 | err_out_mem: | |
2315 | free_cpumask_var(mce_device_initialized); | |
2316 | ||
2317 | err_out: | |
5de97c9f | 2318 | pr_err("Unable to init MCE device (rc: %d)\n", err); |
e9eee03e | 2319 | |
1da177e4 | 2320 | return err; |
1da177e4 | 2321 | } |
cef12ee5 | 2322 | device_initcall_sync(mcheck_init_device); |
a988d334 | 2323 | |
d7c3c9a6 AK |
2324 | /* |
2325 | * Old style boot options parsing. Only for compatibility. | |
2326 | */ | |
2327 | static int __init mcheck_disable(char *str) | |
2328 | { | |
1462594b | 2329 | mca_cfg.disabled = true; |
d7c3c9a6 AK |
2330 | return 1; |
2331 | } | |
2332 | __setup("nomce", mcheck_disable); | |
a988d334 | 2333 | |
5be9ed25 HY |
2334 | #ifdef CONFIG_DEBUG_FS |
2335 | struct dentry *mce_get_debugfs_dir(void) | |
a988d334 | 2336 | { |
5be9ed25 | 2337 | static struct dentry *dmce; |
a988d334 | 2338 | |
5be9ed25 HY |
2339 | if (!dmce) |
2340 | dmce = debugfs_create_dir("mce", NULL); | |
a988d334 | 2341 | |
5be9ed25 HY |
2342 | return dmce; |
2343 | } | |
a988d334 | 2344 | |
bf783f9f HY |
2345 | static void mce_reset(void) |
2346 | { | |
2347 | cpu_missing = 0; | |
c7c9b392 | 2348 | atomic_set(&mce_fake_panicked, 0); |
bf783f9f HY |
2349 | atomic_set(&mce_executing, 0); |
2350 | atomic_set(&mce_callin, 0); | |
2351 | atomic_set(&global_nwo, 0); | |
2352 | } | |
a988d334 | 2353 | |
bf783f9f HY |
2354 | static int fake_panic_get(void *data, u64 *val) |
2355 | { | |
2356 | *val = fake_panic; | |
2357 | return 0; | |
a988d334 IM |
2358 | } |
2359 | ||
bf783f9f | 2360 | static int fake_panic_set(void *data, u64 val) |
a988d334 | 2361 | { |
bf783f9f HY |
2362 | mce_reset(); |
2363 | fake_panic = val; | |
2364 | return 0; | |
a988d334 | 2365 | } |
a988d334 | 2366 | |
bf783f9f HY |
2367 | DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, |
2368 | fake_panic_set, "%llu\n"); | |
d7c3c9a6 | 2369 | |
5e09954a | 2370 | static int __init mcheck_debugfs_init(void) |
d7c3c9a6 | 2371 | { |
bf783f9f HY |
2372 | struct dentry *dmce, *ffake_panic; |
2373 | ||
2374 | dmce = mce_get_debugfs_dir(); | |
2375 | if (!dmce) | |
2376 | return -ENOMEM; | |
2377 | ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, | |
2378 | &fake_panic_fops); | |
2379 | if (!ffake_panic) | |
2380 | return -ENOMEM; | |
2381 | ||
2382 | return 0; | |
d7c3c9a6 | 2383 | } |
fd4cf79f CG |
2384 | #else |
2385 | static int __init mcheck_debugfs_init(void) { return -EINVAL; } | |
5be9ed25 | 2386 | #endif |
fd4cf79f | 2387 | |
3637efb0 TL |
2388 | DEFINE_STATIC_KEY_FALSE(mcsafe_key); |
2389 | EXPORT_SYMBOL_GPL(mcsafe_key); | |
2390 | ||
fd4cf79f CG |
2391 | static int __init mcheck_late_init(void) |
2392 | { | |
3637efb0 TL |
2393 | if (mca_cfg.recovery) |
2394 | static_branch_inc(&mcsafe_key); | |
2395 | ||
fd4cf79f | 2396 | mcheck_debugfs_init(); |
011d8261 | 2397 | cec_init(); |
fd4cf79f CG |
2398 | |
2399 | /* | |
2400 | * Flush out everything that has been logged during early boot, now that | |
2401 | * everything has been initialized (workqueues, decoders, ...). | |
2402 | */ | |
2403 | mce_schedule_work(); | |
2404 | ||
2405 | return 0; | |
2406 | } | |
2407 | late_initcall(mcheck_late_init); |