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Commit | Line | Data |
---|---|---|
a1a499a3 JSR |
1 | /* |
2 | * This only handles 32bit MTRR on 32bit hosts. This is strictly wrong | |
0d2eb44f | 3 | * because MTRRs can span up to 40 bits (36bits on most modern x86) |
a1a499a3 JSR |
4 | */ |
5 | #define DEBUG | |
6 | ||
7 | #include <linux/module.h> | |
1da177e4 | 8 | #include <linux/init.h> |
a1a499a3 | 9 | #include <linux/io.h> |
1da177e4 | 10 | #include <linux/mm.h> |
a1a499a3 | 11 | |
7ebad705 | 12 | #include <asm/processor-flags.h> |
a1a499a3 | 13 | #include <asm/cpufeature.h> |
1da177e4 | 14 | #include <asm/tlbflush.h> |
a1a499a3 JSR |
15 | #include <asm/mtrr.h> |
16 | #include <asm/msr.h> | |
2e5d9c85 | 17 | #include <asm/pat.h> |
a1a499a3 | 18 | |
1da177e4 LT |
19 | #include "mtrr.h" |
20 | ||
de938c51 | 21 | struct fixed_range_block { |
a1a499a3 JSR |
22 | int base_msr; /* start address of an MTRR block */ |
23 | int ranges; /* number of MTRRs in this block */ | |
de938c51 BK |
24 | }; |
25 | ||
26 | static struct fixed_range_block fixed_range_blocks[] = { | |
a1a499a3 JSR |
27 | { MSR_MTRRfix64K_00000, 1 }, /* one 64k MTRR */ |
28 | { MSR_MTRRfix16K_80000, 2 }, /* two 16k MTRRs */ | |
29 | { MSR_MTRRfix4K_C0000, 8 }, /* eight 4k MTRRs */ | |
de938c51 BK |
30 | {} |
31 | }; | |
32 | ||
1da177e4 | 33 | static unsigned long smp_changes_mask; |
2e5d9c85 | 34 | static int mtrr_state_set; |
95ffa243 | 35 | u64 mtrr_tom2; |
1da177e4 | 36 | |
a1a499a3 | 37 | struct mtrr_state_type mtrr_state; |
932d27a7 SY |
38 | EXPORT_SYMBOL_GPL(mtrr_state); |
39 | ||
a1a499a3 | 40 | /* |
3ff42da5 AH |
41 | * BIOS is expected to clear MtrrFixDramModEn bit, see for example |
42 | * "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD | |
43 | * Opteron Processors" (26094 Rev. 3.30 February 2006), section | |
44 | * "13.2.1.2 SYSCFG Register": "The MtrrFixDramModEn bit should be set | |
45 | * to 1 during BIOS initalization of the fixed MTRRs, then cleared to | |
46 | * 0 for operation." | |
47 | */ | |
48 | static inline void k8_check_syscfg_dram_mod_en(void) | |
49 | { | |
50 | u32 lo, hi; | |
51 | ||
52 | if (!((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && | |
53 | (boot_cpu_data.x86 >= 0x0f))) | |
54 | return; | |
55 | ||
56 | rdmsr(MSR_K8_SYSCFG, lo, hi); | |
57 | if (lo & K8_MTRRFIXRANGE_DRAM_MODIFY) { | |
58 | printk(KERN_ERR FW_WARN "MTRR: CPU %u: SYSCFG[MtrrFixDramModEn]" | |
59 | " not cleared by BIOS, clearing this bit\n", | |
60 | smp_processor_id()); | |
61 | lo &= ~K8_MTRRFIXRANGE_DRAM_MODIFY; | |
62 | mtrr_wrmsr(MSR_K8_SYSCFG, lo, hi); | |
63 | } | |
64 | } | |
65 | ||
351e5a70 VP |
66 | /* Get the size of contiguous MTRR range */ |
67 | static u64 get_mtrr_size(u64 mask) | |
68 | { | |
69 | u64 size; | |
70 | ||
71 | mask >>= PAGE_SHIFT; | |
72 | mask |= size_or_mask; | |
73 | size = -mask; | |
74 | size <<= PAGE_SHIFT; | |
75 | return size; | |
76 | } | |
77 | ||
a7f07cfb VP |
78 | /* |
79 | * Check and return the effective type for MTRR-MTRR type overlap. | |
80 | * Returns 1 if the effective type is UNCACHEABLE, else returns 0 | |
81 | */ | |
82 | static int check_type_overlap(u8 *prev, u8 *curr) | |
83 | { | |
84 | if (*prev == MTRR_TYPE_UNCACHABLE || *curr == MTRR_TYPE_UNCACHABLE) { | |
85 | *prev = MTRR_TYPE_UNCACHABLE; | |
86 | *curr = MTRR_TYPE_UNCACHABLE; | |
87 | return 1; | |
88 | } | |
89 | ||
90 | if ((*prev == MTRR_TYPE_WRBACK && *curr == MTRR_TYPE_WRTHROUGH) || | |
91 | (*prev == MTRR_TYPE_WRTHROUGH && *curr == MTRR_TYPE_WRBACK)) { | |
92 | *prev = MTRR_TYPE_WRTHROUGH; | |
93 | *curr = MTRR_TYPE_WRTHROUGH; | |
94 | } | |
95 | ||
96 | if (*prev != *curr) { | |
97 | *prev = MTRR_TYPE_UNCACHABLE; | |
98 | *curr = MTRR_TYPE_UNCACHABLE; | |
99 | return 1; | |
100 | } | |
101 | ||
102 | return 0; | |
103 | } | |
104 | ||
2e5d9c85 | 105 | /* |
351e5a70 | 106 | * Error/Semi-error returns: |
3d3ca416 | 107 | * MTRR_TYPE_INVALID - when MTRR is not enabled |
351e5a70 VP |
108 | * *repeat == 1 implies [start:end] spanned across MTRR range and type returned |
109 | * corresponds only to [start:*partial_end]. | |
110 | * Caller has to lookup again for [*partial_end:end]. | |
2e5d9c85 | 111 | */ |
351e5a70 | 112 | static u8 __mtrr_type_lookup(u64 start, u64 end, u64 *partial_end, int *repeat) |
2e5d9c85 | 113 | { |
114 | int i; | |
115 | u64 base, mask; | |
116 | u8 prev_match, curr_match; | |
117 | ||
351e5a70 | 118 | *repeat = 0; |
2e5d9c85 | 119 | if (!mtrr_state_set) |
3d3ca416 | 120 | return MTRR_TYPE_INVALID; |
2e5d9c85 | 121 | |
9b3aca62 | 122 | if (!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED)) |
3d3ca416 | 123 | return MTRR_TYPE_INVALID; |
2e5d9c85 | 124 | |
125 | /* Make end inclusive end, instead of exclusive */ | |
126 | end--; | |
127 | ||
128 | /* Look in fixed ranges. Just return the type as per start */ | |
9b3aca62 TK |
129 | if ((start < 0x100000) && |
130 | (mtrr_state.have_fixed) && | |
131 | (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED)) { | |
2e5d9c85 | 132 | int idx; |
133 | ||
134 | if (start < 0x80000) { | |
135 | idx = 0; | |
136 | idx += (start >> 16); | |
137 | return mtrr_state.fixed_ranges[idx]; | |
138 | } else if (start < 0xC0000) { | |
139 | idx = 1 * 8; | |
140 | idx += ((start - 0x80000) >> 14); | |
141 | return mtrr_state.fixed_ranges[idx]; | |
cd2f6a5a | 142 | } else { |
2e5d9c85 | 143 | idx = 3 * 8; |
144 | idx += ((start - 0xC0000) >> 12); | |
145 | return mtrr_state.fixed_ranges[idx]; | |
146 | } | |
147 | } | |
148 | ||
149 | /* | |
150 | * Look in variable ranges | |
151 | * Look of multiple ranges matching this address and pick type | |
152 | * as per MTRR precedence | |
153 | */ | |
3d3ca416 | 154 | prev_match = MTRR_TYPE_INVALID; |
2e5d9c85 | 155 | for (i = 0; i < num_var_ranges; ++i) { |
7f0431e3 | 156 | unsigned short start_state, end_state, inclusive; |
2e5d9c85 | 157 | |
158 | if (!(mtrr_state.var_ranges[i].mask_lo & (1 << 11))) | |
159 | continue; | |
160 | ||
161 | base = (((u64)mtrr_state.var_ranges[i].base_hi) << 32) + | |
162 | (mtrr_state.var_ranges[i].base_lo & PAGE_MASK); | |
163 | mask = (((u64)mtrr_state.var_ranges[i].mask_hi) << 32) + | |
164 | (mtrr_state.var_ranges[i].mask_lo & PAGE_MASK); | |
165 | ||
166 | start_state = ((start & mask) == (base & mask)); | |
167 | end_state = ((end & mask) == (base & mask)); | |
7f0431e3 | 168 | inclusive = ((start < base) && (end > base)); |
351e5a70 | 169 | |
7f0431e3 | 170 | if ((start_state != end_state) || inclusive) { |
351e5a70 VP |
171 | /* |
172 | * We have start:end spanning across an MTRR. | |
7f0431e3 TK |
173 | * We split the region into either |
174 | * | |
175 | * - start_state:1 | |
176 | * (start:mtrr_end)(mtrr_end:end) | |
177 | * - end_state:1 | |
178 | * (start:mtrr_start)(mtrr_start:end) | |
179 | * - inclusive:1 | |
180 | * (start:mtrr_start)(mtrr_start:mtrr_end)(mtrr_end:end) | |
181 | * | |
351e5a70 | 182 | * depending on kind of overlap. |
7f0431e3 TK |
183 | * |
184 | * Return the type of the first region and a pointer | |
185 | * to the start of next region so that caller will be | |
186 | * advised to lookup again after having adjusted start | |
187 | * and end. | |
188 | * | |
351e5a70 VP |
189 | * Note: This way we handle multiple overlaps as well. |
190 | */ | |
191 | if (start_state) | |
192 | *partial_end = base + get_mtrr_size(mask); | |
193 | else | |
194 | *partial_end = base; | |
195 | ||
196 | if (unlikely(*partial_end <= start)) { | |
197 | WARN_ON(1); | |
198 | *partial_end = start + PAGE_SIZE; | |
199 | } | |
200 | ||
201 | end = *partial_end - 1; /* end is inclusive */ | |
202 | *repeat = 1; | |
203 | } | |
2e5d9c85 | 204 | |
a1a499a3 | 205 | if ((start & mask) != (base & mask)) |
2e5d9c85 | 206 | continue; |
2e5d9c85 | 207 | |
208 | curr_match = mtrr_state.var_ranges[i].base_lo & 0xff; | |
3d3ca416 | 209 | if (prev_match == MTRR_TYPE_INVALID) { |
2e5d9c85 | 210 | prev_match = curr_match; |
211 | continue; | |
212 | } | |
213 | ||
a7f07cfb VP |
214 | if (check_type_overlap(&prev_match, &curr_match)) |
215 | return curr_match; | |
2e5d9c85 | 216 | } |
217 | ||
95ffa243 YL |
218 | if (mtrr_tom2) { |
219 | if (start >= (1ULL<<32) && (end < mtrr_tom2)) | |
35605a10 YL |
220 | return MTRR_TYPE_WRBACK; |
221 | } | |
222 | ||
3d3ca416 | 223 | if (prev_match != MTRR_TYPE_INVALID) |
2e5d9c85 | 224 | return prev_match; |
225 | ||
226 | return mtrr_state.def_type; | |
227 | } | |
228 | ||
351e5a70 VP |
229 | /* |
230 | * Returns the effective MTRR type for the region | |
231 | * Error return: | |
3d3ca416 | 232 | * MTRR_TYPE_INVALID - when MTRR is not enabled |
351e5a70 VP |
233 | */ |
234 | u8 mtrr_type_lookup(u64 start, u64 end) | |
235 | { | |
236 | u8 type, prev_type; | |
237 | int repeat; | |
238 | u64 partial_end; | |
239 | ||
240 | type = __mtrr_type_lookup(start, end, &partial_end, &repeat); | |
241 | ||
242 | /* | |
243 | * Common path is with repeat = 0. | |
244 | * However, we can have cases where [start:end] spans across some | |
245 | * MTRR range. Do repeated lookups for that case here. | |
246 | */ | |
247 | while (repeat) { | |
248 | prev_type = type; | |
249 | start = partial_end; | |
250 | type = __mtrr_type_lookup(start, end, &partial_end, &repeat); | |
251 | ||
252 | if (check_type_overlap(&prev_type, &type)) | |
253 | return type; | |
254 | } | |
255 | ||
256 | return type; | |
257 | } | |
258 | ||
a1a499a3 | 259 | /* Get the MSR pair relating to a var range */ |
bf8c4817 | 260 | static void |
1da177e4 LT |
261 | get_mtrr_var_range(unsigned int index, struct mtrr_var_range *vr) |
262 | { | |
263 | rdmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi); | |
264 | rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi); | |
265 | } | |
266 | ||
a1a499a3 | 267 | /* Fill the MSR pair relating to a var range */ |
95ffa243 YL |
268 | void fill_mtrr_var_range(unsigned int index, |
269 | u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi) | |
270 | { | |
271 | struct mtrr_var_range *vr; | |
272 | ||
273 | vr = mtrr_state.var_ranges; | |
274 | ||
275 | vr[index].base_lo = base_lo; | |
276 | vr[index].base_hi = base_hi; | |
277 | vr[index].mask_lo = mask_lo; | |
278 | vr[index].mask_hi = mask_hi; | |
279 | } | |
280 | ||
a1a499a3 | 281 | static void get_fixed_ranges(mtrr_type *frs) |
1da177e4 | 282 | { |
a1a499a3 | 283 | unsigned int *p = (unsigned int *)frs; |
1da177e4 LT |
284 | int i; |
285 | ||
3ff42da5 AH |
286 | k8_check_syscfg_dram_mod_en(); |
287 | ||
a036c7a3 | 288 | rdmsr(MSR_MTRRfix64K_00000, p[0], p[1]); |
1da177e4 LT |
289 | |
290 | for (i = 0; i < 2; i++) | |
7d9d55e4 | 291 | rdmsr(MSR_MTRRfix16K_80000 + i, p[2 + i * 2], p[3 + i * 2]); |
1da177e4 | 292 | for (i = 0; i < 8; i++) |
ba5673ff | 293 | rdmsr(MSR_MTRRfix4K_C0000 + i, p[6 + i * 2], p[7 + i * 2]); |
1da177e4 LT |
294 | } |
295 | ||
2b3b4835 BK |
296 | void mtrr_save_fixed_ranges(void *info) |
297 | { | |
84288ad8 AM |
298 | if (cpu_has_mtrr) |
299 | get_fixed_ranges(mtrr_state.fixed_ranges); | |
2b3b4835 BK |
300 | } |
301 | ||
d4c90e37 YL |
302 | static unsigned __initdata last_fixed_start; |
303 | static unsigned __initdata last_fixed_end; | |
304 | static mtrr_type __initdata last_fixed_type; | |
305 | ||
306 | static void __init print_fixed_last(void) | |
307 | { | |
308 | if (!last_fixed_end) | |
309 | return; | |
310 | ||
a1a499a3 JSR |
311 | pr_debug(" %05X-%05X %s\n", last_fixed_start, |
312 | last_fixed_end - 1, mtrr_attrib_to_str(last_fixed_type)); | |
d4c90e37 YL |
313 | |
314 | last_fixed_end = 0; | |
315 | } | |
316 | ||
317 | static void __init update_fixed_last(unsigned base, unsigned end, | |
a1a499a3 | 318 | mtrr_type type) |
d4c90e37 YL |
319 | { |
320 | last_fixed_start = base; | |
321 | last_fixed_end = end; | |
322 | last_fixed_type = type; | |
323 | } | |
324 | ||
a1a499a3 JSR |
325 | static void __init |
326 | print_fixed(unsigned base, unsigned step, const mtrr_type *types) | |
365bff80 JB |
327 | { |
328 | unsigned i; | |
329 | ||
d4c90e37 YL |
330 | for (i = 0; i < 8; ++i, ++types, base += step) { |
331 | if (last_fixed_end == 0) { | |
332 | update_fixed_last(base, base + step, *types); | |
333 | continue; | |
334 | } | |
335 | if (last_fixed_end == base && last_fixed_type == *types) { | |
336 | last_fixed_end = base + step; | |
337 | continue; | |
338 | } | |
339 | /* new segments: gap or different type */ | |
340 | print_fixed_last(); | |
341 | update_fixed_last(base, base + step, *types); | |
342 | } | |
365bff80 JB |
343 | } |
344 | ||
2e5d9c85 | 345 | static void prepare_set(void); |
346 | static void post_set(void); | |
347 | ||
8ad97905 YL |
348 | static void __init print_mtrr_state(void) |
349 | { | |
350 | unsigned int i; | |
351 | int high_width; | |
352 | ||
a1a499a3 JSR |
353 | pr_debug("MTRR default type: %s\n", |
354 | mtrr_attrib_to_str(mtrr_state.def_type)); | |
8ad97905 | 355 | if (mtrr_state.have_fixed) { |
a1a499a3 | 356 | pr_debug("MTRR fixed ranges %sabled:\n", |
9b3aca62 TK |
357 | ((mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED) && |
358 | (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED)) ? | |
359 | "en" : "dis"); | |
8ad97905 YL |
360 | print_fixed(0x00000, 0x10000, mtrr_state.fixed_ranges + 0); |
361 | for (i = 0; i < 2; ++i) | |
a1a499a3 JSR |
362 | print_fixed(0x80000 + i * 0x20000, 0x04000, |
363 | mtrr_state.fixed_ranges + (i + 1) * 8); | |
8ad97905 | 364 | for (i = 0; i < 8; ++i) |
a1a499a3 JSR |
365 | print_fixed(0xC0000 + i * 0x08000, 0x01000, |
366 | mtrr_state.fixed_ranges + (i + 3) * 8); | |
d4c90e37 YL |
367 | |
368 | /* tail */ | |
369 | print_fixed_last(); | |
8ad97905 | 370 | } |
a1a499a3 | 371 | pr_debug("MTRR variable ranges %sabled:\n", |
9b3aca62 | 372 | mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED ? "en" : "dis"); |
a7101d15 | 373 | high_width = (__ffs64(size_or_mask) - (32 - PAGE_SHIFT) + 3) / 4; |
a1a499a3 | 374 | |
8ad97905 YL |
375 | for (i = 0; i < num_var_ranges; ++i) { |
376 | if (mtrr_state.var_ranges[i].mask_lo & (1 << 11)) | |
a1a499a3 JSR |
377 | pr_debug(" %u base %0*X%05X000 mask %0*X%05X000 %s\n", |
378 | i, | |
379 | high_width, | |
380 | mtrr_state.var_ranges[i].base_hi, | |
381 | mtrr_state.var_ranges[i].base_lo >> 12, | |
382 | high_width, | |
383 | mtrr_state.var_ranges[i].mask_hi, | |
384 | mtrr_state.var_ranges[i].mask_lo >> 12, | |
385 | mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & 0xff)); | |
8ad97905 | 386 | else |
a1a499a3 | 387 | pr_debug(" %u disabled\n", i); |
8ad97905 | 388 | } |
a1a499a3 JSR |
389 | if (mtrr_tom2) |
390 | pr_debug("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20); | |
8ad97905 YL |
391 | } |
392 | ||
a1a499a3 | 393 | /* Grab all of the MTRR state for this CPU into *state */ |
9ef231a4 | 394 | void __init get_mtrr_state(void) |
1da177e4 | 395 | { |
1da177e4 | 396 | struct mtrr_var_range *vrs; |
2e5d9c85 | 397 | unsigned long flags; |
a1a499a3 JSR |
398 | unsigned lo, dummy; |
399 | unsigned int i; | |
1da177e4 | 400 | |
1da177e4 LT |
401 | vrs = mtrr_state.var_ranges; |
402 | ||
d9bcc01d | 403 | rdmsr(MSR_MTRRcap, lo, dummy); |
365bff80 JB |
404 | mtrr_state.have_fixed = (lo >> 8) & 1; |
405 | ||
1da177e4 LT |
406 | for (i = 0; i < num_var_ranges; i++) |
407 | get_mtrr_var_range(i, &vrs[i]); | |
365bff80 JB |
408 | if (mtrr_state.have_fixed) |
409 | get_fixed_ranges(mtrr_state.fixed_ranges); | |
1da177e4 | 410 | |
52650257 | 411 | rdmsr(MSR_MTRRdefType, lo, dummy); |
1da177e4 LT |
412 | mtrr_state.def_type = (lo & 0xff); |
413 | mtrr_state.enabled = (lo & 0xc00) >> 10; | |
365bff80 | 414 | |
35605a10 | 415 | if (amd_special_default_mtrr()) { |
0da72a4a | 416 | unsigned low, high; |
a1a499a3 | 417 | |
35605a10 | 418 | /* TOP_MEM2 */ |
0da72a4a | 419 | rdmsr(MSR_K8_TOP_MEM2, low, high); |
95ffa243 YL |
420 | mtrr_tom2 = high; |
421 | mtrr_tom2 <<= 32; | |
422 | mtrr_tom2 |= low; | |
8004dd96 | 423 | mtrr_tom2 &= 0xffffff800000ULL; |
35605a10 | 424 | } |
8ad97905 YL |
425 | |
426 | print_mtrr_state(); | |
427 | ||
2e5d9c85 | 428 | mtrr_state_set = 1; |
429 | ||
430 | /* PAT setup for BP. We need to go through sync steps here */ | |
431 | local_irq_save(flags); | |
432 | prepare_set(); | |
433 | ||
434 | pat_init(); | |
435 | ||
436 | post_set(); | |
437 | local_irq_restore(flags); | |
1da177e4 LT |
438 | } |
439 | ||
a1a499a3 | 440 | /* Some BIOS's are messed up and don't set all MTRRs the same! */ |
1da177e4 LT |
441 | void __init mtrr_state_warn(void) |
442 | { | |
443 | unsigned long mask = smp_changes_mask; | |
444 | ||
445 | if (!mask) | |
446 | return; | |
447 | if (mask & MTRR_CHANGE_MASK_FIXED) | |
a1a499a3 | 448 | pr_warning("mtrr: your CPUs had inconsistent fixed MTRR settings\n"); |
1da177e4 | 449 | if (mask & MTRR_CHANGE_MASK_VARIABLE) |
a1a499a3 | 450 | pr_warning("mtrr: your CPUs had inconsistent variable MTRR settings\n"); |
1da177e4 | 451 | if (mask & MTRR_CHANGE_MASK_DEFTYPE) |
a1a499a3 JSR |
452 | pr_warning("mtrr: your CPUs had inconsistent MTRRdefType settings\n"); |
453 | ||
1da177e4 LT |
454 | printk(KERN_INFO "mtrr: probably your BIOS does not setup all CPUs.\n"); |
455 | printk(KERN_INFO "mtrr: corrected configuration.\n"); | |
456 | } | |
457 | ||
a1a499a3 JSR |
458 | /* |
459 | * Doesn't attempt to pass an error out to MTRR users | |
460 | * because it's quite complicated in some cases and probably not | |
461 | * worth it because the best error handling is to ignore it. | |
462 | */ | |
1da177e4 LT |
463 | void mtrr_wrmsr(unsigned msr, unsigned a, unsigned b) |
464 | { | |
a1a499a3 | 465 | if (wrmsr_safe(msr, a, b) < 0) { |
1da177e4 LT |
466 | printk(KERN_ERR |
467 | "MTRR: CPU %u: Writing MSR %x to %x:%x failed\n", | |
468 | smp_processor_id(), msr, a, b); | |
a1a499a3 | 469 | } |
1da177e4 LT |
470 | } |
471 | ||
de938c51 | 472 | /** |
a1a499a3 JSR |
473 | * set_fixed_range - checks & updates a fixed-range MTRR if it |
474 | * differs from the value it should have | |
1d3381eb RD |
475 | * @msr: MSR address of the MTTR which should be checked and updated |
476 | * @changed: pointer which indicates whether the MTRR needed to be changed | |
477 | * @msrwords: pointer to the MSR values which the MSR should have | |
de938c51 | 478 | */ |
2d2ee8de | 479 | static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords) |
de938c51 BK |
480 | { |
481 | unsigned lo, hi; | |
482 | ||
483 | rdmsr(msr, lo, hi); | |
484 | ||
485 | if (lo != msrwords[0] || hi != msrwords[1]) { | |
de938c51 | 486 | mtrr_wrmsr(msr, msrwords[0], msrwords[1]); |
2d2ee8de | 487 | *changed = true; |
de938c51 BK |
488 | } |
489 | } | |
490 | ||
1d3381eb RD |
491 | /** |
492 | * generic_get_free_region - Get a free MTRR. | |
493 | * @base: The starting (base) address of the region. | |
494 | * @size: The size (in bytes) of the region. | |
495 | * @replace_reg: mtrr index to be replaced; set to invalid value if none. | |
496 | * | |
497 | * Returns: The index of the region on success, else negative on error. | |
498 | */ | |
a1a499a3 JSR |
499 | int |
500 | generic_get_free_region(unsigned long base, unsigned long size, int replace_reg) | |
1da177e4 | 501 | { |
365bff80 | 502 | unsigned long lbase, lsize; |
a1a499a3 JSR |
503 | mtrr_type ltype; |
504 | int i, max; | |
1da177e4 LT |
505 | |
506 | max = num_var_ranges; | |
365bff80 JB |
507 | if (replace_reg >= 0 && replace_reg < max) |
508 | return replace_reg; | |
a1a499a3 | 509 | |
1da177e4 LT |
510 | for (i = 0; i < max; ++i) { |
511 | mtrr_if->get(i, &lbase, &lsize, <ype); | |
512 | if (lsize == 0) | |
513 | return i; | |
514 | } | |
a1a499a3 | 515 | |
1da177e4 LT |
516 | return -ENOSPC; |
517 | } | |
518 | ||
408b664a | 519 | static void generic_get_mtrr(unsigned int reg, unsigned long *base, |
365bff80 | 520 | unsigned long *size, mtrr_type *type) |
1da177e4 | 521 | { |
d5c78673 YL |
522 | u32 mask_lo, mask_hi, base_lo, base_hi; |
523 | unsigned int hi; | |
524 | u64 tmp, mask; | |
1da177e4 | 525 | |
8ad97905 YL |
526 | /* |
527 | * get_mtrr doesn't need to update mtrr_state, also it could be called | |
528 | * from any cpu, so try to print it out directly. | |
529 | */ | |
fa10ba64 | 530 | get_cpu(); |
63516ef6 | 531 | |
1da177e4 | 532 | rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi); |
8ad97905 | 533 | |
1da177e4 | 534 | if ((mask_lo & 0x800) == 0) { |
a1a499a3 | 535 | /* Invalid (i.e. free) range */ |
1da177e4 LT |
536 | *base = 0; |
537 | *size = 0; | |
538 | *type = 0; | |
63516ef6 | 539 | goto out_put_cpu; |
1da177e4 LT |
540 | } |
541 | ||
542 | rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi); | |
543 | ||
63516ef6 | 544 | /* Work out the shifted address mask: */ |
d5c78673 YL |
545 | tmp = (u64)mask_hi << (32 - PAGE_SHIFT) | mask_lo >> PAGE_SHIFT; |
546 | mask = size_or_mask | tmp; | |
63516ef6 YL |
547 | |
548 | /* Expand tmp with high bits to all 1s: */ | |
d5c78673 | 549 | hi = fls64(tmp); |
38cc1c3d | 550 | if (hi > 0) { |
d5c78673 | 551 | tmp |= ~((1ULL<<(hi - 1)) - 1); |
38cc1c3d | 552 | |
d5c78673 | 553 | if (tmp != mask) { |
942fa3b6 | 554 | printk(KERN_WARNING "mtrr: your BIOS has configured an incorrect mask, fixing it.\n"); |
373d4d09 | 555 | add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); |
d5c78673 | 556 | mask = tmp; |
38cc1c3d YL |
557 | } |
558 | } | |
1da177e4 | 559 | |
63516ef6 YL |
560 | /* |
561 | * This works correctly if size is a power of two, i.e. a | |
562 | * contiguous range: | |
563 | */ | |
d5c78673 YL |
564 | *size = -mask; |
565 | *base = (u64)base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT; | |
1da177e4 | 566 | *type = base_lo & 0xff; |
8ad97905 | 567 | |
63516ef6 YL |
568 | out_put_cpu: |
569 | put_cpu(); | |
1da177e4 LT |
570 | } |
571 | ||
de938c51 | 572 | /** |
a1a499a3 JSR |
573 | * set_fixed_ranges - checks & updates the fixed-range MTRRs if they |
574 | * differ from the saved set | |
1d3381eb | 575 | * @frs: pointer to fixed-range MTRR values, saved by get_fixed_ranges() |
de938c51 | 576 | */ |
a1a499a3 | 577 | static int set_fixed_ranges(mtrr_type *frs) |
1da177e4 | 578 | { |
a1a499a3 | 579 | unsigned long long *saved = (unsigned long long *)frs; |
2d2ee8de | 580 | bool changed = false; |
a1a499a3 | 581 | int block = -1, range; |
1da177e4 | 582 | |
3ff42da5 AH |
583 | k8_check_syscfg_dram_mod_en(); |
584 | ||
a1a499a3 JSR |
585 | while (fixed_range_blocks[++block].ranges) { |
586 | for (range = 0; range < fixed_range_blocks[block].ranges; range++) | |
587 | set_fixed_range(fixed_range_blocks[block].base_msr + range, | |
588 | &changed, (unsigned int *)saved++); | |
589 | } | |
1da177e4 | 590 | |
1da177e4 LT |
591 | return changed; |
592 | } | |
593 | ||
a1a499a3 JSR |
594 | /* |
595 | * Set the MSR pair relating to a var range. | |
596 | * Returns true if changes are made. | |
597 | */ | |
2d2ee8de | 598 | static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr) |
1da177e4 LT |
599 | { |
600 | unsigned int lo, hi; | |
2d2ee8de | 601 | bool changed = false; |
1da177e4 LT |
602 | |
603 | rdmsr(MTRRphysBase_MSR(index), lo, hi); | |
604 | if ((vr->base_lo & 0xfffff0ffUL) != (lo & 0xfffff0ffUL) | |
cf94b62f SS |
605 | || (vr->base_hi & (size_and_mask >> (32 - PAGE_SHIFT))) != |
606 | (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) { | |
a1a499a3 | 607 | |
1da177e4 | 608 | mtrr_wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi); |
2d2ee8de | 609 | changed = true; |
1da177e4 LT |
610 | } |
611 | ||
612 | rdmsr(MTRRphysMask_MSR(index), lo, hi); | |
613 | ||
614 | if ((vr->mask_lo & 0xfffff800UL) != (lo & 0xfffff800UL) | |
cf94b62f SS |
615 | || (vr->mask_hi & (size_and_mask >> (32 - PAGE_SHIFT))) != |
616 | (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) { | |
1da177e4 | 617 | mtrr_wrmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi); |
2d2ee8de | 618 | changed = true; |
1da177e4 LT |
619 | } |
620 | return changed; | |
621 | } | |
622 | ||
365bff80 JB |
623 | static u32 deftype_lo, deftype_hi; |
624 | ||
1d3381eb RD |
625 | /** |
626 | * set_mtrr_state - Set the MTRR state for this CPU. | |
627 | * | |
628 | * NOTE: The CPU must already be in a safe state for MTRR changes. | |
629 | * RETURNS: 0 if no changes made, else a mask indicating what was changed. | |
630 | */ | |
365bff80 | 631 | static unsigned long set_mtrr_state(void) |
1da177e4 | 632 | { |
1da177e4 | 633 | unsigned long change_mask = 0; |
a1a499a3 | 634 | unsigned int i; |
1da177e4 | 635 | |
a1a499a3 | 636 | for (i = 0; i < num_var_ranges; i++) { |
1da177e4 LT |
637 | if (set_mtrr_var_ranges(i, &mtrr_state.var_ranges[i])) |
638 | change_mask |= MTRR_CHANGE_MASK_VARIABLE; | |
a1a499a3 | 639 | } |
1da177e4 | 640 | |
365bff80 | 641 | if (mtrr_state.have_fixed && set_fixed_ranges(mtrr_state.fixed_ranges)) |
1da177e4 LT |
642 | change_mask |= MTRR_CHANGE_MASK_FIXED; |
643 | ||
a1a499a3 JSR |
644 | /* |
645 | * Set_mtrr_restore restores the old value of MTRRdefType, | |
646 | * so to set it we fiddle with the saved value: | |
647 | */ | |
1da177e4 LT |
648 | if ((deftype_lo & 0xff) != mtrr_state.def_type |
649 | || ((deftype_lo & 0xc00) >> 10) != mtrr_state.enabled) { | |
a1a499a3 JSR |
650 | |
651 | deftype_lo = (deftype_lo & ~0xcff) | mtrr_state.def_type | | |
652 | (mtrr_state.enabled << 10); | |
1da177e4 LT |
653 | change_mask |= MTRR_CHANGE_MASK_DEFTYPE; |
654 | } | |
655 | ||
656 | return change_mask; | |
657 | } | |
658 | ||
659 | ||
a1a499a3 | 660 | static unsigned long cr4; |
40d6753e | 661 | static DEFINE_RAW_SPINLOCK(set_atomicity_lock); |
1da177e4 LT |
662 | |
663 | /* | |
a1a499a3 JSR |
664 | * Since we are disabling the cache don't allow any interrupts, |
665 | * they would run extremely slow and would only increase the pain. | |
666 | * | |
667 | * The caller must ensure that local interrupts are disabled and | |
668 | * are reenabled after post_set() has been called. | |
1da177e4 | 669 | */ |
182daa55 | 670 | static void prepare_set(void) __acquires(set_atomicity_lock) |
1da177e4 LT |
671 | { |
672 | unsigned long cr0; | |
673 | ||
a1a499a3 JSR |
674 | /* |
675 | * Note that this is not ideal | |
676 | * since the cache is only flushed/disabled for this CPU while the | |
677 | * MTRRs are changed, but changing this requires more invasive | |
678 | * changes to the way the kernel boots | |
679 | */ | |
1da177e4 | 680 | |
40d6753e | 681 | raw_spin_lock(&set_atomicity_lock); |
1da177e4 | 682 | |
a1a499a3 | 683 | /* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */ |
7ebad705 | 684 | cr0 = read_cr0() | X86_CR0_CD; |
1da177e4 LT |
685 | write_cr0(cr0); |
686 | wbinvd(); | |
687 | ||
a1a499a3 JSR |
688 | /* Save value of CR4 and clear Page Global Enable (bit 7) */ |
689 | if (cpu_has_pge) { | |
1e02ce4c AL |
690 | cr4 = __read_cr4(); |
691 | __write_cr4(cr4 & ~X86_CR4_PGE); | |
1da177e4 LT |
692 | } |
693 | ||
694 | /* Flush all TLBs via a mov %cr3, %reg; mov %reg, %cr3 */ | |
ec659934 | 695 | count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); |
1da177e4 LT |
696 | __flush_tlb(); |
697 | ||
a1a499a3 | 698 | /* Save MTRR state */ |
52650257 | 699 | rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi); |
1da177e4 | 700 | |
a1a499a3 | 701 | /* Disable MTRRs, and set the default type to uncached */ |
52650257 | 702 | mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi); |
8dbf4a30 | 703 | wbinvd(); |
1da177e4 LT |
704 | } |
705 | ||
182daa55 | 706 | static void post_set(void) __releases(set_atomicity_lock) |
1da177e4 | 707 | { |
a1a499a3 | 708 | /* Flush TLBs (no need to flush caches - they are disabled) */ |
ec659934 | 709 | count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); |
1da177e4 LT |
710 | __flush_tlb(); |
711 | ||
712 | /* Intel (P6) standard MTRRs */ | |
52650257 | 713 | mtrr_wrmsr(MSR_MTRRdefType, deftype_lo, deftype_hi); |
a1a499a3 JSR |
714 | |
715 | /* Enable caches */ | |
a3d7b7dd | 716 | write_cr0(read_cr0() & ~X86_CR0_CD); |
1da177e4 | 717 | |
a1a499a3 JSR |
718 | /* Restore value of CR4 */ |
719 | if (cpu_has_pge) | |
1e02ce4c | 720 | __write_cr4(cr4); |
40d6753e | 721 | raw_spin_unlock(&set_atomicity_lock); |
1da177e4 LT |
722 | } |
723 | ||
724 | static void generic_set_all(void) | |
725 | { | |
726 | unsigned long mask, count; | |
727 | unsigned long flags; | |
728 | ||
729 | local_irq_save(flags); | |
730 | prepare_set(); | |
731 | ||
732 | /* Actually set the state */ | |
365bff80 | 733 | mask = set_mtrr_state(); |
1da177e4 | 734 | |
2e5d9c85 | 735 | /* also set PAT */ |
736 | pat_init(); | |
737 | ||
1da177e4 LT |
738 | post_set(); |
739 | local_irq_restore(flags); | |
740 | ||
a1a499a3 | 741 | /* Use the atomic bitops to update the global mask */ |
1da177e4 LT |
742 | for (count = 0; count < sizeof mask * 8; ++count) { |
743 | if (mask & 0x01) | |
744 | set_bit(count, &smp_changes_mask); | |
745 | mask >>= 1; | |
746 | } | |
a1a499a3 | 747 | |
1da177e4 LT |
748 | } |
749 | ||
a1a499a3 JSR |
750 | /** |
751 | * generic_set_mtrr - set variable MTRR register on the local CPU. | |
752 | * | |
753 | * @reg: The register to set. | |
754 | * @base: The base address of the region. | |
755 | * @size: The size of the region. If this is 0 the region is disabled. | |
756 | * @type: The type of the region. | |
757 | * | |
758 | * Returns nothing. | |
759 | */ | |
1da177e4 LT |
760 | static void generic_set_mtrr(unsigned int reg, unsigned long base, |
761 | unsigned long size, mtrr_type type) | |
1da177e4 LT |
762 | { |
763 | unsigned long flags; | |
3b520b23 SL |
764 | struct mtrr_var_range *vr; |
765 | ||
766 | vr = &mtrr_state.var_ranges[reg]; | |
1da177e4 LT |
767 | |
768 | local_irq_save(flags); | |
769 | prepare_set(); | |
770 | ||
771 | if (size == 0) { | |
a1a499a3 JSR |
772 | /* |
773 | * The invalid bit is kept in the mask, so we simply | |
774 | * clear the relevant mask register to disable a range. | |
775 | */ | |
1da177e4 | 776 | mtrr_wrmsr(MTRRphysMask_MSR(reg), 0, 0); |
3b520b23 | 777 | memset(vr, 0, sizeof(struct mtrr_var_range)); |
1da177e4 | 778 | } else { |
3b520b23 SL |
779 | vr->base_lo = base << PAGE_SHIFT | type; |
780 | vr->base_hi = (base & size_and_mask) >> (32 - PAGE_SHIFT); | |
781 | vr->mask_lo = -size << PAGE_SHIFT | 0x800; | |
782 | vr->mask_hi = (-size & size_and_mask) >> (32 - PAGE_SHIFT); | |
783 | ||
784 | mtrr_wrmsr(MTRRphysBase_MSR(reg), vr->base_lo, vr->base_hi); | |
785 | mtrr_wrmsr(MTRRphysMask_MSR(reg), vr->mask_lo, vr->mask_hi); | |
1da177e4 LT |
786 | } |
787 | ||
788 | post_set(); | |
789 | local_irq_restore(flags); | |
790 | } | |
791 | ||
a1a499a3 JSR |
792 | int generic_validate_add_page(unsigned long base, unsigned long size, |
793 | unsigned int type) | |
1da177e4 LT |
794 | { |
795 | unsigned long lbase, last; | |
796 | ||
a1a499a3 JSR |
797 | /* |
798 | * For Intel PPro stepping <= 7 | |
799 | * must be 4 MiB aligned and not touch 0x70000000 -> 0x7003FFFF | |
800 | */ | |
1da177e4 LT |
801 | if (is_cpu(INTEL) && boot_cpu_data.x86 == 6 && |
802 | boot_cpu_data.x86_model == 1 && | |
803 | boot_cpu_data.x86_mask <= 7) { | |
804 | if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) { | |
a1a499a3 | 805 | pr_warning("mtrr: base(0x%lx000) is not 4 MiB aligned\n", base); |
1da177e4 LT |
806 | return -EINVAL; |
807 | } | |
9b483417 | 808 | if (!(base + size < 0x70000 || base > 0x7003F) && |
1da177e4 LT |
809 | (type == MTRR_TYPE_WRCOMB |
810 | || type == MTRR_TYPE_WRBACK)) { | |
a1a499a3 | 811 | pr_warning("mtrr: writable mtrr between 0x70000000 and 0x7003FFFF may hang the CPU.\n"); |
1da177e4 LT |
812 | return -EINVAL; |
813 | } | |
814 | } | |
815 | ||
a1a499a3 JSR |
816 | /* |
817 | * Check upper bits of base and last are equal and lower bits are 0 | |
818 | * for base and 1 for last | |
819 | */ | |
1da177e4 LT |
820 | last = base + size - 1; |
821 | for (lbase = base; !(lbase & 1) && (last & 1); | |
a1a499a3 JSR |
822 | lbase = lbase >> 1, last = last >> 1) |
823 | ; | |
1da177e4 | 824 | if (lbase != last) { |
a1a499a3 | 825 | pr_warning("mtrr: base(0x%lx000) is not aligned on a size(0x%lx000) boundary\n", base, size); |
1da177e4 LT |
826 | return -EINVAL; |
827 | } | |
828 | return 0; | |
829 | } | |
830 | ||
1da177e4 LT |
831 | static int generic_have_wrcomb(void) |
832 | { | |
833 | unsigned long config, dummy; | |
d9bcc01d | 834 | rdmsr(MSR_MTRRcap, config, dummy); |
a1a499a3 | 835 | return config & (1 << 10); |
1da177e4 LT |
836 | } |
837 | ||
838 | int positive_have_wrcomb(void) | |
839 | { | |
840 | return 1; | |
841 | } | |
842 | ||
a1a499a3 JSR |
843 | /* |
844 | * Generic structure... | |
1da177e4 | 845 | */ |
3b9cfc0a | 846 | const struct mtrr_ops generic_mtrr_ops = { |
a1a499a3 JSR |
847 | .use_intel_if = 1, |
848 | .set_all = generic_set_all, | |
849 | .get = generic_get_mtrr, | |
850 | .get_free_region = generic_get_free_region, | |
851 | .set = generic_set_mtrr, | |
852 | .validate_add_page = generic_validate_add_page, | |
853 | .have_wrcomb = generic_have_wrcomb, | |
1da177e4 | 854 | }; |