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241771ef 1/*
cdd6c482 2 * Performance events x86 architecture code
241771ef 3 *
98144511
IM		 4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
30dd568c 9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
1da53e02 10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
241771ef
IM		 11 *
12 * For licencing details see kernel-base/COPYING
13 */
14
cdd6c482 15#include <linux/perf_event.h>
241771ef
IM		 16#include <linux/capability.h>
17#include <linux/notifier.h>
18#include <linux/hardirq.h>
19#include <linux/kprobes.h>
4ac13294 20#include <linux/module.h>
241771ef
IM		 21#include <linux/kdebug.h>
22#include <linux/sched.h>
d7d59fb3 23#include <linux/uaccess.h>
74193ef0 24#include <linux/highmem.h>
30dd568c 25#include <linux/cpu.h>
241771ef 26
241771ef 27#include <asm/apic.h>
d7d59fb3 28#include <asm/stacktrace.h>
4e935e47 29#include <asm/nmi.h>
241771ef 30
cdd6c482 31static u64 perf_event_mask __read_mostly;
703e937c 32
cdd6c482
IM		 33/* The maximal number of PEBS events: */
34#define MAX_PEBS_EVENTS 4
30dd568c
MM		 35
36/* The size of a BTS record in bytes: */
37#define BTS_RECORD_SIZE 24
38
39/* The size of a per-cpu BTS buffer in bytes: */
5622f295 40#define BTS_BUFFER_SIZE (BTS_RECORD_SIZE * 2048)
30dd568c
MM		 41
42/* The BTS overflow threshold in bytes from the end of the buffer: */
5622f295 43#define BTS_OVFL_TH (BTS_RECORD_SIZE * 128)
30dd568c
MM		 44
45
46/*
47 * Bits in the debugctlmsr controlling branch tracing.
48 */
49#define X86_DEBUGCTL_TR (1 << 6)
50#define X86_DEBUGCTL_BTS (1 << 7)
51#define X86_DEBUGCTL_BTINT (1 << 8)
52#define X86_DEBUGCTL_BTS_OFF_OS (1 << 9)
53#define X86_DEBUGCTL_BTS_OFF_USR (1 << 10)
54
55/*
56 * A debug store configuration.
57 *
58 * We only support architectures that use 64bit fields.
59 */
60struct debug_store {
61 u64 bts_buffer_base;
62 u64 bts_index;
63 u64 bts_absolute_maximum;
64 u64 bts_interrupt_threshold;
65 u64 pebs_buffer_base;
66 u64 pebs_index;
67 u64 pebs_absolute_maximum;
68 u64 pebs_interrupt_threshold;
cdd6c482 69 u64 pebs_event_reset[MAX_PEBS_EVENTS];
30dd568c
MM		 70};
71
1da53e02 72struct event_constraint {
c91e0f5d
PZ		 73 union {
74 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
75 u64 idxmsk64[1];
76 };
1da53e02
SE		 77 int code;
78 int cmask;
79};
80
cdd6c482 81struct cpu_hw_events {
1da53e02 82 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
43f6201a 83 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
4b39fd96 84 unsigned long interrupts;
b0f3f28e 85 int enabled;
30dd568c 86 struct debug_store *ds;
241771ef 87
1da53e02
SE		 88 int n_events;
89 int n_added;
90 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
91 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
b690081d
SE		 92};
93
c91e0f5d
PZ		 94#define EVENT_CONSTRAINT(c, n, m) { \
95 { .idxmsk64[0] = (n) }, \
96 .code = (c), \
97 .cmask = (m), \
98}
b690081d 99
8433be11
PZ		 100#define INTEL_EVENT_CONSTRAINT(c, n) \
101 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
102
103#define FIXED_EVENT_CONSTRAINT(c, n) \
104 EVENT_CONSTRAINT(c, n, INTEL_ARCH_FIXED_MASK)
105
1da53e02 106#define EVENT_CONSTRAINT_END \
c91e0f5d 107 EVENT_CONSTRAINT(0, 0, 0)
b690081d 108
1da53e02
SE		 109#define for_each_event_constraint(e, c) \
110 for ((e) = (c); (e)->cmask; (e)++)
b690081d 111
241771ef 112/*
5f4ec28f 113 * struct x86_pmu - generic x86 pmu
241771ef 114 */
5f4ec28f 115struct x86_pmu {
faa28ae0
RR		 116 const char *name;
117 int version;
a3288106 118 int (*handle_irq)(struct pt_regs *);
9e35ad38
PZ		 119 void (*disable_all)(void);
120 void (*enable_all)(void);
cdd6c482
IM		 121 void (*enable)(struct hw_perf_event *, int);
122 void (*disable)(struct hw_perf_event *, int);
169e41eb
JSR		 123 unsigned eventsel;
124 unsigned perfctr;
b0f3f28e
PZ		 125 u64 (*event_map)(int);
126 u64 (*raw_event)(u64);
169e41eb 127 int max_events;
cdd6c482
IM		 128 int num_events;
129 int num_events_fixed;
130 int event_bits;
131 u64 event_mask;
04da8a43 132 int apic;
c619b8ff 133 u64 max_period;
9e35ad38 134 u64 intel_ctrl;
30dd568c
MM		 135 void (*enable_bts)(u64 config);
136 void (*disable_bts)(void);
c91e0f5d
PZ		 137 void (*get_event_constraints)(struct cpu_hw_events *cpuc,
138 struct perf_event *event,
139 unsigned long *idxmsk);
140 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
141 struct perf_event *event);
1da53e02 142 const struct event_constraint *event_constraints;
b56a3802
JSR		 143};
144
4a06bd85 145static struct x86_pmu x86_pmu __read_mostly;
b56a3802 146
cdd6c482 147static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
b0f3f28e
PZ		 148 .enabled = 1,
149};
241771ef 150
1da53e02
SE		 151static int x86_perf_event_set_period(struct perf_event *event,
152 struct hw_perf_event *hwc, int idx);
b690081d 153
11d1578f
VW		 154/*
155 * Not sure about some of these
156 */
157static const u64 p6_perfmon_event_map[] =
158{
159 [PERF_COUNT_HW_CPU_CYCLES] = 0x0079,
160 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
f64ccccb
IM		 161 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0f2e,
162 [PERF_COUNT_HW_CACHE_MISSES] = 0x012e,
11d1578f
VW		 163 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
164 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
165 [PERF_COUNT_HW_BUS_CYCLES] = 0x0062,
166};
167
dfc65094 168static u64 p6_pmu_event_map(int hw_event)
11d1578f 169{
dfc65094 170 return p6_perfmon_event_map[hw_event];
11d1578f
VW		 171}
172
9c74fb50 173/*
cdd6c482 174 * Event setting that is specified not to count anything.
9c74fb50
PZ		 175 * We use this to effectively disable a counter.
176 *
177 * L2_RQSTS with 0 MESI unit mask.
178 */
cdd6c482 179#define P6_NOP_EVENT 0x0000002EULL
9c74fb50 180
dfc65094 181static u64 p6_pmu_raw_event(u64 hw_event)
11d1578f
VW		 182{
183#define P6_EVNTSEL_EVENT_MASK 0x000000FFULL
184#define P6_EVNTSEL_UNIT_MASK 0x0000FF00ULL
185#define P6_EVNTSEL_EDGE_MASK 0x00040000ULL
186#define P6_EVNTSEL_INV_MASK 0x00800000ULL
cdd6c482 187#define P6_EVNTSEL_REG_MASK 0xFF000000ULL
11d1578f
VW		 188
189#define P6_EVNTSEL_MASK \
190 (P6_EVNTSEL_EVENT_MASK | \
191 P6_EVNTSEL_UNIT_MASK | \
192 P6_EVNTSEL_EDGE_MASK | \
193 P6_EVNTSEL_INV_MASK | \
cdd6c482 194 P6_EVNTSEL_REG_MASK)
11d1578f 195
dfc65094 196 return hw_event & P6_EVNTSEL_MASK;
11d1578f
VW		 197}
198
1da53e02 199static struct event_constraint intel_p6_event_constraints[] =
b690081d 200{
8433be11
PZ		 201 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FLOPS */
202 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
203 INTEL_EVENT_CONSTRAINT(0x11, 0x1), /* FP_ASSIST */
204 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
205 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
206 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
b690081d
SE		 207 EVENT_CONSTRAINT_END
208};
11d1578f 209
b56a3802
JSR		 210/*
211 * Intel PerfMon v3. Used on Core2 and later.
212 */
b0f3f28e 213static const u64 intel_perfmon_event_map[] =
241771ef 214{
f4dbfa8f
PZ		 215 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
216 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
217 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
218 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
219 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
220 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
221 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
241771ef
IM		 222};
223
1da53e02
SE		 224static struct event_constraint intel_core_event_constraints[] =
225{
8433be11
PZ		 226 FIXED_EVENT_CONSTRAINT(0xc0, (0x3|(1ULL<<32))), /* INSTRUCTIONS_RETIRED */
227 FIXED_EVENT_CONSTRAINT(0x3c, (0x3|(1ULL<<33))), /* UNHALTED_CORE_CYCLES */
228 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
229 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
230 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
231 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
232 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
233 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
234 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
235 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
236 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
b690081d
SE		 237 EVENT_CONSTRAINT_END
238};
239
1da53e02
SE		 240static struct event_constraint intel_nehalem_event_constraints[] =
241{
8433be11
PZ		 242 FIXED_EVENT_CONSTRAINT(0xc0, (0x3|(1ULL<<32))), /* INSTRUCTIONS_RETIRED */
243 FIXED_EVENT_CONSTRAINT(0x3c, (0x3|(1ULL<<33))), /* UNHALTED_CORE_CYCLES */
244 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
245 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
246 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
247 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
248 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
249 INTEL_EVENT_CONSTRAINT(0x4c, 0x3), /* LOAD_HIT_PRE */
250 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
251 INTEL_EVENT_CONSTRAINT(0x52, 0x3), /* L1D_CACHE_PREFETCH_LOCK_FB_HIT */
252 INTEL_EVENT_CONSTRAINT(0x53, 0x3), /* L1D_CACHE_LOCK_FB_HIT */
253 INTEL_EVENT_CONSTRAINT(0xc5, 0x3), /* CACHE_LOCK_CYCLES */
1da53e02
SE		 254 EVENT_CONSTRAINT_END
255};
256
257static struct event_constraint intel_gen_event_constraints[] =
258{
8433be11
PZ		 259 FIXED_EVENT_CONSTRAINT(0xc0, (0x3|(1ULL<<32))), /* INSTRUCTIONS_RETIRED */
260 FIXED_EVENT_CONSTRAINT(0x3c, (0x3|(1ULL<<33))), /* UNHALTED_CORE_CYCLES */
b690081d
SE		 261 EVENT_CONSTRAINT_END
262};
263
dfc65094 264static u64 intel_pmu_event_map(int hw_event)
b56a3802 265{
dfc65094 266 return intel_perfmon_event_map[hw_event];
b56a3802 267}
241771ef 268
8326f44d 269/*
dfc65094 270 * Generalized hw caching related hw_event table, filled
8326f44d 271 * in on a per model basis. A value of 0 means
dfc65094
IM		 272 * 'not supported', -1 means 'hw_event makes no sense on
273 * this CPU', any other value means the raw hw_event
8326f44d
IM		 274 * ID.
275 */
276
277#define C(x) PERF_COUNT_HW_CACHE_##x
278
279static u64 __read_mostly hw_cache_event_ids
280 [PERF_COUNT_HW_CACHE_MAX]
281 [PERF_COUNT_HW_CACHE_OP_MAX]
282 [PERF_COUNT_HW_CACHE_RESULT_MAX];
283
db48cccc 284static __initconst u64 nehalem_hw_cache_event_ids
8326f44d
IM		 285 [PERF_COUNT_HW_CACHE_MAX]
286 [PERF_COUNT_HW_CACHE_OP_MAX]
287 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
288{
289 [ C(L1D) ] = {
290 [ C(OP_READ) ] = {
291 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
292 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
293 },
294 [ C(OP_WRITE) ] = {
295 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
296 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
297 },
298 [ C(OP_PREFETCH) ] = {
299 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
300 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
301 },
302 },
303 [ C(L1I ) ] = {
304 [ C(OP_READ) ] = {
fecc8ac8 305 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
8326f44d
IM		 306 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
307 },
308 [ C(OP_WRITE) ] = {
309 [ C(RESULT_ACCESS) ] = -1,
310 [ C(RESULT_MISS) ] = -1,
311 },
312 [ C(OP_PREFETCH) ] = {
313 [ C(RESULT_ACCESS) ] = 0x0,
314 [ C(RESULT_MISS) ] = 0x0,
315 },
316 },
8be6e8f3 317 [ C(LL ) ] = {
8326f44d
IM		 318 [ C(OP_READ) ] = {
319 [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */
320 [ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */
321 },
322 [ C(OP_WRITE) ] = {
323 [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS */
324 [ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */
325 },
326 [ C(OP_PREFETCH) ] = {
8be6e8f3
PZ		 327 [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference */
328 [ C(RESULT_MISS) ] = 0x412e, /* LLC Misses */
8326f44d
IM		 329 },
330 },
331 [ C(DTLB) ] = {
332 [ C(OP_READ) ] = {
333 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
334 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
335 },
336 [ C(OP_WRITE) ] = {
337 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
338 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
339 },
340 [ C(OP_PREFETCH) ] = {
341 [ C(RESULT_ACCESS) ] = 0x0,
342 [ C(RESULT_MISS) ] = 0x0,
343 },
344 },
345 [ C(ITLB) ] = {
346 [ C(OP_READ) ] = {
347 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
fecc8ac8 348 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
8326f44d
IM		 349 },
350 [ C(OP_WRITE) ] = {
351 [ C(RESULT_ACCESS) ] = -1,
352 [ C(RESULT_MISS) ] = -1,
353 },
354 [ C(OP_PREFETCH) ] = {
355 [ C(RESULT_ACCESS) ] = -1,
356 [ C(RESULT_MISS) ] = -1,
357 },
358 },
359 [ C(BPU ) ] = {
360 [ C(OP_READ) ] = {
361 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
362 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
363 },
364 [ C(OP_WRITE) ] = {
365 [ C(RESULT_ACCESS) ] = -1,
366 [ C(RESULT_MISS) ] = -1,
367 },
368 [ C(OP_PREFETCH) ] = {
369 [ C(RESULT_ACCESS) ] = -1,
370 [ C(RESULT_MISS) ] = -1,
371 },
372 },
373};
374
db48cccc 375static __initconst u64 core2_hw_cache_event_ids
8326f44d
IM		 376 [PERF_COUNT_HW_CACHE_MAX]
377 [PERF_COUNT_HW_CACHE_OP_MAX]
378 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
379{
0312af84
TG		 380 [ C(L1D) ] = {
381 [ C(OP_READ) ] = {
382 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
383 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
384 },
385 [ C(OP_WRITE) ] = {
386 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
387 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
388 },
389 [ C(OP_PREFETCH) ] = {
390 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
391 [ C(RESULT_MISS) ] = 0,
392 },
393 },
394 [ C(L1I ) ] = {
395 [ C(OP_READ) ] = {
396 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
397 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
398 },
399 [ C(OP_WRITE) ] = {
400 [ C(RESULT_ACCESS) ] = -1,
401 [ C(RESULT_MISS) ] = -1,
402 },
403 [ C(OP_PREFETCH) ] = {
404 [ C(RESULT_ACCESS) ] = 0,
405 [ C(RESULT_MISS) ] = 0,
406 },
407 },
8be6e8f3 408 [ C(LL ) ] = {
0312af84
TG		 409 [ C(OP_READ) ] = {
410 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
411 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
412 },
413 [ C(OP_WRITE) ] = {
414 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
415 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
416 },
417 [ C(OP_PREFETCH) ] = {
418 [ C(RESULT_ACCESS) ] = 0,
419 [ C(RESULT_MISS) ] = 0,
420 },
421 },
422 [ C(DTLB) ] = {
423 [ C(OP_READ) ] = {
424 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
425 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
426 },
427 [ C(OP_WRITE) ] = {
428 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
429 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
430 },
431 [ C(OP_PREFETCH) ] = {
432 [ C(RESULT_ACCESS) ] = 0,
433 [ C(RESULT_MISS) ] = 0,
434 },
435 },
436 [ C(ITLB) ] = {
437 [ C(OP_READ) ] = {
438 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
439 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
440 },
441 [ C(OP_WRITE) ] = {
442 [ C(RESULT_ACCESS) ] = -1,
443 [ C(RESULT_MISS) ] = -1,
444 },
445 [ C(OP_PREFETCH) ] = {
446 [ C(RESULT_ACCESS) ] = -1,
447 [ C(RESULT_MISS) ] = -1,
448 },
449 },
450 [ C(BPU ) ] = {
451 [ C(OP_READ) ] = {
452 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
453 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
454 },
455 [ C(OP_WRITE) ] = {
456 [ C(RESULT_ACCESS) ] = -1,
457 [ C(RESULT_MISS) ] = -1,
458 },
459 [ C(OP_PREFETCH) ] = {
460 [ C(RESULT_ACCESS) ] = -1,
461 [ C(RESULT_MISS) ] = -1,
462 },
463 },
8326f44d
IM		 464};
465
db48cccc 466static __initconst u64 atom_hw_cache_event_ids
8326f44d
IM		 467 [PERF_COUNT_HW_CACHE_MAX]
468 [PERF_COUNT_HW_CACHE_OP_MAX]
469 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
470{
ad689220
TG		 471 [ C(L1D) ] = {
472 [ C(OP_READ) ] = {
473 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
474 [ C(RESULT_MISS) ] = 0,
475 },
476 [ C(OP_WRITE) ] = {
fecc8ac8 477 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
ad689220
TG		 478 [ C(RESULT_MISS) ] = 0,
479 },
480 [ C(OP_PREFETCH) ] = {
481 [ C(RESULT_ACCESS) ] = 0x0,
482 [ C(RESULT_MISS) ] = 0,
483 },
484 },
485 [ C(L1I ) ] = {
486 [ C(OP_READ) ] = {
fecc8ac8
YW		 487 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
488 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
ad689220
TG		 489 },
490 [ C(OP_WRITE) ] = {
491 [ C(RESULT_ACCESS) ] = -1,
492 [ C(RESULT_MISS) ] = -1,
493 },
494 [ C(OP_PREFETCH) ] = {
495 [ C(RESULT_ACCESS) ] = 0,
496 [ C(RESULT_MISS) ] = 0,
497 },
498 },
8be6e8f3 499 [ C(LL ) ] = {
ad689220
TG		 500 [ C(OP_READ) ] = {
501 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
502 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
503 },
504 [ C(OP_WRITE) ] = {
505 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
506 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
507 },
508 [ C(OP_PREFETCH) ] = {
509 [ C(RESULT_ACCESS) ] = 0,
510 [ C(RESULT_MISS) ] = 0,
511 },
512 },
513 [ C(DTLB) ] = {
514 [ C(OP_READ) ] = {
fecc8ac8 515 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
ad689220
TG		 516 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
517 },
518 [ C(OP_WRITE) ] = {
fecc8ac8 519 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
ad689220
TG		 520 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
521 },
522 [ C(OP_PREFETCH) ] = {
523 [ C(RESULT_ACCESS) ] = 0,
524 [ C(RESULT_MISS) ] = 0,
525 },
526 },
527 [ C(ITLB) ] = {
528 [ C(OP_READ) ] = {
529 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
530 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
531 },
532 [ C(OP_WRITE) ] = {
533 [ C(RESULT_ACCESS) ] = -1,
534 [ C(RESULT_MISS) ] = -1,
535 },
536 [ C(OP_PREFETCH) ] = {
537 [ C(RESULT_ACCESS) ] = -1,
538 [ C(RESULT_MISS) ] = -1,
539 },
540 },
541 [ C(BPU ) ] = {
542 [ C(OP_READ) ] = {
543 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
544 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
545 },
546 [ C(OP_WRITE) ] = {
547 [ C(RESULT_ACCESS) ] = -1,
548 [ C(RESULT_MISS) ] = -1,
549 },
550 [ C(OP_PREFETCH) ] = {
551 [ C(RESULT_ACCESS) ] = -1,
552 [ C(RESULT_MISS) ] = -1,
553 },
554 },
8326f44d
IM		 555};
556
dfc65094 557static u64 intel_pmu_raw_event(u64 hw_event)
b0f3f28e 558{
82bae4f8
PZ		 559#define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL
560#define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL
ff99be57
PZ		 561#define CORE_EVNTSEL_EDGE_MASK 0x00040000ULL
562#define CORE_EVNTSEL_INV_MASK 0x00800000ULL
fe9081cc 563#define CORE_EVNTSEL_REG_MASK 0xFF000000ULL
b0f3f28e 564
128f048f 565#define CORE_EVNTSEL_MASK \
1da53e02
SE		 566 (INTEL_ARCH_EVTSEL_MASK | \
567 INTEL_ARCH_UNIT_MASK | \
568 INTEL_ARCH_EDGE_MASK | \
569 INTEL_ARCH_INV_MASK | \
570 INTEL_ARCH_CNT_MASK)
b0f3f28e 571
dfc65094 572 return hw_event & CORE_EVNTSEL_MASK;
b0f3f28e
PZ		 573}
574
db48cccc 575static __initconst u64 amd_hw_cache_event_ids
f86748e9
TG		 576 [PERF_COUNT_HW_CACHE_MAX]
577 [PERF_COUNT_HW_CACHE_OP_MAX]
578 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
579{
580 [ C(L1D) ] = {
581 [ C(OP_READ) ] = {
f4db43a3
JSR		 582 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
583 [ C(RESULT_MISS) ] = 0x0041, /* Data Cache Misses */
f86748e9
TG		 584 },
585 [ C(OP_WRITE) ] = {
d9f2a5ec 586 [ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */
f86748e9
TG		 587 [ C(RESULT_MISS) ] = 0,
588 },
589 [ C(OP_PREFETCH) ] = {
f4db43a3
JSR		 590 [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */
591 [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */
f86748e9
TG		 592 },
593 },
594 [ C(L1I ) ] = {
595 [ C(OP_READ) ] = {
596 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches */
597 [ C(RESULT_MISS) ] = 0x0081, /* Instruction cache misses */
598 },
599 [ C(OP_WRITE) ] = {
600 [ C(RESULT_ACCESS) ] = -1,
601 [ C(RESULT_MISS) ] = -1,
602 },
603 [ C(OP_PREFETCH) ] = {
f4db43a3 604 [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */
f86748e9
TG		 605 [ C(RESULT_MISS) ] = 0,
606 },
607 },
8be6e8f3 608 [ C(LL ) ] = {
f86748e9 609 [ C(OP_READ) ] = {
f4db43a3
JSR		 610 [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */
611 [ C(RESULT_MISS) ] = 0x037E, /* L2 Cache Misses : IC+DC */
f86748e9
TG		 612 },
613 [ C(OP_WRITE) ] = {
f4db43a3 614 [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback */
f86748e9
TG		 615 [ C(RESULT_MISS) ] = 0,
616 },
617 [ C(OP_PREFETCH) ] = {
618 [ C(RESULT_ACCESS) ] = 0,
619 [ C(RESULT_MISS) ] = 0,
620 },
621 },
622 [ C(DTLB) ] = {
623 [ C(OP_READ) ] = {
f4db43a3
JSR		 624 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
625 [ C(RESULT_MISS) ] = 0x0046, /* L1 DTLB and L2 DLTB Miss */
f86748e9
TG		 626 },
627 [ C(OP_WRITE) ] = {
628 [ C(RESULT_ACCESS) ] = 0,
629 [ C(RESULT_MISS) ] = 0,
630 },
631 [ C(OP_PREFETCH) ] = {
632 [ C(RESULT_ACCESS) ] = 0,
633 [ C(RESULT_MISS) ] = 0,
634 },
635 },
636 [ C(ITLB) ] = {
637 [ C(OP_READ) ] = {
638 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes */
639 [ C(RESULT_MISS) ] = 0x0085, /* Instr. fetch ITLB misses */
640 },
641 [ C(OP_WRITE) ] = {
642 [ C(RESULT_ACCESS) ] = -1,
643 [ C(RESULT_MISS) ] = -1,
644 },
645 [ C(OP_PREFETCH) ] = {
646 [ C(RESULT_ACCESS) ] = -1,
647 [ C(RESULT_MISS) ] = -1,
648 },
649 },
650 [ C(BPU ) ] = {
651 [ C(OP_READ) ] = {
652 [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr. */
653 [ C(RESULT_MISS) ] = 0x00c3, /* Retired Mispredicted BI */
654 },
655 [ C(OP_WRITE) ] = {
656 [ C(RESULT_ACCESS) ] = -1,
657 [ C(RESULT_MISS) ] = -1,
658 },
659 [ C(OP_PREFETCH) ] = {
660 [ C(RESULT_ACCESS) ] = -1,
661 [ C(RESULT_MISS) ] = -1,
662 },
663 },
664};
665
f87ad35d
JSR		 666/*
667 * AMD Performance Monitor K7 and later.
668 */
b0f3f28e 669static const u64 amd_perfmon_event_map[] =
f87ad35d 670{
f4dbfa8f
PZ		 671 [PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
672 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
673 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0080,
674 [PERF_COUNT_HW_CACHE_MISSES] = 0x0081,
675 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
676 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
f87ad35d
JSR		 677};
678
dfc65094 679static u64 amd_pmu_event_map(int hw_event)
f87ad35d 680{
dfc65094 681 return amd_perfmon_event_map[hw_event];
f87ad35d
JSR		 682}
683
dfc65094 684static u64 amd_pmu_raw_event(u64 hw_event)
b0f3f28e 685{
82bae4f8
PZ		 686#define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL
687#define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL
ff99be57
PZ		 688#define K7_EVNTSEL_EDGE_MASK 0x000040000ULL
689#define K7_EVNTSEL_INV_MASK 0x000800000ULL
cdd6c482 690#define K7_EVNTSEL_REG_MASK 0x0FF000000ULL
b0f3f28e
PZ		 691
692#define K7_EVNTSEL_MASK \
693 (K7_EVNTSEL_EVENT_MASK | \
694 K7_EVNTSEL_UNIT_MASK | \
ff99be57
PZ		 695 K7_EVNTSEL_EDGE_MASK | \
696 K7_EVNTSEL_INV_MASK | \
cdd6c482 697 K7_EVNTSEL_REG_MASK)
b0f3f28e 698
dfc65094 699 return hw_event & K7_EVNTSEL_MASK;
b0f3f28e
PZ		 700}
701
ee06094f 702/*
cdd6c482
IM		 703 * Propagate event elapsed time into the generic event.
704 * Can only be executed on the CPU where the event is active.
ee06094f
IM		 705 * Returns the delta events processed.
706 */
4b7bfd0d 707static u64
cdd6c482
IM		 708x86_perf_event_update(struct perf_event *event,
709 struct hw_perf_event *hwc, int idx)
ee06094f 710{
cdd6c482 711 int shift = 64 - x86_pmu.event_bits;
ec3232bd
PZ		 712 u64 prev_raw_count, new_raw_count;
713 s64 delta;
ee06094f 714
30dd568c
MM		 715 if (idx == X86_PMC_IDX_FIXED_BTS)
716 return 0;
717
ee06094f 718 /*
cdd6c482 719 * Careful: an NMI might modify the previous event value.
ee06094f
IM		 720 *
721 * Our tactic to handle this is to first atomically read and
722 * exchange a new raw count - then add that new-prev delta
cdd6c482 723 * count to the generic event atomically:
ee06094f
IM		 724 */
725again:
726 prev_raw_count = atomic64_read(&hwc->prev_count);
cdd6c482 727 rdmsrl(hwc->event_base + idx, new_raw_count);
ee06094f
IM		 728
729 if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
730 new_raw_count) != prev_raw_count)
731 goto again;
732
733 /*
734 * Now we have the new raw value and have updated the prev
735 * timestamp already. We can now calculate the elapsed delta
cdd6c482 736 * (event-)time and add that to the generic event.
ee06094f
IM		 737 *
738 * Careful, not all hw sign-extends above the physical width
ec3232bd 739 * of the count.
ee06094f 740 */
ec3232bd
PZ		 741 delta = (new_raw_count << shift) - (prev_raw_count << shift);
742 delta >>= shift;
ee06094f 743
cdd6c482 744 atomic64_add(delta, &event->count);
ee06094f 745 atomic64_sub(delta, &hwc->period_left);
4b7bfd0d
RR		 746
747 return new_raw_count;
ee06094f
IM		 748}
749
cdd6c482 750static atomic_t active_events;
4e935e47
PZ		 751static DEFINE_MUTEX(pmc_reserve_mutex);
752
753static bool reserve_pmc_hardware(void)
754{
04da8a43 755#ifdef CONFIG_X86_LOCAL_APIC
4e935e47
PZ		 756 int i;
757
758 if (nmi_watchdog == NMI_LOCAL_APIC)
759 disable_lapic_nmi_watchdog();
760
cdd6c482 761 for (i = 0; i < x86_pmu.num_events; i++) {
4a06bd85 762 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
4e935e47
PZ		 763 goto perfctr_fail;
764 }
765
cdd6c482 766 for (i = 0; i < x86_pmu.num_events; i++) {
4a06bd85 767 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
4e935e47
PZ		 768 goto eventsel_fail;
769 }
04da8a43 770#endif
4e935e47
PZ		 771
772 return true;
773
04da8a43 774#ifdef CONFIG_X86_LOCAL_APIC
4e935e47
PZ		 775eventsel_fail:
776 for (i--; i >= 0; i--)
4a06bd85 777 release_evntsel_nmi(x86_pmu.eventsel + i);
4e935e47 778
cdd6c482 779 i = x86_pmu.num_events;
4e935e47
PZ		 780
781perfctr_fail:
782 for (i--; i >= 0; i--)
4a06bd85 783 release_perfctr_nmi(x86_pmu.perfctr + i);
4e935e47
PZ		 784
785 if (nmi_watchdog == NMI_LOCAL_APIC)
786 enable_lapic_nmi_watchdog();
787
788 return false;
04da8a43 789#endif
4e935e47
PZ		 790}
791
792static void release_pmc_hardware(void)
793{
04da8a43 794#ifdef CONFIG_X86_LOCAL_APIC
4e935e47
PZ		 795 int i;
796
cdd6c482 797 for (i = 0; i < x86_pmu.num_events; i++) {
4a06bd85
RR		 798 release_perfctr_nmi(x86_pmu.perfctr + i);
799 release_evntsel_nmi(x86_pmu.eventsel + i);
4e935e47
PZ		 800 }
801
802 if (nmi_watchdog == NMI_LOCAL_APIC)
803 enable_lapic_nmi_watchdog();
04da8a43 804#endif
4e935e47
PZ		 805}
806
30dd568c
MM		 807static inline bool bts_available(void)
808{
809 return x86_pmu.enable_bts != NULL;
810}
811
812static inline void init_debug_store_on_cpu(int cpu)
813{
cdd6c482 814 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
30dd568c
MM		 815
816 if (!ds)
817 return;
818
819 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
596da17f 820 (u32)((u64)(unsigned long)ds),
821 (u32)((u64)(unsigned long)ds >> 32));
30dd568c
MM		 822}
823
824static inline void fini_debug_store_on_cpu(int cpu)
825{
cdd6c482 826 if (!per_cpu(cpu_hw_events, cpu).ds)
30dd568c
MM		 827 return;
828
829 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
830}
831
832static void release_bts_hardware(void)
833{
834 int cpu;
835
836 if (!bts_available())
837 return;
838
839 get_online_cpus();
840
841 for_each_online_cpu(cpu)
842 fini_debug_store_on_cpu(cpu);
843
844 for_each_possible_cpu(cpu) {
cdd6c482 845 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
30dd568c
MM		 846
847 if (!ds)
848 continue;
849
cdd6c482 850 per_cpu(cpu_hw_events, cpu).ds = NULL;
30dd568c 851
596da17f 852 kfree((void *)(unsigned long)ds->bts_buffer_base);
30dd568c
MM		 853 kfree(ds);
854 }
855
856 put_online_cpus();
857}
858
859static int reserve_bts_hardware(void)
860{
861 int cpu, err = 0;
862
863 if (!bts_available())
747b50aa 864 return 0;
30dd568c
MM		 865
866 get_online_cpus();
867
868 for_each_possible_cpu(cpu) {
869 struct debug_store *ds;
870 void *buffer;
871
872 err = -ENOMEM;
873 buffer = kzalloc(BTS_BUFFER_SIZE, GFP_KERNEL);
874 if (unlikely(!buffer))
875 break;
876
877 ds = kzalloc(sizeof(*ds), GFP_KERNEL);
878 if (unlikely(!ds)) {
879 kfree(buffer);
880 break;
881 }
882
596da17f 883 ds->bts_buffer_base = (u64)(unsigned long)buffer;
30dd568c
MM		 884 ds->bts_index = ds->bts_buffer_base;
885 ds->bts_absolute_maximum =
886 ds->bts_buffer_base + BTS_BUFFER_SIZE;
887 ds->bts_interrupt_threshold =
888 ds->bts_absolute_maximum - BTS_OVFL_TH;
889
cdd6c482 890 per_cpu(cpu_hw_events, cpu).ds = ds;
30dd568c
MM		 891 err = 0;
892 }
893
894 if (err)
895 release_bts_hardware();
896 else {
897 for_each_online_cpu(cpu)
898 init_debug_store_on_cpu(cpu);
899 }
900
901 put_online_cpus();
902
903 return err;
904}
905
cdd6c482 906static void hw_perf_event_destroy(struct perf_event *event)
4e935e47 907{
cdd6c482 908 if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
4e935e47 909 release_pmc_hardware();
30dd568c 910 release_bts_hardware();
4e935e47
PZ		 911 mutex_unlock(&pmc_reserve_mutex);
912 }
913}
914
85cf9dba
RR		 915static inline int x86_pmu_initialized(void)
916{
917 return x86_pmu.handle_irq != NULL;
918}
919
8326f44d 920static inline int
cdd6c482 921set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
8326f44d
IM		 922{
923 unsigned int cache_type, cache_op, cache_result;
924 u64 config, val;
925
926 config = attr->config;
927
928 cache_type = (config >> 0) & 0xff;
929 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
930 return -EINVAL;
931
932 cache_op = (config >> 8) & 0xff;
933 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
934 return -EINVAL;
935
936 cache_result = (config >> 16) & 0xff;
937 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
938 return -EINVAL;
939
940 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
941
942 if (val == 0)
943 return -ENOENT;
944
945 if (val == -1)
946 return -EINVAL;
947
948 hwc->config |= val;
949
950 return 0;
951}
952
30dd568c
MM		 953static void intel_pmu_enable_bts(u64 config)
954{
955 unsigned long debugctlmsr;
956
957 debugctlmsr = get_debugctlmsr();
958
959 debugctlmsr |= X86_DEBUGCTL_TR;
960 debugctlmsr |= X86_DEBUGCTL_BTS;
961 debugctlmsr |= X86_DEBUGCTL_BTINT;
962
963 if (!(config & ARCH_PERFMON_EVENTSEL_OS))
964 debugctlmsr |= X86_DEBUGCTL_BTS_OFF_OS;
965
966 if (!(config & ARCH_PERFMON_EVENTSEL_USR))
967 debugctlmsr |= X86_DEBUGCTL_BTS_OFF_USR;
968
969 update_debugctlmsr(debugctlmsr);
970}
971
972static void intel_pmu_disable_bts(void)
973{
cdd6c482 974 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
30dd568c
MM		 975 unsigned long debugctlmsr;
976
977 if (!cpuc->ds)
978 return;
979
980 debugctlmsr = get_debugctlmsr();
981
982 debugctlmsr &=
983 ~(X86_DEBUGCTL_TR | X86_DEBUGCTL_BTS | X86_DEBUGCTL_BTINT |
984 X86_DEBUGCTL_BTS_OFF_OS | X86_DEBUGCTL_BTS_OFF_USR);
985
986 update_debugctlmsr(debugctlmsr);
987}
988
241771ef 989/*
0d48696f 990 * Setup the hardware configuration for a given attr_type
241771ef 991 */
cdd6c482 992static int __hw_perf_event_init(struct perf_event *event)
241771ef 993{
cdd6c482
IM		 994 struct perf_event_attr *attr = &event->attr;
995 struct hw_perf_event *hwc = &event->hw;
9c74fb50 996 u64 config;
4e935e47 997 int err;
241771ef 998
85cf9dba
RR		 999 if (!x86_pmu_initialized())
1000 return -ENODEV;
241771ef 1001
4e935e47 1002 err = 0;
cdd6c482 1003 if (!atomic_inc_not_zero(&active_events)) {
4e935e47 1004 mutex_lock(&pmc_reserve_mutex);
cdd6c482 1005 if (atomic_read(&active_events) == 0) {
30dd568c
MM		 1006 if (!reserve_pmc_hardware())
1007 err = -EBUSY;
1008 else
747b50aa 1009 err = reserve_bts_hardware();
30dd568c
MM		 1010 }
1011 if (!err)
cdd6c482 1012 atomic_inc(&active_events);
4e935e47
PZ		 1013 mutex_unlock(&pmc_reserve_mutex);
1014 }
1015 if (err)
1016 return err;
1017
cdd6c482 1018 event->destroy = hw_perf_event_destroy;
a1792cda 1019
241771ef 1020 /*
0475f9ea 1021 * Generate PMC IRQs:
241771ef
IM		 1022 * (keep 'enabled' bit clear for now)
1023 */
0475f9ea 1024 hwc->config = ARCH_PERFMON_EVENTSEL_INT;
241771ef 1025
b690081d
SE		 1026 hwc->idx = -1;
1027
241771ef 1028 /*
0475f9ea 1029 * Count user and OS events unless requested not to.
241771ef 1030 */
0d48696f 1031 if (!attr->exclude_user)
0475f9ea 1032 hwc->config |= ARCH_PERFMON_EVENTSEL_USR;
0d48696f 1033 if (!attr->exclude_kernel)
241771ef 1034 hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
0475f9ea 1035
bd2b5b12 1036 if (!hwc->sample_period) {
b23f3325 1037 hwc->sample_period = x86_pmu.max_period;
9e350de3 1038 hwc->last_period = hwc->sample_period;
bd2b5b12 1039 atomic64_set(&hwc->period_left, hwc->sample_period);
04da8a43
IM		 1040 } else {
1041 /*
1042 * If we have a PMU initialized but no APIC
1043 * interrupts, we cannot sample hardware
cdd6c482
IM		 1044 * events (user-space has to fall back and
1045 * sample via a hrtimer based software event):
04da8a43
IM		 1046 */
1047 if (!x86_pmu.apic)
1048 return -EOPNOTSUPP;
bd2b5b12 1049 }
d2517a49 1050
241771ef 1051 /*
dfc65094 1052 * Raw hw_event type provide the config in the hw_event structure
241771ef 1053 */
a21ca2ca
IM		 1054 if (attr->type == PERF_TYPE_RAW) {
1055 hwc->config |= x86_pmu.raw_event(attr->config);
8326f44d 1056 return 0;
241771ef 1057 }
241771ef 1058
8326f44d
IM		 1059 if (attr->type == PERF_TYPE_HW_CACHE)
1060 return set_ext_hw_attr(hwc, attr);
1061
1062 if (attr->config >= x86_pmu.max_events)
1063 return -EINVAL;
9c74fb50 1064
8326f44d
IM		 1065 /*
1066 * The generic map:
1067 */
9c74fb50
PZ		 1068 config = x86_pmu.event_map(attr->config);
1069
1070 if (config == 0)
1071 return -ENOENT;
1072
1073 if (config == -1LL)
1074 return -EINVAL;
1075
747b50aa 1076 /*
1077 * Branch tracing:
1078 */
1079 if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
1653192f 1080 (hwc->sample_period == 1)) {
1081 /* BTS is not supported by this architecture. */
1082 if (!bts_available())
1083 return -EOPNOTSUPP;
1084
1085 /* BTS is currently only allowed for user-mode. */
1086 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1087 return -EOPNOTSUPP;
1088 }
747b50aa 1089
9c74fb50 1090 hwc->config |= config;
4e935e47 1091
241771ef
IM		 1092 return 0;
1093}
1094
11d1578f
VW		 1095static void p6_pmu_disable_all(void)
1096{
cdd6c482 1097 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
9c74fb50 1098 u64 val;
11d1578f
VW		 1099
1100 if (!cpuc->enabled)
1101 return;
1102
1103 cpuc->enabled = 0;
1104 barrier();
1105
1106 /* p6 only has one enable register */
1107 rdmsrl(MSR_P6_EVNTSEL0, val);
1108 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
1109 wrmsrl(MSR_P6_EVNTSEL0, val);
1110}
1111
9e35ad38 1112static void intel_pmu_disable_all(void)
4ac13294 1113{
cdd6c482 1114 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
30dd568c
MM		 1115
1116 if (!cpuc->enabled)
1117 return;
1118
1119 cpuc->enabled = 0;
1120 barrier();
1121
862a1a5f 1122 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
30dd568c
MM		 1123
1124 if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask))
1125 intel_pmu_disable_bts();
241771ef 1126}
b56a3802 1127
9e35ad38 1128static void amd_pmu_disable_all(void)
f87ad35d 1129{
cdd6c482 1130 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
9e35ad38
PZ		 1131 int idx;
1132
1133 if (!cpuc->enabled)
1134 return;
b0f3f28e 1135
b0f3f28e 1136 cpuc->enabled = 0;
60b3df9c
PZ		 1137 /*
1138 * ensure we write the disable before we start disabling the
cdd6c482 1139 * events proper, so that amd_pmu_enable_event() does the
5f4ec28f 1140 * right thing.
60b3df9c 1141 */
b0f3f28e 1142 barrier();
f87ad35d 1143
cdd6c482 1144 for (idx = 0; idx < x86_pmu.num_events; idx++) {
b0f3f28e
PZ		 1145 u64 val;
1146
43f6201a 1147 if (!test_bit(idx, cpuc->active_mask))
4295ee62 1148 continue;
f87ad35d 1149 rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
4295ee62
RR		 1150 if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE))
1151 continue;
1152 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
1153 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
f87ad35d 1154 }
f87ad35d
JSR		 1155}
1156
9e35ad38 1157void hw_perf_disable(void)
b56a3802 1158{
1da53e02
SE		 1159 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1160
85cf9dba 1161 if (!x86_pmu_initialized())
9e35ad38 1162 return;
1da53e02
SE		 1163
1164 if (cpuc->enabled)
1165 cpuc->n_added = 0;
1166
1167 x86_pmu.disable_all();
b56a3802 1168}
241771ef 1169
11d1578f
VW		 1170static void p6_pmu_enable_all(void)
1171{
cdd6c482 1172 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
11d1578f
VW		 1173 unsigned long val;
1174
1175 if (cpuc->enabled)
1176 return;
1177
1178 cpuc->enabled = 1;
1179 barrier();
1180
1181 /* p6 only has one enable register */
1182 rdmsrl(MSR_P6_EVNTSEL0, val);
1183 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
1184 wrmsrl(MSR_P6_EVNTSEL0, val);
1185}
1186
9e35ad38 1187static void intel_pmu_enable_all(void)
b56a3802 1188{
cdd6c482 1189 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
30dd568c
MM		 1190
1191 if (cpuc->enabled)
1192 return;
1193
1194 cpuc->enabled = 1;
1195 barrier();
1196
9e35ad38 1197 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
30dd568c
MM		 1198
1199 if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
cdd6c482
IM		 1200 struct perf_event *event =
1201 cpuc->events[X86_PMC_IDX_FIXED_BTS];
30dd568c 1202
cdd6c482 1203 if (WARN_ON_ONCE(!event))
30dd568c
MM		 1204 return;
1205
cdd6c482 1206 intel_pmu_enable_bts(event->hw.config);
30dd568c 1207 }
b56a3802
JSR		 1208}
1209
9e35ad38 1210static void amd_pmu_enable_all(void)
f87ad35d 1211{
cdd6c482 1212 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
f87ad35d
JSR		 1213 int idx;
1214
9e35ad38 1215 if (cpuc->enabled)
b0f3f28e
PZ		 1216 return;
1217
9e35ad38
PZ		 1218 cpuc->enabled = 1;
1219 barrier();
1220
cdd6c482
IM		 1221 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1222 struct perf_event *event = cpuc->events[idx];
4295ee62 1223 u64 val;
b0f3f28e 1224
43f6201a 1225 if (!test_bit(idx, cpuc->active_mask))
4295ee62 1226 continue;
984b838c 1227
cdd6c482 1228 val = event->hw.config;
4295ee62
RR		 1229 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
1230 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
f87ad35d
JSR		 1231 }
1232}
1233
1da53e02
SE		 1234static const struct pmu pmu;
1235
1236static inline int is_x86_event(struct perf_event *event)
1237{
1238 return event->pmu == &pmu;
1239}
1240
1241static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
1242{
1243 int i, j , w, num;
1244 int weight, wmax;
1245 unsigned long *c;
81269a08 1246 unsigned long constraints[X86_PMC_IDX_MAX][BITS_TO_LONGS(X86_PMC_IDX_MAX)];
1da53e02
SE		 1247 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
1248 struct hw_perf_event *hwc;
1249
1250 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
1251
1252 for (i = 0; i < n; i++) {
1253 x86_pmu.get_event_constraints(cpuc,
1254 cpuc->event_list[i],
1255 constraints[i]);
1256 }
1257
8113070d
SE		 1258 /*
1259 * fastpath, try to reuse previous register
1260 */
1261 for (i = 0, num = n; i < n; i++, num--) {
1262 hwc = &cpuc->event_list[i]->hw;
81269a08 1263 c = constraints[i];
8113070d
SE		 1264
1265 /* never assigned */
1266 if (hwc->idx == -1)
1267 break;
1268
1269 /* constraint still honored */
1270 if (!test_bit(hwc->idx, c))
1271 break;
1272
1273 /* not already used */
1274 if (test_bit(hwc->idx, used_mask))
1275 break;
1276
1277#if 0
1278 pr_debug("CPU%d fast config=0x%llx idx=%d assign=%c\n",
1279 smp_processor_id(),
1280 hwc->config,
1281 hwc->idx,
1282 assign ? 'y' : 'n');
1283#endif
1284
1285 set_bit(hwc->idx, used_mask);
1286 if (assign)
1287 assign[i] = hwc->idx;
1288 }
1289 if (!num)
1290 goto done;
1291
1292 /*
1293 * begin slow path
1294 */
1295
1296 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
1297
1da53e02
SE		 1298 /*
1299 * weight = number of possible counters
1300 *
1301 * 1 = most constrained, only works on one counter
1302 * wmax = least constrained, works on any counter
1303 *
1304 * assign events to counters starting with most
1305 * constrained events.
1306 */
1307 wmax = x86_pmu.num_events;
1308
1309 /*
1310 * when fixed event counters are present,
1311 * wmax is incremented by 1 to account
1312 * for one more choice
1313 */
1314 if (x86_pmu.num_events_fixed)
1315 wmax++;
1316
8113070d 1317 for (w = 1, num = n; num && w <= wmax; w++) {
1da53e02 1318 /* for each event */
8113070d 1319 for (i = 0; num && i < n; i++) {
81269a08 1320 c = constraints[i];
1da53e02
SE		 1321 hwc = &cpuc->event_list[i]->hw;
1322
1323 weight = bitmap_weight(c, X86_PMC_IDX_MAX);
1324 if (weight != w)
1325 continue;
1326
1da53e02
SE		 1327 for_each_bit(j, c, X86_PMC_IDX_MAX) {
1328 if (!test_bit(j, used_mask))
1329 break;
1330 }
1331
1332 if (j == X86_PMC_IDX_MAX)
1333 break;
1da53e02
SE		 1334
1335#if 0
8113070d 1336 pr_debug("CPU%d slow config=0x%llx idx=%d assign=%c\n",
1da53e02
SE		 1337 smp_processor_id(),
1338 hwc->config,
1339 j,
1340 assign ? 'y' : 'n');
1341#endif
1342
8113070d
SE		 1343 set_bit(j, used_mask);
1344
1da53e02
SE		 1345 if (assign)
1346 assign[i] = j;
1347 num--;
1348 }
1349 }
8113070d 1350done:
1da53e02
SE		 1351 /*
1352 * scheduling failed or is just a simulation,
1353 * free resources if necessary
1354 */
1355 if (!assign || num) {
1356 for (i = 0; i < n; i++) {
1357 if (x86_pmu.put_event_constraints)
1358 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
1359 }
1360 }
1361 return num ? -ENOSPC : 0;
1362}
1363
1364/*
1365 * dogrp: true if must collect siblings events (group)
1366 * returns total number of events and error code
1367 */
1368static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
1369{
1370 struct perf_event *event;
1371 int n, max_count;
1372
1373 max_count = x86_pmu.num_events + x86_pmu.num_events_fixed;
1374
1375 /* current number of events already accepted */
1376 n = cpuc->n_events;
1377
1378 if (is_x86_event(leader)) {
1379 if (n >= max_count)
1380 return -ENOSPC;
1381 cpuc->event_list[n] = leader;
1382 n++;
1383 }
1384 if (!dogrp)
1385 return n;
1386
1387 list_for_each_entry(event, &leader->sibling_list, group_entry) {
1388 if (!is_x86_event(event) ||
8113070d 1389 event->state <= PERF_EVENT_STATE_OFF)
1da53e02
SE		 1390 continue;
1391
1392 if (n >= max_count)
1393 return -ENOSPC;
1394
1395 cpuc->event_list[n] = event;
1396 n++;
1397 }
1398 return n;
1399}
1400
1401
1402static inline void x86_assign_hw_event(struct perf_event *event,
1403 struct hw_perf_event *hwc, int idx)
1404{
1405 hwc->idx = idx;
1406
1407 if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
1408 hwc->config_base = 0;
1409 hwc->event_base = 0;
1410 } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
1411 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1412 /*
1413 * We set it so that event_base + idx in wrmsr/rdmsr maps to
1414 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
1415 */
1416 hwc->event_base =
1417 MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
1418 } else {
1419 hwc->config_base = x86_pmu.eventsel;
1420 hwc->event_base = x86_pmu.perfctr;
1421 }
1422}
1423
9e35ad38 1424void hw_perf_enable(void)
ee06094f 1425{
1da53e02
SE		 1426 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1427 struct perf_event *event;
1428 struct hw_perf_event *hwc;
1429 int i;
1430
85cf9dba 1431 if (!x86_pmu_initialized())
2b9ff0db 1432 return;
1da53e02
SE		 1433 if (cpuc->n_added) {
1434 /*
1435 * apply assignment obtained either from
1436 * hw_perf_group_sched_in() or x86_pmu_enable()
1437 *
1438 * step1: save events moving to new counters
1439 * step2: reprogram moved events into new counters
1440 */
1441 for (i = 0; i < cpuc->n_events; i++) {
1442
1443 event = cpuc->event_list[i];
1444 hwc = &event->hw;
1445
1446 if (hwc->idx == -1 || hwc->idx == cpuc->assign[i])
1447 continue;
1448
1449 x86_pmu.disable(hwc, hwc->idx);
1450
1451 clear_bit(hwc->idx, cpuc->active_mask);
1452 barrier();
1453 cpuc->events[hwc->idx] = NULL;
1454
1455 x86_perf_event_update(event, hwc, hwc->idx);
1456
1457 hwc->idx = -1;
1458 }
1459
1460 for (i = 0; i < cpuc->n_events; i++) {
1461
1462 event = cpuc->event_list[i];
1463 hwc = &event->hw;
1464
1465 if (hwc->idx == -1) {
1466 x86_assign_hw_event(event, hwc, cpuc->assign[i]);
1467 x86_perf_event_set_period(event, hwc, hwc->idx);
1468 }
1469 /*
1470 * need to mark as active because x86_pmu_disable()
1471 * clear active_mask and eventsp[] yet it preserves
1472 * idx
1473 */
1474 set_bit(hwc->idx, cpuc->active_mask);
1475 cpuc->events[hwc->idx] = event;
1476
1477 x86_pmu.enable(hwc, hwc->idx);
1478 perf_event_update_userpage(event);
1479 }
1480 cpuc->n_added = 0;
1481 perf_events_lapic_init();
1482 }
9e35ad38 1483 x86_pmu.enable_all();
ee06094f 1484}
ee06094f 1485
19d84dab 1486static inline u64 intel_pmu_get_status(void)
b0f3f28e
PZ		 1487{
1488 u64 status;
1489
b7f8859a 1490 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
b0f3f28e 1491
b7f8859a 1492 return status;
b0f3f28e
PZ		 1493}
1494
dee5d906 1495static inline void intel_pmu_ack_status(u64 ack)
b0f3f28e
PZ		 1496{
1497 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1498}
1499
cdd6c482 1500static inline void x86_pmu_enable_event(struct hw_perf_event *hwc, int idx)
b0f3f28e 1501{
11d1578f 1502 (void)checking_wrmsrl(hwc->config_base + idx,
7c90cc45 1503 hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE);
b0f3f28e
PZ		 1504}
1505
cdd6c482 1506static inline void x86_pmu_disable_event(struct hw_perf_event *hwc, int idx)
b0f3f28e 1507{
11d1578f 1508 (void)checking_wrmsrl(hwc->config_base + idx, hwc->config);
b0f3f28e
PZ		 1509}
1510
2f18d1e8 1511static inline void
cdd6c482 1512intel_pmu_disable_fixed(struct hw_perf_event *hwc, int __idx)
2f18d1e8
IM		 1513{
1514 int idx = __idx - X86_PMC_IDX_FIXED;
1515 u64 ctrl_val, mask;
2f18d1e8
IM		 1516
1517 mask = 0xfULL << (idx * 4);
1518
1519 rdmsrl(hwc->config_base, ctrl_val);
1520 ctrl_val &= ~mask;
11d1578f
VW		 1521 (void)checking_wrmsrl(hwc->config_base, ctrl_val);
1522}
1523
1524static inline void
cdd6c482 1525p6_pmu_disable_event(struct hw_perf_event *hwc, int idx)
11d1578f 1526{
cdd6c482
IM		 1527 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1528 u64 val = P6_NOP_EVENT;
11d1578f 1529
9c74fb50
PZ		 1530 if (cpuc->enabled)
1531 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
11d1578f
VW		 1532
1533 (void)checking_wrmsrl(hwc->config_base + idx, val);
2f18d1e8
IM		 1534}
1535
7e2ae347 1536static inline void
cdd6c482 1537intel_pmu_disable_event(struct hw_perf_event *hwc, int idx)
7e2ae347 1538{
30dd568c
MM		 1539 if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
1540 intel_pmu_disable_bts();
1541 return;
1542 }
1543
d4369891
RR		 1544 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1545 intel_pmu_disable_fixed(hwc, idx);
1546 return;
1547 }
1548
cdd6c482 1549 x86_pmu_disable_event(hwc, idx);
d4369891
RR		 1550}
1551
1552static inline void
cdd6c482 1553amd_pmu_disable_event(struct hw_perf_event *hwc, int idx)
d4369891 1554{
cdd6c482 1555 x86_pmu_disable_event(hwc, idx);
7e2ae347
IM		 1556}
1557
245b2e70 1558static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
241771ef 1559
ee06094f
IM		 1560/*
1561 * Set the next IRQ period, based on the hwc->period_left value.
cdd6c482 1562 * To be called with the event disabled in hw:
ee06094f 1563 */
e4abb5d4 1564static int
cdd6c482
IM		 1565x86_perf_event_set_period(struct perf_event *event,
1566 struct hw_perf_event *hwc, int idx)
241771ef 1567{
2f18d1e8 1568 s64 left = atomic64_read(&hwc->period_left);
e4abb5d4
PZ		 1569 s64 period = hwc->sample_period;
1570 int err, ret = 0;
ee06094f 1571
30dd568c
MM		 1572 if (idx == X86_PMC_IDX_FIXED_BTS)
1573 return 0;
1574
ee06094f 1575 /*
af901ca1 1576 * If we are way outside a reasonable range then just skip forward:
ee06094f
IM		 1577 */
1578 if (unlikely(left <= -period)) {
1579 left = period;
1580 atomic64_set(&hwc->period_left, left);
9e350de3 1581 hwc->last_period = period;
e4abb5d4 1582 ret = 1;
ee06094f
IM		 1583 }
1584
1585 if (unlikely(left <= 0)) {
1586 left += period;
1587 atomic64_set(&hwc->period_left, left);
9e350de3 1588 hwc->last_period = period;
e4abb5d4 1589 ret = 1;
ee06094f 1590 }
1c80f4b5 1591 /*
dfc65094 1592 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1c80f4b5
IM		 1593 */
1594 if (unlikely(left < 2))
1595 left = 2;
241771ef 1596
e4abb5d4
PZ		 1597 if (left > x86_pmu.max_period)
1598 left = x86_pmu.max_period;
1599
245b2e70 1600 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
ee06094f
IM		 1601
1602 /*
cdd6c482 1603 * The hw event starts counting from this event offset,
ee06094f
IM		 1604 * mark it to be able to extra future deltas:
1605 */
2f18d1e8 1606 atomic64_set(&hwc->prev_count, (u64)-left);
ee06094f 1607
cdd6c482
IM		 1608 err = checking_wrmsrl(hwc->event_base + idx,
1609 (u64)(-left) & x86_pmu.event_mask);
e4abb5d4 1610
cdd6c482 1611 perf_event_update_userpage(event);
194002b2 1612
e4abb5d4 1613 return ret;
2f18d1e8
IM		 1614}
1615
1616static inline void
cdd6c482 1617intel_pmu_enable_fixed(struct hw_perf_event *hwc, int __idx)
2f18d1e8
IM		 1618{
1619 int idx = __idx - X86_PMC_IDX_FIXED;
1620 u64 ctrl_val, bits, mask;
1621 int err;
1622
1623 /*
0475f9ea
PM		 1624 * Enable IRQ generation (0x8),
1625 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1626 * if requested:
2f18d1e8 1627 */
0475f9ea
PM		 1628 bits = 0x8ULL;
1629 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1630 bits |= 0x2;
2f18d1e8
IM		 1631 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1632 bits |= 0x1;
1633 bits <<= (idx * 4);
1634 mask = 0xfULL << (idx * 4);
1635
1636 rdmsrl(hwc->config_base, ctrl_val);
1637 ctrl_val &= ~mask;
1638 ctrl_val |= bits;
1639 err = checking_wrmsrl(hwc->config_base, ctrl_val);
7e2ae347
IM		 1640}
1641
cdd6c482 1642static void p6_pmu_enable_event(struct hw_perf_event *hwc, int idx)
11d1578f 1643{
cdd6c482 1644 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
984b838c 1645 u64 val;
11d1578f 1646
984b838c 1647 val = hwc->config;
11d1578f 1648 if (cpuc->enabled)
984b838c
PZ		 1649 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
1650
1651 (void)checking_wrmsrl(hwc->config_base + idx, val);
11d1578f
VW		 1652}
1653
1654
cdd6c482 1655static void intel_pmu_enable_event(struct hw_perf_event *hwc, int idx)
7e2ae347 1656{
30dd568c 1657 if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
cdd6c482 1658 if (!__get_cpu_var(cpu_hw_events).enabled)
30dd568c
MM		 1659 return;
1660
1661 intel_pmu_enable_bts(hwc->config);
1662 return;
1663 }
1664
7c90cc45
RR		 1665 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1666 intel_pmu_enable_fixed(hwc, idx);
1667 return;
1668 }
1669
cdd6c482 1670 x86_pmu_enable_event(hwc, idx);
7c90cc45
RR		 1671}
1672
cdd6c482 1673static void amd_pmu_enable_event(struct hw_perf_event *hwc, int idx)
7c90cc45 1674{
cdd6c482 1675 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
7c90cc45
RR		 1676
1677 if (cpuc->enabled)
cdd6c482 1678 x86_pmu_enable_event(hwc, idx);
241771ef
IM		 1679}
1680
b690081d 1681/*
1da53e02
SE		 1682 * activate a single event
1683 *
1684 * The event is added to the group of enabled events
1685 * but only if it can be scehduled with existing events.
1686 *
1687 * Called with PMU disabled. If successful and return value 1,
1688 * then guaranteed to call perf_enable() and hw_perf_enable()
fe9081cc
PZ		 1689 */
1690static int x86_pmu_enable(struct perf_event *event)
1691{
1692 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1da53e02
SE		 1693 struct hw_perf_event *hwc;
1694 int assign[X86_PMC_IDX_MAX];
1695 int n, n0, ret;
fe9081cc 1696
1da53e02 1697 hwc = &event->hw;
fe9081cc 1698
1da53e02
SE		 1699 n0 = cpuc->n_events;
1700 n = collect_events(cpuc, event, false);
1701 if (n < 0)
1702 return n;
53b441a5 1703
1da53e02
SE		 1704 ret = x86_schedule_events(cpuc, n, assign);
1705 if (ret)
1706 return ret;
1707 /*
1708 * copy new assignment, now we know it is possible
1709 * will be used by hw_perf_enable()
1710 */
1711 memcpy(cpuc->assign, assign, n*sizeof(int));
7e2ae347 1712
1da53e02
SE		 1713 cpuc->n_events = n;
1714 cpuc->n_added = n - n0;
95cdd2e7 1715
1da53e02
SE		 1716 if (hwc->idx != -1)
1717 x86_perf_event_set_period(event, hwc, hwc->idx);
194002b2 1718
95cdd2e7 1719 return 0;
241771ef
IM		 1720}
1721
cdd6c482 1722static void x86_pmu_unthrottle(struct perf_event *event)
a78ac325 1723{
cdd6c482
IM		 1724 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1725 struct hw_perf_event *hwc = &event->hw;
a78ac325
PZ		 1726
1727 if (WARN_ON_ONCE(hwc->idx >= X86_PMC_IDX_MAX ||
cdd6c482 1728 cpuc->events[hwc->idx] != event))
a78ac325
PZ		 1729 return;
1730
1731 x86_pmu.enable(hwc, hwc->idx);
1732}
1733
cdd6c482 1734void perf_event_print_debug(void)
241771ef 1735{
2f18d1e8 1736 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
cdd6c482 1737 struct cpu_hw_events *cpuc;
5bb9efe3 1738 unsigned long flags;
1e125676
IM		 1739 int cpu, idx;
1740
cdd6c482 1741 if (!x86_pmu.num_events)
1e125676 1742 return;
241771ef 1743
5bb9efe3 1744 local_irq_save(flags);
241771ef
IM		 1745
1746 cpu = smp_processor_id();
cdd6c482 1747 cpuc = &per_cpu(cpu_hw_events, cpu);
241771ef 1748
faa28ae0 1749 if (x86_pmu.version >= 2) {
a1ef58f4
JSR		 1750 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1751 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1752 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1753 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1754
1755 pr_info("\n");
1756 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1757 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1758 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1759 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
f87ad35d 1760 }
1da53e02 1761 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
241771ef 1762
cdd6c482 1763 for (idx = 0; idx < x86_pmu.num_events; idx++) {
4a06bd85
RR		 1764 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1765 rdmsrl(x86_pmu.perfctr + idx, pmc_count);
241771ef 1766
245b2e70 1767 prev_left = per_cpu(pmc_prev_left[idx], cpu);
241771ef 1768
a1ef58f4 1769 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
241771ef 1770 cpu, idx, pmc_ctrl);
a1ef58f4 1771 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
241771ef 1772 cpu, idx, pmc_count);
a1ef58f4 1773 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
ee06094f 1774 cpu, idx, prev_left);
241771ef 1775 }
cdd6c482 1776 for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) {
2f18d1e8
IM		 1777 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1778
a1ef58f4 1779 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
2f18d1e8
IM		 1780 cpu, idx, pmc_count);
1781 }
5bb9efe3 1782 local_irq_restore(flags);
241771ef
IM		 1783}
1784
cdd6c482 1785static void intel_pmu_drain_bts_buffer(struct cpu_hw_events *cpuc)
30dd568c
MM		 1786{
1787 struct debug_store *ds = cpuc->ds;
1788 struct bts_record {
1789 u64 from;
1790 u64 to;
1791 u64 flags;
1792 };
cdd6c482 1793 struct perf_event *event = cpuc->events[X86_PMC_IDX_FIXED_BTS];
596da17f 1794 struct bts_record *at, *top;
5622f295
MM		 1795 struct perf_output_handle handle;
1796 struct perf_event_header header;
1797 struct perf_sample_data data;
1798 struct pt_regs regs;
30dd568c 1799
cdd6c482 1800 if (!event)
30dd568c
MM		 1801 return;
1802
1803 if (!ds)
1804 return;
1805
596da17f 1806 at = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
1807 top = (struct bts_record *)(unsigned long)ds->bts_index;
30dd568c 1808
5622f295
MM		 1809 if (top <= at)
1810 return;
1811
596da17f 1812 ds->bts_index = ds->bts_buffer_base;
1813
5622f295 1814
cdd6c482 1815 data.period = event->hw.last_period;
5622f295 1816 data.addr = 0;
5e855db5 1817 data.raw = NULL;
5622f295
MM		 1818 regs.ip = 0;
1819
1820 /*
1821 * Prepare a generic sample, i.e. fill in the invariant fields.
1822 * We will overwrite the from and to address before we output
1823 * the sample.
1824 */
cdd6c482 1825 perf_prepare_sample(&header, &data, event, &regs);
5622f295 1826
cdd6c482 1827 if (perf_output_begin(&handle, event,
5622f295
MM		 1828 header.size * (top - at), 1, 1))
1829 return;
1830
596da17f 1831 for (; at < top; at++) {
5622f295
MM		 1832 data.ip = at->from;
1833 data.addr = at->to;
30dd568c 1834
cdd6c482 1835 perf_output_sample(&handle, &header, &data, event);
30dd568c
MM		 1836 }
1837
5622f295 1838 perf_output_end(&handle);
30dd568c
MM		 1839
1840 /* There's new data available. */
cdd6c482
IM		 1841 event->hw.interrupts++;
1842 event->pending_kill = POLL_IN;
30dd568c
MM		 1843}
1844
cdd6c482 1845static void x86_pmu_disable(struct perf_event *event)
241771ef 1846{
cdd6c482
IM		 1847 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1848 struct hw_perf_event *hwc = &event->hw;
1da53e02 1849 int i, idx = hwc->idx;
241771ef 1850
09534238
RR		 1851 /*
1852 * Must be done before we disable, otherwise the nmi handler
1853 * could reenable again:
1854 */
43f6201a 1855 clear_bit(idx, cpuc->active_mask);
d4369891 1856 x86_pmu.disable(hwc, idx);
241771ef 1857
2f18d1e8
IM		 1858 /*
1859 * Make sure the cleared pointer becomes visible before we
cdd6c482 1860 * (potentially) free the event:
2f18d1e8 1861 */
527e26af 1862 barrier();
241771ef 1863
ee06094f 1864 /*
cdd6c482 1865 * Drain the remaining delta count out of a event
ee06094f
IM		 1866 * that we are disabling:
1867 */
cdd6c482 1868 x86_perf_event_update(event, hwc, idx);
30dd568c
MM		 1869
1870 /* Drain the remaining BTS records. */
5622f295
MM		 1871 if (unlikely(idx == X86_PMC_IDX_FIXED_BTS))
1872 intel_pmu_drain_bts_buffer(cpuc);
30dd568c 1873
cdd6c482 1874 cpuc->events[idx] = NULL;
194002b2 1875
1da53e02
SE		 1876 for (i = 0; i < cpuc->n_events; i++) {
1877 if (event == cpuc->event_list[i]) {
1878
1879 if (x86_pmu.put_event_constraints)
1880 x86_pmu.put_event_constraints(cpuc, event);
1881
1882 while (++i < cpuc->n_events)
1883 cpuc->event_list[i-1] = cpuc->event_list[i];
1884
1885 --cpuc->n_events;
1886 }
1887 }
cdd6c482 1888 perf_event_update_userpage(event);
241771ef
IM		 1889}
1890
7e2ae347 1891/*
cdd6c482
IM		 1892 * Save and restart an expired event. Called by NMI contexts,
1893 * so it has to be careful about preempting normal event ops:
7e2ae347 1894 */
cdd6c482 1895static int intel_pmu_save_and_restart(struct perf_event *event)
241771ef 1896{
cdd6c482 1897 struct hw_perf_event *hwc = &event->hw;
241771ef 1898 int idx = hwc->idx;
e4abb5d4 1899 int ret;
241771ef 1900
cdd6c482
IM		 1901 x86_perf_event_update(event, hwc, idx);
1902 ret = x86_perf_event_set_period(event, hwc, idx);
7e2ae347 1903
cdd6c482
IM		 1904 if (event->state == PERF_EVENT_STATE_ACTIVE)
1905 intel_pmu_enable_event(hwc, idx);
e4abb5d4
PZ		 1906
1907 return ret;
241771ef
IM		 1908}
1909
aaba9801
IM		 1910static void intel_pmu_reset(void)
1911{
cdd6c482 1912 struct debug_store *ds = __get_cpu_var(cpu_hw_events).ds;
aaba9801
IM		 1913 unsigned long flags;
1914 int idx;
1915
cdd6c482 1916 if (!x86_pmu.num_events)
aaba9801
IM		 1917 return;
1918
1919 local_irq_save(flags);
1920
1921 printk("clearing PMU state on CPU#%d\n", smp_processor_id());
1922
cdd6c482 1923 for (idx = 0; idx < x86_pmu.num_events; idx++) {
aaba9801
IM		 1924 checking_wrmsrl(x86_pmu.eventsel + idx, 0ull);
1925 checking_wrmsrl(x86_pmu.perfctr + idx, 0ull);
1926 }
cdd6c482 1927 for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) {
aaba9801
IM		 1928 checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
1929 }
30dd568c
MM		 1930 if (ds)
1931 ds->bts_index = ds->bts_buffer_base;
aaba9801
IM		 1932
1933 local_irq_restore(flags);
1934}
1935
11d1578f
VW		 1936static int p6_pmu_handle_irq(struct pt_regs *regs)
1937{
1938 struct perf_sample_data data;
cdd6c482
IM		 1939 struct cpu_hw_events *cpuc;
1940 struct perf_event *event;
1941 struct hw_perf_event *hwc;
11d1578f
VW		 1942 int idx, handled = 0;
1943 u64 val;
1944
11d1578f 1945 data.addr = 0;
5e855db5 1946 data.raw = NULL;
11d1578f 1947
cdd6c482 1948 cpuc = &__get_cpu_var(cpu_hw_events);
11d1578f 1949
cdd6c482 1950 for (idx = 0; idx < x86_pmu.num_events; idx++) {
11d1578f
VW		 1951 if (!test_bit(idx, cpuc->active_mask))
1952 continue;
1953
cdd6c482
IM		 1954 event = cpuc->events[idx];
1955 hwc = &event->hw;
11d1578f 1956
cdd6c482
IM		 1957 val = x86_perf_event_update(event, hwc, idx);
1958 if (val & (1ULL << (x86_pmu.event_bits - 1)))
11d1578f
VW		 1959 continue;
1960
1961 /*
cdd6c482 1962 * event overflow
11d1578f
VW		 1963 */
1964 handled = 1;
cdd6c482 1965 data.period = event->hw.last_period;
11d1578f 1966
cdd6c482 1967 if (!x86_perf_event_set_period(event, hwc, idx))
11d1578f
VW		 1968 continue;
1969
cdd6c482
IM		 1970 if (perf_event_overflow(event, 1, &data, regs))
1971 p6_pmu_disable_event(hwc, idx);
11d1578f
VW		 1972 }
1973
1974 if (handled)
1975 inc_irq_stat(apic_perf_irqs);
1976
1977 return handled;
1978}
aaba9801 1979
241771ef
IM		 1980/*
1981 * This handler is triggered by the local APIC, so the APIC IRQ handling
1982 * rules apply:
1983 */
a3288106 1984static int intel_pmu_handle_irq(struct pt_regs *regs)
241771ef 1985{
df1a132b 1986 struct perf_sample_data data;
cdd6c482 1987 struct cpu_hw_events *cpuc;
11d1578f 1988 int bit, loops;
4b39fd96 1989 u64 ack, status;
9029a5e3 1990
df1a132b 1991 data.addr = 0;
5e855db5 1992 data.raw = NULL;
df1a132b 1993
cdd6c482 1994 cpuc = &__get_cpu_var(cpu_hw_events);
241771ef 1995
9e35ad38 1996 perf_disable();
5622f295 1997 intel_pmu_drain_bts_buffer(cpuc);
19d84dab 1998 status = intel_pmu_get_status();
9e35ad38
PZ		 1999 if (!status) {
2000 perf_enable();
2001 return 0;
2002 }
87b9cf46 2003
9029a5e3 2004 loops = 0;
241771ef 2005again:
9029a5e3 2006 if (++loops > 100) {
cdd6c482
IM		 2007 WARN_ONCE(1, "perfevents: irq loop stuck!\n");
2008 perf_event_print_debug();
aaba9801
IM		 2009 intel_pmu_reset();
2010 perf_enable();
9029a5e3
IM		 2011 return 1;
2012 }
2013
d278c484 2014 inc_irq_stat(apic_perf_irqs);
241771ef 2015 ack = status;
2f18d1e8 2016 for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
cdd6c482 2017 struct perf_event *event = cpuc->events[bit];
241771ef
IM		 2018
2019 clear_bit(bit, (unsigned long *) &status);
43f6201a 2020 if (!test_bit(bit, cpuc->active_mask))
241771ef
IM		 2021 continue;
2022
cdd6c482 2023 if (!intel_pmu_save_and_restart(event))
e4abb5d4
PZ		 2024 continue;
2025
cdd6c482 2026 data.period = event->hw.last_period;
60f916de 2027
cdd6c482
IM		 2028 if (perf_event_overflow(event, 1, &data, regs))
2029 intel_pmu_disable_event(&event->hw, bit);
241771ef
IM		 2030 }
2031
dee5d906 2032 intel_pmu_ack_status(ack);
241771ef
IM		 2033
2034 /*
2035 * Repeat if there is more work to be done:
2036 */
19d84dab 2037 status = intel_pmu_get_status();
241771ef
IM		 2038 if (status)
2039 goto again;
b0f3f28e 2040
48e22d56 2041 perf_enable();
9e35ad38
PZ		 2042
2043 return 1;
1b023a96
MG		 2044}
2045
a3288106 2046static int amd_pmu_handle_irq(struct pt_regs *regs)
a29aa8a7 2047{
df1a132b 2048 struct perf_sample_data data;
cdd6c482
IM		 2049 struct cpu_hw_events *cpuc;
2050 struct perf_event *event;
2051 struct hw_perf_event *hwc;
11d1578f 2052 int idx, handled = 0;
9029a5e3
IM		 2053 u64 val;
2054
df1a132b 2055 data.addr = 0;
5e855db5 2056 data.raw = NULL;
df1a132b 2057
cdd6c482 2058 cpuc = &__get_cpu_var(cpu_hw_events);
962bf7a6 2059
cdd6c482 2060 for (idx = 0; idx < x86_pmu.num_events; idx++) {
43f6201a 2061 if (!test_bit(idx, cpuc->active_mask))
a29aa8a7 2062 continue;
962bf7a6 2063
cdd6c482
IM		 2064 event = cpuc->events[idx];
2065 hwc = &event->hw;
a4016a79 2066
cdd6c482
IM		 2067 val = x86_perf_event_update(event, hwc, idx);
2068 if (val & (1ULL << (x86_pmu.event_bits - 1)))
48e22d56 2069 continue;
962bf7a6 2070
9e350de3 2071 /*
cdd6c482 2072 * event overflow
9e350de3
PZ		 2073 */
2074 handled = 1;
cdd6c482 2075 data.period = event->hw.last_period;
9e350de3 2076
cdd6c482 2077 if (!x86_perf_event_set_period(event, hwc, idx))
e4abb5d4
PZ		 2078 continue;
2079
cdd6c482
IM		 2080 if (perf_event_overflow(event, 1, &data, regs))
2081 amd_pmu_disable_event(hwc, idx);
a29aa8a7 2082 }
962bf7a6 2083
9e350de3
PZ		 2084 if (handled)
2085 inc_irq_stat(apic_perf_irqs);
2086
a29aa8a7
RR		 2087 return handled;
2088}
39d81eab 2089
b6276f35
PZ		 2090void smp_perf_pending_interrupt(struct pt_regs *regs)
2091{
2092 irq_enter();
2093 ack_APIC_irq();
2094 inc_irq_stat(apic_pending_irqs);
cdd6c482 2095 perf_event_do_pending();
b6276f35
PZ		 2096 irq_exit();
2097}
2098
cdd6c482 2099void set_perf_event_pending(void)
b6276f35 2100{
04da8a43 2101#ifdef CONFIG_X86_LOCAL_APIC
7d428966
PZ		 2102 if (!x86_pmu.apic || !x86_pmu_initialized())
2103 return;
2104
b6276f35 2105 apic->send_IPI_self(LOCAL_PENDING_VECTOR);
04da8a43 2106#endif
b6276f35
PZ		 2107}
2108
cdd6c482 2109void perf_events_lapic_init(void)
241771ef 2110{
04da8a43
IM		 2111#ifdef CONFIG_X86_LOCAL_APIC
2112 if (!x86_pmu.apic || !x86_pmu_initialized())
241771ef 2113 return;
85cf9dba 2114
241771ef 2115 /*
c323d95f 2116 * Always use NMI for PMU
241771ef 2117 */
c323d95f 2118 apic_write(APIC_LVTPC, APIC_DM_NMI);
04da8a43 2119#endif
241771ef
IM		 2120}
2121
2122static int __kprobes
cdd6c482 2123perf_event_nmi_handler(struct notifier_block *self,
241771ef
IM		 2124 unsigned long cmd, void *__args)
2125{
2126 struct die_args *args = __args;
2127 struct pt_regs *regs;
b0f3f28e 2128
cdd6c482 2129 if (!atomic_read(&active_events))
63a809a2
PZ		 2130 return NOTIFY_DONE;
2131
b0f3f28e
PZ		 2132 switch (cmd) {
2133 case DIE_NMI:
2134 case DIE_NMI_IPI:
2135 break;
241771ef 2136
b0f3f28e 2137 default:
241771ef 2138 return NOTIFY_DONE;
b0f3f28e 2139 }
241771ef
IM		 2140
2141 regs = args->regs;
2142
04da8a43 2143#ifdef CONFIG_X86_LOCAL_APIC
241771ef 2144 apic_write(APIC_LVTPC, APIC_DM_NMI);
04da8a43 2145#endif
a4016a79
PZ		 2146 /*
2147 * Can't rely on the handled return value to say it was our NMI, two
cdd6c482 2148 * events could trigger 'simultaneously' raising two back-to-back NMIs.
a4016a79
PZ		 2149 *
2150 * If the first NMI handles both, the latter will be empty and daze
2151 * the CPU.
2152 */
a3288106 2153 x86_pmu.handle_irq(regs);
241771ef 2154
a4016a79 2155 return NOTIFY_STOP;
241771ef
IM		 2156}
2157
c91e0f5d
PZ		 2158static struct event_constraint bts_constraint =
2159 EVENT_CONSTRAINT(0, 1ULL << X86_PMC_IDX_FIXED_BTS, 0);
1da53e02
SE		 2160
2161static int intel_special_constraints(struct perf_event *event,
c91e0f5d 2162 unsigned long *idxmsk)
1da53e02
SE		 2163{
2164 unsigned int hw_event;
2165
2166 hw_event = event->hw.config & INTEL_ARCH_EVENT_MASK;
2167
2168 if (unlikely((hw_event ==
2169 x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS)) &&
2170 (event->hw.sample_period == 1))) {
2171
2172 bitmap_copy((unsigned long *)idxmsk,
2173 (unsigned long *)bts_constraint.idxmsk,
2174 X86_PMC_IDX_MAX);
2175 return 1;
2176 }
2177 return 0;
2178}
2179
2180static void intel_get_event_constraints(struct cpu_hw_events *cpuc,
2181 struct perf_event *event,
c91e0f5d 2182 unsigned long *idxmsk)
1da53e02
SE		 2183{
2184 const struct event_constraint *c;
2185
2186 /*
2187 * cleanup bitmask
2188 */
c91e0f5d 2189 bitmap_zero(idxmsk, X86_PMC_IDX_MAX);
1da53e02
SE		 2190
2191 if (intel_special_constraints(event, idxmsk))
2192 return;
2193
2194 if (x86_pmu.event_constraints) {
2195 for_each_event_constraint(c, x86_pmu.event_constraints) {
2196 if ((event->hw.config & c->cmask) == c->code) {
c91e0f5d 2197 bitmap_copy(idxmsk, c->idxmsk, X86_PMC_IDX_MAX);
1da53e02
SE		 2198 return;
2199 }
2200 }
2201 }
2202 /* no constraints, means supports all generic counters */
2203 bitmap_fill((unsigned long *)idxmsk, x86_pmu.num_events);
2204}
2205
2206static void amd_get_event_constraints(struct cpu_hw_events *cpuc,
2207 struct perf_event *event,
c91e0f5d 2208 unsigned long *idxmsk)
1da53e02 2209{
8113070d 2210 /* no constraints, means supports all generic counters */
c91e0f5d 2211 bitmap_fill(idxmsk, x86_pmu.num_events);
1da53e02
SE		 2212}
2213
2214static int x86_event_sched_in(struct perf_event *event,
2215 struct perf_cpu_context *cpuctx, int cpu)
2216{
2217 int ret = 0;
2218
2219 event->state = PERF_EVENT_STATE_ACTIVE;
2220 event->oncpu = cpu;
2221 event->tstamp_running += event->ctx->time - event->tstamp_stopped;
2222
2223 if (!is_x86_event(event))
2224 ret = event->pmu->enable(event);
2225
2226 if (!ret && !is_software_event(event))
2227 cpuctx->active_oncpu++;
2228
2229 if (!ret && event->attr.exclusive)
2230 cpuctx->exclusive = 1;
2231
2232 return ret;
2233}
2234
2235static void x86_event_sched_out(struct perf_event *event,
2236 struct perf_cpu_context *cpuctx, int cpu)
2237{
2238 event->state = PERF_EVENT_STATE_INACTIVE;
2239 event->oncpu = -1;
2240
2241 if (!is_x86_event(event))
2242 event->pmu->disable(event);
2243
2244 event->tstamp_running -= event->ctx->time - event->tstamp_stopped;
2245
2246 if (!is_software_event(event))
2247 cpuctx->active_oncpu--;
2248
2249 if (event->attr.exclusive || !cpuctx->active_oncpu)
2250 cpuctx->exclusive = 0;
2251}
2252
2253/*
2254 * Called to enable a whole group of events.
2255 * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
2256 * Assumes the caller has disabled interrupts and has
2257 * frozen the PMU with hw_perf_save_disable.
2258 *
2259 * called with PMU disabled. If successful and return value 1,
2260 * then guaranteed to call perf_enable() and hw_perf_enable()
2261 */
2262int hw_perf_group_sched_in(struct perf_event *leader,
2263 struct perf_cpu_context *cpuctx,
2264 struct perf_event_context *ctx, int cpu)
2265{
2266 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2267 struct perf_event *sub;
2268 int assign[X86_PMC_IDX_MAX];
2269 int n0, n1, ret;
2270
2271 /* n0 = total number of events */
2272 n0 = collect_events(cpuc, leader, true);
2273 if (n0 < 0)
2274 return n0;
2275
2276 ret = x86_schedule_events(cpuc, n0, assign);
2277 if (ret)
2278 return ret;
2279
2280 ret = x86_event_sched_in(leader, cpuctx, cpu);
2281 if (ret)
2282 return ret;
2283
2284 n1 = 1;
2285 list_for_each_entry(sub, &leader->sibling_list, group_entry) {
8113070d 2286 if (sub->state > PERF_EVENT_STATE_OFF) {
1da53e02
SE		 2287 ret = x86_event_sched_in(sub, cpuctx, cpu);
2288 if (ret)
2289 goto undo;
2290 ++n1;
2291 }
2292 }
2293 /*
2294 * copy new assignment, now we know it is possible
2295 * will be used by hw_perf_enable()
2296 */
2297 memcpy(cpuc->assign, assign, n0*sizeof(int));
2298
2299 cpuc->n_events = n0;
2300 cpuc->n_added = n1;
2301 ctx->nr_active += n1;
2302
2303 /*
2304 * 1 means successful and events are active
2305 * This is not quite true because we defer
2306 * actual activation until hw_perf_enable() but
2307 * this way we* ensure caller won't try to enable
2308 * individual events
2309 */
2310 return 1;
2311undo:
2312 x86_event_sched_out(leader, cpuctx, cpu);
2313 n0 = 1;
2314 list_for_each_entry(sub, &leader->sibling_list, group_entry) {
2315 if (sub->state == PERF_EVENT_STATE_ACTIVE) {
2316 x86_event_sched_out(sub, cpuctx, cpu);
2317 if (++n0 == n1)
2318 break;
2319 }
2320 }
2321 return ret;
2322}
2323
cdd6c482
IM		 2324static __read_mostly struct notifier_block perf_event_nmi_notifier = {
2325 .notifier_call = perf_event_nmi_handler,
5b75af0a
MG		 2326 .next = NULL,
2327 .priority = 1
241771ef
IM		 2328};
2329
db48cccc 2330static __initconst struct x86_pmu p6_pmu = {
11d1578f
VW		 2331 .name = "p6",
2332 .handle_irq = p6_pmu_handle_irq,
2333 .disable_all = p6_pmu_disable_all,
2334 .enable_all = p6_pmu_enable_all,
cdd6c482
IM		 2335 .enable = p6_pmu_enable_event,
2336 .disable = p6_pmu_disable_event,
11d1578f
VW		 2337 .eventsel = MSR_P6_EVNTSEL0,
2338 .perfctr = MSR_P6_PERFCTR0,
2339 .event_map = p6_pmu_event_map,
2340 .raw_event = p6_pmu_raw_event,
2341 .max_events = ARRAY_SIZE(p6_perfmon_event_map),
04da8a43 2342 .apic = 1,
11d1578f
VW		 2343 .max_period = (1ULL << 31) - 1,
2344 .version = 0,
cdd6c482 2345 .num_events = 2,
11d1578f 2346 /*
cdd6c482 2347 * Events have 40 bits implemented. However they are designed such
11d1578f 2348 * that bits [32-39] are sign extensions of bit 31. As such the
cdd6c482 2349 * effective width of a event for P6-like PMU is 32 bits only.
11d1578f
VW		 2350 *
2351 * See IA-32 Intel Architecture Software developer manual Vol 3B
2352 */
cdd6c482
IM		 2353 .event_bits = 32,
2354 .event_mask = (1ULL << 32) - 1,
1da53e02
SE		 2355 .get_event_constraints = intel_get_event_constraints,
2356 .event_constraints = intel_p6_event_constraints
11d1578f
VW		 2357};
2358
db48cccc 2359static __initconst struct x86_pmu intel_pmu = {
faa28ae0 2360 .name = "Intel",
39d81eab 2361 .handle_irq = intel_pmu_handle_irq,
9e35ad38
PZ		 2362 .disable_all = intel_pmu_disable_all,
2363 .enable_all = intel_pmu_enable_all,
cdd6c482
IM		 2364 .enable = intel_pmu_enable_event,
2365 .disable = intel_pmu_disable_event,
b56a3802
JSR		 2366 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
2367 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
5f4ec28f
RR		 2368 .event_map = intel_pmu_event_map,
2369 .raw_event = intel_pmu_raw_event,
b56a3802 2370 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
04da8a43 2371 .apic = 1,
c619b8ff
RR		 2372 /*
2373 * Intel PMCs cannot be accessed sanely above 32 bit width,
2374 * so we install an artificial 1<<31 period regardless of
cdd6c482 2375 * the generic event period:
c619b8ff
RR		 2376 */
2377 .max_period = (1ULL << 31) - 1,
30dd568c
MM		 2378 .enable_bts = intel_pmu_enable_bts,
2379 .disable_bts = intel_pmu_disable_bts,
1da53e02 2380 .get_event_constraints = intel_get_event_constraints
b56a3802
JSR		 2381};
2382
db48cccc 2383static __initconst struct x86_pmu amd_pmu = {
faa28ae0 2384 .name = "AMD",
39d81eab 2385 .handle_irq = amd_pmu_handle_irq,
9e35ad38
PZ		 2386 .disable_all = amd_pmu_disable_all,
2387 .enable_all = amd_pmu_enable_all,
cdd6c482
IM		 2388 .enable = amd_pmu_enable_event,
2389 .disable = amd_pmu_disable_event,
f87ad35d
JSR		 2390 .eventsel = MSR_K7_EVNTSEL0,
2391 .perfctr = MSR_K7_PERFCTR0,
5f4ec28f
RR		 2392 .event_map = amd_pmu_event_map,
2393 .raw_event = amd_pmu_raw_event,
f87ad35d 2394 .max_events = ARRAY_SIZE(amd_perfmon_event_map),
cdd6c482
IM		 2395 .num_events = 4,
2396 .event_bits = 48,
2397 .event_mask = (1ULL << 48) - 1,
04da8a43 2398 .apic = 1,
c619b8ff
RR		 2399 /* use highest bit to detect overflow */
2400 .max_period = (1ULL << 47) - 1,
1da53e02 2401 .get_event_constraints = amd_get_event_constraints
f87ad35d
JSR		 2402};
2403
db48cccc 2404static __init int p6_pmu_init(void)
11d1578f 2405{
11d1578f
VW		 2406 switch (boot_cpu_data.x86_model) {
2407 case 1:
2408 case 3: /* Pentium Pro */
2409 case 5:
2410 case 6: /* Pentium II */
2411 case 7:
2412 case 8:
2413 case 11: /* Pentium III */
11d1578f
VW		 2414 case 9:
2415 case 13:
f1c6a581
DQ		 2416 /* Pentium M */
2417 break;
11d1578f
VW		 2418 default:
2419 pr_cont("unsupported p6 CPU model %d ",
2420 boot_cpu_data.x86_model);
2421 return -ENODEV;
2422 }
2423
04da8a43
IM		 2424 x86_pmu = p6_pmu;
2425
11d1578f
VW		 2426 return 0;
2427}
2428
db48cccc 2429static __init int intel_pmu_init(void)
241771ef 2430{
7bb497bd 2431 union cpuid10_edx edx;
241771ef 2432 union cpuid10_eax eax;
703e937c 2433 unsigned int unused;
7bb497bd 2434 unsigned int ebx;
faa28ae0 2435 int version;
241771ef 2436
11d1578f
VW		 2437 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
2438 /* check for P6 processor family */
2439 if (boot_cpu_data.x86 == 6) {
2440 return p6_pmu_init();
2441 } else {
72eae04d 2442 return -ENODEV;
11d1578f
VW		 2443 }
2444 }
da1a776b 2445
241771ef
IM		 2446 /*
2447 * Check whether the Architectural PerfMon supports
dfc65094 2448 * Branch Misses Retired hw_event or not.
241771ef 2449 */
703e937c 2450 cpuid(10, &eax.full, &ebx, &unused, &edx.full);
241771ef 2451 if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
72eae04d 2452 return -ENODEV;
241771ef 2453
faa28ae0
RR		 2454 version = eax.split.version_id;
2455 if (version < 2)
72eae04d 2456 return -ENODEV;
7bb497bd 2457
1123e3ad
IM		 2458 x86_pmu = intel_pmu;
2459 x86_pmu.version = version;
cdd6c482
IM		 2460 x86_pmu.num_events = eax.split.num_events;
2461 x86_pmu.event_bits = eax.split.bit_width;
2462 x86_pmu.event_mask = (1ULL << eax.split.bit_width) - 1;
066d7dea
IM		 2463
2464 /*
cdd6c482
IM		 2465 * Quirk: v2 perfmon does not report fixed-purpose events, so
2466 * assume at least 3 events:
066d7dea 2467 */
cdd6c482 2468 x86_pmu.num_events_fixed = max((int)edx.split.num_events_fixed, 3);
b56a3802 2469
8326f44d 2470 /*
1123e3ad 2471 * Install the hw-cache-events table:
8326f44d
IM		 2472 */
2473 switch (boot_cpu_data.x86_model) {
dc81081b
YW		 2474 case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
2475 case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
2476 case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
2477 case 29: /* six-core 45 nm xeon "Dunnington" */
8326f44d 2478 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
820a6442 2479 sizeof(hw_cache_event_ids));
8326f44d 2480
1da53e02 2481 x86_pmu.event_constraints = intel_core_event_constraints;
1123e3ad 2482 pr_cont("Core2 events, ");
8326f44d 2483 break;
8326f44d
IM		 2484 case 26:
2485 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
820a6442 2486 sizeof(hw_cache_event_ids));
8326f44d 2487
1da53e02 2488 x86_pmu.event_constraints = intel_nehalem_event_constraints;
1123e3ad 2489 pr_cont("Nehalem/Corei7 events, ");
8326f44d
IM		 2490 break;
2491 case 28:
2492 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
820a6442 2493 sizeof(hw_cache_event_ids));
8326f44d 2494
1da53e02 2495 x86_pmu.event_constraints = intel_gen_event_constraints;
1123e3ad 2496 pr_cont("Atom events, ");
8326f44d 2497 break;
1da53e02
SE		 2498 default:
2499 /*
2500 * default constraints for v2 and up
2501 */
2502 x86_pmu.event_constraints = intel_gen_event_constraints;
2503 pr_cont("generic architected perfmon, ");
8326f44d 2504 }
72eae04d 2505 return 0;
b56a3802
JSR		 2506}
2507
db48cccc 2508static __init int amd_pmu_init(void)
f87ad35d 2509{
4d2be126
JSR		 2510 /* Performance-monitoring supported from K7 and later: */
2511 if (boot_cpu_data.x86 < 6)
2512 return -ENODEV;
2513
4a06bd85 2514 x86_pmu = amd_pmu;
f86748e9 2515
f4db43a3
JSR		 2516 /* Events are common for all AMDs */
2517 memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
2518 sizeof(hw_cache_event_ids));
f86748e9 2519
72eae04d 2520 return 0;
f87ad35d
JSR		 2521}
2522
12558038
CG		 2523static void __init pmu_check_apic(void)
2524{
2525 if (cpu_has_apic)
2526 return;
2527
2528 x86_pmu.apic = 0;
2529 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
2530 pr_info("no hardware sampling interrupt available.\n");
2531}
2532
cdd6c482 2533void __init init_hw_perf_events(void)
b56a3802 2534{
72eae04d
RR		 2535 int err;
2536
cdd6c482 2537 pr_info("Performance Events: ");
1123e3ad 2538
b56a3802
JSR		 2539 switch (boot_cpu_data.x86_vendor) {
2540 case X86_VENDOR_INTEL:
72eae04d 2541 err = intel_pmu_init();
b56a3802 2542 break;
f87ad35d 2543 case X86_VENDOR_AMD:
72eae04d 2544 err = amd_pmu_init();
f87ad35d 2545 break;
4138960a
RR		 2546 default:
2547 return;
b56a3802 2548 }
1123e3ad 2549 if (err != 0) {
cdd6c482 2550 pr_cont("no PMU driver, software events only.\n");
b56a3802 2551 return;
1123e3ad 2552 }
b56a3802 2553
12558038
CG		 2554 pmu_check_apic();
2555
1123e3ad 2556 pr_cont("%s PMU driver.\n", x86_pmu.name);
faa28ae0 2557
cdd6c482
IM		 2558 if (x86_pmu.num_events > X86_PMC_MAX_GENERIC) {
2559 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
2560 x86_pmu.num_events, X86_PMC_MAX_GENERIC);
2561 x86_pmu.num_events = X86_PMC_MAX_GENERIC;
241771ef 2562 }
cdd6c482
IM		 2563 perf_event_mask = (1 << x86_pmu.num_events) - 1;
2564 perf_max_events = x86_pmu.num_events;
241771ef 2565
cdd6c482
IM		 2566 if (x86_pmu.num_events_fixed > X86_PMC_MAX_FIXED) {
2567 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
2568 x86_pmu.num_events_fixed, X86_PMC_MAX_FIXED);
2569 x86_pmu.num_events_fixed = X86_PMC_MAX_FIXED;
703e937c 2570 }
862a1a5f 2571
cdd6c482
IM		 2572 perf_event_mask |=
2573 ((1LL << x86_pmu.num_events_fixed)-1) << X86_PMC_IDX_FIXED;
2574 x86_pmu.intel_ctrl = perf_event_mask;
241771ef 2575
cdd6c482
IM		 2576 perf_events_lapic_init();
2577 register_die_notifier(&perf_event_nmi_notifier);
1123e3ad 2578
57c0c15b
IM		 2579 pr_info("... version: %d\n", x86_pmu.version);
2580 pr_info("... bit width: %d\n", x86_pmu.event_bits);
2581 pr_info("... generic registers: %d\n", x86_pmu.num_events);
2582 pr_info("... value mask: %016Lx\n", x86_pmu.event_mask);
2583 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
2584 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_events_fixed);
2585 pr_info("... event mask: %016Lx\n", perf_event_mask);
241771ef 2586}
621a01ea 2587
cdd6c482 2588static inline void x86_pmu_read(struct perf_event *event)
ee06094f 2589{
cdd6c482 2590 x86_perf_event_update(event, &event->hw, event->hw.idx);
ee06094f
IM		 2591}
2592
4aeb0b42
RR		 2593static const struct pmu pmu = {
2594 .enable = x86_pmu_enable,
2595 .disable = x86_pmu_disable,
2596 .read = x86_pmu_read,
a78ac325 2597 .unthrottle = x86_pmu_unthrottle,
621a01ea
IM		 2598};
2599
1da53e02
SE		 2600/*
2601 * validate a single event group
2602 *
2603 * validation include:
2604 * - check events are compatible which each other
2605 * - events do not compete for the same counter
2606 * - number of events <= number of counters
2607 *
2608 * validation ensures the group can be loaded onto the
2609 * PMU if it was the only group available.
2610 */
fe9081cc
PZ		 2611static int validate_group(struct perf_event *event)
2612{
1da53e02 2613 struct perf_event *leader = event->group_leader;
502568d5
PZ		 2614 struct cpu_hw_events *fake_cpuc;
2615 int ret, n;
fe9081cc 2616
502568d5
PZ		 2617 ret = -ENOMEM;
2618 fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
2619 if (!fake_cpuc)
2620 goto out;
fe9081cc 2621
1da53e02
SE		 2622 /*
2623 * the event is not yet connected with its
2624 * siblings therefore we must first collect
2625 * existing siblings, then add the new event
2626 * before we can simulate the scheduling
2627 */
502568d5
PZ		 2628 ret = -ENOSPC;
2629 n = collect_events(fake_cpuc, leader, true);
1da53e02 2630 if (n < 0)
502568d5 2631 goto out_free;
fe9081cc 2632
502568d5
PZ		 2633 fake_cpuc->n_events = n;
2634 n = collect_events(fake_cpuc, event, false);
1da53e02 2635 if (n < 0)
502568d5 2636 goto out_free;
fe9081cc 2637
502568d5 2638 fake_cpuc->n_events = n;
1da53e02 2639
502568d5
PZ		 2640 ret = x86_schedule_events(fake_cpuc, n, NULL);
2641
2642out_free:
2643 kfree(fake_cpuc);
2644out:
2645 return ret;
fe9081cc
PZ		 2646}
2647
cdd6c482 2648const struct pmu *hw_perf_event_init(struct perf_event *event)
621a01ea 2649{
8113070d 2650 const struct pmu *tmp;
621a01ea
IM		 2651 int err;
2652
cdd6c482 2653 err = __hw_perf_event_init(event);
fe9081cc 2654 if (!err) {
8113070d
SE		 2655 /*
2656 * we temporarily connect event to its pmu
2657 * such that validate_group() can classify
2658 * it as an x86 event using is_x86_event()
2659 */
2660 tmp = event->pmu;
2661 event->pmu = &pmu;
2662
fe9081cc
PZ		 2663 if (event->group_leader != event)
2664 err = validate_group(event);
8113070d
SE		 2665
2666 event->pmu = tmp;
fe9081cc 2667 }
a1792cda 2668 if (err) {
cdd6c482
IM		 2669 if (event->destroy)
2670 event->destroy(event);
9ea98e19 2671 return ERR_PTR(err);
a1792cda 2672 }
621a01ea 2673
4aeb0b42 2674 return &pmu;
621a01ea 2675}
d7d59fb3
PZ		 2676
2677/*
2678 * callchain support
2679 */
2680
2681static inline
f9188e02 2682void callchain_store(struct perf_callchain_entry *entry, u64 ip)
d7d59fb3 2683{
f9188e02 2684 if (entry->nr < PERF_MAX_STACK_DEPTH)
d7d59fb3
PZ		 2685 entry->ip[entry->nr++] = ip;
2686}
2687
245b2e70
TH		 2688static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
2689static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry);
d7d59fb3
PZ		 2690
2691
2692static void
2693backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
2694{
2695 /* Ignore warnings */
2696}
2697
2698static void backtrace_warning(void *data, char *msg)
2699{
2700 /* Ignore warnings */
2701}
2702
2703static int backtrace_stack(void *data, char *name)
2704{
038e836e 2705 return 0;
d7d59fb3
PZ		 2706}
2707
2708static void backtrace_address(void *data, unsigned long addr, int reliable)
2709{
2710 struct perf_callchain_entry *entry = data;
2711
2712 if (reliable)
2713 callchain_store(entry, addr);
2714}
2715
2716static const struct stacktrace_ops backtrace_ops = {
2717 .warning = backtrace_warning,
2718 .warning_symbol = backtrace_warning_symbol,
2719 .stack = backtrace_stack,
2720 .address = backtrace_address,
06d65bda 2721 .walk_stack = print_context_stack_bp,
d7d59fb3
PZ		 2722};
2723
038e836e
IM		 2724#include "../dumpstack.h"
2725
d7d59fb3
PZ		 2726static void
2727perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
2728{
f9188e02 2729 callchain_store(entry, PERF_CONTEXT_KERNEL);
038e836e 2730 callchain_store(entry, regs->ip);
d7d59fb3 2731
48b5ba9c 2732 dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
d7d59fb3
PZ		 2733}
2734
74193ef0
PZ		 2735/*
2736 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
2737 */
2738static unsigned long
2739copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
d7d59fb3 2740{
74193ef0
PZ		 2741 unsigned long offset, addr = (unsigned long)from;
2742 int type = in_nmi() ? KM_NMI : KM_IRQ0;
2743 unsigned long size, len = 0;
2744 struct page *page;
2745 void *map;
d7d59fb3
PZ		 2746 int ret;
2747
74193ef0
PZ		 2748 do {
2749 ret = __get_user_pages_fast(addr, 1, 0, &page);
2750 if (!ret)
2751 break;
d7d59fb3 2752
74193ef0
PZ		 2753 offset = addr & (PAGE_SIZE - 1);
2754 size = min(PAGE_SIZE - offset, n - len);
d7d59fb3 2755
74193ef0
PZ		 2756 map = kmap_atomic(page, type);
2757 memcpy(to, map+offset, size);
2758 kunmap_atomic(map, type);
2759 put_page(page);
2760
2761 len += size;
2762 to += size;
2763 addr += size;
2764
2765 } while (len < n);
2766
2767 return len;
2768}
2769
2770static int copy_stack_frame(const void __user *fp, struct stack_frame *frame)
2771{
2772 unsigned long bytes;
2773
2774 bytes = copy_from_user_nmi(frame, fp, sizeof(*frame));
2775
2776 return bytes == sizeof(*frame);
d7d59fb3
PZ		 2777}
2778
2779static void
2780perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
2781{
2782 struct stack_frame frame;
2783 const void __user *fp;
2784
5a6cec3a
IM		 2785 if (!user_mode(regs))
2786 regs = task_pt_regs(current);
2787
74193ef0 2788 fp = (void __user *)regs->bp;
d7d59fb3 2789
f9188e02 2790 callchain_store(entry, PERF_CONTEXT_USER);
d7d59fb3
PZ		 2791 callchain_store(entry, regs->ip);
2792
f9188e02 2793 while (entry->nr < PERF_MAX_STACK_DEPTH) {
038e836e 2794 frame.next_frame = NULL;
d7d59fb3
PZ		 2795 frame.return_address = 0;
2796
2797 if (!copy_stack_frame(fp, &frame))
2798 break;
2799
5a6cec3a 2800 if ((unsigned long)fp < regs->sp)
d7d59fb3
PZ		 2801 break;
2802
2803 callchain_store(entry, frame.return_address);
038e836e 2804 fp = frame.next_frame;
d7d59fb3
PZ		 2805 }
2806}
2807
2808static void
2809perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
2810{
2811 int is_user;
2812
2813 if (!regs)
2814 return;
2815
2816 is_user = user_mode(regs);
2817
d7d59fb3
PZ		 2818 if (is_user && current->state != TASK_RUNNING)
2819 return;
2820
2821 if (!is_user)
2822 perf_callchain_kernel(regs, entry);
2823
2824 if (current->mm)
2825 perf_callchain_user(regs, entry);
2826}
2827
2828struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
2829{
2830 struct perf_callchain_entry *entry;
2831
2832 if (in_nmi())
245b2e70 2833 entry = &__get_cpu_var(pmc_nmi_entry);
d7d59fb3 2834 else
245b2e70 2835 entry = &__get_cpu_var(pmc_irq_entry);
d7d59fb3
PZ		 2836
2837 entry->nr = 0;
2838
2839 perf_do_callchain(regs, entry);
2840
2841 return entry;
2842}
30dd568c 2843
cdd6c482 2844void hw_perf_event_setup_online(int cpu)
30dd568c
MM		 2845{
2846 init_debug_store_on_cpu(cpu);
2847}
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