[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kernel / cpu / proc.c

#include <linux/smp.h>
#include <linux/timex.h>
#include <linux/string.h>
#include <asm/semaphore.h>
#include <linux/seq_file.h>
#include <linux/cpufreq.h>

/*
 *	Get CPU information for use by the procfs.
 */
static int show_cpuinfo(struct seq_file *m, void *v)
{
	/* 
	 * These flag bits must match the definitions in <asm/cpufeature.h>.
	 * NULL means this bit is undefined or reserved; either way it doesn't
	 * have meaning as far as Linux is concerned.  Note that it's important
	 * to realize there is a difference between this table and CPUID -- if
	 * applications want to get the raw CPUID data, they should access
	 * /dev/cpu/<cpu_nr>/cpuid instead.
	 */
	static const char * const x86_cap_flags[] = {
		/* Intel-defined */
	        "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
	        "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
	        "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
	        "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", "pbe",

		/* AMD-defined */
		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, "mp", "nx", NULL, "mmxext", NULL,
		NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm",
		"3dnowext", "3dnow",

		/* Transmeta-defined */
		"recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

		/* Other (Linux-defined) */
		"cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",
		NULL, NULL, NULL, NULL,
		"constant_tsc", "up", NULL, "arch_perfmon",
		"pebs", "bts", NULL, "sync_rdtsc",
		"rep_good", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

		/* Intel-defined (#2) */
		"pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
		"tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
		NULL, NULL, "dca", NULL, NULL, NULL, NULL, "popcnt",
		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

		/* VIA/Cyrix/Centaur-defined */
		NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
		"ace2", "ace2_en", "phe", "phe_en", "pmm", "pmm_en", NULL, NULL,
		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

		/* AMD-defined (#2) */
		"lahf_lm", "cmp_legacy", "svm", "extapic", "cr8_legacy",
		"altmovcr8", "abm", "sse4a",
		"misalignsse", "3dnowprefetch",
		"osvw", "ibs", NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

		/* Auxiliary (Linux-defined) */
		"ida", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
	};
	static const char * const x86_power_flags[] = {
		"ts",	/* temperature sensor */
		"fid",  /* frequency id control */
		"vid",  /* voltage id control */
		"ttp",  /* thermal trip */
		"tm",
		"stc",
		"100mhzsteps",
		"hwpstate",
		"",	/* constant_tsc - moved to flags */
		/* nothing */
	};
	struct cpuinfo_x86 *c = v;
	int i, n = 0;
	int fpu_exception;

#ifdef CONFIG_SMP
	if (!cpu_online(n))
		return 0;
	n = c->cpu_index;
#endif
	seq_printf(m, "processor\t: %d\n"
		"vendor_id\t: %s\n"
		"cpu family\t: %d\n"
		"model\t\t: %d\n"
		"model name\t: %s\n",
		n,
		c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
		c->x86,
		c->x86_model,
		c->x86_model_id[0] ? c->x86_model_id : "unknown");

	if (c->x86_mask || c->cpuid_level >= 0)
		seq_printf(m, "stepping\t: %d\n", c->x86_mask);
	else
		seq_printf(m, "stepping\t: unknown\n");

	if ( cpu_has(c, X86_FEATURE_TSC) ) {
		unsigned int freq = cpufreq_quick_get(n);
		if (!freq)
			freq = cpu_khz;
		seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
			freq / 1000, (freq % 1000));
	}

	/* Cache size */
	if (c->x86_cache_size >= 0)
		seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
#ifdef CONFIG_X86_HT
	if (c->x86_max_cores * smp_num_siblings > 1) {
		seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
		seq_printf(m, "siblings\t: %d\n",
				cpus_weight(per_cpu(cpu_core_map, n)));
		seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
		seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
	}
#endif
	
	/* We use exception 16 if we have hardware math and we've either seen it or the CPU claims it is internal */
	fpu_exception = c->hard_math && (ignore_fpu_irq || cpu_has_fpu);
	seq_printf(m, "fdiv_bug\t: %s\n"
			"hlt_bug\t\t: %s\n"
			"f00f_bug\t: %s\n"
			"coma_bug\t: %s\n"
			"fpu\t\t: %s\n"
			"fpu_exception\t: %s\n"
			"cpuid level\t: %d\n"
			"wp\t\t: %s\n"
			"flags\t\t:",
		     c->fdiv_bug ? "yes" : "no",
		     c->hlt_works_ok ? "no" : "yes",
		     c->f00f_bug ? "yes" : "no",
		     c->coma_bug ? "yes" : "no",
		     c->hard_math ? "yes" : "no",
		     fpu_exception ? "yes" : "no",
		     c->cpuid_level,
		     c->wp_works_ok ? "yes" : "no");

	for ( i = 0 ; i < 32*NCAPINTS ; i++ )
		if ( test_bit(i, c->x86_capability) &&
		     x86_cap_flags[i] != NULL )
			seq_printf(m, " %s", x86_cap_flags[i]);

	for (i = 0; i < 32; i++)
		if (c->x86_power & (1 << i)) {
			if (i < ARRAY_SIZE(x86_power_flags) &&
			    x86_power_flags[i])
				seq_printf(m, "%s%s",
					   x86_power_flags[i][0]?" ":"",
					   x86_power_flags[i]);
			else
				seq_printf(m, " [%d]", i);
		}

	seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
		     c->loops_per_jiffy/(500000/HZ),
		     (c->loops_per_jiffy/(5000/HZ)) % 100);
	seq_printf(m, "clflush size\t: %u\n\n", c->x86_clflush_size);

	return 0;
}

static void *c_start(struct seq_file *m, loff_t *pos)
{
	if (*pos == 0)	/* just in case, cpu 0 is not the first */
		*pos = first_cpu(cpu_possible_map);
	if ((*pos) < NR_CPUS && cpu_possible(*pos))
		return &cpu_data(*pos);
	return NULL;
}
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
{
	*pos = next_cpu(*pos, cpu_possible_map);
	return c_start(m, pos);
}
static void c_stop(struct seq_file *m, void *v)
{
}
struct seq_operations cpuinfo_op = {
	.start	= c_start,
	.next	= c_next,
	.stop	= c_stop,
	.show	= show_cpuinfo,
};
Commit	Line	Data
1da177e4 LT	1	#include <linux/smp.h>
	2	#include <linux/timex.h>
	3	#include <linux/string.h>
	4	#include <asm/semaphore.h>
	5	#include <linux/seq_file.h>
95235ca2	6	#include <linux/cpufreq.h>
1da177e4 LT	7
	8	/*
	9	* Get CPU information for use by the procfs.
	10	*/
	11	static int show_cpuinfo(struct seq_file m, void v)
	12	{
	13	/*
	14	* These flag bits must match the definitions in <asm/cpufeature.h>.
	15	* NULL means this bit is undefined or reserved; either way it doesn't
	16	* have meaning as far as Linux is concerned. Note that it's important
	17	* to realize there is a difference between this table and CPUID -- if
	18	* applications want to get the raw CPUID data, they should access
	19	* /dev/cpu/<cpu_nr>/cpuid instead.
	20	*/
7f35bf92	21	static const char * const x86_cap_flags[] = {
1da177e4 LT	22	/* Intel-defined */
	23	"fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
	24	"cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
	25	"pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
	26	"fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", "pbe",
	27
	28	/* AMD-defined */
3c3b73b6	29	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1da177e4 LT	30	NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
1da177e4 LT	31	NULL, NULL, NULL, "mp", "nx", NULL, "mmxext", NULL,
ec481536 PA	32	NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm",
ec481536 PA	33	"3dnowext", "3dnow",
1da177e4 LT	34
	35	/* Transmeta-defined */
	36	"recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
	37	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
	38	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
	39	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
	40
	41	/* Other (Linux-defined) */
	42	"cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",
	43	NULL, NULL, NULL, NULL,
ec481536 PA	44	"constant_tsc", "up", NULL, "arch_perfmon",
	45	"pebs", "bts", NULL, "sync_rdtsc",
	46	"rep_good", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1da177e4 LT	47	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
	48
	49	/* Intel-defined (#2) */
9d95dd84	50	"pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
dcf10307	51	"tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
f790cd30	52	NULL, NULL, "dca", NULL, NULL, NULL, NULL, "popcnt",
1da177e4 LT	53	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
	54
	55	/* VIA/Cyrix/Centaur-defined */
	56	NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
224f611c	57	"ace2", "ace2_en", "phe", "phe_en", "pmm", "pmm_en", NULL, NULL,
1da177e4 LT	58	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
	59	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
	60
	61	/* AMD-defined (#2) */
ec481536 PA	62	"lahf_lm", "cmp_legacy", "svm", "extapic", "cr8_legacy",
	63	"altmovcr8", "abm", "sse4a",
	64	"misalignsse", "3dnowprefetch",
	65	"osvw", "ibs", NULL, NULL, NULL, NULL,
1da177e4 LT	66	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1da177e4 LT	67	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1d67953f VP	68
	69	/* Auxiliary (Linux-defined) */
	70	"ida", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
	71	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
	72	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
	73	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1da177e4	74	};
7f35bf92	75	static const char * const x86_power_flags[] = {
3f98bc49 AK	76	"ts", /* temperature sensor */
	77	"fid", /* frequency id control */
	78	"vid", /* voltage id control */
	79	"ttp", /* thermal trip */
	80	"tm",
	81	"stc",
f790cd30 AK	82	"100mhzsteps",
f790cd30 AK	83	"hwpstate",
d824395c	84	"", /* constant_tsc - moved to flags */
f790cd30	85	/* nothing */
3f98bc49	86	};
1da177e4	87	struct cpuinfo_x86 *c = v;
92cb7612	88	int i, n = 0;
1da177e4 LT	89	int fpu_exception;
	90
	91	#ifdef CONFIG_SMP
	92	if (!cpu_online(n))
	93	return 0;
92cb7612	94	n = c->cpu_index;
1da177e4 LT	95	#endif
	96	seq_printf(m, "processor\t: %d\n"
	97	"vendor_id\t: %s\n"
	98	"cpu family\t: %d\n"
	99	"model\t\t: %d\n"
	100	"model name\t: %s\n",
	101	n,
	102	c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
	103	c->x86,
	104	c->x86_model,
	105	c->x86_model_id[0] ? c->x86_model_id : "unknown");
	106
	107	if (c->x86_mask \|\| c->cpuid_level >= 0)
	108	seq_printf(m, "stepping\t: %d\n", c->x86_mask);
	109	else
	110	seq_printf(m, "stepping\t: unknown\n");
	111
	112	if ( cpu_has(c, X86_FEATURE_TSC) ) {
95235ca2 VP	113	unsigned int freq = cpufreq_quick_get(n);
	114	if (!freq)
	115	freq = cpu_khz;
a3a255e7	116	seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
95235ca2	117	freq / 1000, (freq % 1000));
1da177e4 LT	118	}
	119
	120	/* Cache size */
	121	if (c->x86_cache_size >= 0)
	122	seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
	123	#ifdef CONFIG_X86_HT
94605eff	124	if (c->x86_max_cores * smp_num_siblings > 1) {
4b89aff9	125	seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
08357611 MT	126	seq_printf(m, "siblings\t: %d\n",
08357611 MT	127	cpus_weight(per_cpu(cpu_core_map, n)));
4b89aff9	128	seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
94605eff	129	seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
db468681	130	}
1da177e4 LT	131	#endif
	132
	133	/* We use exception 16 if we have hardware math and we've either seen it or the CPU claims it is internal */
	134	fpu_exception = c->hard_math && (ignore_fpu_irq \|\| cpu_has_fpu);
	135	seq_printf(m, "fdiv_bug\t: %s\n"
	136	"hlt_bug\t\t: %s\n"
	137	"f00f_bug\t: %s\n"
	138	"coma_bug\t: %s\n"
	139	"fpu\t\t: %s\n"
	140	"fpu_exception\t: %s\n"
	141	"cpuid level\t: %d\n"
	142	"wp\t\t: %s\n"
	143	"flags\t\t:",
	144	c->fdiv_bug ? "yes" : "no",
	145	c->hlt_works_ok ? "no" : "yes",
	146	c->f00f_bug ? "yes" : "no",
	147	c->coma_bug ? "yes" : "no",
	148	c->hard_math ? "yes" : "no",
	149	fpu_exception ? "yes" : "no",
	150	c->cpuid_level,
	151	c->wp_works_ok ? "yes" : "no");
	152
	153	for ( i = 0 ; i < 32*NCAPINTS ; i++ )
	154	if ( test_bit(i, c->x86_capability) &&
	155	x86_cap_flags[i] != NULL )
	156	seq_printf(m, " %s", x86_cap_flags[i]);
	157
3f98bc49 AK	158	for (i = 0; i < 32; i++)
	159	if (c->x86_power & (1 << i)) {
	160	if (i < ARRAY_SIZE(x86_power_flags) &&
	161	x86_power_flags[i])
	162	seq_printf(m, "%s%s",
	163	x86_power_flags[i][0]?" ":"",
	164	x86_power_flags[i]);
	165	else
	166	seq_printf(m, " [%d]", i);
	167	}
	168
770d132f	169	seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
1da177e4 LT	170	c->loops_per_jiffy/(500000/HZ),
1da177e4 LT	171	(c->loops_per_jiffy/(5000/HZ)) % 100);
770d132f	172	seq_printf(m, "clflush size\t: %u\n\n", c->x86_clflush_size);
3dd9d514	173
1da177e4 LT	174	return 0;
	175	}
	176
	177	static void c_start(struct seq_file m, loff_t *pos)
	178	{
92cb7612 MT	179	if (pos == 0) / just in case, cpu 0 is not the first */
	180	*pos = first_cpu(cpu_possible_map);
	181	if ((pos) < NR_CPUS && cpu_possible(pos))
	182	return &cpu_data(*pos);
	183	return NULL;
1da177e4 LT	184	}
	185	static void c_next(struct seq_file m, void v, loff_t pos)
	186	{
92cb7612	187	pos = next_cpu(pos, cpu_possible_map);
1da177e4 LT	188	return c_start(m, pos);
	189	}
	190	static void c_stop(struct seq_file m, void v)
	191	{
	192	}
	193	struct seq_operations cpuinfo_op = {
	194	.start = c_start,
	195	.next = c_next,
	196	.stop = c_stop,
	197	.show = show_cpuinfo,
	198	};