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Commit | Line | Data |
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5d0cf410 | 1 | #include <linux/clocksource.h> |
e9e2cdb4 | 2 | #include <linux/clockchips.h> |
4588c1f0 | 3 | #include <linux/interrupt.h> |
69c60c88 | 4 | #include <linux/export.h> |
28769149 | 5 | #include <linux/delay.h> |
5d0cf410 | 6 | #include <linux/errno.h> |
334955ef | 7 | #include <linux/i8253.h> |
5a0e3ad6 | 8 | #include <linux/slab.h> |
5d0cf410 JS |
9 | #include <linux/hpet.h> |
10 | #include <linux/init.h> | |
58ac1e76 | 11 | #include <linux/cpu.h> |
4588c1f0 IM |
12 | #include <linux/pm.h> |
13 | #include <linux/io.h> | |
5d0cf410 | 14 | |
cd4d09ec | 15 | #include <asm/cpufeature.h> |
d746d1eb | 16 | #include <asm/irqdomain.h> |
28769149 | 17 | #include <asm/fixmap.h> |
4588c1f0 | 18 | #include <asm/hpet.h> |
16f871bc | 19 | #include <asm/time.h> |
5d0cf410 | 20 | |
4588c1f0 | 21 | #define HPET_MASK CLOCKSOURCE_MASK(32) |
5d0cf410 | 22 | |
b10db7f0 PM |
23 | /* FSEC = 10^-15 |
24 | NSEC = 10^-9 */ | |
4588c1f0 | 25 | #define FSEC_PER_NSEC 1000000L |
5d0cf410 | 26 | |
26afe5f2 | 27 | #define HPET_DEV_USED_BIT 2 |
28 | #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT) | |
29 | #define HPET_DEV_VALID 0x8 | |
30 | #define HPET_DEV_FSB_CAP 0x1000 | |
31 | #define HPET_DEV_PERI_CAP 0x2000 | |
32 | ||
f1c18071 TG |
33 | #define HPET_MIN_CYCLES 128 |
34 | #define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1)) | |
35 | ||
e9e2cdb4 TG |
36 | /* |
37 | * HPET address is set in acpi/boot.c, when an ACPI entry exists | |
38 | */ | |
4588c1f0 | 39 | unsigned long hpet_address; |
c8bc6f3c | 40 | u8 hpet_blockid; /* OS timer block num */ |
3d45ac4b | 41 | bool hpet_msi_disable; |
73472a46 | 42 | |
e951e4af | 43 | #ifdef CONFIG_PCI_MSI |
3d45ac4b | 44 | static unsigned int hpet_num_timers; |
e951e4af | 45 | #endif |
4588c1f0 | 46 | static void __iomem *hpet_virt_address; |
e9e2cdb4 | 47 | |
58ac1e76 | 48 | struct hpet_dev { |
4588c1f0 IM |
49 | struct clock_event_device evt; |
50 | unsigned int num; | |
51 | int cpu; | |
52 | unsigned int irq; | |
53 | unsigned int flags; | |
54 | char name[10]; | |
58ac1e76 | 55 | }; |
56 | ||
a3819e3e | 57 | static inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev) |
3f7787b3 FW |
58 | { |
59 | return container_of(evtdev, struct hpet_dev, evt); | |
60 | } | |
61 | ||
5946fa3d | 62 | inline unsigned int hpet_readl(unsigned int a) |
e9e2cdb4 TG |
63 | { |
64 | return readl(hpet_virt_address + a); | |
65 | } | |
66 | ||
5946fa3d | 67 | static inline void hpet_writel(unsigned int d, unsigned int a) |
e9e2cdb4 TG |
68 | { |
69 | writel(d, hpet_virt_address + a); | |
70 | } | |
71 | ||
28769149 | 72 | #ifdef CONFIG_X86_64 |
28769149 | 73 | #include <asm/pgtable.h> |
2387ce57 | 74 | #endif |
28769149 | 75 | |
06a24dec TG |
76 | static inline void hpet_set_mapping(void) |
77 | { | |
78 | hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE); | |
79 | } | |
80 | ||
81 | static inline void hpet_clear_mapping(void) | |
82 | { | |
83 | iounmap(hpet_virt_address); | |
84 | hpet_virt_address = NULL; | |
85 | } | |
86 | ||
e9e2cdb4 TG |
87 | /* |
88 | * HPET command line enable / disable | |
89 | */ | |
3d45ac4b JB |
90 | bool boot_hpet_disable; |
91 | bool hpet_force_user; | |
92 | static bool hpet_verbose; | |
e9e2cdb4 | 93 | |
4588c1f0 | 94 | static int __init hpet_setup(char *str) |
e9e2cdb4 | 95 | { |
b2d6aba9 JB |
96 | while (str) { |
97 | char *next = strchr(str, ','); | |
98 | ||
99 | if (next) | |
100 | *next++ = 0; | |
e9e2cdb4 | 101 | if (!strncmp("disable", str, 7)) |
3d45ac4b | 102 | boot_hpet_disable = true; |
b17530bd | 103 | if (!strncmp("force", str, 5)) |
3d45ac4b | 104 | hpet_force_user = true; |
b98103a5 | 105 | if (!strncmp("verbose", str, 7)) |
3d45ac4b | 106 | hpet_verbose = true; |
b2d6aba9 | 107 | str = next; |
e9e2cdb4 TG |
108 | } |
109 | return 1; | |
110 | } | |
111 | __setup("hpet=", hpet_setup); | |
112 | ||
28769149 TG |
113 | static int __init disable_hpet(char *str) |
114 | { | |
3d45ac4b | 115 | boot_hpet_disable = true; |
28769149 TG |
116 | return 1; |
117 | } | |
118 | __setup("nohpet", disable_hpet); | |
119 | ||
e9e2cdb4 TG |
120 | static inline int is_hpet_capable(void) |
121 | { | |
4588c1f0 | 122 | return !boot_hpet_disable && hpet_address; |
e9e2cdb4 TG |
123 | } |
124 | ||
125 | /* | |
126 | * HPET timer interrupt enable / disable | |
127 | */ | |
3d45ac4b | 128 | static bool hpet_legacy_int_enabled; |
e9e2cdb4 TG |
129 | |
130 | /** | |
131 | * is_hpet_enabled - check whether the hpet timer interrupt is enabled | |
132 | */ | |
133 | int is_hpet_enabled(void) | |
134 | { | |
135 | return is_hpet_capable() && hpet_legacy_int_enabled; | |
136 | } | |
1bdbdaac | 137 | EXPORT_SYMBOL_GPL(is_hpet_enabled); |
e9e2cdb4 | 138 | |
b98103a5 AH |
139 | static void _hpet_print_config(const char *function, int line) |
140 | { | |
141 | u32 i, timers, l, h; | |
142 | printk(KERN_INFO "hpet: %s(%d):\n", function, line); | |
143 | l = hpet_readl(HPET_ID); | |
144 | h = hpet_readl(HPET_PERIOD); | |
145 | timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; | |
146 | printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h); | |
147 | l = hpet_readl(HPET_CFG); | |
148 | h = hpet_readl(HPET_STATUS); | |
149 | printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h); | |
150 | l = hpet_readl(HPET_COUNTER); | |
151 | h = hpet_readl(HPET_COUNTER+4); | |
152 | printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h); | |
153 | ||
154 | for (i = 0; i < timers; i++) { | |
155 | l = hpet_readl(HPET_Tn_CFG(i)); | |
156 | h = hpet_readl(HPET_Tn_CFG(i)+4); | |
157 | printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n", | |
158 | i, l, h); | |
159 | l = hpet_readl(HPET_Tn_CMP(i)); | |
160 | h = hpet_readl(HPET_Tn_CMP(i)+4); | |
161 | printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n", | |
162 | i, l, h); | |
163 | l = hpet_readl(HPET_Tn_ROUTE(i)); | |
164 | h = hpet_readl(HPET_Tn_ROUTE(i)+4); | |
165 | printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n", | |
166 | i, l, h); | |
167 | } | |
168 | } | |
169 | ||
170 | #define hpet_print_config() \ | |
171 | do { \ | |
172 | if (hpet_verbose) \ | |
02f1f217 | 173 | _hpet_print_config(__func__, __LINE__); \ |
b98103a5 AH |
174 | } while (0) |
175 | ||
e9e2cdb4 TG |
176 | /* |
177 | * When the hpet driver (/dev/hpet) is enabled, we need to reserve | |
178 | * timer 0 and timer 1 in case of RTC emulation. | |
179 | */ | |
180 | #ifdef CONFIG_HPET | |
f0ed4e69 | 181 | |
5f79f2f2 | 182 | static void hpet_reserve_msi_timers(struct hpet_data *hd); |
f0ed4e69 | 183 | |
5946fa3d | 184 | static void hpet_reserve_platform_timers(unsigned int id) |
e9e2cdb4 TG |
185 | { |
186 | struct hpet __iomem *hpet = hpet_virt_address; | |
37a47db8 BR |
187 | struct hpet_timer __iomem *timer = &hpet->hpet_timers[2]; |
188 | unsigned int nrtimers, i; | |
e9e2cdb4 TG |
189 | struct hpet_data hd; |
190 | ||
191 | nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; | |
192 | ||
4588c1f0 IM |
193 | memset(&hd, 0, sizeof(hd)); |
194 | hd.hd_phys_address = hpet_address; | |
195 | hd.hd_address = hpet; | |
196 | hd.hd_nirqs = nrtimers; | |
e9e2cdb4 TG |
197 | hpet_reserve_timer(&hd, 0); |
198 | ||
199 | #ifdef CONFIG_HPET_EMULATE_RTC | |
200 | hpet_reserve_timer(&hd, 1); | |
201 | #endif | |
5761d64b | 202 | |
64a76f66 DB |
203 | /* |
204 | * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254 | |
205 | * is wrong for i8259!) not the output IRQ. Many BIOS writers | |
206 | * don't bother configuring *any* comparator interrupts. | |
207 | */ | |
e9e2cdb4 TG |
208 | hd.hd_irq[0] = HPET_LEGACY_8254; |
209 | hd.hd_irq[1] = HPET_LEGACY_RTC; | |
210 | ||
fc3fbc45 | 211 | for (i = 2; i < nrtimers; timer++, i++) { |
4588c1f0 IM |
212 | hd.hd_irq[i] = (readl(&timer->hpet_config) & |
213 | Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT; | |
fc3fbc45 | 214 | } |
5761d64b | 215 | |
f0ed4e69 | 216 | hpet_reserve_msi_timers(&hd); |
26afe5f2 | 217 | |
e9e2cdb4 | 218 | hpet_alloc(&hd); |
5761d64b | 219 | |
e9e2cdb4 TG |
220 | } |
221 | #else | |
5946fa3d | 222 | static void hpet_reserve_platform_timers(unsigned int id) { } |
e9e2cdb4 TG |
223 | #endif |
224 | ||
225 | /* | |
226 | * Common hpet info | |
227 | */ | |
ab0e08f1 | 228 | static unsigned long hpet_freq; |
e9e2cdb4 | 229 | |
c8b5db7d | 230 | static struct clock_event_device hpet_clockevent; |
e9e2cdb4 | 231 | |
8d6f0c82 | 232 | static void hpet_stop_counter(void) |
e9e2cdb4 | 233 | { |
3d45ac4b | 234 | u32 cfg = hpet_readl(HPET_CFG); |
e9e2cdb4 TG |
235 | cfg &= ~HPET_CFG_ENABLE; |
236 | hpet_writel(cfg, HPET_CFG); | |
7a6f9cbb AH |
237 | } |
238 | ||
239 | static void hpet_reset_counter(void) | |
240 | { | |
e9e2cdb4 TG |
241 | hpet_writel(0, HPET_COUNTER); |
242 | hpet_writel(0, HPET_COUNTER + 4); | |
8d6f0c82 AH |
243 | } |
244 | ||
245 | static void hpet_start_counter(void) | |
246 | { | |
5946fa3d | 247 | unsigned int cfg = hpet_readl(HPET_CFG); |
e9e2cdb4 TG |
248 | cfg |= HPET_CFG_ENABLE; |
249 | hpet_writel(cfg, HPET_CFG); | |
250 | } | |
251 | ||
8d6f0c82 AH |
252 | static void hpet_restart_counter(void) |
253 | { | |
254 | hpet_stop_counter(); | |
7a6f9cbb | 255 | hpet_reset_counter(); |
8d6f0c82 AH |
256 | hpet_start_counter(); |
257 | } | |
258 | ||
59c69f2a VP |
259 | static void hpet_resume_device(void) |
260 | { | |
bfe0c1cc | 261 | force_hpet_resume(); |
59c69f2a VP |
262 | } |
263 | ||
17622339 | 264 | static void hpet_resume_counter(struct clocksource *cs) |
59c69f2a VP |
265 | { |
266 | hpet_resume_device(); | |
8d6f0c82 | 267 | hpet_restart_counter(); |
59c69f2a VP |
268 | } |
269 | ||
610bf2f1 | 270 | static void hpet_enable_legacy_int(void) |
e9e2cdb4 | 271 | { |
5946fa3d | 272 | unsigned int cfg = hpet_readl(HPET_CFG); |
e9e2cdb4 TG |
273 | |
274 | cfg |= HPET_CFG_LEGACY; | |
275 | hpet_writel(cfg, HPET_CFG); | |
3d45ac4b | 276 | hpet_legacy_int_enabled = true; |
e9e2cdb4 TG |
277 | } |
278 | ||
610bf2f1 VP |
279 | static void hpet_legacy_clockevent_register(void) |
280 | { | |
610bf2f1 VP |
281 | /* Start HPET legacy interrupts */ |
282 | hpet_enable_legacy_int(); | |
283 | ||
610bf2f1 VP |
284 | /* |
285 | * Start hpet with the boot cpu mask and make it | |
286 | * global after the IO_APIC has been initialized. | |
287 | */ | |
803ff8a7 | 288 | hpet_clockevent.cpumask = cpumask_of(boot_cpu_data.cpu_index); |
ab0e08f1 TG |
289 | clockevents_config_and_register(&hpet_clockevent, hpet_freq, |
290 | HPET_MIN_PROG_DELTA, 0x7FFFFFFF); | |
610bf2f1 VP |
291 | global_clock_event = &hpet_clockevent; |
292 | printk(KERN_DEBUG "hpet clockevent registered\n"); | |
293 | } | |
294 | ||
c8b5db7d | 295 | static int hpet_set_periodic(struct clock_event_device *evt, int timer) |
e9e2cdb4 | 296 | { |
5946fa3d | 297 | unsigned int cfg, cmp, now; |
e9e2cdb4 TG |
298 | uint64_t delta; |
299 | ||
c8b5db7d VK |
300 | hpet_stop_counter(); |
301 | delta = ((uint64_t)(NSEC_PER_SEC / HZ)) * evt->mult; | |
302 | delta >>= evt->shift; | |
303 | now = hpet_readl(HPET_COUNTER); | |
304 | cmp = now + (unsigned int)delta; | |
305 | cfg = hpet_readl(HPET_Tn_CFG(timer)); | |
306 | cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL | | |
307 | HPET_TN_32BIT; | |
308 | hpet_writel(cfg, HPET_Tn_CFG(timer)); | |
309 | hpet_writel(cmp, HPET_Tn_CMP(timer)); | |
310 | udelay(1); | |
311 | /* | |
312 | * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL | |
313 | * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL | |
314 | * bit is automatically cleared after the first write. | |
315 | * (See AMD-8111 HyperTransport I/O Hub Data Sheet, | |
316 | * Publication # 24674) | |
317 | */ | |
318 | hpet_writel((unsigned int)delta, HPET_Tn_CMP(timer)); | |
319 | hpet_start_counter(); | |
320 | hpet_print_config(); | |
321 | ||
322 | return 0; | |
323 | } | |
324 | ||
325 | static int hpet_set_oneshot(struct clock_event_device *evt, int timer) | |
326 | { | |
327 | unsigned int cfg; | |
328 | ||
329 | cfg = hpet_readl(HPET_Tn_CFG(timer)); | |
330 | cfg &= ~HPET_TN_PERIODIC; | |
331 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
332 | hpet_writel(cfg, HPET_Tn_CFG(timer)); | |
333 | ||
334 | return 0; | |
335 | } | |
336 | ||
337 | static int hpet_shutdown(struct clock_event_device *evt, int timer) | |
338 | { | |
339 | unsigned int cfg; | |
340 | ||
341 | cfg = hpet_readl(HPET_Tn_CFG(timer)); | |
342 | cfg &= ~HPET_TN_ENABLE; | |
343 | hpet_writel(cfg, HPET_Tn_CFG(timer)); | |
344 | ||
345 | return 0; | |
346 | } | |
347 | ||
348 | static int hpet_resume(struct clock_event_device *evt, int timer) | |
349 | { | |
350 | if (!timer) { | |
351 | hpet_enable_legacy_int(); | |
352 | } else { | |
353 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
354 | ||
aaaec6fc | 355 | irq_domain_deactivate_irq(irq_get_irq_data(hdev->irq)); |
c8b5db7d | 356 | irq_domain_activate_irq(irq_get_irq_data(hdev->irq)); |
bb1a2c26 | 357 | disable_hardirq(hdev->irq); |
c8b5db7d VK |
358 | irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu)); |
359 | enable_irq(hdev->irq); | |
e9e2cdb4 | 360 | } |
c8b5db7d VK |
361 | hpet_print_config(); |
362 | ||
363 | return 0; | |
e9e2cdb4 TG |
364 | } |
365 | ||
b40d575b | 366 | static int hpet_next_event(unsigned long delta, |
367 | struct clock_event_device *evt, int timer) | |
e9e2cdb4 | 368 | { |
f7676254 | 369 | u32 cnt; |
995bd3bb | 370 | s32 res; |
e9e2cdb4 TG |
371 | |
372 | cnt = hpet_readl(HPET_COUNTER); | |
f7676254 | 373 | cnt += (u32) delta; |
b40d575b | 374 | hpet_writel(cnt, HPET_Tn_CMP(timer)); |
e9e2cdb4 | 375 | |
72d43d9b | 376 | /* |
995bd3bb TG |
377 | * HPETs are a complete disaster. The compare register is |
378 | * based on a equal comparison and neither provides a less | |
379 | * than or equal functionality (which would require to take | |
380 | * the wraparound into account) nor a simple count down event | |
381 | * mode. Further the write to the comparator register is | |
382 | * delayed internally up to two HPET clock cycles in certain | |
f1c18071 TG |
383 | * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even |
384 | * longer delays. We worked around that by reading back the | |
385 | * compare register, but that required another workaround for | |
386 | * ICH9,10 chips where the first readout after write can | |
387 | * return the old stale value. We already had a minimum | |
388 | * programming delta of 5us enforced, but a NMI or SMI hitting | |
995bd3bb TG |
389 | * between the counter readout and the comparator write can |
390 | * move us behind that point easily. Now instead of reading | |
391 | * the compare register back several times, we make the ETIME | |
392 | * decision based on the following: Return ETIME if the | |
f1c18071 | 393 | * counter value after the write is less than HPET_MIN_CYCLES |
995bd3bb | 394 | * away from the event or if the counter is already ahead of |
f1c18071 TG |
395 | * the event. The minimum programming delta for the generic |
396 | * clockevents code is set to 1.5 * HPET_MIN_CYCLES. | |
72d43d9b | 397 | */ |
995bd3bb | 398 | res = (s32)(cnt - hpet_readl(HPET_COUNTER)); |
72d43d9b | 399 | |
f1c18071 | 400 | return res < HPET_MIN_CYCLES ? -ETIME : 0; |
e9e2cdb4 TG |
401 | } |
402 | ||
c8b5db7d | 403 | static int hpet_legacy_shutdown(struct clock_event_device *evt) |
b40d575b | 404 | { |
c8b5db7d VK |
405 | return hpet_shutdown(evt, 0); |
406 | } | |
407 | ||
408 | static int hpet_legacy_set_oneshot(struct clock_event_device *evt) | |
409 | { | |
410 | return hpet_set_oneshot(evt, 0); | |
411 | } | |
412 | ||
413 | static int hpet_legacy_set_periodic(struct clock_event_device *evt) | |
414 | { | |
415 | return hpet_set_periodic(evt, 0); | |
416 | } | |
417 | ||
418 | static int hpet_legacy_resume(struct clock_event_device *evt) | |
419 | { | |
420 | return hpet_resume(evt, 0); | |
b40d575b | 421 | } |
422 | ||
423 | static int hpet_legacy_next_event(unsigned long delta, | |
424 | struct clock_event_device *evt) | |
425 | { | |
426 | return hpet_next_event(delta, evt, 0); | |
427 | } | |
428 | ||
c8b5db7d VK |
429 | /* |
430 | * The hpet clock event device | |
431 | */ | |
432 | static struct clock_event_device hpet_clockevent = { | |
433 | .name = "hpet", | |
434 | .features = CLOCK_EVT_FEAT_PERIODIC | | |
435 | CLOCK_EVT_FEAT_ONESHOT, | |
436 | .set_state_periodic = hpet_legacy_set_periodic, | |
437 | .set_state_oneshot = hpet_legacy_set_oneshot, | |
438 | .set_state_shutdown = hpet_legacy_shutdown, | |
439 | .tick_resume = hpet_legacy_resume, | |
440 | .set_next_event = hpet_legacy_next_event, | |
441 | .irq = 0, | |
442 | .rating = 50, | |
443 | }; | |
444 | ||
58ac1e76 | 445 | /* |
446 | * HPET MSI Support | |
447 | */ | |
26afe5f2 | 448 | #ifdef CONFIG_PCI_MSI |
5f79f2f2 VP |
449 | |
450 | static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev); | |
451 | static struct hpet_dev *hpet_devs; | |
3cb96f0c | 452 | static struct irq_domain *hpet_domain; |
5f79f2f2 | 453 | |
d0fbca8f | 454 | void hpet_msi_unmask(struct irq_data *data) |
58ac1e76 | 455 | { |
ff96b4d0 | 456 | struct hpet_dev *hdev = irq_data_get_irq_handler_data(data); |
5946fa3d | 457 | unsigned int cfg; |
58ac1e76 | 458 | |
459 | /* unmask it */ | |
460 | cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); | |
6acf5a8c | 461 | cfg |= HPET_TN_ENABLE | HPET_TN_FSB; |
58ac1e76 | 462 | hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); |
463 | } | |
464 | ||
d0fbca8f | 465 | void hpet_msi_mask(struct irq_data *data) |
58ac1e76 | 466 | { |
ff96b4d0 | 467 | struct hpet_dev *hdev = irq_data_get_irq_handler_data(data); |
5946fa3d | 468 | unsigned int cfg; |
58ac1e76 | 469 | |
470 | /* mask it */ | |
471 | cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); | |
6acf5a8c | 472 | cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB); |
58ac1e76 | 473 | hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); |
474 | } | |
475 | ||
d0fbca8f | 476 | void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg) |
58ac1e76 | 477 | { |
58ac1e76 | 478 | hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num)); |
479 | hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4); | |
480 | } | |
481 | ||
d0fbca8f | 482 | void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg) |
58ac1e76 | 483 | { |
58ac1e76 | 484 | msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num)); |
485 | msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4); | |
486 | msg->address_hi = 0; | |
487 | } | |
488 | ||
c8b5db7d | 489 | static int hpet_msi_shutdown(struct clock_event_device *evt) |
26afe5f2 | 490 | { |
491 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
c8b5db7d VK |
492 | |
493 | return hpet_shutdown(evt, hdev->num); | |
494 | } | |
495 | ||
496 | static int hpet_msi_set_oneshot(struct clock_event_device *evt) | |
497 | { | |
498 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
499 | ||
500 | return hpet_set_oneshot(evt, hdev->num); | |
501 | } | |
502 | ||
503 | static int hpet_msi_set_periodic(struct clock_event_device *evt) | |
504 | { | |
505 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
506 | ||
507 | return hpet_set_periodic(evt, hdev->num); | |
508 | } | |
509 | ||
510 | static int hpet_msi_resume(struct clock_event_device *evt) | |
511 | { | |
512 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
513 | ||
514 | return hpet_resume(evt, hdev->num); | |
26afe5f2 | 515 | } |
516 | ||
517 | static int hpet_msi_next_event(unsigned long delta, | |
518 | struct clock_event_device *evt) | |
519 | { | |
520 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
521 | return hpet_next_event(delta, evt, hdev->num); | |
522 | } | |
523 | ||
26afe5f2 | 524 | static irqreturn_t hpet_interrupt_handler(int irq, void *data) |
525 | { | |
526 | struct hpet_dev *dev = (struct hpet_dev *)data; | |
527 | struct clock_event_device *hevt = &dev->evt; | |
528 | ||
529 | if (!hevt->event_handler) { | |
530 | printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n", | |
531 | dev->num); | |
532 | return IRQ_HANDLED; | |
533 | } | |
534 | ||
535 | hevt->event_handler(hevt); | |
536 | return IRQ_HANDLED; | |
537 | } | |
538 | ||
539 | static int hpet_setup_irq(struct hpet_dev *dev) | |
540 | { | |
541 | ||
542 | if (request_irq(dev->irq, hpet_interrupt_handler, | |
d20d2efb | 543 | IRQF_TIMER | IRQF_NOBALANCING, |
507fa3a3 | 544 | dev->name, dev)) |
26afe5f2 | 545 | return -1; |
546 | ||
547 | disable_irq(dev->irq); | |
0de26520 | 548 | irq_set_affinity(dev->irq, cpumask_of(dev->cpu)); |
26afe5f2 | 549 | enable_irq(dev->irq); |
550 | ||
c81bba49 YL |
551 | printk(KERN_DEBUG "hpet: %s irq %d for MSI\n", |
552 | dev->name, dev->irq); | |
553 | ||
26afe5f2 | 554 | return 0; |
555 | } | |
556 | ||
557 | /* This should be called in specific @cpu */ | |
558 | static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu) | |
559 | { | |
560 | struct clock_event_device *evt = &hdev->evt; | |
26afe5f2 | 561 | |
562 | WARN_ON(cpu != smp_processor_id()); | |
563 | if (!(hdev->flags & HPET_DEV_VALID)) | |
564 | return; | |
565 | ||
26afe5f2 | 566 | hdev->cpu = cpu; |
567 | per_cpu(cpu_hpet_dev, cpu) = hdev; | |
568 | evt->name = hdev->name; | |
569 | hpet_setup_irq(hdev); | |
570 | evt->irq = hdev->irq; | |
571 | ||
572 | evt->rating = 110; | |
573 | evt->features = CLOCK_EVT_FEAT_ONESHOT; | |
c8b5db7d | 574 | if (hdev->flags & HPET_DEV_PERI_CAP) { |
26afe5f2 | 575 | evt->features |= CLOCK_EVT_FEAT_PERIODIC; |
c8b5db7d VK |
576 | evt->set_state_periodic = hpet_msi_set_periodic; |
577 | } | |
26afe5f2 | 578 | |
c8b5db7d VK |
579 | evt->set_state_shutdown = hpet_msi_shutdown; |
580 | evt->set_state_oneshot = hpet_msi_set_oneshot; | |
581 | evt->tick_resume = hpet_msi_resume; | |
26afe5f2 | 582 | evt->set_next_event = hpet_msi_next_event; |
320ab2b0 | 583 | evt->cpumask = cpumask_of(hdev->cpu); |
ab0e08f1 TG |
584 | |
585 | clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA, | |
586 | 0x7FFFFFFF); | |
26afe5f2 | 587 | } |
588 | ||
589 | #ifdef CONFIG_HPET | |
590 | /* Reserve at least one timer for userspace (/dev/hpet) */ | |
591 | #define RESERVE_TIMERS 1 | |
592 | #else | |
593 | #define RESERVE_TIMERS 0 | |
594 | #endif | |
5f79f2f2 VP |
595 | |
596 | static void hpet_msi_capability_lookup(unsigned int start_timer) | |
26afe5f2 | 597 | { |
598 | unsigned int id; | |
599 | unsigned int num_timers; | |
600 | unsigned int num_timers_used = 0; | |
3cb96f0c | 601 | int i, irq; |
26afe5f2 | 602 | |
73472a46 PV |
603 | if (hpet_msi_disable) |
604 | return; | |
605 | ||
39fe05e5 SL |
606 | if (boot_cpu_has(X86_FEATURE_ARAT)) |
607 | return; | |
26afe5f2 | 608 | id = hpet_readl(HPET_ID); |
609 | ||
610 | num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT); | |
611 | num_timers++; /* Value read out starts from 0 */ | |
b98103a5 | 612 | hpet_print_config(); |
26afe5f2 | 613 | |
3cb96f0c JL |
614 | hpet_domain = hpet_create_irq_domain(hpet_blockid); |
615 | if (!hpet_domain) | |
616 | return; | |
617 | ||
26afe5f2 | 618 | hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL); |
619 | if (!hpet_devs) | |
620 | return; | |
621 | ||
622 | hpet_num_timers = num_timers; | |
623 | ||
624 | for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) { | |
625 | struct hpet_dev *hdev = &hpet_devs[num_timers_used]; | |
5946fa3d | 626 | unsigned int cfg = hpet_readl(HPET_Tn_CFG(i)); |
26afe5f2 | 627 | |
628 | /* Only consider HPET timer with MSI support */ | |
629 | if (!(cfg & HPET_TN_FSB_CAP)) | |
630 | continue; | |
631 | ||
cb17b2a6 TG |
632 | hdev->flags = 0; |
633 | if (cfg & HPET_TN_PERIODIC_CAP) | |
634 | hdev->flags |= HPET_DEV_PERI_CAP; | |
635 | sprintf(hdev->name, "hpet%d", i); | |
636 | hdev->num = i; | |
637 | ||
3cb96f0c | 638 | irq = hpet_assign_irq(hpet_domain, hdev, hdev->num); |
bafac298 | 639 | if (irq <= 0) |
3cb96f0c JL |
640 | continue; |
641 | ||
3cb96f0c | 642 | hdev->irq = irq; |
26afe5f2 | 643 | hdev->flags |= HPET_DEV_FSB_CAP; |
644 | hdev->flags |= HPET_DEV_VALID; | |
645 | num_timers_used++; | |
646 | if (num_timers_used == num_possible_cpus()) | |
647 | break; | |
648 | } | |
649 | ||
650 | printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n", | |
651 | num_timers, num_timers_used); | |
652 | } | |
653 | ||
5f79f2f2 VP |
654 | #ifdef CONFIG_HPET |
655 | static void hpet_reserve_msi_timers(struct hpet_data *hd) | |
656 | { | |
657 | int i; | |
658 | ||
659 | if (!hpet_devs) | |
660 | return; | |
661 | ||
662 | for (i = 0; i < hpet_num_timers; i++) { | |
663 | struct hpet_dev *hdev = &hpet_devs[i]; | |
664 | ||
665 | if (!(hdev->flags & HPET_DEV_VALID)) | |
666 | continue; | |
667 | ||
668 | hd->hd_irq[hdev->num] = hdev->irq; | |
669 | hpet_reserve_timer(hd, hdev->num); | |
670 | } | |
671 | } | |
672 | #endif | |
673 | ||
26afe5f2 | 674 | static struct hpet_dev *hpet_get_unused_timer(void) |
675 | { | |
676 | int i; | |
677 | ||
678 | if (!hpet_devs) | |
679 | return NULL; | |
680 | ||
681 | for (i = 0; i < hpet_num_timers; i++) { | |
682 | struct hpet_dev *hdev = &hpet_devs[i]; | |
683 | ||
684 | if (!(hdev->flags & HPET_DEV_VALID)) | |
685 | continue; | |
686 | if (test_and_set_bit(HPET_DEV_USED_BIT, | |
687 | (unsigned long *)&hdev->flags)) | |
688 | continue; | |
689 | return hdev; | |
690 | } | |
691 | return NULL; | |
692 | } | |
693 | ||
694 | struct hpet_work_struct { | |
695 | struct delayed_work work; | |
696 | struct completion complete; | |
697 | }; | |
698 | ||
699 | static void hpet_work(struct work_struct *w) | |
700 | { | |
701 | struct hpet_dev *hdev; | |
702 | int cpu = smp_processor_id(); | |
703 | struct hpet_work_struct *hpet_work; | |
704 | ||
705 | hpet_work = container_of(w, struct hpet_work_struct, work.work); | |
706 | ||
707 | hdev = hpet_get_unused_timer(); | |
708 | if (hdev) | |
709 | init_one_hpet_msi_clockevent(hdev, cpu); | |
710 | ||
711 | complete(&hpet_work->complete); | |
712 | } | |
713 | ||
48d7f6c7 | 714 | static int hpet_cpuhp_online(unsigned int cpu) |
26afe5f2 | 715 | { |
26afe5f2 | 716 | struct hpet_work_struct work; |
48d7f6c7 SAS |
717 | |
718 | INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work); | |
719 | init_completion(&work.complete); | |
720 | /* FIXME: add schedule_work_on() */ | |
721 | schedule_delayed_work_on(cpu, &work.work, 0); | |
722 | wait_for_completion(&work.complete); | |
723 | destroy_delayed_work_on_stack(&work.work); | |
724 | return 0; | |
725 | } | |
726 | ||
727 | static int hpet_cpuhp_dead(unsigned int cpu) | |
728 | { | |
26afe5f2 | 729 | struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu); |
730 | ||
48d7f6c7 SAS |
731 | if (!hdev) |
732 | return 0; | |
733 | free_irq(hdev->irq, hdev); | |
734 | hdev->flags &= ~HPET_DEV_USED; | |
735 | per_cpu(cpu_hpet_dev, cpu) = NULL; | |
736 | return 0; | |
26afe5f2 | 737 | } |
738 | #else | |
739 | ||
5f79f2f2 VP |
740 | static void hpet_msi_capability_lookup(unsigned int start_timer) |
741 | { | |
742 | return; | |
743 | } | |
744 | ||
745 | #ifdef CONFIG_HPET | |
746 | static void hpet_reserve_msi_timers(struct hpet_data *hd) | |
26afe5f2 | 747 | { |
748 | return; | |
749 | } | |
5f79f2f2 | 750 | #endif |
26afe5f2 | 751 | |
48d7f6c7 SAS |
752 | #define hpet_cpuhp_online NULL |
753 | #define hpet_cpuhp_dead NULL | |
26afe5f2 | 754 | |
755 | #endif | |
756 | ||
6bb74df4 JS |
757 | /* |
758 | * Clock source related code | |
759 | */ | |
f99fd22e WL |
760 | #if defined(CONFIG_SMP) && defined(CONFIG_64BIT) |
761 | /* | |
762 | * Reading the HPET counter is a very slow operation. If a large number of | |
763 | * CPUs are trying to access the HPET counter simultaneously, it can cause | |
764 | * massive delay and slow down system performance dramatically. This may | |
765 | * happen when HPET is the default clock source instead of TSC. For a | |
766 | * really large system with hundreds of CPUs, the slowdown may be so | |
767 | * severe that it may actually crash the system because of a NMI watchdog | |
768 | * soft lockup, for example. | |
769 | * | |
770 | * If multiple CPUs are trying to access the HPET counter at the same time, | |
771 | * we don't actually need to read the counter multiple times. Instead, the | |
772 | * other CPUs can use the counter value read by the first CPU in the group. | |
773 | * | |
774 | * This special feature is only enabled on x86-64 systems. It is unlikely | |
775 | * that 32-bit x86 systems will have enough CPUs to require this feature | |
776 | * with its associated locking overhead. And we also need 64-bit atomic | |
777 | * read. | |
778 | * | |
779 | * The lock and the hpet value are stored together and can be read in a | |
780 | * single atomic 64-bit read. It is explicitly assumed that arch_spinlock_t | |
781 | * is 32 bits in size. | |
782 | */ | |
783 | union hpet_lock { | |
784 | struct { | |
785 | arch_spinlock_t lock; | |
786 | u32 value; | |
787 | }; | |
788 | u64 lockval; | |
789 | }; | |
790 | ||
791 | static union hpet_lock hpet __cacheline_aligned = { | |
792 | { .lock = __ARCH_SPIN_LOCK_UNLOCKED, }, | |
793 | }; | |
794 | ||
a5a1d1c2 | 795 | static u64 read_hpet(struct clocksource *cs) |
f99fd22e WL |
796 | { |
797 | unsigned long flags; | |
798 | union hpet_lock old, new; | |
799 | ||
800 | BUILD_BUG_ON(sizeof(union hpet_lock) != 8); | |
801 | ||
802 | /* | |
803 | * Read HPET directly if in NMI. | |
804 | */ | |
805 | if (in_nmi()) | |
a5a1d1c2 | 806 | return (u64)hpet_readl(HPET_COUNTER); |
f99fd22e WL |
807 | |
808 | /* | |
809 | * Read the current state of the lock and HPET value atomically. | |
810 | */ | |
811 | old.lockval = READ_ONCE(hpet.lockval); | |
812 | ||
813 | if (arch_spin_is_locked(&old.lock)) | |
814 | goto contended; | |
815 | ||
816 | local_irq_save(flags); | |
817 | if (arch_spin_trylock(&hpet.lock)) { | |
818 | new.value = hpet_readl(HPET_COUNTER); | |
819 | /* | |
820 | * Use WRITE_ONCE() to prevent store tearing. | |
821 | */ | |
822 | WRITE_ONCE(hpet.value, new.value); | |
823 | arch_spin_unlock(&hpet.lock); | |
824 | local_irq_restore(flags); | |
a5a1d1c2 | 825 | return (u64)new.value; |
f99fd22e WL |
826 | } |
827 | local_irq_restore(flags); | |
828 | ||
829 | contended: | |
830 | /* | |
831 | * Contended case | |
832 | * -------------- | |
833 | * Wait until the HPET value change or the lock is free to indicate | |
834 | * its value is up-to-date. | |
835 | * | |
836 | * It is possible that old.value has already contained the latest | |
837 | * HPET value while the lock holder was in the process of releasing | |
838 | * the lock. Checking for lock state change will enable us to return | |
839 | * the value immediately instead of waiting for the next HPET reader | |
840 | * to come along. | |
841 | */ | |
842 | do { | |
843 | cpu_relax(); | |
844 | new.lockval = READ_ONCE(hpet.lockval); | |
845 | } while ((new.value == old.value) && arch_spin_is_locked(&new.lock)); | |
846 | ||
a5a1d1c2 | 847 | return (u64)new.value; |
f99fd22e WL |
848 | } |
849 | #else | |
850 | /* | |
851 | * For UP or 32-bit. | |
852 | */ | |
a5a1d1c2 | 853 | static u64 read_hpet(struct clocksource *cs) |
6bb74df4 | 854 | { |
a5a1d1c2 | 855 | return (u64)hpet_readl(HPET_COUNTER); |
6bb74df4 | 856 | } |
f99fd22e | 857 | #endif |
6bb74df4 JS |
858 | |
859 | static struct clocksource clocksource_hpet = { | |
860 | .name = "hpet", | |
861 | .rating = 250, | |
862 | .read = read_hpet, | |
863 | .mask = HPET_MASK, | |
6bb74df4 | 864 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
8d6f0c82 | 865 | .resume = hpet_resume_counter, |
6bb74df4 JS |
866 | }; |
867 | ||
610bf2f1 | 868 | static int hpet_clocksource_register(void) |
e9e2cdb4 | 869 | { |
6fd592da | 870 | u64 start, now; |
a5a1d1c2 | 871 | u64 t1; |
e9e2cdb4 | 872 | |
e9e2cdb4 | 873 | /* Start the counter */ |
8d6f0c82 | 874 | hpet_restart_counter(); |
e9e2cdb4 | 875 | |
075bcd1f | 876 | /* Verify whether hpet counter works */ |
8e19608e | 877 | t1 = hpet_readl(HPET_COUNTER); |
4ea1636b | 878 | start = rdtsc(); |
075bcd1f TG |
879 | |
880 | /* | |
881 | * We don't know the TSC frequency yet, but waiting for | |
882 | * 200000 TSC cycles is safe: | |
883 | * 4 GHz == 50us | |
884 | * 1 GHz == 200us | |
885 | */ | |
886 | do { | |
887 | rep_nop(); | |
4ea1636b | 888 | now = rdtsc(); |
075bcd1f TG |
889 | } while ((now - start) < 200000UL); |
890 | ||
8e19608e | 891 | if (t1 == hpet_readl(HPET_COUNTER)) { |
075bcd1f TG |
892 | printk(KERN_WARNING |
893 | "HPET counter not counting. HPET disabled\n"); | |
610bf2f1 | 894 | return -ENODEV; |
075bcd1f TG |
895 | } |
896 | ||
f12a15be | 897 | clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq); |
610bf2f1 VP |
898 | return 0; |
899 | } | |
900 | ||
396e2c6f JB |
901 | static u32 *hpet_boot_cfg; |
902 | ||
b02a7f22 PM |
903 | /** |
904 | * hpet_enable - Try to setup the HPET timer. Returns 1 on success. | |
610bf2f1 VP |
905 | */ |
906 | int __init hpet_enable(void) | |
907 | { | |
396e2c6f | 908 | u32 hpet_period, cfg, id; |
ab0e08f1 | 909 | u64 freq; |
396e2c6f | 910 | unsigned int i, last; |
610bf2f1 VP |
911 | |
912 | if (!is_hpet_capable()) | |
913 | return 0; | |
914 | ||
915 | hpet_set_mapping(); | |
916 | ||
917 | /* | |
918 | * Read the period and check for a sane value: | |
919 | */ | |
920 | hpet_period = hpet_readl(HPET_PERIOD); | |
a6825f1c TG |
921 | |
922 | /* | |
923 | * AMD SB700 based systems with spread spectrum enabled use a | |
924 | * SMM based HPET emulation to provide proper frequency | |
925 | * setting. The SMM code is initialized with the first HPET | |
926 | * register access and takes some time to complete. During | |
927 | * this time the config register reads 0xffffffff. We check | |
928 | * for max. 1000 loops whether the config register reads a non | |
929 | * 0xffffffff value to make sure that HPET is up and running | |
930 | * before we go further. A counting loop is safe, as the HPET | |
931 | * access takes thousands of CPU cycles. On non SB700 based | |
932 | * machines this check is only done once and has no side | |
933 | * effects. | |
934 | */ | |
935 | for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) { | |
936 | if (i == 1000) { | |
937 | printk(KERN_WARNING | |
938 | "HPET config register value = 0xFFFFFFFF. " | |
939 | "Disabling HPET\n"); | |
940 | goto out_nohpet; | |
941 | } | |
942 | } | |
943 | ||
610bf2f1 VP |
944 | if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) |
945 | goto out_nohpet; | |
946 | ||
ab0e08f1 TG |
947 | /* |
948 | * The period is a femto seconds value. Convert it to a | |
949 | * frequency. | |
950 | */ | |
951 | freq = FSEC_PER_SEC; | |
952 | do_div(freq, hpet_period); | |
953 | hpet_freq = freq; | |
954 | ||
610bf2f1 VP |
955 | /* |
956 | * Read the HPET ID register to retrieve the IRQ routing | |
957 | * information and the number of channels | |
958 | */ | |
959 | id = hpet_readl(HPET_ID); | |
b98103a5 | 960 | hpet_print_config(); |
610bf2f1 | 961 | |
396e2c6f JB |
962 | last = (id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT; |
963 | ||
610bf2f1 VP |
964 | #ifdef CONFIG_HPET_EMULATE_RTC |
965 | /* | |
966 | * The legacy routing mode needs at least two channels, tick timer | |
967 | * and the rtc emulation channel. | |
968 | */ | |
396e2c6f | 969 | if (!last) |
610bf2f1 VP |
970 | goto out_nohpet; |
971 | #endif | |
972 | ||
396e2c6f JB |
973 | cfg = hpet_readl(HPET_CFG); |
974 | hpet_boot_cfg = kmalloc((last + 2) * sizeof(*hpet_boot_cfg), | |
975 | GFP_KERNEL); | |
976 | if (hpet_boot_cfg) | |
977 | *hpet_boot_cfg = cfg; | |
978 | else | |
979 | pr_warn("HPET initial state will not be saved\n"); | |
980 | cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY); | |
1b38a3a1 | 981 | hpet_writel(cfg, HPET_CFG); |
396e2c6f JB |
982 | if (cfg) |
983 | pr_warn("HPET: Unrecognized bits %#x set in global cfg\n", | |
984 | cfg); | |
985 | ||
986 | for (i = 0; i <= last; ++i) { | |
987 | cfg = hpet_readl(HPET_Tn_CFG(i)); | |
988 | if (hpet_boot_cfg) | |
989 | hpet_boot_cfg[i + 1] = cfg; | |
990 | cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB); | |
991 | hpet_writel(cfg, HPET_Tn_CFG(i)); | |
992 | cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP | |
993 | | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE | |
994 | | HPET_TN_FSB | HPET_TN_FSB_CAP); | |
995 | if (cfg) | |
996 | pr_warn("HPET: Unrecognized bits %#x set in cfg#%u\n", | |
997 | cfg, i); | |
998 | } | |
999 | hpet_print_config(); | |
1000 | ||
610bf2f1 VP |
1001 | if (hpet_clocksource_register()) |
1002 | goto out_nohpet; | |
1003 | ||
e9e2cdb4 | 1004 | if (id & HPET_ID_LEGSUP) { |
610bf2f1 | 1005 | hpet_legacy_clockevent_register(); |
e9e2cdb4 TG |
1006 | return 1; |
1007 | } | |
1008 | return 0; | |
5d0cf410 | 1009 | |
e9e2cdb4 | 1010 | out_nohpet: |
06a24dec | 1011 | hpet_clear_mapping(); |
bacbe999 | 1012 | hpet_address = 0; |
e9e2cdb4 TG |
1013 | return 0; |
1014 | } | |
1015 | ||
28769149 TG |
1016 | /* |
1017 | * Needs to be late, as the reserve_timer code calls kalloc ! | |
1018 | * | |
1019 | * Not a problem on i386 as hpet_enable is called from late_time_init, | |
1020 | * but on x86_64 it is necessary ! | |
1021 | */ | |
1022 | static __init int hpet_late_init(void) | |
1023 | { | |
48d7f6c7 | 1024 | int ret; |
26afe5f2 | 1025 | |
59c69f2a | 1026 | if (boot_hpet_disable) |
28769149 TG |
1027 | return -ENODEV; |
1028 | ||
59c69f2a VP |
1029 | if (!hpet_address) { |
1030 | if (!force_hpet_address) | |
1031 | return -ENODEV; | |
1032 | ||
1033 | hpet_address = force_hpet_address; | |
1034 | hpet_enable(); | |
59c69f2a VP |
1035 | } |
1036 | ||
39c04b55 JF |
1037 | if (!hpet_virt_address) |
1038 | return -ENODEV; | |
1039 | ||
39fe05e5 SL |
1040 | if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP) |
1041 | hpet_msi_capability_lookup(2); | |
1042 | else | |
1043 | hpet_msi_capability_lookup(0); | |
1044 | ||
28769149 | 1045 | hpet_reserve_platform_timers(hpet_readl(HPET_ID)); |
b98103a5 | 1046 | hpet_print_config(); |
59c69f2a | 1047 | |
73472a46 PV |
1048 | if (hpet_msi_disable) |
1049 | return 0; | |
1050 | ||
39fe05e5 SL |
1051 | if (boot_cpu_has(X86_FEATURE_ARAT)) |
1052 | return 0; | |
1053 | ||
26afe5f2 | 1054 | /* This notifier should be called after workqueue is ready */ |
73c1b41e | 1055 | ret = cpuhp_setup_state(CPUHP_AP_X86_HPET_ONLINE, "x86/hpet:online", |
48d7f6c7 SAS |
1056 | hpet_cpuhp_online, NULL); |
1057 | if (ret) | |
1058 | return ret; | |
73c1b41e | 1059 | ret = cpuhp_setup_state(CPUHP_X86_HPET_DEAD, "x86/hpet:dead", NULL, |
48d7f6c7 SAS |
1060 | hpet_cpuhp_dead); |
1061 | if (ret) | |
1062 | goto err_cpuhp; | |
28769149 | 1063 | return 0; |
48d7f6c7 SAS |
1064 | |
1065 | err_cpuhp: | |
1066 | cpuhp_remove_state(CPUHP_AP_X86_HPET_ONLINE); | |
1067 | return ret; | |
28769149 TG |
1068 | } |
1069 | fs_initcall(hpet_late_init); | |
1070 | ||
c86c7fbc OH |
1071 | void hpet_disable(void) |
1072 | { | |
ff487808 | 1073 | if (is_hpet_capable() && hpet_virt_address) { |
396e2c6f | 1074 | unsigned int cfg = hpet_readl(HPET_CFG), id, last; |
c86c7fbc | 1075 | |
396e2c6f JB |
1076 | if (hpet_boot_cfg) |
1077 | cfg = *hpet_boot_cfg; | |
1078 | else if (hpet_legacy_int_enabled) { | |
c86c7fbc | 1079 | cfg &= ~HPET_CFG_LEGACY; |
3d45ac4b | 1080 | hpet_legacy_int_enabled = false; |
c86c7fbc OH |
1081 | } |
1082 | cfg &= ~HPET_CFG_ENABLE; | |
1083 | hpet_writel(cfg, HPET_CFG); | |
396e2c6f JB |
1084 | |
1085 | if (!hpet_boot_cfg) | |
1086 | return; | |
1087 | ||
1088 | id = hpet_readl(HPET_ID); | |
1089 | last = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT); | |
1090 | ||
1091 | for (id = 0; id <= last; ++id) | |
1092 | hpet_writel(hpet_boot_cfg[id + 1], HPET_Tn_CFG(id)); | |
1093 | ||
1094 | if (*hpet_boot_cfg & HPET_CFG_ENABLE) | |
1095 | hpet_writel(*hpet_boot_cfg, HPET_CFG); | |
c86c7fbc OH |
1096 | } |
1097 | } | |
1098 | ||
e9e2cdb4 TG |
1099 | #ifdef CONFIG_HPET_EMULATE_RTC |
1100 | ||
1101 | /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET | |
1102 | * is enabled, we support RTC interrupt functionality in software. | |
1103 | * RTC has 3 kinds of interrupts: | |
1104 | * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock | |
1105 | * is updated | |
1106 | * 2) Alarm Interrupt - generate an interrupt at a specific time of day | |
1107 | * 3) Periodic Interrupt - generate periodic interrupt, with frequencies | |
1108 | * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2) | |
1109 | * (1) and (2) above are implemented using polling at a frequency of | |
1110 | * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt | |
1111 | * overhead. (DEFAULT_RTC_INT_FREQ) | |
1112 | * For (3), we use interrupts at 64Hz or user specified periodic | |
1113 | * frequency, whichever is higher. | |
1114 | */ | |
1115 | #include <linux/mc146818rtc.h> | |
1116 | #include <linux/rtc.h> | |
1117 | ||
1118 | #define DEFAULT_RTC_INT_FREQ 64 | |
1119 | #define DEFAULT_RTC_SHIFT 6 | |
1120 | #define RTC_NUM_INTS 1 | |
1121 | ||
1122 | static unsigned long hpet_rtc_flags; | |
7e2a31da | 1123 | static int hpet_prev_update_sec; |
e9e2cdb4 TG |
1124 | static struct rtc_time hpet_alarm_time; |
1125 | static unsigned long hpet_pie_count; | |
ff08f76d | 1126 | static u32 hpet_t1_cmp; |
5946fa3d JB |
1127 | static u32 hpet_default_delta; |
1128 | static u32 hpet_pie_delta; | |
e9e2cdb4 TG |
1129 | static unsigned long hpet_pie_limit; |
1130 | ||
1bdbdaac BW |
1131 | static rtc_irq_handler irq_handler; |
1132 | ||
ff08f76d PE |
1133 | /* |
1134 | * Check that the hpet counter c1 is ahead of the c2 | |
1135 | */ | |
1136 | static inline int hpet_cnt_ahead(u32 c1, u32 c2) | |
1137 | { | |
1138 | return (s32)(c2 - c1) < 0; | |
1139 | } | |
1140 | ||
1bdbdaac BW |
1141 | /* |
1142 | * Registers a IRQ handler. | |
1143 | */ | |
1144 | int hpet_register_irq_handler(rtc_irq_handler handler) | |
1145 | { | |
1146 | if (!is_hpet_enabled()) | |
1147 | return -ENODEV; | |
1148 | if (irq_handler) | |
1149 | return -EBUSY; | |
1150 | ||
1151 | irq_handler = handler; | |
1152 | ||
1153 | return 0; | |
1154 | } | |
1155 | EXPORT_SYMBOL_GPL(hpet_register_irq_handler); | |
1156 | ||
1157 | /* | |
1158 | * Deregisters the IRQ handler registered with hpet_register_irq_handler() | |
1159 | * and does cleanup. | |
1160 | */ | |
1161 | void hpet_unregister_irq_handler(rtc_irq_handler handler) | |
1162 | { | |
1163 | if (!is_hpet_enabled()) | |
1164 | return; | |
1165 | ||
1166 | irq_handler = NULL; | |
1167 | hpet_rtc_flags = 0; | |
1168 | } | |
1169 | EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler); | |
1170 | ||
e9e2cdb4 TG |
1171 | /* |
1172 | * Timer 1 for RTC emulation. We use one shot mode, as periodic mode | |
1173 | * is not supported by all HPET implementations for timer 1. | |
1174 | * | |
1175 | * hpet_rtc_timer_init() is called when the rtc is initialized. | |
1176 | */ | |
1177 | int hpet_rtc_timer_init(void) | |
1178 | { | |
5946fa3d JB |
1179 | unsigned int cfg, cnt, delta; |
1180 | unsigned long flags; | |
e9e2cdb4 TG |
1181 | |
1182 | if (!is_hpet_enabled()) | |
1183 | return 0; | |
1184 | ||
1185 | if (!hpet_default_delta) { | |
1186 | uint64_t clc; | |
1187 | ||
1188 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
1189 | clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT; | |
5946fa3d | 1190 | hpet_default_delta = clc; |
e9e2cdb4 TG |
1191 | } |
1192 | ||
1193 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
1194 | delta = hpet_default_delta; | |
1195 | else | |
1196 | delta = hpet_pie_delta; | |
1197 | ||
1198 | local_irq_save(flags); | |
1199 | ||
1200 | cnt = delta + hpet_readl(HPET_COUNTER); | |
1201 | hpet_writel(cnt, HPET_T1_CMP); | |
1202 | hpet_t1_cmp = cnt; | |
1203 | ||
1204 | cfg = hpet_readl(HPET_T1_CFG); | |
1205 | cfg &= ~HPET_TN_PERIODIC; | |
1206 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
1207 | hpet_writel(cfg, HPET_T1_CFG); | |
1208 | ||
1209 | local_irq_restore(flags); | |
1210 | ||
1211 | return 1; | |
1212 | } | |
1bdbdaac | 1213 | EXPORT_SYMBOL_GPL(hpet_rtc_timer_init); |
e9e2cdb4 | 1214 | |
2ded6e6a ML |
1215 | static void hpet_disable_rtc_channel(void) |
1216 | { | |
3d45ac4b | 1217 | u32 cfg = hpet_readl(HPET_T1_CFG); |
2ded6e6a ML |
1218 | cfg &= ~HPET_TN_ENABLE; |
1219 | hpet_writel(cfg, HPET_T1_CFG); | |
1220 | } | |
1221 | ||
e9e2cdb4 TG |
1222 | /* |
1223 | * The functions below are called from rtc driver. | |
1224 | * Return 0 if HPET is not being used. | |
1225 | * Otherwise do the necessary changes and return 1. | |
1226 | */ | |
1227 | int hpet_mask_rtc_irq_bit(unsigned long bit_mask) | |
1228 | { | |
1229 | if (!is_hpet_enabled()) | |
1230 | return 0; | |
1231 | ||
1232 | hpet_rtc_flags &= ~bit_mask; | |
2ded6e6a ML |
1233 | if (unlikely(!hpet_rtc_flags)) |
1234 | hpet_disable_rtc_channel(); | |
1235 | ||
e9e2cdb4 TG |
1236 | return 1; |
1237 | } | |
1bdbdaac | 1238 | EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit); |
e9e2cdb4 TG |
1239 | |
1240 | int hpet_set_rtc_irq_bit(unsigned long bit_mask) | |
1241 | { | |
1242 | unsigned long oldbits = hpet_rtc_flags; | |
1243 | ||
1244 | if (!is_hpet_enabled()) | |
1245 | return 0; | |
1246 | ||
1247 | hpet_rtc_flags |= bit_mask; | |
1248 | ||
7e2a31da DB |
1249 | if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE)) |
1250 | hpet_prev_update_sec = -1; | |
1251 | ||
e9e2cdb4 TG |
1252 | if (!oldbits) |
1253 | hpet_rtc_timer_init(); | |
1254 | ||
1255 | return 1; | |
1256 | } | |
1bdbdaac | 1257 | EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit); |
e9e2cdb4 TG |
1258 | |
1259 | int hpet_set_alarm_time(unsigned char hrs, unsigned char min, | |
1260 | unsigned char sec) | |
1261 | { | |
1262 | if (!is_hpet_enabled()) | |
1263 | return 0; | |
1264 | ||
1265 | hpet_alarm_time.tm_hour = hrs; | |
1266 | hpet_alarm_time.tm_min = min; | |
1267 | hpet_alarm_time.tm_sec = sec; | |
1268 | ||
1269 | return 1; | |
1270 | } | |
1bdbdaac | 1271 | EXPORT_SYMBOL_GPL(hpet_set_alarm_time); |
e9e2cdb4 TG |
1272 | |
1273 | int hpet_set_periodic_freq(unsigned long freq) | |
1274 | { | |
1275 | uint64_t clc; | |
1276 | ||
1277 | if (!is_hpet_enabled()) | |
1278 | return 0; | |
1279 | ||
1280 | if (freq <= DEFAULT_RTC_INT_FREQ) | |
1281 | hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; | |
1282 | else { | |
1283 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
1284 | do_div(clc, freq); | |
1285 | clc >>= hpet_clockevent.shift; | |
5946fa3d | 1286 | hpet_pie_delta = clc; |
b4a5e8a1 | 1287 | hpet_pie_limit = 0; |
e9e2cdb4 TG |
1288 | } |
1289 | return 1; | |
1290 | } | |
1bdbdaac | 1291 | EXPORT_SYMBOL_GPL(hpet_set_periodic_freq); |
e9e2cdb4 TG |
1292 | |
1293 | int hpet_rtc_dropped_irq(void) | |
1294 | { | |
1295 | return is_hpet_enabled(); | |
1296 | } | |
1bdbdaac | 1297 | EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq); |
e9e2cdb4 TG |
1298 | |
1299 | static void hpet_rtc_timer_reinit(void) | |
1300 | { | |
2ded6e6a | 1301 | unsigned int delta; |
e9e2cdb4 TG |
1302 | int lost_ints = -1; |
1303 | ||
2ded6e6a ML |
1304 | if (unlikely(!hpet_rtc_flags)) |
1305 | hpet_disable_rtc_channel(); | |
e9e2cdb4 TG |
1306 | |
1307 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
1308 | delta = hpet_default_delta; | |
1309 | else | |
1310 | delta = hpet_pie_delta; | |
1311 | ||
1312 | /* | |
1313 | * Increment the comparator value until we are ahead of the | |
1314 | * current count. | |
1315 | */ | |
1316 | do { | |
1317 | hpet_t1_cmp += delta; | |
1318 | hpet_writel(hpet_t1_cmp, HPET_T1_CMP); | |
1319 | lost_ints++; | |
ff08f76d | 1320 | } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER))); |
e9e2cdb4 TG |
1321 | |
1322 | if (lost_ints) { | |
1323 | if (hpet_rtc_flags & RTC_PIE) | |
1324 | hpet_pie_count += lost_ints; | |
1325 | if (printk_ratelimit()) | |
7e2a31da | 1326 | printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n", |
e9e2cdb4 TG |
1327 | lost_ints); |
1328 | } | |
1329 | } | |
1330 | ||
1331 | irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) | |
1332 | { | |
1333 | struct rtc_time curr_time; | |
1334 | unsigned long rtc_int_flag = 0; | |
1335 | ||
1336 | hpet_rtc_timer_reinit(); | |
1bdbdaac | 1337 | memset(&curr_time, 0, sizeof(struct rtc_time)); |
e9e2cdb4 TG |
1338 | |
1339 | if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) | |
22cc1ca3 | 1340 | mc146818_get_time(&curr_time); |
e9e2cdb4 TG |
1341 | |
1342 | if (hpet_rtc_flags & RTC_UIE && | |
1343 | curr_time.tm_sec != hpet_prev_update_sec) { | |
7e2a31da DB |
1344 | if (hpet_prev_update_sec >= 0) |
1345 | rtc_int_flag = RTC_UF; | |
e9e2cdb4 TG |
1346 | hpet_prev_update_sec = curr_time.tm_sec; |
1347 | } | |
1348 | ||
1349 | if (hpet_rtc_flags & RTC_PIE && | |
1350 | ++hpet_pie_count >= hpet_pie_limit) { | |
1351 | rtc_int_flag |= RTC_PF; | |
1352 | hpet_pie_count = 0; | |
1353 | } | |
1354 | ||
8ee291f8 | 1355 | if (hpet_rtc_flags & RTC_AIE && |
e9e2cdb4 TG |
1356 | (curr_time.tm_sec == hpet_alarm_time.tm_sec) && |
1357 | (curr_time.tm_min == hpet_alarm_time.tm_min) && | |
1358 | (curr_time.tm_hour == hpet_alarm_time.tm_hour)) | |
1359 | rtc_int_flag |= RTC_AF; | |
1360 | ||
1361 | if (rtc_int_flag) { | |
1362 | rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); | |
1bdbdaac BW |
1363 | if (irq_handler) |
1364 | irq_handler(rtc_int_flag, dev_id); | |
e9e2cdb4 TG |
1365 | } |
1366 | return IRQ_HANDLED; | |
1367 | } | |
1bdbdaac | 1368 | EXPORT_SYMBOL_GPL(hpet_rtc_interrupt); |
e9e2cdb4 | 1369 | #endif |