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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 1994 Linus Torvalds |
3 | * | |
4 | * Pentium III FXSR, SSE support | |
5 | * General FPU state handling cleanups | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | */ | |
8 | ||
1da177e4 | 9 | #include <linux/sched.h> |
129f6946 | 10 | #include <linux/module.h> |
44210111 | 11 | #include <linux/regset.h> |
1da177e4 LT |
12 | #include <asm/processor.h> |
13 | #include <asm/i387.h> | |
14 | #include <asm/math_emu.h> | |
15 | #include <asm/sigcontext.h> | |
16 | #include <asm/user.h> | |
17 | #include <asm/ptrace.h> | |
18 | #include <asm/uaccess.h> | |
19 | ||
44210111 RM |
20 | #ifdef CONFIG_X86_64 |
21 | ||
22 | #include <asm/sigcontext32.h> | |
23 | #include <asm/user32.h> | |
24 | ||
25 | #else | |
26 | ||
27 | #define save_i387_ia32 save_i387 | |
28 | #define restore_i387_ia32 restore_i387 | |
29 | ||
30 | #define _fpstate_ia32 _fpstate | |
31 | #define user_i387_ia32_struct user_i387_struct | |
32 | #define user32_fxsr_struct user_fxsr_struct | |
33 | ||
34 | #endif | |
35 | ||
1da177e4 LT |
36 | #ifdef CONFIG_MATH_EMULATION |
37 | #define HAVE_HWFP (boot_cpu_data.hard_math) | |
38 | #else | |
39 | #define HAVE_HWFP 1 | |
40 | #endif | |
41 | ||
148a1424 | 42 | static unsigned int mxcsr_feature_mask __read_mostly = 0xffffffffu; |
1da177e4 LT |
43 | |
44 | void mxcsr_feature_mask_init(void) | |
45 | { | |
46 | unsigned long mask = 0; | |
47 | clts(); | |
48 | if (cpu_has_fxsr) { | |
3b095a04 CG |
49 | memset(¤t->thread.i387.fxsave, 0, |
50 | sizeof(struct i387_fxsave_struct)); | |
51 | asm volatile("fxsave %0" : : "m" (current->thread.i387.fxsave)); | |
1da177e4 | 52 | mask = current->thread.i387.fxsave.mxcsr_mask; |
3b095a04 CG |
53 | if (mask == 0) |
54 | mask = 0x0000ffbf; | |
55 | } | |
1da177e4 LT |
56 | mxcsr_feature_mask &= mask; |
57 | stts(); | |
58 | } | |
59 | ||
44210111 RM |
60 | #ifdef CONFIG_X86_64 |
61 | /* | |
62 | * Called at bootup to set up the initial FPU state that is later cloned | |
63 | * into all processes. | |
64 | */ | |
65 | void __cpuinit fpu_init(void) | |
66 | { | |
67 | unsigned long oldcr0 = read_cr0(); | |
68 | extern void __bad_fxsave_alignment(void); | |
69 | ||
70 | if (offsetof(struct task_struct, thread.i387.fxsave) & 15) | |
71 | __bad_fxsave_alignment(); | |
72 | set_in_cr4(X86_CR4_OSFXSR); | |
73 | set_in_cr4(X86_CR4_OSXMMEXCPT); | |
74 | ||
75 | write_cr0(oldcr0 & ~((1UL<<3)|(1UL<<2))); /* clear TS and EM */ | |
76 | ||
77 | mxcsr_feature_mask_init(); | |
78 | /* clean state in init */ | |
79 | current_thread_info()->status = 0; | |
80 | clear_used_math(); | |
81 | } | |
82 | #endif /* CONFIG_X86_64 */ | |
83 | ||
1da177e4 LT |
84 | /* |
85 | * The _current_ task is using the FPU for the first time | |
86 | * so initialize it and set the mxcsr to its default | |
87 | * value at reset if we support XMM instructions and then | |
88 | * remeber the current task has used the FPU. | |
89 | */ | |
90 | void init_fpu(struct task_struct *tsk) | |
91 | { | |
44210111 RM |
92 | if (tsk_used_math(tsk)) { |
93 | if (tsk == current) | |
94 | unlazy_fpu(tsk); | |
95 | return; | |
96 | } | |
97 | ||
1da177e4 | 98 | if (cpu_has_fxsr) { |
3b095a04 CG |
99 | memset(&tsk->thread.i387.fxsave, 0, |
100 | sizeof(struct i387_fxsave_struct)); | |
1da177e4 LT |
101 | tsk->thread.i387.fxsave.cwd = 0x37f; |
102 | if (cpu_has_xmm) | |
44210111 | 103 | tsk->thread.i387.fxsave.mxcsr = MXCSR_DEFAULT; |
1da177e4 | 104 | } else { |
3b095a04 CG |
105 | memset(&tsk->thread.i387.fsave, 0, |
106 | sizeof(struct i387_fsave_struct)); | |
1da177e4 LT |
107 | tsk->thread.i387.fsave.cwd = 0xffff037fu; |
108 | tsk->thread.i387.fsave.swd = 0xffff0000u; | |
109 | tsk->thread.i387.fsave.twd = 0xffffffffu; | |
110 | tsk->thread.i387.fsave.fos = 0xffff0000u; | |
111 | } | |
44210111 RM |
112 | /* |
113 | * Only the device not available exception or ptrace can call init_fpu. | |
114 | */ | |
1da177e4 LT |
115 | set_stopped_child_used_math(tsk); |
116 | } | |
117 | ||
44210111 RM |
118 | int fpregs_active(struct task_struct *target, const struct user_regset *regset) |
119 | { | |
120 | return tsk_used_math(target) ? regset->n : 0; | |
121 | } | |
1da177e4 | 122 | |
44210111 | 123 | int xfpregs_active(struct task_struct *target, const struct user_regset *regset) |
1da177e4 | 124 | { |
44210111 RM |
125 | return (cpu_has_fxsr && tsk_used_math(target)) ? regset->n : 0; |
126 | } | |
1da177e4 | 127 | |
44210111 RM |
128 | int xfpregs_get(struct task_struct *target, const struct user_regset *regset, |
129 | unsigned int pos, unsigned int count, | |
130 | void *kbuf, void __user *ubuf) | |
131 | { | |
132 | if (!cpu_has_fxsr) | |
133 | return -ENODEV; | |
134 | ||
18a86221 | 135 | init_fpu(target); |
44210111 RM |
136 | |
137 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
138 | &target->thread.i387.fxsave, 0, -1); | |
1da177e4 | 139 | } |
44210111 RM |
140 | |
141 | int xfpregs_set(struct task_struct *target, const struct user_regset *regset, | |
142 | unsigned int pos, unsigned int count, | |
143 | const void *kbuf, const void __user *ubuf) | |
144 | { | |
145 | int ret; | |
146 | ||
147 | if (!cpu_has_fxsr) | |
148 | return -ENODEV; | |
149 | ||
18a86221 | 150 | init_fpu(target); |
44210111 RM |
151 | set_stopped_child_used_math(target); |
152 | ||
153 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
154 | &target->thread.i387.fxsave, 0, -1); | |
155 | ||
156 | /* | |
157 | * mxcsr reserved bits must be masked to zero for security reasons. | |
158 | */ | |
159 | target->thread.i387.fxsave.mxcsr &= mxcsr_feature_mask; | |
160 | ||
161 | return ret; | |
162 | } | |
163 | ||
164 | #if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION | |
1da177e4 | 165 | |
1da177e4 LT |
166 | /* |
167 | * FPU tag word conversions. | |
168 | */ | |
169 | ||
3b095a04 | 170 | static inline unsigned short twd_i387_to_fxsr(unsigned short twd) |
1da177e4 LT |
171 | { |
172 | unsigned int tmp; /* to avoid 16 bit prefixes in the code */ | |
3b095a04 | 173 | |
1da177e4 | 174 | /* Transform each pair of bits into 01 (valid) or 00 (empty) */ |
3b095a04 | 175 | tmp = ~twd; |
44210111 | 176 | tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */ |
3b095a04 CG |
177 | /* and move the valid bits to the lower byte. */ |
178 | tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */ | |
179 | tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */ | |
180 | tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */ | |
3b095a04 | 181 | return tmp; |
1da177e4 LT |
182 | } |
183 | ||
1da177e4 | 184 | #define FPREG_ADDR(f, n) ((void *)&(f)->st_space + (n) * 16); |
44210111 RM |
185 | #define FP_EXP_TAG_VALID 0 |
186 | #define FP_EXP_TAG_ZERO 1 | |
187 | #define FP_EXP_TAG_SPECIAL 2 | |
188 | #define FP_EXP_TAG_EMPTY 3 | |
189 | ||
190 | static inline u32 twd_fxsr_to_i387(struct i387_fxsave_struct *fxsave) | |
191 | { | |
192 | struct _fpxreg *st; | |
193 | u32 tos = (fxsave->swd >> 11) & 7; | |
194 | u32 twd = (unsigned long) fxsave->twd; | |
195 | u32 tag; | |
196 | u32 ret = 0xffff0000u; | |
197 | int i; | |
1da177e4 | 198 | |
44210111 | 199 | for (i = 0; i < 8; i++, twd >>= 1) { |
3b095a04 CG |
200 | if (twd & 0x1) { |
201 | st = FPREG_ADDR(fxsave, (i - tos) & 7); | |
1da177e4 | 202 | |
3b095a04 | 203 | switch (st->exponent & 0x7fff) { |
1da177e4 | 204 | case 0x7fff: |
44210111 | 205 | tag = FP_EXP_TAG_SPECIAL; |
1da177e4 LT |
206 | break; |
207 | case 0x0000: | |
3b095a04 CG |
208 | if (!st->significand[0] && |
209 | !st->significand[1] && | |
210 | !st->significand[2] && | |
44210111 RM |
211 | !st->significand[3]) |
212 | tag = FP_EXP_TAG_ZERO; | |
213 | else | |
214 | tag = FP_EXP_TAG_SPECIAL; | |
1da177e4 LT |
215 | break; |
216 | default: | |
44210111 RM |
217 | if (st->significand[3] & 0x8000) |
218 | tag = FP_EXP_TAG_VALID; | |
219 | else | |
220 | tag = FP_EXP_TAG_SPECIAL; | |
1da177e4 LT |
221 | break; |
222 | } | |
223 | } else { | |
44210111 | 224 | tag = FP_EXP_TAG_EMPTY; |
1da177e4 | 225 | } |
44210111 | 226 | ret |= tag << (2 * i); |
1da177e4 LT |
227 | } |
228 | return ret; | |
229 | } | |
230 | ||
231 | /* | |
44210111 | 232 | * FXSR floating point environment conversions. |
1da177e4 LT |
233 | */ |
234 | ||
44210111 RM |
235 | static void convert_from_fxsr(struct user_i387_ia32_struct *env, |
236 | struct task_struct *tsk) | |
1da177e4 | 237 | { |
44210111 RM |
238 | struct i387_fxsave_struct *fxsave = &tsk->thread.i387.fxsave; |
239 | struct _fpreg *to = (struct _fpreg *) &env->st_space[0]; | |
240 | struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0]; | |
241 | int i; | |
1da177e4 | 242 | |
44210111 RM |
243 | env->cwd = fxsave->cwd | 0xffff0000u; |
244 | env->swd = fxsave->swd | 0xffff0000u; | |
245 | env->twd = twd_fxsr_to_i387(fxsave); | |
246 | ||
247 | #ifdef CONFIG_X86_64 | |
248 | env->fip = fxsave->rip; | |
249 | env->foo = fxsave->rdp; | |
250 | if (tsk == current) { | |
251 | /* | |
252 | * should be actually ds/cs at fpu exception time, but | |
253 | * that information is not available in 64bit mode. | |
254 | */ | |
255 | asm("mov %%ds,%0" : "=r" (env->fos)); | |
256 | asm("mov %%cs,%0" : "=r" (env->fcs)); | |
1da177e4 | 257 | } else { |
44210111 RM |
258 | struct pt_regs *regs = task_pt_regs(tsk); |
259 | env->fos = 0xffff0000 | tsk->thread.ds; | |
260 | env->fcs = regs->cs; | |
1da177e4 | 261 | } |
44210111 RM |
262 | #else |
263 | env->fip = fxsave->fip; | |
264 | env->fcs = fxsave->fcs; | |
265 | env->foo = fxsave->foo; | |
266 | env->fos = fxsave->fos; | |
267 | #endif | |
1da177e4 | 268 | |
44210111 RM |
269 | for (i = 0; i < 8; ++i) |
270 | memcpy(&to[i], &from[i], sizeof(to[0])); | |
1da177e4 LT |
271 | } |
272 | ||
44210111 RM |
273 | static void convert_to_fxsr(struct task_struct *tsk, |
274 | const struct user_i387_ia32_struct *env) | |
1da177e4 | 275 | |
1da177e4 | 276 | { |
44210111 RM |
277 | struct i387_fxsave_struct *fxsave = &tsk->thread.i387.fxsave; |
278 | struct _fpreg *from = (struct _fpreg *) &env->st_space[0]; | |
279 | struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0]; | |
280 | int i; | |
1da177e4 | 281 | |
44210111 RM |
282 | fxsave->cwd = env->cwd; |
283 | fxsave->swd = env->swd; | |
284 | fxsave->twd = twd_i387_to_fxsr(env->twd); | |
285 | fxsave->fop = (u16) ((u32) env->fcs >> 16); | |
286 | #ifdef CONFIG_X86_64 | |
287 | fxsave->rip = env->fip; | |
288 | fxsave->rdp = env->foo; | |
289 | /* cs and ds ignored */ | |
290 | #else | |
291 | fxsave->fip = env->fip; | |
292 | fxsave->fcs = (env->fcs & 0xffff); | |
293 | fxsave->foo = env->foo; | |
294 | fxsave->fos = env->fos; | |
295 | #endif | |
1da177e4 | 296 | |
44210111 RM |
297 | for (i = 0; i < 8; ++i) |
298 | memcpy(&to[i], &from[i], sizeof(from[0])); | |
1da177e4 LT |
299 | } |
300 | ||
44210111 RM |
301 | int fpregs_get(struct task_struct *target, const struct user_regset *regset, |
302 | unsigned int pos, unsigned int count, | |
303 | void *kbuf, void __user *ubuf) | |
1da177e4 | 304 | { |
44210111 | 305 | struct user_i387_ia32_struct env; |
1da177e4 | 306 | |
44210111 RM |
307 | if (!HAVE_HWFP) |
308 | return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf); | |
1da177e4 | 309 | |
18a86221 | 310 | init_fpu(target); |
1da177e4 | 311 | |
44210111 RM |
312 | if (!cpu_has_fxsr) |
313 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
314 | &target->thread.i387.fsave, 0, -1); | |
1da177e4 | 315 | |
44210111 RM |
316 | if (kbuf && pos == 0 && count == sizeof(env)) { |
317 | convert_from_fxsr(kbuf, target); | |
318 | return 0; | |
1da177e4 | 319 | } |
44210111 RM |
320 | |
321 | convert_from_fxsr(&env, target); | |
322 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &env, 0, -1); | |
1da177e4 LT |
323 | } |
324 | ||
44210111 RM |
325 | int fpregs_set(struct task_struct *target, const struct user_regset *regset, |
326 | unsigned int pos, unsigned int count, | |
327 | const void *kbuf, const void __user *ubuf) | |
1da177e4 | 328 | { |
44210111 RM |
329 | struct user_i387_ia32_struct env; |
330 | int ret; | |
1da177e4 | 331 | |
44210111 RM |
332 | if (!HAVE_HWFP) |
333 | return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf); | |
1da177e4 | 334 | |
18a86221 | 335 | init_fpu(target); |
44210111 RM |
336 | set_stopped_child_used_math(target); |
337 | ||
338 | if (!cpu_has_fxsr) | |
339 | return user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
340 | &target->thread.i387.fsave, 0, -1); | |
341 | ||
342 | if (pos > 0 || count < sizeof(env)) | |
343 | convert_from_fxsr(&env, target); | |
344 | ||
345 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1); | |
346 | if (!ret) | |
347 | convert_to_fxsr(target, &env); | |
348 | ||
349 | return ret; | |
1da177e4 LT |
350 | } |
351 | ||
352 | /* | |
353 | * Signal frame handlers. | |
354 | */ | |
355 | ||
44210111 | 356 | static inline int save_i387_fsave(struct _fpstate_ia32 __user *buf) |
1da177e4 LT |
357 | { |
358 | struct task_struct *tsk = current; | |
359 | ||
3b095a04 | 360 | unlazy_fpu(tsk); |
1da177e4 | 361 | tsk->thread.i387.fsave.status = tsk->thread.i387.fsave.swd; |
3b095a04 CG |
362 | if (__copy_to_user(buf, &tsk->thread.i387.fsave, |
363 | sizeof(struct i387_fsave_struct))) | |
1da177e4 LT |
364 | return -1; |
365 | return 1; | |
366 | } | |
367 | ||
44210111 | 368 | static int save_i387_fxsave(struct _fpstate_ia32 __user *buf) |
1da177e4 LT |
369 | { |
370 | struct task_struct *tsk = current; | |
44210111 | 371 | struct user_i387_ia32_struct env; |
1da177e4 LT |
372 | int err = 0; |
373 | ||
3b095a04 | 374 | unlazy_fpu(tsk); |
1da177e4 | 375 | |
44210111 RM |
376 | convert_from_fxsr(&env, tsk); |
377 | if (__copy_to_user(buf, &env, sizeof(env))) | |
1da177e4 LT |
378 | return -1; |
379 | ||
3b095a04 CG |
380 | err |= __put_user(tsk->thread.i387.fxsave.swd, &buf->status); |
381 | err |= __put_user(X86_FXSR_MAGIC, &buf->magic); | |
382 | if (err) | |
1da177e4 LT |
383 | return -1; |
384 | ||
3b095a04 CG |
385 | if (__copy_to_user(&buf->_fxsr_env[0], &tsk->thread.i387.fxsave, |
386 | sizeof(struct i387_fxsave_struct))) | |
1da177e4 LT |
387 | return -1; |
388 | return 1; | |
389 | } | |
390 | ||
44210111 | 391 | int save_i387_ia32(struct _fpstate_ia32 __user *buf) |
1da177e4 | 392 | { |
3b095a04 | 393 | if (!used_math()) |
1da177e4 LT |
394 | return 0; |
395 | ||
396 | /* This will cause a "finit" to be triggered by the next | |
397 | * attempted FPU operation by the 'current' process. | |
398 | */ | |
399 | clear_used_math(); | |
400 | ||
3b095a04 CG |
401 | if (HAVE_HWFP) { |
402 | if (cpu_has_fxsr) { | |
403 | return save_i387_fxsave(buf); | |
1da177e4 | 404 | } else { |
3b095a04 | 405 | return save_i387_fsave(buf); |
1da177e4 LT |
406 | } |
407 | } else { | |
44210111 RM |
408 | return fpregs_soft_get(current, NULL, |
409 | 0, sizeof(struct user_i387_ia32_struct), | |
410 | NULL, buf) ? -1 : 1; | |
1da177e4 LT |
411 | } |
412 | } | |
413 | ||
44210111 | 414 | static inline int restore_i387_fsave(struct _fpstate_ia32 __user *buf) |
1da177e4 LT |
415 | { |
416 | struct task_struct *tsk = current; | |
3b095a04 CG |
417 | clear_fpu(tsk); |
418 | return __copy_from_user(&tsk->thread.i387.fsave, buf, | |
419 | sizeof(struct i387_fsave_struct)); | |
1da177e4 LT |
420 | } |
421 | ||
44210111 | 422 | static int restore_i387_fxsave(struct _fpstate_ia32 __user *buf) |
1da177e4 LT |
423 | { |
424 | int err; | |
425 | struct task_struct *tsk = current; | |
44210111 | 426 | struct user_i387_ia32_struct env; |
3b095a04 CG |
427 | clear_fpu(tsk); |
428 | err = __copy_from_user(&tsk->thread.i387.fxsave, &buf->_fxsr_env[0], | |
429 | sizeof(struct i387_fxsave_struct)); | |
1da177e4 LT |
430 | /* mxcsr reserved bits must be masked to zero for security reasons */ |
431 | tsk->thread.i387.fxsave.mxcsr &= mxcsr_feature_mask; | |
44210111 RM |
432 | if (err || __copy_from_user(&env, buf, sizeof(env))) |
433 | return 1; | |
434 | convert_to_fxsr(tsk, &env); | |
435 | return 0; | |
1da177e4 LT |
436 | } |
437 | ||
44210111 | 438 | int restore_i387_ia32(struct _fpstate_ia32 __user *buf) |
1da177e4 LT |
439 | { |
440 | int err; | |
441 | ||
3b095a04 CG |
442 | if (HAVE_HWFP) { |
443 | if (cpu_has_fxsr) { | |
444 | err = restore_i387_fxsave(buf); | |
1da177e4 | 445 | } else { |
3b095a04 | 446 | err = restore_i387_fsave(buf); |
1da177e4 LT |
447 | } |
448 | } else { | |
44210111 RM |
449 | err = fpregs_soft_set(current, NULL, |
450 | 0, sizeof(struct user_i387_ia32_struct), | |
451 | NULL, buf) != 0; | |
1da177e4 LT |
452 | } |
453 | set_used_math(); | |
454 | return err; | |
455 | } | |
456 | ||
1da177e4 LT |
457 | /* |
458 | * FPU state for core dumps. | |
60b3b9af RM |
459 | * This is only used for a.out dumps now. |
460 | * It is declared generically using elf_fpregset_t (which is | |
461 | * struct user_i387_struct) but is in fact only used for 32-bit | |
462 | * dumps, so on 64-bit it is really struct user_i387_ia32_struct. | |
1da177e4 | 463 | */ |
3b095a04 | 464 | int dump_fpu(struct pt_regs *regs, struct user_i387_struct *fpu) |
1da177e4 LT |
465 | { |
466 | int fpvalid; | |
467 | struct task_struct *tsk = current; | |
468 | ||
469 | fpvalid = !!used_math(); | |
60b3b9af RM |
470 | if (fpvalid) |
471 | fpvalid = !fpregs_get(tsk, NULL, | |
472 | 0, sizeof(struct user_i387_ia32_struct), | |
473 | fpu, NULL); | |
1da177e4 LT |
474 | |
475 | return fpvalid; | |
476 | } | |
129f6946 | 477 | EXPORT_SYMBOL(dump_fpu); |
1da177e4 | 478 | |
60b3b9af | 479 | #endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */ |