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Commit | Line | Data |
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8d016ef1 | 1 | /* |
835c34a1 | 2 | * 8253/PIT functions |
8d016ef1 JS |
3 | * |
4 | */ | |
e9e2cdb4 | 5 | #include <linux/clockchips.h> |
18de5bc4 | 6 | #include <linux/interrupt.h> |
c8344bc2 | 7 | #include <linux/spinlock.h> |
8d016ef1 | 8 | #include <linux/jiffies.h> |
8d016ef1 | 9 | #include <linux/module.h> |
08604bd9 | 10 | #include <linux/timex.h> |
c8344bc2 JSR |
11 | #include <linux/delay.h> |
12 | #include <linux/init.h> | |
13 | #include <linux/io.h> | |
8d016ef1 | 14 | |
8d016ef1 | 15 | #include <asm/i8253.h> |
4713e22c | 16 | #include <asm/hpet.h> |
c8344bc2 | 17 | #include <asm/smp.h> |
8d016ef1 | 18 | |
8d016ef1 JS |
19 | DEFINE_SPINLOCK(i8253_lock); |
20 | EXPORT_SYMBOL(i8253_lock); | |
21 | ||
1a0c009a TG |
22 | #ifdef CONFIG_X86_32 |
23 | static void pit_disable_clocksource(void); | |
24 | #else | |
25 | static inline void pit_disable_clocksource(void) { } | |
26 | #endif | |
27 | ||
e9e2cdb4 TG |
28 | /* |
29 | * HPET replaces the PIT, when enabled. So we need to know, which of | |
30 | * the two timers is used | |
31 | */ | |
32 | struct clock_event_device *global_clock_event; | |
33 | ||
34 | /* | |
35 | * Initialize the PIT timer. | |
36 | * | |
37 | * This is also called after resume to bring the PIT into operation again. | |
38 | */ | |
39 | static void init_pit_timer(enum clock_event_mode mode, | |
40 | struct clock_event_device *evt) | |
41 | { | |
5f627f8e | 42 | spin_lock(&i8253_lock); |
e9e2cdb4 | 43 | |
c8344bc2 | 44 | switch (mode) { |
e9e2cdb4 TG |
45 | case CLOCK_EVT_MODE_PERIODIC: |
46 | /* binary, mode 2, LSB/MSB, ch 0 */ | |
466eed22 AC |
47 | outb_pit(0x34, PIT_MODE); |
48 | outb_pit(LATCH & 0xff , PIT_CH0); /* LSB */ | |
49 | outb_pit(LATCH >> 8 , PIT_CH0); /* MSB */ | |
e9e2cdb4 TG |
50 | break; |
51 | ||
e9e2cdb4 TG |
52 | case CLOCK_EVT_MODE_SHUTDOWN: |
53 | case CLOCK_EVT_MODE_UNUSED: | |
7671988b TG |
54 | if (evt->mode == CLOCK_EVT_MODE_PERIODIC || |
55 | evt->mode == CLOCK_EVT_MODE_ONESHOT) { | |
466eed22 AC |
56 | outb_pit(0x30, PIT_MODE); |
57 | outb_pit(0, PIT_CH0); | |
58 | outb_pit(0, PIT_CH0); | |
7671988b | 59 | } |
1a0c009a | 60 | pit_disable_clocksource(); |
18de5bc4 TG |
61 | break; |
62 | ||
6b3964cd | 63 | case CLOCK_EVT_MODE_ONESHOT: |
e9e2cdb4 | 64 | /* One shot setup */ |
1a0c009a | 65 | pit_disable_clocksource(); |
466eed22 | 66 | outb_pit(0x38, PIT_MODE); |
18de5bc4 TG |
67 | break; |
68 | ||
69 | case CLOCK_EVT_MODE_RESUME: | |
70 | /* Nothing to do here */ | |
e9e2cdb4 TG |
71 | break; |
72 | } | |
5f627f8e | 73 | spin_unlock(&i8253_lock); |
e9e2cdb4 TG |
74 | } |
75 | ||
76 | /* | |
77 | * Program the next event in oneshot mode | |
78 | * | |
79 | * Delta is given in PIT ticks | |
80 | */ | |
81 | static int pit_next_event(unsigned long delta, struct clock_event_device *evt) | |
8d016ef1 | 82 | { |
5f627f8e | 83 | spin_lock(&i8253_lock); |
466eed22 AC |
84 | outb_pit(delta & 0xff , PIT_CH0); /* LSB */ |
85 | outb_pit(delta >> 8 , PIT_CH0); /* MSB */ | |
5f627f8e | 86 | spin_unlock(&i8253_lock); |
e9e2cdb4 TG |
87 | |
88 | return 0; | |
89 | } | |
90 | ||
91 | /* | |
92 | * On UP the PIT can serve all of the possible timer functions. On SMP systems | |
93 | * it can be solely used for the global tick. | |
94 | * | |
27b46d76 | 95 | * The profiling and update capabilities are switched off once the local apic is |
e9e2cdb4 TG |
96 | * registered. This mechanism replaces the previous #ifdef LOCAL_APIC - |
97 | * !using_apic_timer decisions in do_timer_interrupt_hook() | |
98 | */ | |
c8344bc2 | 99 | static struct clock_event_device pit_ce = { |
e9e2cdb4 TG |
100 | .name = "pit", |
101 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
102 | .set_mode = init_pit_timer, | |
103 | .set_next_event = pit_next_event, | |
104 | .shift = 32, | |
105 | .irq = 0, | |
106 | }; | |
107 | ||
108 | /* | |
109 | * Initialize the conversion factor and the min/max deltas of the clock event | |
110 | * structure and register the clock event source with the framework. | |
111 | */ | |
112 | void __init setup_pit_timer(void) | |
113 | { | |
114 | /* | |
115 | * Start pit with the boot cpu mask and make it global after the | |
116 | * IO_APIC has been initialized. | |
117 | */ | |
c8344bc2 JSR |
118 | pit_ce.cpumask = cpumask_of(smp_processor_id()); |
119 | pit_ce.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, pit_ce.shift); | |
120 | pit_ce.max_delta_ns = clockevent_delta2ns(0x7FFF, &pit_ce); | |
121 | pit_ce.min_delta_ns = clockevent_delta2ns(0xF, &pit_ce); | |
122 | ||
123 | clockevents_register_device(&pit_ce); | |
124 | global_clock_event = &pit_ce; | |
8d016ef1 | 125 | } |
5d0cf410 | 126 | |
f5e0e93f | 127 | #ifndef CONFIG_X86_64 |
5d0cf410 JS |
128 | /* |
129 | * Since the PIT overflows every tick, its not very useful | |
130 | * to just read by itself. So use jiffies to emulate a free | |
131 | * running counter: | |
132 | */ | |
8e19608e | 133 | static cycle_t pit_read(struct clocksource *cs) |
5d0cf410 | 134 | { |
c8344bc2 JSR |
135 | static int old_count; |
136 | static u32 old_jifs; | |
5d0cf410 JS |
137 | unsigned long flags; |
138 | int count; | |
6415ce9a | 139 | u32 jifs; |
5d0cf410 JS |
140 | |
141 | spin_lock_irqsave(&i8253_lock, flags); | |
e9e2cdb4 | 142 | /* |
6415ce9a JS |
143 | * Although our caller may have the read side of xtime_lock, |
144 | * this is now a seqlock, and we are cheating in this routine | |
145 | * by having side effects on state that we cannot undo if | |
146 | * there is a collision on the seqlock and our caller has to | |
147 | * retry. (Namely, old_jifs and old_count.) So we must treat | |
148 | * jiffies as volatile despite the lock. We read jiffies | |
149 | * before latching the timer count to guarantee that although | |
150 | * the jiffies value might be older than the count (that is, | |
151 | * the counter may underflow between the last point where | |
152 | * jiffies was incremented and the point where we latch the | |
153 | * count), it cannot be newer. | |
154 | */ | |
155 | jifs = jiffies; | |
466eed22 AC |
156 | outb_pit(0x00, PIT_MODE); /* latch the count ASAP */ |
157 | count = inb_pit(PIT_CH0); /* read the latched count */ | |
158 | count |= inb_pit(PIT_CH0) << 8; | |
5d0cf410 JS |
159 | |
160 | /* VIA686a test code... reset the latch if count > max + 1 */ | |
161 | if (count > LATCH) { | |
466eed22 AC |
162 | outb_pit(0x34, PIT_MODE); |
163 | outb_pit(LATCH & 0xff, PIT_CH0); | |
164 | outb_pit(LATCH >> 8, PIT_CH0); | |
5d0cf410 JS |
165 | count = LATCH - 1; |
166 | } | |
5d0cf410 | 167 | |
6415ce9a JS |
168 | /* |
169 | * It's possible for count to appear to go the wrong way for a | |
170 | * couple of reasons: | |
171 | * | |
172 | * 1. The timer counter underflows, but we haven't handled the | |
173 | * resulting interrupt and incremented jiffies yet. | |
174 | * 2. Hardware problem with the timer, not giving us continuous time, | |
175 | * the counter does small "jumps" upwards on some Pentium systems, | |
176 | * (see c't 95/10 page 335 for Neptun bug.) | |
177 | * | |
178 | * Previous attempts to handle these cases intelligently were | |
179 | * buggy, so we just do the simple thing now. | |
180 | */ | |
c8344bc2 | 181 | if (count > old_count && jifs == old_jifs) |
6415ce9a | 182 | count = old_count; |
c8344bc2 | 183 | |
6415ce9a JS |
184 | old_count = count; |
185 | old_jifs = jifs; | |
186 | ||
187 | spin_unlock_irqrestore(&i8253_lock, flags); | |
5d0cf410 | 188 | |
6415ce9a | 189 | count = (LATCH - 1) - count; |
5d0cf410 JS |
190 | |
191 | return (cycle_t)(jifs * LATCH) + count; | |
192 | } | |
193 | ||
c8344bc2 JSR |
194 | static struct clocksource pit_cs = { |
195 | .name = "pit", | |
196 | .rating = 110, | |
197 | .read = pit_read, | |
198 | .mask = CLOCKSOURCE_MASK(32), | |
199 | .mult = 0, | |
200 | .shift = 20, | |
5d0cf410 JS |
201 | }; |
202 | ||
1a0c009a TG |
203 | static void pit_disable_clocksource(void) |
204 | { | |
205 | /* | |
206 | * Use mult to check whether it is registered or not | |
207 | */ | |
c8344bc2 JSR |
208 | if (pit_cs.mult) { |
209 | clocksource_unregister(&pit_cs); | |
210 | pit_cs.mult = 0; | |
1a0c009a TG |
211 | } |
212 | } | |
213 | ||
5d0cf410 JS |
214 | static int __init init_pit_clocksource(void) |
215 | { | |
316da3b3 TG |
216 | /* |
217 | * Several reasons not to register PIT as a clocksource: | |
218 | * | |
219 | * - On SMP PIT does not scale due to i8253_lock | |
220 | * - when HPET is enabled | |
221 | * - when local APIC timer is active (PIT is switched off) | |
222 | */ | |
223 | if (num_possible_cpus() > 1 || is_hpet_enabled() || | |
c8344bc2 | 224 | pit_ce.mode != CLOCK_EVT_MODE_PERIODIC) |
5d0cf410 JS |
225 | return 0; |
226 | ||
c8344bc2 JSR |
227 | pit_cs.mult = clocksource_hz2mult(CLOCK_TICK_RATE, pit_cs.shift); |
228 | ||
229 | return clocksource_register(&pit_cs); | |
5d0cf410 | 230 | } |
6bb74df4 | 231 | arch_initcall(init_pit_clocksource); |
f5e0e93f | 232 | |
c8344bc2 | 233 | #endif /* !CONFIG_X86_64 */ |