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21fd5132 | 1 | #include <linux/linkage.h> |
21fd5132 PM |
2 | #include <linux/errno.h> |
3 | #include <linux/signal.h> | |
4 | #include <linux/sched.h> | |
5 | #include <linux/ioport.h> | |
6 | #include <linux/interrupt.h> | |
21fd5132 | 7 | #include <linux/timex.h> |
21fd5132 PM |
8 | #include <linux/slab.h> |
9 | #include <linux/random.h> | |
10 | #include <linux/init.h> | |
11 | #include <linux/kernel_stat.h> | |
12 | #include <linux/sysdev.h> | |
13 | #include <linux/bitops.h> | |
7bafaf30 JSR |
14 | #include <linux/acpi.h> |
15 | #include <linux/io.h> | |
16 | #include <linux/delay.h> | |
21fd5132 | 17 | |
21fd5132 PM |
18 | #include <asm/atomic.h> |
19 | #include <asm/system.h> | |
21fd5132 | 20 | #include <asm/timer.h> |
21fd5132 | 21 | #include <asm/hw_irq.h> |
21fd5132 | 22 | #include <asm/pgtable.h> |
21fd5132 PM |
23 | #include <asm/desc.h> |
24 | #include <asm/apic.h> | |
21fd5132 PM |
25 | #include <asm/i8259.h> |
26 | ||
27 | /* | |
28 | * This is the 'legacy' 8259A Programmable Interrupt Controller, | |
29 | * present in the majority of PC/AT boxes. | |
30 | * plus some generic x86 specific things if generic specifics makes | |
31 | * any sense at all. | |
32 | */ | |
33 | ||
34 | static int i8259A_auto_eoi; | |
5619c280 | 35 | DEFINE_RAW_SPINLOCK(i8259A_lock); |
21fd5132 | 36 | static void mask_and_ack_8259A(unsigned int); |
b81bb373 JP |
37 | static void mask_8259A(void); |
38 | static void unmask_8259A(void); | |
39 | static void disable_8259A_irq(unsigned int irq); | |
40 | static void enable_8259A_irq(unsigned int irq); | |
41 | static void init_8259A(int auto_eoi); | |
42 | static int i8259A_irq_pending(unsigned int irq); | |
21fd5132 PM |
43 | |
44 | struct irq_chip i8259A_chip = { | |
45 | .name = "XT-PIC", | |
46 | .mask = disable_8259A_irq, | |
47 | .disable = disable_8259A_irq, | |
48 | .unmask = enable_8259A_irq, | |
49 | .mask_ack = mask_and_ack_8259A, | |
50 | }; | |
51 | ||
52 | /* | |
53 | * 8259A PIC functions to handle ISA devices: | |
54 | */ | |
55 | ||
56 | /* | |
57 | * This contains the irq mask for both 8259A irq controllers, | |
58 | */ | |
59 | unsigned int cached_irq_mask = 0xffff; | |
60 | ||
61 | /* | |
62 | * Not all IRQs can be routed through the IO-APIC, eg. on certain (older) | |
63 | * boards the timer interrupt is not really connected to any IO-APIC pin, | |
64 | * it's fed to the master 8259A's IR0 line only. | |
65 | * | |
66 | * Any '1' bit in this mask means the IRQ is routed through the IO-APIC. | |
67 | * this 'mixed mode' IRQ handling costs nothing because it's only used | |
68 | * at IRQ setup time. | |
69 | */ | |
70 | unsigned long io_apic_irqs; | |
71 | ||
b81bb373 | 72 | static void disable_8259A_irq(unsigned int irq) |
21fd5132 PM |
73 | { |
74 | unsigned int mask = 1 << irq; | |
75 | unsigned long flags; | |
76 | ||
5619c280 | 77 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
21fd5132 PM |
78 | cached_irq_mask |= mask; |
79 | if (irq & 8) | |
80 | outb(cached_slave_mask, PIC_SLAVE_IMR); | |
81 | else | |
82 | outb(cached_master_mask, PIC_MASTER_IMR); | |
5619c280 | 83 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
21fd5132 PM |
84 | } |
85 | ||
b81bb373 | 86 | static void enable_8259A_irq(unsigned int irq) |
21fd5132 PM |
87 | { |
88 | unsigned int mask = ~(1 << irq); | |
89 | unsigned long flags; | |
90 | ||
5619c280 | 91 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
21fd5132 PM |
92 | cached_irq_mask &= mask; |
93 | if (irq & 8) | |
94 | outb(cached_slave_mask, PIC_SLAVE_IMR); | |
95 | else | |
96 | outb(cached_master_mask, PIC_MASTER_IMR); | |
5619c280 | 97 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
21fd5132 PM |
98 | } |
99 | ||
b81bb373 | 100 | static int i8259A_irq_pending(unsigned int irq) |
21fd5132 PM |
101 | { |
102 | unsigned int mask = 1<<irq; | |
103 | unsigned long flags; | |
104 | int ret; | |
105 | ||
5619c280 | 106 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
21fd5132 PM |
107 | if (irq < 8) |
108 | ret = inb(PIC_MASTER_CMD) & mask; | |
109 | else | |
110 | ret = inb(PIC_SLAVE_CMD) & (mask >> 8); | |
5619c280 | 111 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
21fd5132 PM |
112 | |
113 | return ret; | |
114 | } | |
115 | ||
b81bb373 | 116 | static void make_8259A_irq(unsigned int irq) |
21fd5132 PM |
117 | { |
118 | disable_irq_nosync(irq); | |
119 | io_apic_irqs &= ~(1<<irq); | |
120 | set_irq_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq, | |
121 | "XT"); | |
122 | enable_irq(irq); | |
123 | } | |
124 | ||
125 | /* | |
126 | * This function assumes to be called rarely. Switching between | |
127 | * 8259A registers is slow. | |
128 | * This has to be protected by the irq controller spinlock | |
129 | * before being called. | |
130 | */ | |
131 | static inline int i8259A_irq_real(unsigned int irq) | |
132 | { | |
133 | int value; | |
134 | int irqmask = 1<<irq; | |
135 | ||
136 | if (irq < 8) { | |
680afbf9 | 137 | outb(0x0B, PIC_MASTER_CMD); /* ISR register */ |
21fd5132 | 138 | value = inb(PIC_MASTER_CMD) & irqmask; |
680afbf9 | 139 | outb(0x0A, PIC_MASTER_CMD); /* back to the IRR register */ |
21fd5132 PM |
140 | return value; |
141 | } | |
680afbf9 | 142 | outb(0x0B, PIC_SLAVE_CMD); /* ISR register */ |
21fd5132 | 143 | value = inb(PIC_SLAVE_CMD) & (irqmask >> 8); |
680afbf9 | 144 | outb(0x0A, PIC_SLAVE_CMD); /* back to the IRR register */ |
21fd5132 PM |
145 | return value; |
146 | } | |
147 | ||
148 | /* | |
149 | * Careful! The 8259A is a fragile beast, it pretty | |
150 | * much _has_ to be done exactly like this (mask it | |
151 | * first, _then_ send the EOI, and the order of EOI | |
152 | * to the two 8259s is important! | |
153 | */ | |
154 | static void mask_and_ack_8259A(unsigned int irq) | |
155 | { | |
156 | unsigned int irqmask = 1 << irq; | |
157 | unsigned long flags; | |
158 | ||
5619c280 | 159 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
21fd5132 PM |
160 | /* |
161 | * Lightweight spurious IRQ detection. We do not want | |
162 | * to overdo spurious IRQ handling - it's usually a sign | |
163 | * of hardware problems, so we only do the checks we can | |
164 | * do without slowing down good hardware unnecessarily. | |
165 | * | |
166 | * Note that IRQ7 and IRQ15 (the two spurious IRQs | |
167 | * usually resulting from the 8259A-1|2 PICs) occur | |
168 | * even if the IRQ is masked in the 8259A. Thus we | |
169 | * can check spurious 8259A IRQs without doing the | |
170 | * quite slow i8259A_irq_real() call for every IRQ. | |
171 | * This does not cover 100% of spurious interrupts, | |
172 | * but should be enough to warn the user that there | |
173 | * is something bad going on ... | |
174 | */ | |
175 | if (cached_irq_mask & irqmask) | |
176 | goto spurious_8259A_irq; | |
177 | cached_irq_mask |= irqmask; | |
178 | ||
179 | handle_real_irq: | |
180 | if (irq & 8) { | |
181 | inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */ | |
182 | outb(cached_slave_mask, PIC_SLAVE_IMR); | |
21fd5132 | 183 | /* 'Specific EOI' to slave */ |
3e8631d2 | 184 | outb(0x60+(irq&7), PIC_SLAVE_CMD); |
21fd5132 | 185 | /* 'Specific EOI' to master-IRQ2 */ |
3e8631d2 | 186 | outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD); |
21fd5132 PM |
187 | } else { |
188 | inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */ | |
189 | outb(cached_master_mask, PIC_MASTER_IMR); | |
3e8631d2 | 190 | outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */ |
21fd5132 | 191 | } |
5619c280 | 192 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
21fd5132 PM |
193 | return; |
194 | ||
195 | spurious_8259A_irq: | |
196 | /* | |
197 | * this is the slow path - should happen rarely. | |
198 | */ | |
199 | if (i8259A_irq_real(irq)) | |
200 | /* | |
201 | * oops, the IRQ _is_ in service according to the | |
202 | * 8259A - not spurious, go handle it. | |
203 | */ | |
204 | goto handle_real_irq; | |
205 | ||
206 | { | |
207 | static int spurious_irq_mask; | |
208 | /* | |
209 | * At this point we can be sure the IRQ is spurious, | |
210 | * lets ACK and report it. [once per IRQ] | |
211 | */ | |
212 | if (!(spurious_irq_mask & irqmask)) { | |
21fd5132 PM |
213 | printk(KERN_DEBUG |
214 | "spurious 8259A interrupt: IRQ%d.\n", irq); | |
21fd5132 PM |
215 | spurious_irq_mask |= irqmask; |
216 | } | |
217 | atomic_inc(&irq_err_count); | |
218 | /* | |
219 | * Theoretically we do not have to handle this IRQ, | |
220 | * but in Linux this does not cause problems and is | |
221 | * simpler for us. | |
222 | */ | |
223 | goto handle_real_irq; | |
224 | } | |
225 | } | |
226 | ||
227 | static char irq_trigger[2]; | |
228 | /** | |
229 | * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ | |
230 | */ | |
231 | static void restore_ELCR(char *trigger) | |
232 | { | |
233 | outb(trigger[0], 0x4d0); | |
234 | outb(trigger[1], 0x4d1); | |
235 | } | |
236 | ||
237 | static void save_ELCR(char *trigger) | |
238 | { | |
239 | /* IRQ 0,1,2,8,13 are marked as reserved */ | |
240 | trigger[0] = inb(0x4d0) & 0xF8; | |
241 | trigger[1] = inb(0x4d1) & 0xDE; | |
242 | } | |
243 | ||
244 | static int i8259A_resume(struct sys_device *dev) | |
245 | { | |
246 | init_8259A(i8259A_auto_eoi); | |
247 | restore_ELCR(irq_trigger); | |
248 | return 0; | |
249 | } | |
250 | ||
251 | static int i8259A_suspend(struct sys_device *dev, pm_message_t state) | |
252 | { | |
253 | save_ELCR(irq_trigger); | |
254 | return 0; | |
255 | } | |
256 | ||
257 | static int i8259A_shutdown(struct sys_device *dev) | |
258 | { | |
259 | /* Put the i8259A into a quiescent state that | |
260 | * the kernel initialization code can get it | |
261 | * out of. | |
262 | */ | |
263 | outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */ | |
264 | outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-1 */ | |
265 | return 0; | |
266 | } | |
267 | ||
268 | static struct sysdev_class i8259_sysdev_class = { | |
269 | .name = "i8259", | |
270 | .suspend = i8259A_suspend, | |
271 | .resume = i8259A_resume, | |
272 | .shutdown = i8259A_shutdown, | |
273 | }; | |
274 | ||
275 | static struct sys_device device_i8259A = { | |
276 | .id = 0, | |
277 | .cls = &i8259_sysdev_class, | |
278 | }; | |
279 | ||
280 | static int __init i8259A_init_sysfs(void) | |
281 | { | |
282 | int error = sysdev_class_register(&i8259_sysdev_class); | |
283 | if (!error) | |
284 | error = sysdev_register(&device_i8259A); | |
285 | return error; | |
286 | } | |
287 | ||
288 | device_initcall(i8259A_init_sysfs); | |
289 | ||
b81bb373 | 290 | static void mask_8259A(void) |
d94d93ca SS |
291 | { |
292 | unsigned long flags; | |
293 | ||
5619c280 | 294 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
d94d93ca SS |
295 | |
296 | outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */ | |
297 | outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */ | |
298 | ||
5619c280 | 299 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
d94d93ca SS |
300 | } |
301 | ||
b81bb373 | 302 | static void unmask_8259A(void) |
d94d93ca SS |
303 | { |
304 | unsigned long flags; | |
305 | ||
5619c280 | 306 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
d94d93ca SS |
307 | |
308 | outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */ | |
309 | outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */ | |
310 | ||
5619c280 | 311 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
d94d93ca SS |
312 | } |
313 | ||
b81bb373 | 314 | static void init_8259A(int auto_eoi) |
21fd5132 PM |
315 | { |
316 | unsigned long flags; | |
317 | ||
318 | i8259A_auto_eoi = auto_eoi; | |
319 | ||
5619c280 | 320 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
21fd5132 PM |
321 | |
322 | outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */ | |
323 | outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */ | |
324 | ||
325 | /* | |
326 | * outb_pic - this has to work on a wide range of PC hardware. | |
327 | */ | |
328 | outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */ | |
c46e62f7 PM |
329 | |
330 | /* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 on x86-64, | |
7bafaf30 | 331 | to 0x20-0x27 on i386 */ |
21fd5132 | 332 | outb_pic(IRQ0_VECTOR, PIC_MASTER_IMR); |
c46e62f7 | 333 | |
21fd5132 | 334 | /* 8259A-1 (the master) has a slave on IR2 */ |
c46e62f7 PM |
335 | outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); |
336 | ||
21fd5132 PM |
337 | if (auto_eoi) /* master does Auto EOI */ |
338 | outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR); | |
339 | else /* master expects normal EOI */ | |
340 | outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR); | |
341 | ||
342 | outb_pic(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */ | |
c46e62f7 PM |
343 | |
344 | /* ICW2: 8259A-2 IR0-7 mapped to IRQ8_VECTOR */ | |
21fd5132 PM |
345 | outb_pic(IRQ8_VECTOR, PIC_SLAVE_IMR); |
346 | /* 8259A-2 is a slave on master's IR2 */ | |
347 | outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR); | |
348 | /* (slave's support for AEOI in flat mode is to be investigated) */ | |
349 | outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); | |
350 | ||
21fd5132 PM |
351 | if (auto_eoi) |
352 | /* | |
353 | * In AEOI mode we just have to mask the interrupt | |
354 | * when acking. | |
355 | */ | |
356 | i8259A_chip.mask_ack = disable_8259A_irq; | |
357 | else | |
358 | i8259A_chip.mask_ack = mask_and_ack_8259A; | |
359 | ||
360 | udelay(100); /* wait for 8259A to initialize */ | |
361 | ||
362 | outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */ | |
363 | outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */ | |
364 | ||
5619c280 | 365 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
21fd5132 | 366 | } |
b81bb373 | 367 | |
ef354866 JP |
368 | /* |
369 | * make i8259 a driver so that we can select pic functions at run time. the goal | |
370 | * is to make x86 binary compatible among pc compatible and non-pc compatible | |
371 | * platforms, such as x86 MID. | |
372 | */ | |
373 | ||
28a3c93d JP |
374 | static void legacy_pic_noop(void) { }; |
375 | static void legacy_pic_uint_noop(unsigned int unused) { }; | |
376 | static void legacy_pic_int_noop(int unused) { }; | |
ef354866 JP |
377 | |
378 | static struct irq_chip dummy_pic_chip = { | |
379 | .name = "dummy pic", | |
380 | .mask = legacy_pic_uint_noop, | |
381 | .unmask = legacy_pic_uint_noop, | |
382 | .disable = legacy_pic_uint_noop, | |
383 | .mask_ack = legacy_pic_uint_noop, | |
384 | }; | |
385 | static int legacy_pic_irq_pending_noop(unsigned int irq) | |
386 | { | |
387 | return 0; | |
388 | } | |
389 | ||
390 | struct legacy_pic null_legacy_pic = { | |
391 | .nr_legacy_irqs = 0, | |
392 | .chip = &dummy_pic_chip, | |
393 | .mask_all = legacy_pic_noop, | |
394 | .restore_mask = legacy_pic_noop, | |
395 | .init = legacy_pic_int_noop, | |
396 | .irq_pending = legacy_pic_irq_pending_noop, | |
397 | .make_irq = legacy_pic_uint_noop, | |
398 | }; | |
399 | ||
400 | struct legacy_pic default_legacy_pic = { | |
401 | .nr_legacy_irqs = NR_IRQS_LEGACY, | |
402 | .chip = &i8259A_chip, | |
403 | .mask_all = mask_8259A, | |
404 | .restore_mask = unmask_8259A, | |
405 | .init = init_8259A, | |
406 | .irq_pending = i8259A_irq_pending, | |
407 | .make_irq = make_8259A_irq, | |
408 | }; | |
409 | ||
410 | struct legacy_pic *legacy_pic = &default_legacy_pic; |