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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo | |
5 | * | |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
1da177e4 LT |
28 | #include <linux/mc146818rtc.h> |
29 | #include <linux/compiler.h> | |
30 | #include <linux/acpi.h> | |
129f6946 | 31 | #include <linux/module.h> |
1da177e4 | 32 | #include <linux/sysdev.h> |
2d3fcc1c | 33 | #include <linux/pci.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
1d16b53e | 38 | #include <linux/jiffies.h> /* time_after() */ |
54d5d424 | 39 | |
1da177e4 LT |
40 | #include <asm/io.h> |
41 | #include <asm/smp.h> | |
42 | #include <asm/desc.h> | |
43 | #include <asm/timer.h> | |
306e440d | 44 | #include <asm/i8259.h> |
3e4ff115 | 45 | #include <asm/nmi.h> |
2d3fcc1c | 46 | #include <asm/msidef.h> |
8b955b0d | 47 | #include <asm/hypertransport.h> |
1da177e4 LT |
48 | |
49 | #include <mach_apic.h> | |
874c4fe3 | 50 | #include <mach_apicdef.h> |
1da177e4 | 51 | |
1da177e4 LT |
52 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
53 | atomic_t irq_mis_count; | |
54 | ||
fcfd636a EB |
55 | /* Where if anywhere is the i8259 connect in external int mode */ |
56 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
57 | ||
1da177e4 | 58 | static DEFINE_SPINLOCK(ioapic_lock); |
0a1ad60d | 59 | static DEFINE_SPINLOCK(vector_lock); |
1da177e4 | 60 | |
f9262c12 | 61 | |
1da177e4 LT |
62 | /* |
63 | * Is the SiS APIC rmw bug present ? | |
64 | * -1 = don't know, 0 = no, 1 = yes | |
65 | */ | |
66 | int sis_apic_bug = -1; | |
67 | ||
68 | /* | |
69 | * # of IRQ routing registers | |
70 | */ | |
71 | int nr_ioapic_registers[MAX_IO_APICS]; | |
72 | ||
9f640ccb AS |
73 | /* I/O APIC entries */ |
74 | struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS]; | |
75 | int nr_ioapics; | |
76 | ||
584f734d AS |
77 | /* MP IRQ source entries */ |
78 | struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; | |
79 | ||
80 | /* # of MP IRQ source entries */ | |
81 | int mp_irq_entries; | |
82 | ||
1a3f239d | 83 | static int disable_timer_pin_1 __initdata; |
66759a01 | 84 | |
1da177e4 LT |
85 | /* |
86 | * Rough estimation of how many shared IRQs there are, can | |
87 | * be changed anytime. | |
88 | */ | |
89 | #define MAX_PLUS_SHARED_IRQS NR_IRQS | |
90 | #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS) | |
91 | ||
92 | /* | |
93 | * This is performance-critical, we want to do it O(1) | |
94 | * | |
95 | * the indexing order of this array favors 1:1 mappings | |
96 | * between pins and IRQs. | |
97 | */ | |
98 | ||
99 | static struct irq_pin_list { | |
100 | int apic, pin, next; | |
101 | } irq_2_pin[PIN_MAP_SIZE]; | |
102 | ||
130fe05d LT |
103 | struct io_apic { |
104 | unsigned int index; | |
105 | unsigned int unused[3]; | |
106 | unsigned int data; | |
107 | }; | |
108 | ||
109 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
110 | { | |
111 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
112 | + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK); | |
113 | } | |
114 | ||
115 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) | |
116 | { | |
117 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
118 | writel(reg, &io_apic->index); | |
119 | return readl(&io_apic->data); | |
120 | } | |
121 | ||
122 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
123 | { | |
124 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
125 | writel(reg, &io_apic->index); | |
126 | writel(value, &io_apic->data); | |
127 | } | |
128 | ||
129 | /* | |
130 | * Re-write a value: to be used for read-modify-write | |
131 | * cycles where the read already set up the index register. | |
132 | * | |
133 | * Older SiS APIC requires we rewrite the index register | |
134 | */ | |
135 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
136 | { | |
cb468984 | 137 | volatile struct io_apic __iomem *io_apic = io_apic_base(apic); |
130fe05d LT |
138 | if (sis_apic_bug) |
139 | writel(reg, &io_apic->index); | |
140 | writel(value, &io_apic->data); | |
141 | } | |
142 | ||
cf4c6a2f AK |
143 | union entry_union { |
144 | struct { u32 w1, w2; }; | |
145 | struct IO_APIC_route_entry entry; | |
146 | }; | |
147 | ||
148 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
149 | { | |
150 | union entry_union eu; | |
151 | unsigned long flags; | |
152 | spin_lock_irqsave(&ioapic_lock, flags); | |
153 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
154 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
155 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
156 | return eu.entry; | |
157 | } | |
158 | ||
f9dadfa7 LT |
159 | /* |
160 | * When we write a new IO APIC routing entry, we need to write the high | |
161 | * word first! If the mask bit in the low word is clear, we will enable | |
162 | * the interrupt, and we need to make sure the entry is fully populated | |
163 | * before that happens. | |
164 | */ | |
d15512f4 AK |
165 | static void |
166 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 167 | { |
cf4c6a2f AK |
168 | union entry_union eu; |
169 | eu.entry = e; | |
f9dadfa7 LT |
170 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
171 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
172 | } |
173 | ||
174 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
175 | { | |
176 | unsigned long flags; | |
177 | spin_lock_irqsave(&ioapic_lock, flags); | |
178 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
179 | spin_unlock_irqrestore(&ioapic_lock, flags); |
180 | } | |
181 | ||
182 | /* | |
183 | * When we mask an IO APIC routing entry, we need to write the low | |
184 | * word first, in order to set the mask bit before we change the | |
185 | * high bits! | |
186 | */ | |
187 | static void ioapic_mask_entry(int apic, int pin) | |
188 | { | |
189 | unsigned long flags; | |
190 | union entry_union eu = { .entry.mask = 1 }; | |
191 | ||
cf4c6a2f AK |
192 | spin_lock_irqsave(&ioapic_lock, flags); |
193 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
194 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
195 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
196 | } | |
197 | ||
1da177e4 LT |
198 | /* |
199 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
200 | * shared ISA-space IRQs, so we have to support them. We are super | |
201 | * fast in the common case, and fast for shared ISA-space IRQs. | |
202 | */ | |
203 | static void add_pin_to_irq(unsigned int irq, int apic, int pin) | |
204 | { | |
205 | static int first_free_entry = NR_IRQS; | |
206 | struct irq_pin_list *entry = irq_2_pin + irq; | |
207 | ||
208 | while (entry->next) | |
209 | entry = irq_2_pin + entry->next; | |
210 | ||
211 | if (entry->pin != -1) { | |
212 | entry->next = first_free_entry; | |
213 | entry = irq_2_pin + entry->next; | |
214 | if (++first_free_entry >= PIN_MAP_SIZE) | |
215 | panic("io_apic.c: whoops"); | |
216 | } | |
217 | entry->apic = apic; | |
218 | entry->pin = pin; | |
219 | } | |
220 | ||
221 | /* | |
222 | * Reroute an IRQ to a different pin. | |
223 | */ | |
224 | static void __init replace_pin_at_irq(unsigned int irq, | |
225 | int oldapic, int oldpin, | |
226 | int newapic, int newpin) | |
227 | { | |
228 | struct irq_pin_list *entry = irq_2_pin + irq; | |
229 | ||
230 | while (1) { | |
231 | if (entry->apic == oldapic && entry->pin == oldpin) { | |
232 | entry->apic = newapic; | |
233 | entry->pin = newpin; | |
234 | } | |
235 | if (!entry->next) | |
236 | break; | |
237 | entry = irq_2_pin + entry->next; | |
238 | } | |
239 | } | |
240 | ||
241 | static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable) | |
242 | { | |
243 | struct irq_pin_list *entry = irq_2_pin + irq; | |
244 | unsigned int pin, reg; | |
245 | ||
246 | for (;;) { | |
247 | pin = entry->pin; | |
248 | if (pin == -1) | |
249 | break; | |
250 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
251 | reg &= ~disable; | |
252 | reg |= enable; | |
253 | io_apic_modify(entry->apic, 0x10 + pin*2, reg); | |
254 | if (!entry->next) | |
255 | break; | |
256 | entry = irq_2_pin + entry->next; | |
257 | } | |
258 | } | |
259 | ||
260 | /* mask = 1 */ | |
261 | static void __mask_IO_APIC_irq (unsigned int irq) | |
262 | { | |
263 | __modify_IO_APIC_irq(irq, 0x00010000, 0); | |
264 | } | |
265 | ||
266 | /* mask = 0 */ | |
267 | static void __unmask_IO_APIC_irq (unsigned int irq) | |
268 | { | |
269 | __modify_IO_APIC_irq(irq, 0, 0x00010000); | |
270 | } | |
271 | ||
272 | /* mask = 1, trigger = 0 */ | |
273 | static void __mask_and_edge_IO_APIC_irq (unsigned int irq) | |
274 | { | |
275 | __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000); | |
276 | } | |
277 | ||
278 | /* mask = 0, trigger = 1 */ | |
279 | static void __unmask_and_level_IO_APIC_irq (unsigned int irq) | |
280 | { | |
281 | __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000); | |
282 | } | |
283 | ||
284 | static void mask_IO_APIC_irq (unsigned int irq) | |
285 | { | |
286 | unsigned long flags; | |
287 | ||
288 | spin_lock_irqsave(&ioapic_lock, flags); | |
289 | __mask_IO_APIC_irq(irq); | |
290 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
291 | } | |
292 | ||
293 | static void unmask_IO_APIC_irq (unsigned int irq) | |
294 | { | |
295 | unsigned long flags; | |
296 | ||
297 | spin_lock_irqsave(&ioapic_lock, flags); | |
298 | __unmask_IO_APIC_irq(irq); | |
299 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
300 | } | |
301 | ||
302 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) | |
303 | { | |
304 | struct IO_APIC_route_entry entry; | |
1da177e4 LT |
305 | |
306 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ | |
cf4c6a2f | 307 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
308 | if (entry.delivery_mode == dest_SMI) |
309 | return; | |
310 | ||
311 | /* | |
312 | * Disable it in the IO-APIC irq-routing table: | |
313 | */ | |
f9dadfa7 | 314 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
315 | } |
316 | ||
317 | static void clear_IO_APIC (void) | |
318 | { | |
319 | int apic, pin; | |
320 | ||
321 | for (apic = 0; apic < nr_ioapics; apic++) | |
322 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
323 | clear_IO_APIC_pin(apic, pin); | |
324 | } | |
325 | ||
54d5d424 | 326 | #ifdef CONFIG_SMP |
1da177e4 LT |
327 | static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask) |
328 | { | |
329 | unsigned long flags; | |
330 | int pin; | |
331 | struct irq_pin_list *entry = irq_2_pin + irq; | |
332 | unsigned int apicid_value; | |
54d5d424 | 333 | cpumask_t tmp; |
1da177e4 | 334 | |
54d5d424 AR |
335 | cpus_and(tmp, cpumask, cpu_online_map); |
336 | if (cpus_empty(tmp)) | |
337 | tmp = TARGET_CPUS; | |
338 | ||
339 | cpus_and(cpumask, tmp, CPU_MASK_ALL); | |
340 | ||
1da177e4 LT |
341 | apicid_value = cpu_mask_to_apicid(cpumask); |
342 | /* Prepare to do the io_apic_write */ | |
343 | apicid_value = apicid_value << 24; | |
344 | spin_lock_irqsave(&ioapic_lock, flags); | |
345 | for (;;) { | |
346 | pin = entry->pin; | |
347 | if (pin == -1) | |
348 | break; | |
349 | io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value); | |
350 | if (!entry->next) | |
351 | break; | |
352 | entry = irq_2_pin + entry->next; | |
353 | } | |
9f0a5ba5 | 354 | irq_desc[irq].affinity = cpumask; |
1da177e4 LT |
355 | spin_unlock_irqrestore(&ioapic_lock, flags); |
356 | } | |
357 | ||
358 | #if defined(CONFIG_IRQBALANCE) | |
359 | # include <asm/processor.h> /* kernel_thread() */ | |
360 | # include <linux/kernel_stat.h> /* kstat */ | |
361 | # include <linux/slab.h> /* kmalloc() */ | |
1d16b53e | 362 | # include <linux/timer.h> |
1da177e4 | 363 | |
1da177e4 | 364 | #define IRQBALANCE_CHECK_ARCH -999 |
1b61b910 ZY |
365 | #define MAX_BALANCED_IRQ_INTERVAL (5*HZ) |
366 | #define MIN_BALANCED_IRQ_INTERVAL (HZ/2) | |
367 | #define BALANCED_IRQ_MORE_DELTA (HZ/10) | |
368 | #define BALANCED_IRQ_LESS_DELTA (HZ) | |
369 | ||
370 | static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH; | |
371 | static int physical_balance __read_mostly; | |
372 | static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL; | |
1da177e4 LT |
373 | |
374 | static struct irq_cpu_info { | |
375 | unsigned long * last_irq; | |
376 | unsigned long * irq_delta; | |
377 | unsigned long irq; | |
378 | } irq_cpu_data[NR_CPUS]; | |
379 | ||
380 | #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq) | |
381 | #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq]) | |
382 | #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq]) | |
383 | ||
384 | #define IDLE_ENOUGH(cpu,now) \ | |
385 | (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1)) | |
386 | ||
387 | #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask) | |
388 | ||
d5a7430d | 389 | #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i))) |
1da177e4 | 390 | |
1b61b910 ZY |
391 | static cpumask_t balance_irq_affinity[NR_IRQS] = { |
392 | [0 ... NR_IRQS-1] = CPU_MASK_ALL | |
393 | }; | |
1da177e4 | 394 | |
1b61b910 ZY |
395 | void set_balance_irq_affinity(unsigned int irq, cpumask_t mask) |
396 | { | |
397 | balance_irq_affinity[irq] = mask; | |
398 | } | |
1da177e4 LT |
399 | |
400 | static unsigned long move(int curr_cpu, cpumask_t allowed_mask, | |
401 | unsigned long now, int direction) | |
402 | { | |
403 | int search_idle = 1; | |
404 | int cpu = curr_cpu; | |
405 | ||
406 | goto inside; | |
407 | ||
408 | do { | |
409 | if (unlikely(cpu == curr_cpu)) | |
410 | search_idle = 0; | |
411 | inside: | |
412 | if (direction == 1) { | |
413 | cpu++; | |
414 | if (cpu >= NR_CPUS) | |
415 | cpu = 0; | |
416 | } else { | |
417 | cpu--; | |
418 | if (cpu == -1) | |
419 | cpu = NR_CPUS-1; | |
420 | } | |
421 | } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) || | |
422 | (search_idle && !IDLE_ENOUGH(cpu,now))); | |
423 | ||
424 | return cpu; | |
425 | } | |
426 | ||
427 | static inline void balance_irq(int cpu, int irq) | |
428 | { | |
429 | unsigned long now = jiffies; | |
430 | cpumask_t allowed_mask; | |
431 | unsigned int new_cpu; | |
432 | ||
433 | if (irqbalance_disabled) | |
434 | return; | |
435 | ||
1b61b910 | 436 | cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]); |
1da177e4 LT |
437 | new_cpu = move(cpu, allowed_mask, now, 1); |
438 | if (cpu != new_cpu) { | |
54d5d424 | 439 | set_pending_irq(irq, cpumask_of_cpu(new_cpu)); |
1da177e4 LT |
440 | } |
441 | } | |
442 | ||
443 | static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold) | |
444 | { | |
445 | int i, j; | |
edc2cbf4 | 446 | |
394e3902 AM |
447 | for_each_online_cpu(i) { |
448 | for (j = 0; j < NR_IRQS; j++) { | |
1da177e4 LT |
449 | if (!irq_desc[j].action) |
450 | continue; | |
451 | /* Is it a significant load ? */ | |
452 | if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) < | |
453 | useful_load_threshold) | |
454 | continue; | |
455 | balance_irq(i, j); | |
456 | } | |
457 | } | |
458 | balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL, | |
459 | balanced_irq_interval - BALANCED_IRQ_LESS_DELTA); | |
460 | return; | |
461 | } | |
462 | ||
463 | static void do_irq_balance(void) | |
464 | { | |
465 | int i, j; | |
466 | unsigned long max_cpu_irq = 0, min_cpu_irq = (~0); | |
467 | unsigned long move_this_load = 0; | |
468 | int max_loaded = 0, min_loaded = 0; | |
469 | int load; | |
470 | unsigned long useful_load_threshold = balanced_irq_interval + 10; | |
471 | int selected_irq; | |
472 | int tmp_loaded, first_attempt = 1; | |
473 | unsigned long tmp_cpu_irq; | |
474 | unsigned long imbalance = 0; | |
475 | cpumask_t allowed_mask, target_cpu_mask, tmp; | |
476 | ||
c8912599 | 477 | for_each_possible_cpu(i) { |
1da177e4 LT |
478 | int package_index; |
479 | CPU_IRQ(i) = 0; | |
480 | if (!cpu_online(i)) | |
481 | continue; | |
482 | package_index = CPU_TO_PACKAGEINDEX(i); | |
483 | for (j = 0; j < NR_IRQS; j++) { | |
484 | unsigned long value_now, delta; | |
950f4427 TG |
485 | /* Is this an active IRQ or balancing disabled ? */ |
486 | if (!irq_desc[j].action || irq_balancing_disabled(j)) | |
1da177e4 LT |
487 | continue; |
488 | if ( package_index == i ) | |
489 | IRQ_DELTA(package_index,j) = 0; | |
490 | /* Determine the total count per processor per IRQ */ | |
491 | value_now = (unsigned long) kstat_cpu(i).irqs[j]; | |
492 | ||
493 | /* Determine the activity per processor per IRQ */ | |
494 | delta = value_now - LAST_CPU_IRQ(i,j); | |
495 | ||
496 | /* Update last_cpu_irq[][] for the next time */ | |
497 | LAST_CPU_IRQ(i,j) = value_now; | |
498 | ||
499 | /* Ignore IRQs whose rate is less than the clock */ | |
500 | if (delta < useful_load_threshold) | |
501 | continue; | |
502 | /* update the load for the processor or package total */ | |
503 | IRQ_DELTA(package_index,j) += delta; | |
504 | ||
505 | /* Keep track of the higher numbered sibling as well */ | |
506 | if (i != package_index) | |
507 | CPU_IRQ(i) += delta; | |
508 | /* | |
509 | * We have sibling A and sibling B in the package | |
510 | * | |
511 | * cpu_irq[A] = load for cpu A + load for cpu B | |
512 | * cpu_irq[B] = load for cpu B | |
513 | */ | |
514 | CPU_IRQ(package_index) += delta; | |
515 | } | |
516 | } | |
517 | /* Find the least loaded processor package */ | |
394e3902 | 518 | for_each_online_cpu(i) { |
1da177e4 LT |
519 | if (i != CPU_TO_PACKAGEINDEX(i)) |
520 | continue; | |
521 | if (min_cpu_irq > CPU_IRQ(i)) { | |
522 | min_cpu_irq = CPU_IRQ(i); | |
523 | min_loaded = i; | |
524 | } | |
525 | } | |
526 | max_cpu_irq = ULONG_MAX; | |
527 | ||
528 | tryanothercpu: | |
529 | /* Look for heaviest loaded processor. | |
530 | * We may come back to get the next heaviest loaded processor. | |
531 | * Skip processors with trivial loads. | |
532 | */ | |
533 | tmp_cpu_irq = 0; | |
534 | tmp_loaded = -1; | |
394e3902 | 535 | for_each_online_cpu(i) { |
1da177e4 LT |
536 | if (i != CPU_TO_PACKAGEINDEX(i)) |
537 | continue; | |
538 | if (max_cpu_irq <= CPU_IRQ(i)) | |
539 | continue; | |
540 | if (tmp_cpu_irq < CPU_IRQ(i)) { | |
541 | tmp_cpu_irq = CPU_IRQ(i); | |
542 | tmp_loaded = i; | |
543 | } | |
544 | } | |
545 | ||
546 | if (tmp_loaded == -1) { | |
547 | /* In the case of small number of heavy interrupt sources, | |
548 | * loading some of the cpus too much. We use Ingo's original | |
549 | * approach to rotate them around. | |
550 | */ | |
551 | if (!first_attempt && imbalance >= useful_load_threshold) { | |
552 | rotate_irqs_among_cpus(useful_load_threshold); | |
553 | return; | |
554 | } | |
555 | goto not_worth_the_effort; | |
556 | } | |
557 | ||
558 | first_attempt = 0; /* heaviest search */ | |
559 | max_cpu_irq = tmp_cpu_irq; /* load */ | |
560 | max_loaded = tmp_loaded; /* processor */ | |
561 | imbalance = (max_cpu_irq - min_cpu_irq) / 2; | |
562 | ||
1da177e4 LT |
563 | /* if imbalance is less than approx 10% of max load, then |
564 | * observe diminishing returns action. - quit | |
565 | */ | |
edc2cbf4 | 566 | if (imbalance < (max_cpu_irq >> 3)) |
1da177e4 | 567 | goto not_worth_the_effort; |
1da177e4 LT |
568 | |
569 | tryanotherirq: | |
570 | /* if we select an IRQ to move that can't go where we want, then | |
571 | * see if there is another one to try. | |
572 | */ | |
573 | move_this_load = 0; | |
574 | selected_irq = -1; | |
575 | for (j = 0; j < NR_IRQS; j++) { | |
576 | /* Is this an active IRQ? */ | |
577 | if (!irq_desc[j].action) | |
578 | continue; | |
579 | if (imbalance <= IRQ_DELTA(max_loaded,j)) | |
580 | continue; | |
581 | /* Try to find the IRQ that is closest to the imbalance | |
582 | * without going over. | |
583 | */ | |
584 | if (move_this_load < IRQ_DELTA(max_loaded,j)) { | |
585 | move_this_load = IRQ_DELTA(max_loaded,j); | |
586 | selected_irq = j; | |
587 | } | |
588 | } | |
589 | if (selected_irq == -1) { | |
590 | goto tryanothercpu; | |
591 | } | |
592 | ||
593 | imbalance = move_this_load; | |
594 | ||
27b46d76 | 595 | /* For physical_balance case, we accumulated both load |
1da177e4 LT |
596 | * values in the one of the siblings cpu_irq[], |
597 | * to use the same code for physical and logical processors | |
598 | * as much as possible. | |
599 | * | |
600 | * NOTE: the cpu_irq[] array holds the sum of the load for | |
601 | * sibling A and sibling B in the slot for the lowest numbered | |
602 | * sibling (A), _AND_ the load for sibling B in the slot for | |
603 | * the higher numbered sibling. | |
604 | * | |
605 | * We seek the least loaded sibling by making the comparison | |
606 | * (A+B)/2 vs B | |
607 | */ | |
608 | load = CPU_IRQ(min_loaded) >> 1; | |
d5a7430d | 609 | for_each_cpu_mask(j, per_cpu(cpu_sibling_map, min_loaded)) { |
1da177e4 LT |
610 | if (load > CPU_IRQ(j)) { |
611 | /* This won't change cpu_sibling_map[min_loaded] */ | |
612 | load = CPU_IRQ(j); | |
613 | min_loaded = j; | |
614 | } | |
615 | } | |
616 | ||
1b61b910 ZY |
617 | cpus_and(allowed_mask, |
618 | cpu_online_map, | |
619 | balance_irq_affinity[selected_irq]); | |
1da177e4 LT |
620 | target_cpu_mask = cpumask_of_cpu(min_loaded); |
621 | cpus_and(tmp, target_cpu_mask, allowed_mask); | |
622 | ||
623 | if (!cpus_empty(tmp)) { | |
1da177e4 | 624 | /* mark for change destination */ |
54d5d424 AR |
625 | set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded)); |
626 | ||
1da177e4 LT |
627 | /* Since we made a change, come back sooner to |
628 | * check for more variation. | |
629 | */ | |
630 | balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL, | |
631 | balanced_irq_interval - BALANCED_IRQ_LESS_DELTA); | |
632 | return; | |
633 | } | |
634 | goto tryanotherirq; | |
635 | ||
636 | not_worth_the_effort: | |
637 | /* | |
638 | * if we did not find an IRQ to move, then adjust the time interval | |
639 | * upward | |
640 | */ | |
641 | balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL, | |
642 | balanced_irq_interval + BALANCED_IRQ_MORE_DELTA); | |
1da177e4 LT |
643 | return; |
644 | } | |
645 | ||
646 | static int balanced_irq(void *unused) | |
647 | { | |
648 | int i; | |
649 | unsigned long prev_balance_time = jiffies; | |
650 | long time_remaining = balanced_irq_interval; | |
651 | ||
1da177e4 LT |
652 | /* push everything to CPU 0 to give us a starting point. */ |
653 | for (i = 0 ; i < NR_IRQS ; i++) { | |
cd916d31 | 654 | irq_desc[i].pending_mask = cpumask_of_cpu(0); |
54d5d424 | 655 | set_pending_irq(i, cpumask_of_cpu(0)); |
1da177e4 LT |
656 | } |
657 | ||
83144186 | 658 | set_freezable(); |
1da177e4 | 659 | for ( ; ; ) { |
52e6e630 | 660 | time_remaining = schedule_timeout_interruptible(time_remaining); |
3e1d1d28 | 661 | try_to_freeze(); |
1da177e4 LT |
662 | if (time_after(jiffies, |
663 | prev_balance_time+balanced_irq_interval)) { | |
f3705136 | 664 | preempt_disable(); |
1da177e4 LT |
665 | do_irq_balance(); |
666 | prev_balance_time = jiffies; | |
667 | time_remaining = balanced_irq_interval; | |
f3705136 | 668 | preempt_enable(); |
1da177e4 LT |
669 | } |
670 | } | |
671 | return 0; | |
672 | } | |
673 | ||
674 | static int __init balanced_irq_init(void) | |
675 | { | |
676 | int i; | |
677 | struct cpuinfo_x86 *c; | |
678 | cpumask_t tmp; | |
679 | ||
680 | cpus_shift_right(tmp, cpu_online_map, 2); | |
681 | c = &boot_cpu_data; | |
682 | /* When not overwritten by the command line ask subarchitecture. */ | |
683 | if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH) | |
684 | irqbalance_disabled = NO_BALANCE_IRQ; | |
685 | if (irqbalance_disabled) | |
686 | return 0; | |
687 | ||
688 | /* disable irqbalance completely if there is only one processor online */ | |
689 | if (num_online_cpus() < 2) { | |
690 | irqbalance_disabled = 1; | |
691 | return 0; | |
692 | } | |
693 | /* | |
694 | * Enable physical balance only if more than 1 physical processor | |
695 | * is present | |
696 | */ | |
697 | if (smp_num_siblings > 1 && !cpus_empty(tmp)) | |
698 | physical_balance = 1; | |
699 | ||
394e3902 | 700 | for_each_online_cpu(i) { |
1da177e4 LT |
701 | irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL); |
702 | irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL); | |
703 | if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) { | |
704 | printk(KERN_ERR "balanced_irq_init: out of memory"); | |
705 | goto failed; | |
706 | } | |
707 | memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS); | |
708 | memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS); | |
709 | } | |
710 | ||
711 | printk(KERN_INFO "Starting balanced_irq\n"); | |
f26d6a2b | 712 | if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd"))) |
1da177e4 | 713 | return 0; |
f26d6a2b | 714 | printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq"); |
1da177e4 | 715 | failed: |
c8912599 | 716 | for_each_possible_cpu(i) { |
4ae6673e | 717 | kfree(irq_cpu_data[i].irq_delta); |
394e3902 | 718 | irq_cpu_data[i].irq_delta = NULL; |
4ae6673e | 719 | kfree(irq_cpu_data[i].last_irq); |
394e3902 | 720 | irq_cpu_data[i].last_irq = NULL; |
1da177e4 LT |
721 | } |
722 | return 0; | |
723 | } | |
724 | ||
c2481cc4 | 725 | int __devinit irqbalance_disable(char *str) |
1da177e4 LT |
726 | { |
727 | irqbalance_disabled = 1; | |
9b41046c | 728 | return 1; |
1da177e4 LT |
729 | } |
730 | ||
731 | __setup("noirqbalance", irqbalance_disable); | |
732 | ||
1da177e4 | 733 | late_initcall(balanced_irq_init); |
1da177e4 | 734 | #endif /* CONFIG_IRQBALANCE */ |
54d5d424 | 735 | #endif /* CONFIG_SMP */ |
1da177e4 LT |
736 | |
737 | #ifndef CONFIG_SMP | |
75604d7f | 738 | void send_IPI_self(int vector) |
1da177e4 LT |
739 | { |
740 | unsigned int cfg; | |
741 | ||
742 | /* | |
743 | * Wait for idle. | |
744 | */ | |
745 | apic_wait_icr_idle(); | |
746 | cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL; | |
747 | /* | |
748 | * Send the IPI. The write to APIC_ICR fires this off. | |
749 | */ | |
750 | apic_write_around(APIC_ICR, cfg); | |
751 | } | |
752 | #endif /* !CONFIG_SMP */ | |
753 | ||
754 | ||
755 | /* | |
756 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
757 | * specific CPU-side IRQs. | |
758 | */ | |
759 | ||
760 | #define MAX_PIRQS 8 | |
761 | static int pirq_entries [MAX_PIRQS]; | |
762 | static int pirqs_enabled; | |
763 | int skip_ioapic_setup; | |
764 | ||
1da177e4 LT |
765 | static int __init ioapic_pirq_setup(char *str) |
766 | { | |
767 | int i, max; | |
768 | int ints[MAX_PIRQS+1]; | |
769 | ||
770 | get_options(str, ARRAY_SIZE(ints), ints); | |
771 | ||
772 | for (i = 0; i < MAX_PIRQS; i++) | |
773 | pirq_entries[i] = -1; | |
774 | ||
775 | pirqs_enabled = 1; | |
776 | apic_printk(APIC_VERBOSE, KERN_INFO | |
777 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
778 | max = MAX_PIRQS; | |
779 | if (ints[0] < MAX_PIRQS) | |
780 | max = ints[0]; | |
781 | ||
782 | for (i = 0; i < max; i++) { | |
783 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
784 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
785 | /* | |
786 | * PIRQs are mapped upside down, usually. | |
787 | */ | |
788 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
789 | } | |
790 | return 1; | |
791 | } | |
792 | ||
793 | __setup("pirq=", ioapic_pirq_setup); | |
794 | ||
795 | /* | |
796 | * Find the IRQ entry number of a certain pin. | |
797 | */ | |
798 | static int find_irq_entry(int apic, int pin, int type) | |
799 | { | |
800 | int i; | |
801 | ||
802 | for (i = 0; i < mp_irq_entries; i++) | |
803 | if (mp_irqs[i].mpc_irqtype == type && | |
804 | (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid || | |
805 | mp_irqs[i].mpc_dstapic == MP_APIC_ALL) && | |
806 | mp_irqs[i].mpc_dstirq == pin) | |
807 | return i; | |
808 | ||
809 | return -1; | |
810 | } | |
811 | ||
812 | /* | |
813 | * Find the pin to which IRQ[irq] (ISA) is connected | |
814 | */ | |
fcfd636a | 815 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
816 | { |
817 | int i; | |
818 | ||
819 | for (i = 0; i < mp_irq_entries; i++) { | |
820 | int lbus = mp_irqs[i].mpc_srcbus; | |
821 | ||
d27e2b8e | 822 | if (test_bit(lbus, mp_bus_not_pci) && |
1da177e4 LT |
823 | (mp_irqs[i].mpc_irqtype == type) && |
824 | (mp_irqs[i].mpc_srcbusirq == irq)) | |
825 | ||
826 | return mp_irqs[i].mpc_dstirq; | |
827 | } | |
828 | return -1; | |
829 | } | |
830 | ||
fcfd636a EB |
831 | static int __init find_isa_irq_apic(int irq, int type) |
832 | { | |
833 | int i; | |
834 | ||
835 | for (i = 0; i < mp_irq_entries; i++) { | |
836 | int lbus = mp_irqs[i].mpc_srcbus; | |
837 | ||
73b2961b | 838 | if (test_bit(lbus, mp_bus_not_pci) && |
fcfd636a EB |
839 | (mp_irqs[i].mpc_irqtype == type) && |
840 | (mp_irqs[i].mpc_srcbusirq == irq)) | |
841 | break; | |
842 | } | |
843 | if (i < mp_irq_entries) { | |
844 | int apic; | |
845 | for(apic = 0; apic < nr_ioapics; apic++) { | |
846 | if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic) | |
847 | return apic; | |
848 | } | |
849 | } | |
850 | ||
851 | return -1; | |
852 | } | |
853 | ||
1da177e4 LT |
854 | /* |
855 | * Find a specific PCI IRQ entry. | |
856 | * Not an __init, possibly needed by modules | |
857 | */ | |
858 | static int pin_2_irq(int idx, int apic, int pin); | |
859 | ||
860 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
861 | { | |
862 | int apic, i, best_guess = -1; | |
863 | ||
864 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, " | |
865 | "slot:%d, pin:%d.\n", bus, slot, pin); | |
866 | if (mp_bus_id_to_pci_bus[bus] == -1) { | |
867 | printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
868 | return -1; | |
869 | } | |
870 | for (i = 0; i < mp_irq_entries; i++) { | |
871 | int lbus = mp_irqs[i].mpc_srcbus; | |
872 | ||
873 | for (apic = 0; apic < nr_ioapics; apic++) | |
874 | if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic || | |
875 | mp_irqs[i].mpc_dstapic == MP_APIC_ALL) | |
876 | break; | |
877 | ||
47cab822 | 878 | if (!test_bit(lbus, mp_bus_not_pci) && |
1da177e4 LT |
879 | !mp_irqs[i].mpc_irqtype && |
880 | (bus == lbus) && | |
881 | (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) { | |
882 | int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq); | |
883 | ||
884 | if (!(apic || IO_APIC_IRQ(irq))) | |
885 | continue; | |
886 | ||
887 | if (pin == (mp_irqs[i].mpc_srcbusirq & 3)) | |
888 | return irq; | |
889 | /* | |
890 | * Use the first all-but-pin matching entry as a | |
891 | * best-guess fuzzy result for broken mptables. | |
892 | */ | |
893 | if (best_guess < 0) | |
894 | best_guess = irq; | |
895 | } | |
896 | } | |
897 | return best_guess; | |
898 | } | |
129f6946 | 899 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); |
1da177e4 LT |
900 | |
901 | /* | |
902 | * This function currently is only a helper for the i386 smp boot process where | |
903 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
904 | * so mask in all cases should simply be TARGET_CPUS | |
905 | */ | |
54d5d424 | 906 | #ifdef CONFIG_SMP |
1da177e4 LT |
907 | void __init setup_ioapic_dest(void) |
908 | { | |
909 | int pin, ioapic, irq, irq_entry; | |
910 | ||
911 | if (skip_ioapic_setup == 1) | |
912 | return; | |
913 | ||
914 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
915 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
916 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
917 | if (irq_entry == -1) | |
918 | continue; | |
919 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
920 | set_ioapic_affinity_irq(irq, TARGET_CPUS); | |
921 | } | |
922 | ||
923 | } | |
924 | } | |
54d5d424 | 925 | #endif |
1da177e4 | 926 | |
c0a282c2 | 927 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
928 | /* |
929 | * EISA Edge/Level control register, ELCR | |
930 | */ | |
931 | static int EISA_ELCR(unsigned int irq) | |
932 | { | |
933 | if (irq < 16) { | |
934 | unsigned int port = 0x4d0 + (irq >> 3); | |
935 | return (inb(port) >> (irq & 7)) & 1; | |
936 | } | |
937 | apic_printk(APIC_VERBOSE, KERN_INFO | |
938 | "Broken MPtable reports ISA irq %d\n", irq); | |
939 | return 0; | |
940 | } | |
c0a282c2 | 941 | #endif |
1da177e4 | 942 | |
6728801d AS |
943 | /* ISA interrupts are always polarity zero edge triggered, |
944 | * when listed as conforming in the MP table. */ | |
945 | ||
946 | #define default_ISA_trigger(idx) (0) | |
947 | #define default_ISA_polarity(idx) (0) | |
948 | ||
1da177e4 LT |
949 | /* EISA interrupts are always polarity zero and can be edge or level |
950 | * trigger depending on the ELCR value. If an interrupt is listed as | |
951 | * EISA conforming in the MP table, that means its trigger type must | |
952 | * be read in from the ELCR */ | |
953 | ||
954 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq)) | |
6728801d | 955 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
956 | |
957 | /* PCI interrupts are always polarity one level triggered, | |
958 | * when listed as conforming in the MP table. */ | |
959 | ||
960 | #define default_PCI_trigger(idx) (1) | |
961 | #define default_PCI_polarity(idx) (1) | |
962 | ||
963 | /* MCA interrupts are always polarity zero level triggered, | |
964 | * when listed as conforming in the MP table. */ | |
965 | ||
966 | #define default_MCA_trigger(idx) (1) | |
6728801d | 967 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 968 | |
61fd47e0 | 969 | static int MPBIOS_polarity(int idx) |
1da177e4 LT |
970 | { |
971 | int bus = mp_irqs[idx].mpc_srcbus; | |
972 | int polarity; | |
973 | ||
974 | /* | |
975 | * Determine IRQ line polarity (high active or low active): | |
976 | */ | |
977 | switch (mp_irqs[idx].mpc_irqflag & 3) | |
978 | { | |
979 | case 0: /* conforms, ie. bus-type dependent polarity */ | |
980 | { | |
6728801d AS |
981 | polarity = test_bit(bus, mp_bus_not_pci)? |
982 | default_ISA_polarity(idx): | |
983 | default_PCI_polarity(idx); | |
1da177e4 LT |
984 | break; |
985 | } | |
986 | case 1: /* high active */ | |
987 | { | |
988 | polarity = 0; | |
989 | break; | |
990 | } | |
991 | case 2: /* reserved */ | |
992 | { | |
993 | printk(KERN_WARNING "broken BIOS!!\n"); | |
994 | polarity = 1; | |
995 | break; | |
996 | } | |
997 | case 3: /* low active */ | |
998 | { | |
999 | polarity = 1; | |
1000 | break; | |
1001 | } | |
1002 | default: /* invalid */ | |
1003 | { | |
1004 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1005 | polarity = 1; | |
1006 | break; | |
1007 | } | |
1008 | } | |
1009 | return polarity; | |
1010 | } | |
1011 | ||
1012 | static int MPBIOS_trigger(int idx) | |
1013 | { | |
1014 | int bus = mp_irqs[idx].mpc_srcbus; | |
1015 | int trigger; | |
1016 | ||
1017 | /* | |
1018 | * Determine IRQ trigger mode (edge or level sensitive): | |
1019 | */ | |
1020 | switch ((mp_irqs[idx].mpc_irqflag>>2) & 3) | |
1021 | { | |
1022 | case 0: /* conforms, ie. bus-type dependent */ | |
1023 | { | |
9c0076cb AS |
1024 | trigger = test_bit(bus, mp_bus_not_pci)? |
1025 | default_ISA_trigger(idx): | |
1026 | default_PCI_trigger(idx); | |
c0a282c2 | 1027 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
1028 | switch (mp_bus_id_to_type[bus]) |
1029 | { | |
1030 | case MP_BUS_ISA: /* ISA pin */ | |
1031 | { | |
9c0076cb | 1032 | /* set before the switch */ |
1da177e4 LT |
1033 | break; |
1034 | } | |
1035 | case MP_BUS_EISA: /* EISA pin */ | |
1036 | { | |
1037 | trigger = default_EISA_trigger(idx); | |
1038 | break; | |
1039 | } | |
1040 | case MP_BUS_PCI: /* PCI pin */ | |
1041 | { | |
9c0076cb | 1042 | /* set before the switch */ |
1da177e4 LT |
1043 | break; |
1044 | } | |
1045 | case MP_BUS_MCA: /* MCA pin */ | |
1046 | { | |
1047 | trigger = default_MCA_trigger(idx); | |
1048 | break; | |
1049 | } | |
1da177e4 LT |
1050 | default: |
1051 | { | |
1052 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1053 | trigger = 1; | |
1054 | break; | |
1055 | } | |
1056 | } | |
c0a282c2 | 1057 | #endif |
1da177e4 LT |
1058 | break; |
1059 | } | |
1060 | case 1: /* edge */ | |
1061 | { | |
1062 | trigger = 0; | |
1063 | break; | |
1064 | } | |
1065 | case 2: /* reserved */ | |
1066 | { | |
1067 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1068 | trigger = 1; | |
1069 | break; | |
1070 | } | |
1071 | case 3: /* level */ | |
1072 | { | |
1073 | trigger = 1; | |
1074 | break; | |
1075 | } | |
1076 | default: /* invalid */ | |
1077 | { | |
1078 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1079 | trigger = 0; | |
1080 | break; | |
1081 | } | |
1082 | } | |
1083 | return trigger; | |
1084 | } | |
1085 | ||
1086 | static inline int irq_polarity(int idx) | |
1087 | { | |
1088 | return MPBIOS_polarity(idx); | |
1089 | } | |
1090 | ||
1091 | static inline int irq_trigger(int idx) | |
1092 | { | |
1093 | return MPBIOS_trigger(idx); | |
1094 | } | |
1095 | ||
1096 | static int pin_2_irq(int idx, int apic, int pin) | |
1097 | { | |
1098 | int irq, i; | |
1099 | int bus = mp_irqs[idx].mpc_srcbus; | |
1100 | ||
1101 | /* | |
1102 | * Debugging check, we are in big trouble if this message pops up! | |
1103 | */ | |
1104 | if (mp_irqs[idx].mpc_dstirq != pin) | |
1105 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); | |
1106 | ||
643befed AS |
1107 | if (test_bit(bus, mp_bus_not_pci)) |
1108 | irq = mp_irqs[idx].mpc_srcbusirq; | |
1109 | else { | |
1110 | /* | |
1111 | * PCI IRQs are mapped in order | |
1112 | */ | |
1113 | i = irq = 0; | |
1114 | while (i < apic) | |
1115 | irq += nr_ioapic_registers[i++]; | |
1116 | irq += pin; | |
1da177e4 | 1117 | |
643befed AS |
1118 | /* |
1119 | * For MPS mode, so far only needed by ES7000 platform | |
1120 | */ | |
1121 | if (ioapic_renumber_irq) | |
1122 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1123 | } |
1124 | ||
1125 | /* | |
1126 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1127 | */ | |
1128 | if ((pin >= 16) && (pin <= 23)) { | |
1129 | if (pirq_entries[pin-16] != -1) { | |
1130 | if (!pirq_entries[pin-16]) { | |
1131 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1132 | "disabling PIRQ%d\n", pin-16); | |
1133 | } else { | |
1134 | irq = pirq_entries[pin-16]; | |
1135 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1136 | "using PIRQ%d -> IRQ %d\n", | |
1137 | pin-16, irq); | |
1138 | } | |
1139 | } | |
1140 | } | |
1141 | return irq; | |
1142 | } | |
1143 | ||
1144 | static inline int IO_APIC_irq_trigger(int irq) | |
1145 | { | |
1146 | int apic, idx, pin; | |
1147 | ||
1148 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1149 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1150 | idx = find_irq_entry(apic,pin,mp_INT); | |
1151 | if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin))) | |
1152 | return irq_trigger(idx); | |
1153 | } | |
1154 | } | |
1155 | /* | |
1156 | * nonexistent IRQs are edge default | |
1157 | */ | |
1158 | return 0; | |
1159 | } | |
1160 | ||
1161 | /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */ | |
7e95b593 | 1162 | static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 }; |
1da177e4 | 1163 | |
ace80ab7 | 1164 | static int __assign_irq_vector(int irq) |
1da177e4 | 1165 | { |
8339f000 | 1166 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; |
dbeb2be2 | 1167 | int vector, offset; |
1da177e4 | 1168 | |
ace80ab7 | 1169 | BUG_ON((unsigned)irq >= NR_IRQ_VECTORS); |
0a1ad60d | 1170 | |
b940d22d EB |
1171 | if (irq_vector[irq] > 0) |
1172 | return irq_vector[irq]; | |
ace80ab7 | 1173 | |
0a1ad60d | 1174 | vector = current_vector; |
8339f000 EB |
1175 | offset = current_offset; |
1176 | next: | |
1177 | vector += 8; | |
1178 | if (vector >= FIRST_SYSTEM_VECTOR) { | |
1179 | offset = (offset + 1) % 8; | |
1180 | vector = FIRST_DEVICE_VECTOR + offset; | |
1181 | } | |
1182 | if (vector == current_vector) | |
1183 | return -ENOSPC; | |
dbeb2be2 | 1184 | if (test_and_set_bit(vector, used_vectors)) |
8339f000 | 1185 | goto next; |
8339f000 EB |
1186 | |
1187 | current_vector = vector; | |
1188 | current_offset = offset; | |
b940d22d | 1189 | irq_vector[irq] = vector; |
ace80ab7 EB |
1190 | |
1191 | return vector; | |
1192 | } | |
0a1ad60d | 1193 | |
ace80ab7 EB |
1194 | static int assign_irq_vector(int irq) |
1195 | { | |
1196 | unsigned long flags; | |
1197 | int vector; | |
1198 | ||
1199 | spin_lock_irqsave(&vector_lock, flags); | |
1200 | vector = __assign_irq_vector(irq); | |
26a3c49c | 1201 | spin_unlock_irqrestore(&vector_lock, flags); |
1da177e4 | 1202 | |
0a1ad60d | 1203 | return vector; |
1da177e4 | 1204 | } |
f5b9ed7a | 1205 | static struct irq_chip ioapic_chip; |
1da177e4 LT |
1206 | |
1207 | #define IOAPIC_AUTO -1 | |
1208 | #define IOAPIC_EDGE 0 | |
1209 | #define IOAPIC_LEVEL 1 | |
1210 | ||
d1bef4ed | 1211 | static void ioapic_register_intr(int irq, int vector, unsigned long trigger) |
1da177e4 | 1212 | { |
6ebcc00e | 1213 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
cc75b92d TG |
1214 | trigger == IOAPIC_LEVEL) { |
1215 | irq_desc[irq].status |= IRQ_LEVEL; | |
a460e745 IM |
1216 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
1217 | handle_fasteoi_irq, "fasteoi"); | |
cc75b92d TG |
1218 | } else { |
1219 | irq_desc[irq].status &= ~IRQ_LEVEL; | |
a460e745 IM |
1220 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
1221 | handle_edge_irq, "edge"); | |
cc75b92d | 1222 | } |
ace80ab7 | 1223 | set_intr_gate(vector, interrupt[irq]); |
1da177e4 LT |
1224 | } |
1225 | ||
1226 | static void __init setup_IO_APIC_irqs(void) | |
1227 | { | |
1228 | struct IO_APIC_route_entry entry; | |
1229 | int apic, pin, idx, irq, first_notcon = 1, vector; | |
1da177e4 LT |
1230 | |
1231 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1232 | ||
1233 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1234 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1235 | ||
1236 | /* | |
1237 | * add it to the IO-APIC irq-routing table: | |
1238 | */ | |
1239 | memset(&entry,0,sizeof(entry)); | |
1240 | ||
1241 | entry.delivery_mode = INT_DELIVERY_MODE; | |
1242 | entry.dest_mode = INT_DEST_MODE; | |
1243 | entry.mask = 0; /* enable IRQ */ | |
1244 | entry.dest.logical.logical_dest = | |
1245 | cpu_mask_to_apicid(TARGET_CPUS); | |
1246 | ||
1247 | idx = find_irq_entry(apic,pin,mp_INT); | |
1248 | if (idx == -1) { | |
1249 | if (first_notcon) { | |
1250 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1251 | " IO-APIC (apicid-pin) %d-%d", | |
1252 | mp_ioapics[apic].mpc_apicid, | |
1253 | pin); | |
1254 | first_notcon = 0; | |
1255 | } else | |
1256 | apic_printk(APIC_VERBOSE, ", %d-%d", | |
1257 | mp_ioapics[apic].mpc_apicid, pin); | |
1258 | continue; | |
1259 | } | |
1260 | ||
20d225b9 YL |
1261 | if (!first_notcon) { |
1262 | apic_printk(APIC_VERBOSE, " not connected.\n"); | |
1263 | first_notcon = 1; | |
1264 | } | |
1265 | ||
1da177e4 LT |
1266 | entry.trigger = irq_trigger(idx); |
1267 | entry.polarity = irq_polarity(idx); | |
1268 | ||
1269 | if (irq_trigger(idx)) { | |
1270 | entry.trigger = 1; | |
1271 | entry.mask = 1; | |
1272 | } | |
1273 | ||
1274 | irq = pin_2_irq(idx, apic, pin); | |
1275 | /* | |
1276 | * skip adding the timer int on secondary nodes, which causes | |
1277 | * a small but painful rift in the time-space continuum | |
1278 | */ | |
1279 | if (multi_timer_check(apic, irq)) | |
1280 | continue; | |
1281 | else | |
1282 | add_pin_to_irq(irq, apic, pin); | |
1283 | ||
1284 | if (!apic && !IO_APIC_IRQ(irq)) | |
1285 | continue; | |
1286 | ||
1287 | if (IO_APIC_IRQ(irq)) { | |
1288 | vector = assign_irq_vector(irq); | |
1289 | entry.vector = vector; | |
1290 | ioapic_register_intr(irq, vector, IOAPIC_AUTO); | |
1291 | ||
1292 | if (!apic && (irq < 16)) | |
1293 | disable_8259A_irq(irq); | |
1294 | } | |
a2249cba | 1295 | ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
1296 | } |
1297 | } | |
1298 | ||
1299 | if (!first_notcon) | |
1300 | apic_printk(APIC_VERBOSE, " not connected.\n"); | |
1301 | } | |
1302 | ||
1303 | /* | |
1304 | * Set up the 8259A-master output pin: | |
1305 | */ | |
fcfd636a | 1306 | static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector) |
1da177e4 LT |
1307 | { |
1308 | struct IO_APIC_route_entry entry; | |
1da177e4 LT |
1309 | |
1310 | memset(&entry,0,sizeof(entry)); | |
1311 | ||
1312 | disable_8259A_irq(0); | |
1313 | ||
1314 | /* mask LVT0 */ | |
1315 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); | |
1316 | ||
1317 | /* | |
1318 | * We use logical delivery to get the timer IRQ | |
1319 | * to the first CPU. | |
1320 | */ | |
1321 | entry.dest_mode = INT_DEST_MODE; | |
1322 | entry.mask = 0; /* unmask IRQ now */ | |
1323 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); | |
1324 | entry.delivery_mode = INT_DELIVERY_MODE; | |
1325 | entry.polarity = 0; | |
1326 | entry.trigger = 0; | |
1327 | entry.vector = vector; | |
1328 | ||
1329 | /* | |
1330 | * The timer IRQ doesn't have to know that behind the | |
1331 | * scene we have a 8259A-master in AEOI mode ... | |
1332 | */ | |
f5b9ed7a IM |
1333 | irq_desc[0].chip = &ioapic_chip; |
1334 | set_irq_handler(0, handle_edge_irq); | |
1da177e4 LT |
1335 | |
1336 | /* | |
1337 | * Add it to the IO-APIC irq-routing table: | |
1338 | */ | |
cf4c6a2f | 1339 | ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
1340 | |
1341 | enable_8259A_irq(0); | |
1342 | } | |
1343 | ||
1da177e4 LT |
1344 | void __init print_IO_APIC(void) |
1345 | { | |
1346 | int apic, i; | |
1347 | union IO_APIC_reg_00 reg_00; | |
1348 | union IO_APIC_reg_01 reg_01; | |
1349 | union IO_APIC_reg_02 reg_02; | |
1350 | union IO_APIC_reg_03 reg_03; | |
1351 | unsigned long flags; | |
1352 | ||
1353 | if (apic_verbosity == APIC_QUIET) | |
1354 | return; | |
1355 | ||
1356 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); | |
1357 | for (i = 0; i < nr_ioapics; i++) | |
1358 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
1359 | mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]); | |
1360 | ||
1361 | /* | |
1362 | * We are a bit conservative about what we expect. We have to | |
1363 | * know about every hardware change ASAP. | |
1364 | */ | |
1365 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1366 | ||
1367 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1368 | ||
1369 | spin_lock_irqsave(&ioapic_lock, flags); | |
1370 | reg_00.raw = io_apic_read(apic, 0); | |
1371 | reg_01.raw = io_apic_read(apic, 1); | |
1372 | if (reg_01.bits.version >= 0x10) | |
1373 | reg_02.raw = io_apic_read(apic, 2); | |
1374 | if (reg_01.bits.version >= 0x20) | |
1375 | reg_03.raw = io_apic_read(apic, 3); | |
1376 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1377 | ||
1378 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid); | |
1379 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); | |
1380 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1381 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1382 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 LT |
1383 | |
1384 | printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw); | |
1385 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); | |
1da177e4 LT |
1386 | |
1387 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1388 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1389 | |
1390 | /* | |
1391 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1392 | * but the value of reg_02 is read as the previous read register | |
1393 | * value, so ignore it if reg_02 == reg_01. | |
1394 | */ | |
1395 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1396 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1397 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1398 | } |
1399 | ||
1400 | /* | |
1401 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1402 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1403 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1404 | */ | |
1405 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1406 | reg_03.raw != reg_01.raw) { | |
1407 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1408 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1409 | } |
1410 | ||
1411 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1412 | ||
1413 | printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol" | |
1414 | " Stat Dest Deli Vect: \n"); | |
1415 | ||
1416 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1417 | struct IO_APIC_route_entry entry; | |
1418 | ||
cf4c6a2f | 1419 | entry = ioapic_read_entry(apic, i); |
1da177e4 LT |
1420 | |
1421 | printk(KERN_DEBUG " %02x %03X %02X ", | |
1422 | i, | |
1423 | entry.dest.logical.logical_dest, | |
1424 | entry.dest.physical.physical_dest | |
1425 | ); | |
1426 | ||
1427 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1428 | entry.mask, | |
1429 | entry.trigger, | |
1430 | entry.irr, | |
1431 | entry.polarity, | |
1432 | entry.delivery_status, | |
1433 | entry.dest_mode, | |
1434 | entry.delivery_mode, | |
1435 | entry.vector | |
1436 | ); | |
1437 | } | |
1438 | } | |
1da177e4 LT |
1439 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
1440 | for (i = 0; i < NR_IRQS; i++) { | |
1441 | struct irq_pin_list *entry = irq_2_pin + i; | |
1442 | if (entry->pin < 0) | |
1443 | continue; | |
ace80ab7 | 1444 | printk(KERN_DEBUG "IRQ%d ", i); |
1da177e4 LT |
1445 | for (;;) { |
1446 | printk("-> %d:%d", entry->apic, entry->pin); | |
1447 | if (!entry->next) | |
1448 | break; | |
1449 | entry = irq_2_pin + entry->next; | |
1450 | } | |
1451 | printk("\n"); | |
1452 | } | |
1453 | ||
1454 | printk(KERN_INFO ".................................... done.\n"); | |
1455 | ||
1456 | return; | |
1457 | } | |
1458 | ||
1459 | #if 0 | |
1460 | ||
1461 | static void print_APIC_bitfield (int base) | |
1462 | { | |
1463 | unsigned int v; | |
1464 | int i, j; | |
1465 | ||
1466 | if (apic_verbosity == APIC_QUIET) | |
1467 | return; | |
1468 | ||
1469 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1470 | for (i = 0; i < 8; i++) { | |
1471 | v = apic_read(base + i*0x10); | |
1472 | for (j = 0; j < 32; j++) { | |
1473 | if (v & (1<<j)) | |
1474 | printk("1"); | |
1475 | else | |
1476 | printk("0"); | |
1477 | } | |
1478 | printk("\n"); | |
1479 | } | |
1480 | } | |
1481 | ||
1482 | void /*__init*/ print_local_APIC(void * dummy) | |
1483 | { | |
1484 | unsigned int v, ver, maxlvt; | |
1485 | ||
1486 | if (apic_verbosity == APIC_QUIET) | |
1487 | return; | |
1488 | ||
1489 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1490 | smp_processor_id(), hard_smp_processor_id()); | |
05f2d12c JS |
1491 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, |
1492 | GET_APIC_ID(read_apic_id())); | |
1da177e4 LT |
1493 | v = apic_read(APIC_LVR); |
1494 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1495 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1496 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1497 | |
1498 | v = apic_read(APIC_TASKPRI); | |
1499 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1500 | ||
1501 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ | |
1502 | v = apic_read(APIC_ARBPRI); | |
1503 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1504 | v & APIC_ARBPRI_MASK); | |
1505 | v = apic_read(APIC_PROCPRI); | |
1506 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1507 | } | |
1508 | ||
1509 | v = apic_read(APIC_EOI); | |
1510 | printk(KERN_DEBUG "... APIC EOI: %08x\n", v); | |
1511 | v = apic_read(APIC_RRR); | |
1512 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1513 | v = apic_read(APIC_LDR); | |
1514 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
1515 | v = apic_read(APIC_DFR); | |
1516 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1517 | v = apic_read(APIC_SPIV); | |
1518 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1519 | ||
1520 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1521 | print_APIC_bitfield(APIC_ISR); | |
1522 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1523 | print_APIC_bitfield(APIC_TMR); | |
1524 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1525 | print_APIC_bitfield(APIC_IRR); | |
1526 | ||
1527 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ | |
1528 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1529 | apic_write(APIC_ESR, 0); | |
1530 | v = apic_read(APIC_ESR); | |
1531 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1532 | } | |
1533 | ||
1534 | v = apic_read(APIC_ICR); | |
1535 | printk(KERN_DEBUG "... APIC ICR: %08x\n", v); | |
1536 | v = apic_read(APIC_ICR2); | |
1537 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", v); | |
1538 | ||
1539 | v = apic_read(APIC_LVTT); | |
1540 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1541 | ||
1542 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1543 | v = apic_read(APIC_LVTPC); | |
1544 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1545 | } | |
1546 | v = apic_read(APIC_LVT0); | |
1547 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1548 | v = apic_read(APIC_LVT1); | |
1549 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1550 | ||
1551 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1552 | v = apic_read(APIC_LVTERR); | |
1553 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1554 | } | |
1555 | ||
1556 | v = apic_read(APIC_TMICT); | |
1557 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1558 | v = apic_read(APIC_TMCCT); | |
1559 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1560 | v = apic_read(APIC_TDCR); | |
1561 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
1562 | printk("\n"); | |
1563 | } | |
1564 | ||
1565 | void print_all_local_APICs (void) | |
1566 | { | |
1567 | on_each_cpu(print_local_APIC, NULL, 1, 1); | |
1568 | } | |
1569 | ||
1570 | void /*__init*/ print_PIC(void) | |
1571 | { | |
1da177e4 LT |
1572 | unsigned int v; |
1573 | unsigned long flags; | |
1574 | ||
1575 | if (apic_verbosity == APIC_QUIET) | |
1576 | return; | |
1577 | ||
1578 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1579 | ||
1580 | spin_lock_irqsave(&i8259A_lock, flags); | |
1581 | ||
1582 | v = inb(0xa1) << 8 | inb(0x21); | |
1583 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1584 | ||
1585 | v = inb(0xa0) << 8 | inb(0x20); | |
1586 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1587 | ||
1588 | outb(0x0b,0xa0); | |
1589 | outb(0x0b,0x20); | |
1590 | v = inb(0xa0) << 8 | inb(0x20); | |
1591 | outb(0x0a,0xa0); | |
1592 | outb(0x0a,0x20); | |
1593 | ||
1594 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1595 | ||
1596 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1597 | ||
1598 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1599 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1600 | } | |
1601 | ||
1602 | #endif /* 0 */ | |
1603 | ||
1604 | static void __init enable_IO_APIC(void) | |
1605 | { | |
1606 | union IO_APIC_reg_01 reg_01; | |
fcfd636a EB |
1607 | int i8259_apic, i8259_pin; |
1608 | int i, apic; | |
1da177e4 LT |
1609 | unsigned long flags; |
1610 | ||
1611 | for (i = 0; i < PIN_MAP_SIZE; i++) { | |
1612 | irq_2_pin[i].pin = -1; | |
1613 | irq_2_pin[i].next = 0; | |
1614 | } | |
1615 | if (!pirqs_enabled) | |
1616 | for (i = 0; i < MAX_PIRQS; i++) | |
1617 | pirq_entries[i] = -1; | |
1618 | ||
1619 | /* | |
1620 | * The number of IO-APIC IRQ registers (== #pins): | |
1621 | */ | |
fcfd636a | 1622 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1623 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1624 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1625 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
1626 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1627 | } | |
1628 | for(apic = 0; apic < nr_ioapics; apic++) { | |
1629 | int pin; | |
1630 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1631 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1632 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1633 | entry = ioapic_read_entry(apic, pin); |
fcfd636a EB |
1634 | |
1635 | ||
1636 | /* If the interrupt line is enabled and in ExtInt mode | |
1637 | * I have found the pin where the i8259 is connected. | |
1638 | */ | |
1639 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1640 | ioapic_i8259.apic = apic; | |
1641 | ioapic_i8259.pin = pin; | |
1642 | goto found_i8259; | |
1643 | } | |
1644 | } | |
1645 | } | |
1646 | found_i8259: | |
1647 | /* Look to see what if the MP table has reported the ExtINT */ | |
1648 | /* If we could not find the appropriate pin by looking at the ioapic | |
1649 | * the i8259 probably is not connected the ioapic but give the | |
1650 | * mptable a chance anyway. | |
1651 | */ | |
1652 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1653 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1654 | /* Trust the MP table if nothing is setup in the hardware */ | |
1655 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1656 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1657 | ioapic_i8259.pin = i8259_pin; | |
1658 | ioapic_i8259.apic = i8259_apic; | |
1659 | } | |
1660 | /* Complain if the MP table and the hardware disagree */ | |
1661 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1662 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1663 | { | |
1664 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1665 | } |
1666 | ||
1667 | /* | |
1668 | * Do not trust the IO-APIC being empty at bootup | |
1669 | */ | |
1670 | clear_IO_APIC(); | |
1671 | } | |
1672 | ||
1673 | /* | |
1674 | * Not an __init, needed by the reboot code | |
1675 | */ | |
1676 | void disable_IO_APIC(void) | |
1677 | { | |
1678 | /* | |
1679 | * Clear the IO-APIC before rebooting: | |
1680 | */ | |
1681 | clear_IO_APIC(); | |
1682 | ||
650927ef | 1683 | /* |
0b968d23 | 1684 | * If the i8259 is routed through an IOAPIC |
650927ef | 1685 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1686 | * so legacy interrupts can be delivered. |
650927ef | 1687 | */ |
fcfd636a | 1688 | if (ioapic_i8259.pin != -1) { |
650927ef | 1689 | struct IO_APIC_route_entry entry; |
650927ef EB |
1690 | |
1691 | memset(&entry, 0, sizeof(entry)); | |
1692 | entry.mask = 0; /* Enabled */ | |
1693 | entry.trigger = 0; /* Edge */ | |
1694 | entry.irr = 0; | |
1695 | entry.polarity = 0; /* High */ | |
1696 | entry.delivery_status = 0; | |
1697 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1698 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1699 | entry.vector = 0; |
76865c3f | 1700 | entry.dest.physical.physical_dest = |
05f2d12c | 1701 | GET_APIC_ID(read_apic_id()); |
650927ef EB |
1702 | |
1703 | /* | |
1704 | * Add it to the IO-APIC irq-routing table: | |
1705 | */ | |
cf4c6a2f | 1706 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1707 | } |
fcfd636a | 1708 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
1da177e4 LT |
1709 | } |
1710 | ||
1711 | /* | |
1712 | * function to set the IO-APIC physical IDs based on the | |
1713 | * values stored in the MPC table. | |
1714 | * | |
1715 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1716 | */ | |
1717 | ||
1718 | #ifndef CONFIG_X86_NUMAQ | |
1719 | static void __init setup_ioapic_ids_from_mpc(void) | |
1720 | { | |
1721 | union IO_APIC_reg_00 reg_00; | |
1722 | physid_mask_t phys_id_present_map; | |
1723 | int apic; | |
1724 | int i; | |
1725 | unsigned char old_id; | |
1726 | unsigned long flags; | |
1727 | ||
ca05fea6 NP |
1728 | /* |
1729 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
1730 | * no meaning without the serial APIC bus. | |
1731 | */ | |
7c5c1e42 SL |
1732 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
1733 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 1734 | return; |
1da177e4 LT |
1735 | /* |
1736 | * This is broken; anything with a real cpu count has to | |
1737 | * circumvent this idiocy regardless. | |
1738 | */ | |
1739 | phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map); | |
1740 | ||
1741 | /* | |
1742 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1743 | */ | |
1744 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1745 | ||
1746 | /* Read the register 0 value */ | |
1747 | spin_lock_irqsave(&ioapic_lock, flags); | |
1748 | reg_00.raw = io_apic_read(apic, 0); | |
1749 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1750 | ||
1751 | old_id = mp_ioapics[apic].mpc_apicid; | |
1752 | ||
1753 | if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) { | |
1754 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", | |
1755 | apic, mp_ioapics[apic].mpc_apicid); | |
1756 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1757 | reg_00.bits.ID); | |
1758 | mp_ioapics[apic].mpc_apicid = reg_00.bits.ID; | |
1759 | } | |
1760 | ||
1da177e4 LT |
1761 | /* |
1762 | * Sanity check, is the ID really free? Every APIC in a | |
1763 | * system must have a unique ID or we get lots of nice | |
1764 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
1765 | */ | |
1766 | if (check_apicid_used(phys_id_present_map, | |
1767 | mp_ioapics[apic].mpc_apicid)) { | |
1768 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", | |
1769 | apic, mp_ioapics[apic].mpc_apicid); | |
1770 | for (i = 0; i < get_physical_broadcast(); i++) | |
1771 | if (!physid_isset(i, phys_id_present_map)) | |
1772 | break; | |
1773 | if (i >= get_physical_broadcast()) | |
1774 | panic("Max APIC ID exceeded!\n"); | |
1775 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1776 | i); | |
1777 | physid_set(i, phys_id_present_map); | |
1778 | mp_ioapics[apic].mpc_apicid = i; | |
1779 | } else { | |
1780 | physid_mask_t tmp; | |
1781 | tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid); | |
1782 | apic_printk(APIC_VERBOSE, "Setting %d in the " | |
1783 | "phys_id_present_map\n", | |
1784 | mp_ioapics[apic].mpc_apicid); | |
1785 | physids_or(phys_id_present_map, phys_id_present_map, tmp); | |
1786 | } | |
1787 | ||
1788 | ||
1789 | /* | |
1790 | * We need to adjust the IRQ routing table | |
1791 | * if the ID changed. | |
1792 | */ | |
1793 | if (old_id != mp_ioapics[apic].mpc_apicid) | |
1794 | for (i = 0; i < mp_irq_entries; i++) | |
1795 | if (mp_irqs[i].mpc_dstapic == old_id) | |
1796 | mp_irqs[i].mpc_dstapic | |
1797 | = mp_ioapics[apic].mpc_apicid; | |
1798 | ||
1799 | /* | |
1800 | * Read the right value from the MPC table and | |
1801 | * write it into the ID register. | |
1802 | */ | |
1803 | apic_printk(APIC_VERBOSE, KERN_INFO | |
1804 | "...changing IO-APIC physical APIC ID to %d ...", | |
1805 | mp_ioapics[apic].mpc_apicid); | |
1806 | ||
1807 | reg_00.bits.ID = mp_ioapics[apic].mpc_apicid; | |
1808 | spin_lock_irqsave(&ioapic_lock, flags); | |
1809 | io_apic_write(apic, 0, reg_00.raw); | |
1810 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1811 | ||
1812 | /* | |
1813 | * Sanity check | |
1814 | */ | |
1815 | spin_lock_irqsave(&ioapic_lock, flags); | |
1816 | reg_00.raw = io_apic_read(apic, 0); | |
1817 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1818 | if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid) | |
1819 | printk("could not set ID!\n"); | |
1820 | else | |
1821 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
1822 | } | |
1823 | } | |
1824 | #else | |
1825 | static void __init setup_ioapic_ids_from_mpc(void) { } | |
1826 | #endif | |
1827 | ||
7ce0bcfd | 1828 | int no_timer_check __initdata; |
8542b200 ZA |
1829 | |
1830 | static int __init notimercheck(char *s) | |
1831 | { | |
1832 | no_timer_check = 1; | |
1833 | return 1; | |
1834 | } | |
1835 | __setup("no_timer_check", notimercheck); | |
1836 | ||
1da177e4 LT |
1837 | /* |
1838 | * There is a nasty bug in some older SMP boards, their mptable lies | |
1839 | * about the timer IRQ. We do the following to work around the situation: | |
1840 | * | |
1841 | * - timer IRQ defaults to IO-APIC IRQ | |
1842 | * - if this function detects that timer IRQs are defunct, then we fall | |
1843 | * back to ISA timer IRQs | |
1844 | */ | |
f0a7a5c9 | 1845 | static int __init timer_irq_works(void) |
1da177e4 LT |
1846 | { |
1847 | unsigned long t1 = jiffies; | |
4aae0702 | 1848 | unsigned long flags; |
1da177e4 | 1849 | |
8542b200 ZA |
1850 | if (no_timer_check) |
1851 | return 1; | |
1852 | ||
4aae0702 | 1853 | local_save_flags(flags); |
1da177e4 LT |
1854 | local_irq_enable(); |
1855 | /* Let ten ticks pass... */ | |
1856 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 1857 | local_irq_restore(flags); |
1da177e4 LT |
1858 | |
1859 | /* | |
1860 | * Expect a few ticks at least, to be sure some possible | |
1861 | * glue logic does not lock up after one or two first | |
1862 | * ticks in a non-ExtINT mode. Also the local APIC | |
1863 | * might have cached one ExtINT interrupt. Finally, at | |
1864 | * least one tick may be lost due to delays. | |
1865 | */ | |
1d16b53e | 1866 | if (time_after(jiffies, t1 + 4)) |
1da177e4 LT |
1867 | return 1; |
1868 | ||
1869 | return 0; | |
1870 | } | |
1871 | ||
1872 | /* | |
1873 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
1874 | * number of pending IRQ events unhandled. These cases are very rare, | |
1875 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
1876 | * better to do it this way as thus we do not have to be aware of | |
1877 | * 'pending' interrupts in the IRQ path, except at this point. | |
1878 | */ | |
1879 | /* | |
1880 | * Edge triggered needs to resend any interrupt | |
1881 | * that was delayed but this is now handled in the device | |
1882 | * independent code. | |
1883 | */ | |
1884 | ||
1885 | /* | |
f5b9ed7a IM |
1886 | * Startup quirk: |
1887 | * | |
1da177e4 LT |
1888 | * Starting up a edge-triggered IO-APIC interrupt is |
1889 | * nasty - we need to make sure that we get the edge. | |
1890 | * If it is already asserted for some reason, we need | |
1891 | * return 1 to indicate that is was pending. | |
1892 | * | |
1893 | * This is not complete - we should be able to fake | |
1894 | * an edge even if it isn't on the 8259A... | |
f5b9ed7a IM |
1895 | * |
1896 | * (We do this for level-triggered IRQs too - it cannot hurt.) | |
1da177e4 | 1897 | */ |
f5b9ed7a | 1898 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
1899 | { |
1900 | int was_pending = 0; | |
1901 | unsigned long flags; | |
1902 | ||
1903 | spin_lock_irqsave(&ioapic_lock, flags); | |
1904 | if (irq < 16) { | |
1905 | disable_8259A_irq(irq); | |
1906 | if (i8259A_irq_pending(irq)) | |
1907 | was_pending = 1; | |
1908 | } | |
1909 | __unmask_IO_APIC_irq(irq); | |
1910 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1911 | ||
1912 | return was_pending; | |
1913 | } | |
1914 | ||
f5b9ed7a | 1915 | static void ack_ioapic_irq(unsigned int irq) |
1da177e4 | 1916 | { |
ace80ab7 | 1917 | move_native_irq(irq); |
1da177e4 LT |
1918 | ack_APIC_irq(); |
1919 | } | |
1920 | ||
f5b9ed7a | 1921 | static void ack_ioapic_quirk_irq(unsigned int irq) |
1da177e4 LT |
1922 | { |
1923 | unsigned long v; | |
1924 | int i; | |
1925 | ||
ace80ab7 | 1926 | move_native_irq(irq); |
1da177e4 LT |
1927 | /* |
1928 | * It appears there is an erratum which affects at least version 0x11 | |
1929 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
1930 | * chipsets). Under certain conditions a level-triggered interrupt is | |
1931 | * erroneously delivered as edge-triggered one but the respective IRR | |
1932 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
1933 | * message but it will never arrive and further interrupts are blocked | |
1934 | * from the source. The exact reason is so far unknown, but the | |
1935 | * phenomenon was observed when two consecutive interrupt requests | |
1936 | * from a given source get delivered to the same CPU and the source is | |
1937 | * temporarily disabled in between. | |
1938 | * | |
1939 | * A workaround is to simulate an EOI message manually. We achieve it | |
1940 | * by setting the trigger mode to edge and then to level when the edge | |
1941 | * trigger mode gets detected in the TMR of a local APIC for a | |
1942 | * level-triggered interrupt. We mask the source for the time of the | |
1943 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
1944 | * The idea is from Manfred Spraul. --macro | |
1945 | */ | |
b940d22d | 1946 | i = irq_vector[irq]; |
1da177e4 LT |
1947 | |
1948 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); | |
1949 | ||
1950 | ack_APIC_irq(); | |
1951 | ||
1952 | if (!(v & (1 << (i & 0x1f)))) { | |
1953 | atomic_inc(&irq_mis_count); | |
1954 | spin_lock(&ioapic_lock); | |
1955 | __mask_and_edge_IO_APIC_irq(irq); | |
1956 | __unmask_and_level_IO_APIC_irq(irq); | |
1957 | spin_unlock(&ioapic_lock); | |
1958 | } | |
1959 | } | |
1960 | ||
ace80ab7 | 1961 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 1962 | { |
b940d22d | 1963 | send_IPI_self(irq_vector[irq]); |
c0ad90a3 IM |
1964 | |
1965 | return 1; | |
1966 | } | |
1967 | ||
f5b9ed7a IM |
1968 | static struct irq_chip ioapic_chip __read_mostly = { |
1969 | .name = "IO-APIC", | |
ace80ab7 EB |
1970 | .startup = startup_ioapic_irq, |
1971 | .mask = mask_IO_APIC_irq, | |
1972 | .unmask = unmask_IO_APIC_irq, | |
1973 | .ack = ack_ioapic_irq, | |
1974 | .eoi = ack_ioapic_quirk_irq, | |
54d5d424 | 1975 | #ifdef CONFIG_SMP |
ace80ab7 | 1976 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 1977 | #endif |
ace80ab7 | 1978 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
1979 | }; |
1980 | ||
1da177e4 LT |
1981 | |
1982 | static inline void init_IO_APIC_traps(void) | |
1983 | { | |
1984 | int irq; | |
1985 | ||
1986 | /* | |
1987 | * NOTE! The local APIC isn't very good at handling | |
1988 | * multiple interrupts at the same interrupt level. | |
1989 | * As the interrupt level is determined by taking the | |
1990 | * vector number and shifting that right by 4, we | |
1991 | * want to spread these out a bit so that they don't | |
1992 | * all fall in the same interrupt level. | |
1993 | * | |
1994 | * Also, we've got to be careful not to trash gate | |
1995 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1996 | */ | |
1997 | for (irq = 0; irq < NR_IRQS ; irq++) { | |
addfc66b | 1998 | if (IO_APIC_IRQ(irq) && !irq_vector[irq]) { |
1da177e4 LT |
1999 | /* |
2000 | * Hmm.. We don't have an entry for this, | |
2001 | * so default to an old-fashioned 8259 | |
2002 | * interrupt if we can.. | |
2003 | */ | |
2004 | if (irq < 16) | |
2005 | make_8259A_irq(irq); | |
2006 | else | |
2007 | /* Strange. Oh, well.. */ | |
f5b9ed7a | 2008 | irq_desc[irq].chip = &no_irq_chip; |
1da177e4 LT |
2009 | } |
2010 | } | |
2011 | } | |
2012 | ||
f5b9ed7a IM |
2013 | /* |
2014 | * The local APIC irq-chip implementation: | |
2015 | */ | |
1da177e4 | 2016 | |
f5b9ed7a IM |
2017 | static void ack_apic(unsigned int irq) |
2018 | { | |
2019 | ack_APIC_irq(); | |
1da177e4 LT |
2020 | } |
2021 | ||
f5b9ed7a | 2022 | static void mask_lapic_irq (unsigned int irq) |
1da177e4 LT |
2023 | { |
2024 | unsigned long v; | |
2025 | ||
2026 | v = apic_read(APIC_LVT0); | |
2027 | apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); | |
2028 | } | |
2029 | ||
f5b9ed7a | 2030 | static void unmask_lapic_irq (unsigned int irq) |
1da177e4 | 2031 | { |
f5b9ed7a | 2032 | unsigned long v; |
1da177e4 | 2033 | |
f5b9ed7a IM |
2034 | v = apic_read(APIC_LVT0); |
2035 | apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED); | |
2036 | } | |
1da177e4 | 2037 | |
f5b9ed7a IM |
2038 | static struct irq_chip lapic_chip __read_mostly = { |
2039 | .name = "local-APIC-edge", | |
2040 | .mask = mask_lapic_irq, | |
2041 | .unmask = unmask_lapic_irq, | |
2042 | .eoi = ack_apic, | |
1da177e4 LT |
2043 | }; |
2044 | ||
e9427101 | 2045 | static void __init setup_nmi(void) |
1da177e4 LT |
2046 | { |
2047 | /* | |
2048 | * Dirty trick to enable the NMI watchdog ... | |
2049 | * We put the 8259A master into AEOI mode and | |
2050 | * unmask on all local APICs LVT0 as NMI. | |
2051 | * | |
2052 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2053 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2054 | * the NMI handler or the timer interrupt. | |
2055 | */ | |
2056 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); | |
2057 | ||
e9427101 | 2058 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2059 | |
2060 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2061 | } | |
2062 | ||
2063 | /* | |
2064 | * This looks a bit hackish but it's about the only one way of sending | |
2065 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2066 | * not support the ExtINT mode, unfortunately. We need to send these | |
2067 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2068 | * 8259A interrupt line asserted until INTA. --macro | |
2069 | */ | |
28acf285 | 2070 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2071 | { |
fcfd636a | 2072 | int apic, pin, i; |
1da177e4 LT |
2073 | struct IO_APIC_route_entry entry0, entry1; |
2074 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2075 | |
fcfd636a | 2076 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2077 | if (pin == -1) { |
2078 | WARN_ON_ONCE(1); | |
2079 | return; | |
2080 | } | |
fcfd636a | 2081 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2082 | if (apic == -1) { |
2083 | WARN_ON_ONCE(1); | |
1da177e4 | 2084 | return; |
956fb531 | 2085 | } |
1da177e4 | 2086 | |
cf4c6a2f | 2087 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2088 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2089 | |
2090 | memset(&entry1, 0, sizeof(entry1)); | |
2091 | ||
2092 | entry1.dest_mode = 0; /* physical delivery */ | |
2093 | entry1.mask = 0; /* unmask IRQ now */ | |
2094 | entry1.dest.physical.physical_dest = hard_smp_processor_id(); | |
2095 | entry1.delivery_mode = dest_ExtINT; | |
2096 | entry1.polarity = entry0.polarity; | |
2097 | entry1.trigger = 0; | |
2098 | entry1.vector = 0; | |
2099 | ||
cf4c6a2f | 2100 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2101 | |
2102 | save_control = CMOS_READ(RTC_CONTROL); | |
2103 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2104 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2105 | RTC_FREQ_SELECT); | |
2106 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2107 | ||
2108 | i = 100; | |
2109 | while (i-- > 0) { | |
2110 | mdelay(10); | |
2111 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2112 | i -= 10; | |
2113 | } | |
2114 | ||
2115 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2116 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2117 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2118 | |
cf4c6a2f | 2119 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2120 | } |
2121 | ||
2122 | /* | |
2123 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2124 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2125 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2126 | * fanatically on his truly buggy board. | |
2127 | */ | |
8542b200 | 2128 | static inline void __init check_timer(void) |
1da177e4 | 2129 | { |
fcfd636a | 2130 | int apic1, pin1, apic2, pin2; |
1da177e4 | 2131 | int vector; |
a0176e24 | 2132 | unsigned int ver; |
4aae0702 IM |
2133 | unsigned long flags; |
2134 | ||
2135 | local_irq_save(flags); | |
d4d25dec | 2136 | |
a0176e24 IM |
2137 | ver = apic_read(APIC_LVR); |
2138 | ver = GET_APIC_VERSION(ver); | |
2139 | ||
1da177e4 LT |
2140 | /* |
2141 | * get/set the timer IRQ vector: | |
2142 | */ | |
2143 | disable_8259A_irq(0); | |
2144 | vector = assign_irq_vector(0); | |
2145 | set_intr_gate(vector, interrupt[0]); | |
2146 | ||
2147 | /* | |
d11d5794 MR |
2148 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2149 | * wire has to be disabled in the local APIC. Also | |
2150 | * timer interrupts need to be acknowledged manually in | |
2151 | * the 8259A for the i82489DX when using the NMI | |
2152 | * watchdog as that APIC treats NMIs as level-triggered. | |
2153 | * The AEOI mode will finish them in the 8259A | |
2154 | * automatically. | |
1da177e4 LT |
2155 | */ |
2156 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); | |
2157 | init_8259A(1); | |
d11d5794 | 2158 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); |
1da177e4 | 2159 | |
fcfd636a EB |
2160 | pin1 = find_isa_irq_pin(0, mp_INT); |
2161 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2162 | pin2 = ioapic_i8259.pin; | |
2163 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2164 | |
fcfd636a EB |
2165 | printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n", |
2166 | vector, apic1, pin1, apic2, pin2); | |
1da177e4 LT |
2167 | |
2168 | if (pin1 != -1) { | |
2169 | /* | |
2170 | * Ok, does IRQ0 through the IOAPIC work? | |
2171 | */ | |
2172 | unmask_IO_APIC_irq(0); | |
2173 | if (timer_irq_works()) { | |
2174 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 LT |
2175 | setup_nmi(); |
2176 | enable_8259A_irq(0); | |
1da177e4 | 2177 | } |
66759a01 CE |
2178 | if (disable_timer_pin_1 > 0) |
2179 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2180 | goto out; |
1da177e4 | 2181 | } |
fcfd636a EB |
2182 | clear_IO_APIC_pin(apic1, pin1); |
2183 | printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to " | |
2184 | "IO-APIC\n"); | |
1da177e4 LT |
2185 | } |
2186 | ||
2187 | printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... "); | |
2188 | if (pin2 != -1) { | |
2189 | printk("\n..... (found pin %d) ...", pin2); | |
2190 | /* | |
2191 | * legacy devices should be connected to IO APIC #0 | |
2192 | */ | |
fcfd636a | 2193 | setup_ExtINT_IRQ0_pin(apic2, pin2, vector); |
ecd29476 | 2194 | enable_8259A_irq(0); |
1da177e4 LT |
2195 | if (timer_irq_works()) { |
2196 | printk("works.\n"); | |
2197 | if (pin1 != -1) | |
fcfd636a | 2198 | replace_pin_at_irq(0, apic1, pin1, apic2, pin2); |
1da177e4 | 2199 | else |
fcfd636a | 2200 | add_pin_to_irq(0, apic2, pin2); |
1da177e4 | 2201 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 2202 | disable_8259A_irq(0); |
1da177e4 | 2203 | setup_nmi(); |
60134ebe | 2204 | enable_8259A_irq(0); |
1da177e4 | 2205 | } |
4aae0702 | 2206 | goto out; |
1da177e4 LT |
2207 | } |
2208 | /* | |
2209 | * Cleanup, just in case ... | |
2210 | */ | |
ecd29476 | 2211 | disable_8259A_irq(0); |
fcfd636a | 2212 | clear_IO_APIC_pin(apic2, pin2); |
1da177e4 LT |
2213 | } |
2214 | printk(" failed.\n"); | |
2215 | ||
2216 | if (nmi_watchdog == NMI_IO_APIC) { | |
2217 | printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n"); | |
2218 | nmi_watchdog = 0; | |
2219 | } | |
d11d5794 | 2220 | timer_ack = 0; |
1da177e4 LT |
2221 | |
2222 | printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ..."); | |
2223 | ||
a460e745 | 2224 | set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq, |
2e188938 | 2225 | "fasteoi"); |
1da177e4 LT |
2226 | apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */ |
2227 | enable_8259A_irq(0); | |
2228 | ||
2229 | if (timer_irq_works()) { | |
2230 | printk(" works.\n"); | |
4aae0702 | 2231 | goto out; |
1da177e4 | 2232 | } |
e67465f1 | 2233 | disable_8259A_irq(0); |
1da177e4 LT |
2234 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector); |
2235 | printk(" failed.\n"); | |
2236 | ||
2237 | printk(KERN_INFO "...trying to set up timer as ExtINT IRQ..."); | |
2238 | ||
1da177e4 LT |
2239 | init_8259A(0); |
2240 | make_8259A_irq(0); | |
2241 | apic_write_around(APIC_LVT0, APIC_DM_EXTINT); | |
2242 | ||
2243 | unlock_ExtINT_logic(); | |
2244 | ||
2245 | if (timer_irq_works()) { | |
2246 | printk(" works.\n"); | |
4aae0702 | 2247 | goto out; |
1da177e4 LT |
2248 | } |
2249 | printk(" failed :(.\n"); | |
2250 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " | |
2251 | "report. Then try booting with the 'noapic' option"); | |
4aae0702 IM |
2252 | out: |
2253 | local_irq_restore(flags); | |
1da177e4 LT |
2254 | } |
2255 | ||
2256 | /* | |
2257 | * | |
2258 | * IRQ's that are handled by the PIC in the MPS IOAPIC case. | |
2259 | * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ. | |
2260 | * Linux doesn't really care, as it's not actually used | |
2261 | * for any interrupt handling anyway. | |
2262 | */ | |
2263 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
2264 | ||
2265 | void __init setup_IO_APIC(void) | |
2266 | { | |
dbeb2be2 RR |
2267 | int i; |
2268 | ||
2269 | /* Reserve all the system vectors. */ | |
2270 | for (i = FIRST_SYSTEM_VECTOR; i < NR_VECTORS; i++) | |
2271 | set_bit(i, used_vectors); | |
2272 | ||
1da177e4 LT |
2273 | enable_IO_APIC(); |
2274 | ||
2275 | if (acpi_ioapic) | |
2276 | io_apic_irqs = ~0; /* all IRQs go through IOAPIC */ | |
2277 | else | |
2278 | io_apic_irqs = ~PIC_IRQS; | |
2279 | ||
2280 | printk("ENABLING IO-APIC IRQs\n"); | |
2281 | ||
2282 | /* | |
2283 | * Set up IO-APIC IRQ routing. | |
2284 | */ | |
2285 | if (!acpi_ioapic) | |
2286 | setup_ioapic_ids_from_mpc(); | |
2287 | sync_Arb_IDs(); | |
2288 | setup_IO_APIC_irqs(); | |
2289 | init_IO_APIC_traps(); | |
1e4c85f9 | 2290 | check_timer(); |
1da177e4 LT |
2291 | if (!acpi_ioapic) |
2292 | print_IO_APIC(); | |
2293 | } | |
2294 | ||
2295 | /* | |
2296 | * Called after all the initialization is done. If we didnt find any | |
2297 | * APIC bugs then we can allow the modify fast path | |
2298 | */ | |
2299 | ||
2300 | static int __init io_apic_bug_finalize(void) | |
2301 | { | |
2302 | if(sis_apic_bug == -1) | |
2303 | sis_apic_bug = 0; | |
2304 | return 0; | |
2305 | } | |
2306 | ||
2307 | late_initcall(io_apic_bug_finalize); | |
2308 | ||
2309 | struct sysfs_ioapic_data { | |
2310 | struct sys_device dev; | |
2311 | struct IO_APIC_route_entry entry[0]; | |
2312 | }; | |
2313 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; | |
2314 | ||
438510f6 | 2315 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
2316 | { |
2317 | struct IO_APIC_route_entry *entry; | |
2318 | struct sysfs_ioapic_data *data; | |
1da177e4 LT |
2319 | int i; |
2320 | ||
2321 | data = container_of(dev, struct sysfs_ioapic_data, dev); | |
2322 | entry = data->entry; | |
cf4c6a2f AK |
2323 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++) |
2324 | entry[i] = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
2325 | |
2326 | return 0; | |
2327 | } | |
2328 | ||
2329 | static int ioapic_resume(struct sys_device *dev) | |
2330 | { | |
2331 | struct IO_APIC_route_entry *entry; | |
2332 | struct sysfs_ioapic_data *data; | |
2333 | unsigned long flags; | |
2334 | union IO_APIC_reg_00 reg_00; | |
2335 | int i; | |
2336 | ||
2337 | data = container_of(dev, struct sysfs_ioapic_data, dev); | |
2338 | entry = data->entry; | |
2339 | ||
2340 | spin_lock_irqsave(&ioapic_lock, flags); | |
2341 | reg_00.raw = io_apic_read(dev->id, 0); | |
2342 | if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) { | |
2343 | reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid; | |
2344 | io_apic_write(dev->id, 0, reg_00.raw); | |
2345 | } | |
1da177e4 | 2346 | spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
2347 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++) |
2348 | ioapic_write_entry(dev->id, i, entry[i]); | |
1da177e4 LT |
2349 | |
2350 | return 0; | |
2351 | } | |
2352 | ||
2353 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 2354 | .name = "ioapic", |
1da177e4 LT |
2355 | .suspend = ioapic_suspend, |
2356 | .resume = ioapic_resume, | |
2357 | }; | |
2358 | ||
2359 | static int __init ioapic_init_sysfs(void) | |
2360 | { | |
2361 | struct sys_device * dev; | |
2362 | int i, size, error = 0; | |
2363 | ||
2364 | error = sysdev_class_register(&ioapic_sysdev_class); | |
2365 | if (error) | |
2366 | return error; | |
2367 | ||
2368 | for (i = 0; i < nr_ioapics; i++ ) { | |
2369 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] | |
2370 | * sizeof(struct IO_APIC_route_entry); | |
2371 | mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL); | |
2372 | if (!mp_ioapic_data[i]) { | |
2373 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2374 | continue; | |
2375 | } | |
2376 | memset(mp_ioapic_data[i], 0, size); | |
2377 | dev = &mp_ioapic_data[i]->dev; | |
2378 | dev->id = i; | |
2379 | dev->cls = &ioapic_sysdev_class; | |
2380 | error = sysdev_register(dev); | |
2381 | if (error) { | |
2382 | kfree(mp_ioapic_data[i]); | |
2383 | mp_ioapic_data[i] = NULL; | |
2384 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2385 | continue; | |
2386 | } | |
2387 | } | |
2388 | ||
2389 | return 0; | |
2390 | } | |
2391 | ||
2392 | device_initcall(ioapic_init_sysfs); | |
2393 | ||
3fc471ed | 2394 | /* |
95d77884 | 2395 | * Dynamic irq allocate and deallocation |
3fc471ed EB |
2396 | */ |
2397 | int create_irq(void) | |
2398 | { | |
ace80ab7 | 2399 | /* Allocate an unused irq */ |
306a22c2 | 2400 | int irq, new, vector = 0; |
3fc471ed | 2401 | unsigned long flags; |
3fc471ed | 2402 | |
ace80ab7 EB |
2403 | irq = -ENOSPC; |
2404 | spin_lock_irqsave(&vector_lock, flags); | |
2405 | for (new = (NR_IRQS - 1); new >= 0; new--) { | |
2406 | if (platform_legacy_irq(new)) | |
2407 | continue; | |
2408 | if (irq_vector[new] != 0) | |
2409 | continue; | |
2410 | vector = __assign_irq_vector(new); | |
2411 | if (likely(vector > 0)) | |
2412 | irq = new; | |
2413 | break; | |
2414 | } | |
2415 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 2416 | |
ace80ab7 | 2417 | if (irq >= 0) { |
3fc471ed | 2418 | set_intr_gate(vector, interrupt[irq]); |
3fc471ed EB |
2419 | dynamic_irq_init(irq); |
2420 | } | |
2421 | return irq; | |
2422 | } | |
2423 | ||
2424 | void destroy_irq(unsigned int irq) | |
2425 | { | |
2426 | unsigned long flags; | |
3fc471ed EB |
2427 | |
2428 | dynamic_irq_cleanup(irq); | |
2429 | ||
2430 | spin_lock_irqsave(&vector_lock, flags); | |
9d9ad4b5 | 2431 | clear_bit(irq_vector[irq], used_vectors); |
3fc471ed EB |
2432 | irq_vector[irq] = 0; |
2433 | spin_unlock_irqrestore(&vector_lock, flags); | |
2434 | } | |
3fc471ed | 2435 | |
2d3fcc1c | 2436 | /* |
27b46d76 | 2437 | * MSI message composition |
2d3fcc1c EB |
2438 | */ |
2439 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 2440 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 2441 | { |
2d3fcc1c EB |
2442 | int vector; |
2443 | unsigned dest; | |
2444 | ||
2445 | vector = assign_irq_vector(irq); | |
2446 | if (vector >= 0) { | |
2447 | dest = cpu_mask_to_apicid(TARGET_CPUS); | |
2448 | ||
2449 | msg->address_hi = MSI_ADDR_BASE_HI; | |
2450 | msg->address_lo = | |
2451 | MSI_ADDR_BASE_LO | | |
2452 | ((INT_DEST_MODE == 0) ? | |
2453 | MSI_ADDR_DEST_MODE_PHYSICAL: | |
2454 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
2455 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2456 | MSI_ADDR_REDIRECTION_CPU: | |
2457 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
2458 | MSI_ADDR_DEST_ID(dest); | |
2459 | ||
2460 | msg->data = | |
2461 | MSI_DATA_TRIGGER_EDGE | | |
2462 | MSI_DATA_LEVEL_ASSERT | | |
2463 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2464 | MSI_DATA_DELIVERY_FIXED: | |
2465 | MSI_DATA_DELIVERY_LOWPRI) | | |
2466 | MSI_DATA_VECTOR(vector); | |
2467 | } | |
2468 | return vector; | |
2469 | } | |
2470 | ||
3b7d1921 EB |
2471 | #ifdef CONFIG_SMP |
2472 | static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask) | |
2d3fcc1c | 2473 | { |
3b7d1921 EB |
2474 | struct msi_msg msg; |
2475 | unsigned int dest; | |
2476 | cpumask_t tmp; | |
2d3fcc1c | 2477 | int vector; |
3b7d1921 EB |
2478 | |
2479 | cpus_and(tmp, mask, cpu_online_map); | |
2480 | if (cpus_empty(tmp)) | |
2481 | tmp = TARGET_CPUS; | |
2d3fcc1c EB |
2482 | |
2483 | vector = assign_irq_vector(irq); | |
3b7d1921 EB |
2484 | if (vector < 0) |
2485 | return; | |
2d3fcc1c | 2486 | |
3b7d1921 EB |
2487 | dest = cpu_mask_to_apicid(mask); |
2488 | ||
2489 | read_msi_msg(irq, &msg); | |
2490 | ||
2491 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
2492 | msg.data |= MSI_DATA_VECTOR(vector); | |
2493 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
2494 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
2495 | ||
2496 | write_msi_msg(irq, &msg); | |
9f0a5ba5 | 2497 | irq_desc[irq].affinity = mask; |
2d3fcc1c | 2498 | } |
3b7d1921 | 2499 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 2500 | |
3b7d1921 EB |
2501 | /* |
2502 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
2503 | * which implement the MSI or MSI-X Capability Structure. | |
2504 | */ | |
2505 | static struct irq_chip msi_chip = { | |
2506 | .name = "PCI-MSI", | |
2507 | .unmask = unmask_msi_irq, | |
2508 | .mask = mask_msi_irq, | |
2509 | .ack = ack_ioapic_irq, | |
2510 | #ifdef CONFIG_SMP | |
2511 | .set_affinity = set_msi_irq_affinity, | |
2512 | #endif | |
2513 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
2514 | }; |
2515 | ||
f7feaca7 | 2516 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
3b7d1921 EB |
2517 | { |
2518 | struct msi_msg msg; | |
f7feaca7 EB |
2519 | int irq, ret; |
2520 | irq = create_irq(); | |
2521 | if (irq < 0) | |
2522 | return irq; | |
2523 | ||
3b7d1921 | 2524 | ret = msi_compose_msg(dev, irq, &msg); |
f7feaca7 EB |
2525 | if (ret < 0) { |
2526 | destroy_irq(irq); | |
3b7d1921 | 2527 | return ret; |
f7feaca7 | 2528 | } |
3b7d1921 | 2529 | |
7fe3730d | 2530 | set_irq_msi(irq, desc); |
3b7d1921 EB |
2531 | write_msi_msg(irq, &msg); |
2532 | ||
a460e745 IM |
2533 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, |
2534 | "edge"); | |
3b7d1921 | 2535 | |
7fe3730d | 2536 | return 0; |
3b7d1921 EB |
2537 | } |
2538 | ||
2539 | void arch_teardown_msi_irq(unsigned int irq) | |
2540 | { | |
f7feaca7 | 2541 | destroy_irq(irq); |
3b7d1921 EB |
2542 | } |
2543 | ||
2d3fcc1c EB |
2544 | #endif /* CONFIG_PCI_MSI */ |
2545 | ||
8b955b0d EB |
2546 | /* |
2547 | * Hypertransport interrupt support | |
2548 | */ | |
2549 | #ifdef CONFIG_HT_IRQ | |
2550 | ||
2551 | #ifdef CONFIG_SMP | |
2552 | ||
2553 | static void target_ht_irq(unsigned int irq, unsigned int dest) | |
2554 | { | |
ec68307c EB |
2555 | struct ht_irq_msg msg; |
2556 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 2557 | |
ec68307c EB |
2558 | msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK); |
2559 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); | |
8b955b0d | 2560 | |
ec68307c EB |
2561 | msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest); |
2562 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); | |
8b955b0d | 2563 | |
ec68307c | 2564 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
2565 | } |
2566 | ||
2567 | static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask) | |
2568 | { | |
2569 | unsigned int dest; | |
2570 | cpumask_t tmp; | |
2571 | ||
2572 | cpus_and(tmp, mask, cpu_online_map); | |
2573 | if (cpus_empty(tmp)) | |
2574 | tmp = TARGET_CPUS; | |
2575 | ||
2576 | cpus_and(mask, tmp, CPU_MASK_ALL); | |
2577 | ||
2578 | dest = cpu_mask_to_apicid(mask); | |
2579 | ||
2580 | target_ht_irq(irq, dest); | |
9f0a5ba5 | 2581 | irq_desc[irq].affinity = mask; |
8b955b0d EB |
2582 | } |
2583 | #endif | |
2584 | ||
c37e108d | 2585 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
2586 | .name = "PCI-HT", |
2587 | .mask = mask_ht_irq, | |
2588 | .unmask = unmask_ht_irq, | |
2589 | .ack = ack_ioapic_irq, | |
2590 | #ifdef CONFIG_SMP | |
2591 | .set_affinity = set_ht_irq_affinity, | |
2592 | #endif | |
2593 | .retrigger = ioapic_retrigger_irq, | |
2594 | }; | |
2595 | ||
2596 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
2597 | { | |
2598 | int vector; | |
2599 | ||
2600 | vector = assign_irq_vector(irq); | |
2601 | if (vector >= 0) { | |
ec68307c | 2602 | struct ht_irq_msg msg; |
8b955b0d EB |
2603 | unsigned dest; |
2604 | cpumask_t tmp; | |
2605 | ||
2606 | cpus_clear(tmp); | |
2607 | cpu_set(vector >> 8, tmp); | |
2608 | dest = cpu_mask_to_apicid(tmp); | |
2609 | ||
ec68307c | 2610 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 2611 | |
ec68307c EB |
2612 | msg.address_lo = |
2613 | HT_IRQ_LOW_BASE | | |
8b955b0d EB |
2614 | HT_IRQ_LOW_DEST_ID(dest) | |
2615 | HT_IRQ_LOW_VECTOR(vector) | | |
2616 | ((INT_DEST_MODE == 0) ? | |
2617 | HT_IRQ_LOW_DM_PHYSICAL : | |
2618 | HT_IRQ_LOW_DM_LOGICAL) | | |
2619 | HT_IRQ_LOW_RQEOI_EDGE | | |
2620 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2621 | HT_IRQ_LOW_MT_FIXED : | |
2622 | HT_IRQ_LOW_MT_ARBITRATED) | | |
2623 | HT_IRQ_LOW_IRQ_MASKED; | |
2624 | ||
ec68307c | 2625 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 2626 | |
a460e745 IM |
2627 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
2628 | handle_edge_irq, "edge"); | |
8b955b0d EB |
2629 | } |
2630 | return vector; | |
2631 | } | |
2632 | #endif /* CONFIG_HT_IRQ */ | |
2633 | ||
1da177e4 LT |
2634 | /* -------------------------------------------------------------------------- |
2635 | ACPI-based IOAPIC Configuration | |
2636 | -------------------------------------------------------------------------- */ | |
2637 | ||
888ba6c6 | 2638 | #ifdef CONFIG_ACPI |
1da177e4 LT |
2639 | |
2640 | int __init io_apic_get_unique_id (int ioapic, int apic_id) | |
2641 | { | |
2642 | union IO_APIC_reg_00 reg_00; | |
2643 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
2644 | physid_mask_t tmp; | |
2645 | unsigned long flags; | |
2646 | int i = 0; | |
2647 | ||
2648 | /* | |
2649 | * The P4 platform supports up to 256 APIC IDs on two separate APIC | |
2650 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
2651 | * supports up to 16 on one shared APIC bus. | |
2652 | * | |
2653 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full | |
2654 | * advantage of new APIC bus architecture. | |
2655 | */ | |
2656 | ||
2657 | if (physids_empty(apic_id_map)) | |
2658 | apic_id_map = ioapic_phys_id_map(phys_cpu_present_map); | |
2659 | ||
2660 | spin_lock_irqsave(&ioapic_lock, flags); | |
2661 | reg_00.raw = io_apic_read(ioapic, 0); | |
2662 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2663 | ||
2664 | if (apic_id >= get_physical_broadcast()) { | |
2665 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
2666 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
2667 | apic_id = reg_00.bits.ID; | |
2668 | } | |
2669 | ||
2670 | /* | |
2671 | * Every APIC in a system must have a unique ID or we get lots of nice | |
2672 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2673 | */ | |
2674 | if (check_apicid_used(apic_id_map, apic_id)) { | |
2675 | ||
2676 | for (i = 0; i < get_physical_broadcast(); i++) { | |
2677 | if (!check_apicid_used(apic_id_map, i)) | |
2678 | break; | |
2679 | } | |
2680 | ||
2681 | if (i == get_physical_broadcast()) | |
2682 | panic("Max apic_id exceeded!\n"); | |
2683 | ||
2684 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
2685 | "trying %d\n", ioapic, apic_id, i); | |
2686 | ||
2687 | apic_id = i; | |
2688 | } | |
2689 | ||
2690 | tmp = apicid_to_cpu_present(apic_id); | |
2691 | physids_or(apic_id_map, apic_id_map, tmp); | |
2692 | ||
2693 | if (reg_00.bits.ID != apic_id) { | |
2694 | reg_00.bits.ID = apic_id; | |
2695 | ||
2696 | spin_lock_irqsave(&ioapic_lock, flags); | |
2697 | io_apic_write(ioapic, 0, reg_00.raw); | |
2698 | reg_00.raw = io_apic_read(ioapic, 0); | |
2699 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2700 | ||
2701 | /* Sanity check */ | |
6070f9ec AD |
2702 | if (reg_00.bits.ID != apic_id) { |
2703 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
2704 | return -1; | |
2705 | } | |
1da177e4 LT |
2706 | } |
2707 | ||
2708 | apic_printk(APIC_VERBOSE, KERN_INFO | |
2709 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
2710 | ||
2711 | return apic_id; | |
2712 | } | |
2713 | ||
2714 | ||
2715 | int __init io_apic_get_version (int ioapic) | |
2716 | { | |
2717 | union IO_APIC_reg_01 reg_01; | |
2718 | unsigned long flags; | |
2719 | ||
2720 | spin_lock_irqsave(&ioapic_lock, flags); | |
2721 | reg_01.raw = io_apic_read(ioapic, 1); | |
2722 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2723 | ||
2724 | return reg_01.bits.version; | |
2725 | } | |
2726 | ||
2727 | ||
2728 | int __init io_apic_get_redir_entries (int ioapic) | |
2729 | { | |
2730 | union IO_APIC_reg_01 reg_01; | |
2731 | unsigned long flags; | |
2732 | ||
2733 | spin_lock_irqsave(&ioapic_lock, flags); | |
2734 | reg_01.raw = io_apic_read(ioapic, 1); | |
2735 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2736 | ||
2737 | return reg_01.bits.entries; | |
2738 | } | |
2739 | ||
2740 | ||
2741 | int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low) | |
2742 | { | |
2743 | struct IO_APIC_route_entry entry; | |
1da177e4 LT |
2744 | |
2745 | if (!IO_APIC_IRQ(irq)) { | |
2746 | printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
2747 | ioapic); | |
2748 | return -EINVAL; | |
2749 | } | |
2750 | ||
2751 | /* | |
2752 | * Generate a PCI IRQ routing entry and program the IOAPIC accordingly. | |
2753 | * Note that we mask (disable) IRQs now -- these get enabled when the | |
2754 | * corresponding device driver registers for this IRQ. | |
2755 | */ | |
2756 | ||
2757 | memset(&entry,0,sizeof(entry)); | |
2758 | ||
2759 | entry.delivery_mode = INT_DELIVERY_MODE; | |
2760 | entry.dest_mode = INT_DEST_MODE; | |
2761 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); | |
2762 | entry.trigger = edge_level; | |
2763 | entry.polarity = active_high_low; | |
2764 | entry.mask = 1; | |
2765 | ||
2766 | /* | |
2767 | * IRQs < 16 are already in the irq_2_pin[] map | |
2768 | */ | |
2769 | if (irq >= 16) | |
2770 | add_pin_to_irq(irq, ioapic, pin); | |
2771 | ||
2772 | entry.vector = assign_irq_vector(irq); | |
2773 | ||
2774 | apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry " | |
2775 | "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic, | |
2776 | mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq, | |
2777 | edge_level, active_high_low); | |
2778 | ||
2779 | ioapic_register_intr(irq, entry.vector, edge_level); | |
2780 | ||
2781 | if (!ioapic && (irq < 16)) | |
2782 | disable_8259A_irq(irq); | |
2783 | ||
a2249cba | 2784 | ioapic_write_entry(ioapic, pin, entry); |
1da177e4 LT |
2785 | |
2786 | return 0; | |
2787 | } | |
2788 | ||
61fd47e0 SL |
2789 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
2790 | { | |
2791 | int i; | |
2792 | ||
2793 | if (skip_ioapic_setup) | |
2794 | return -1; | |
2795 | ||
2796 | for (i = 0; i < mp_irq_entries; i++) | |
2797 | if (mp_irqs[i].mpc_irqtype == mp_INT && | |
2798 | mp_irqs[i].mpc_srcbusirq == bus_irq) | |
2799 | break; | |
2800 | if (i >= mp_irq_entries) | |
2801 | return -1; | |
2802 | ||
2803 | *trigger = irq_trigger(i); | |
2804 | *polarity = irq_polarity(i); | |
2805 | return 0; | |
2806 | } | |
2807 | ||
888ba6c6 | 2808 | #endif /* CONFIG_ACPI */ |
1a3f239d RR |
2809 | |
2810 | static int __init parse_disable_timer_pin_1(char *arg) | |
2811 | { | |
2812 | disable_timer_pin_1 = 1; | |
2813 | return 0; | |
2814 | } | |
2815 | early_param("disable_timer_pin_1", parse_disable_timer_pin_1); | |
2816 | ||
2817 | static int __init parse_enable_timer_pin_1(char *arg) | |
2818 | { | |
2819 | disable_timer_pin_1 = -1; | |
2820 | return 0; | |
2821 | } | |
2822 | early_param("enable_timer_pin_1", parse_enable_timer_pin_1); | |
2823 | ||
2824 | static int __init parse_noapic(char *arg) | |
2825 | { | |
2826 | /* disable IO-APIC */ | |
2827 | disable_ioapic_setup(); | |
2828 | return 0; | |
2829 | } | |
2830 | early_param("noapic", parse_noapic); |