[mirror_ubuntu-artful-kernel.git] / arch / x86 / kernel / microcode_amd.c

/*
 *  AMD CPU Microcode Update Driver for Linux
 *  Copyright (C) 2008-2011 Advanced Micro Devices Inc.
 *
 *  Author: Peter Oruba <peter.oruba@amd.com>
 *
 *  Based on work by:
 *  Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
 *
 *  Maintainers:
 *  Andreas Herrmann <herrmann.der.user@googlemail.com>
 *  Borislav Petkov <bp@alien8.de>
 *
 *  This driver allows to upgrade microcode on F10h AMD
 *  CPUs and later.
 *
 *  Licensed under the terms of the GNU General Public
 *  License version 2. See file COPYING for details.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/firmware.h>
#include <linux/pci_ids.h>
#include <linux/uaccess.h>
#include <linux/vmalloc.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>

#include <asm/microcode.h>
#include <asm/processor.h>
#include <asm/msr.h>

MODULE_DESCRIPTION("AMD Microcode Update Driver");
MODULE_AUTHOR("Peter Oruba");
MODULE_LICENSE("GPL v2");

#define UCODE_MAGIC                0x00414d44
#define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
#define UCODE_UCODE_TYPE           0x00000001

struct equiv_cpu_entry {
	u32	installed_cpu;
	u32	fixed_errata_mask;
	u32	fixed_errata_compare;
	u16	equiv_cpu;
	u16	res;
} __attribute__((packed));

struct microcode_header_amd {
	u32	data_code;
	u32	patch_id;
	u16	mc_patch_data_id;
	u8	mc_patch_data_len;
	u8	init_flag;
	u32	mc_patch_data_checksum;
	u32	nb_dev_id;
	u32	sb_dev_id;
	u16	processor_rev_id;
	u8	nb_rev_id;
	u8	sb_rev_id;
	u8	bios_api_rev;
	u8	reserved1[3];
	u32	match_reg[8];
} __attribute__((packed));

struct microcode_amd {
	struct microcode_header_amd	hdr;
	unsigned int			mpb[0];
};

#define SECTION_HDR_SIZE	8
#define CONTAINER_HDR_SZ	12

static struct equiv_cpu_entry *equiv_cpu_table;

struct ucode_patch {
	struct list_head plist;
	void *data;
	u32 patch_id;
	u16 equiv_cpu;
};

static LIST_HEAD(pcache);

static u16 find_equiv_id(unsigned int cpu)
{
	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
	int i = 0;

	if (!equiv_cpu_table)
		return 0;

	while (equiv_cpu_table[i].installed_cpu != 0) {
		if (uci->cpu_sig.sig == equiv_cpu_table[i].installed_cpu)
			return equiv_cpu_table[i].equiv_cpu;

		i++;
	}
	return 0;
}

static u32 find_cpu_family_by_equiv_cpu(u16 equiv_cpu)
{
	int i = 0;

	BUG_ON(!equiv_cpu_table);

	while (equiv_cpu_table[i].equiv_cpu != 0) {
		if (equiv_cpu == equiv_cpu_table[i].equiv_cpu)
			return equiv_cpu_table[i].installed_cpu;
		i++;
	}
	return 0;
}

/*
 * a small, trivial cache of per-family ucode patches
 */
static struct ucode_patch *cache_find_patch(u16 equiv_cpu)
{
	struct ucode_patch *p;

	list_for_each_entry(p, &pcache, plist)
		if (p->equiv_cpu == equiv_cpu)
			return p;
	return NULL;
}

static void update_cache(struct ucode_patch *new_patch)
{
	struct ucode_patch *p;

	list_for_each_entry(p, &pcache, plist) {
		if (p->equiv_cpu == new_patch->equiv_cpu) {
			if (p->patch_id >= new_patch->patch_id)
				/* we already have the latest patch */
				return;

			list_replace(&p->plist, &new_patch->plist);
			kfree(p->data);
			kfree(p);
			return;
		}
	}
	/* no patch found, add it */
	list_add_tail(&new_patch->plist, &pcache);
}

static void free_cache(void)
{
	struct ucode_patch *p, *tmp;

	list_for_each_entry_safe(p, tmp, &pcache, plist) {
		__list_del(p->plist.prev, p->plist.next);
		kfree(p->data);
		kfree(p);
	}
}

static struct ucode_patch *find_patch(unsigned int cpu)
{
	u16 equiv_id;

	equiv_id = find_equiv_id(cpu);
	if (!equiv_id)
		return NULL;

	return cache_find_patch(equiv_id);
}

static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
{
	struct cpuinfo_x86 *c = &cpu_data(cpu);

	csig->sig = cpuid_eax(0x00000001);
	csig->rev = c->microcode;
	pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);

	return 0;
}

static unsigned int verify_patch_size(int cpu, u32 patch_size,
				      unsigned int size)
{
	struct cpuinfo_x86 *c = &cpu_data(cpu);
	u32 max_size;

#define F1XH_MPB_MAX_SIZE 2048
#define F14H_MPB_MAX_SIZE 1824
#define F15H_MPB_MAX_SIZE 4096

	switch (c->x86) {
	case 0x14:
		max_size = F14H_MPB_MAX_SIZE;
		break;
	case 0x15:
		max_size = F15H_MPB_MAX_SIZE;
		break;
	default:
		max_size = F1XH_MPB_MAX_SIZE;
		break;
	}

	if (patch_size > min_t(u32, size, max_size)) {
		pr_err("patch size mismatch\n");
		return 0;
	}

	return patch_size;
}

static int apply_microcode_amd(int cpu)
{
	struct cpuinfo_x86 *c = &cpu_data(cpu);
	struct microcode_amd *mc_amd;
	struct ucode_cpu_info *uci;
	struct ucode_patch *p;
	u32 rev, dummy;

	BUG_ON(raw_smp_processor_id() != cpu);

	uci = ucode_cpu_info + cpu;

	p = find_patch(cpu);
	if (!p)
		return 0;

	mc_amd  = p->data;
	uci->mc = p->data;

	rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);

	/* need to apply patch? */
	if (rev >= mc_amd->hdr.patch_id) {
		c->microcode = rev;
		return 0;
	}

	wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);

	/* verify patch application was successful */
	rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
	if (rev != mc_amd->hdr.patch_id) {
		pr_err("CPU%d: update failed for patch_level=0x%08x\n",
		       cpu, mc_amd->hdr.patch_id);
		return -1;
	}

	pr_info("CPU%d: new patch_level=0x%08x\n", cpu, rev);
	uci->cpu_sig.rev = rev;
	c->microcode = rev;

	return 0;
}

static int install_equiv_cpu_table(const u8 *buf)
{
	unsigned int *ibuf = (unsigned int *)buf;
	unsigned int type = ibuf[1];
	unsigned int size = ibuf[2];

	if (type != UCODE_EQUIV_CPU_TABLE_TYPE || !size) {
		pr_err("empty section/"
		       "invalid type field in container file section header\n");
		return -EINVAL;
	}

	equiv_cpu_table = vmalloc(size);
	if (!equiv_cpu_table) {
		pr_err("failed to allocate equivalent CPU table\n");
		return -ENOMEM;
	}

	memcpy(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size);

	/* add header length */
	return size + CONTAINER_HDR_SZ;
}

static void free_equiv_cpu_table(void)
{
	vfree(equiv_cpu_table);
	equiv_cpu_table = NULL;
}

static void cleanup(void)
{
	free_equiv_cpu_table();
	free_cache();
}

/*
 * We return the current size even if some of the checks failed so that
 * we can skip over the next patch. If we return a negative value, we
 * signal a grave error like a memory allocation has failed and the
 * driver cannot continue functioning normally. In such cases, we tear
 * down everything we've used up so far and exit.
 */
static int verify_and_add_patch(unsigned int cpu, u8 *fw, unsigned int leftover)
{
	struct cpuinfo_x86 *c = &cpu_data(cpu);
	struct microcode_header_amd *mc_hdr;
	struct ucode_patch *patch;
	unsigned int patch_size, crnt_size, ret;
	u32 proc_fam;
	u16 proc_id;

	patch_size  = *(u32 *)(fw + 4);
	crnt_size   = patch_size + SECTION_HDR_SIZE;
	mc_hdr	    = (struct microcode_header_amd *)(fw + SECTION_HDR_SIZE);
	proc_id	    = mc_hdr->processor_rev_id;

	proc_fam = find_cpu_family_by_equiv_cpu(proc_id);
	if (!proc_fam) {
		pr_err("No patch family for equiv ID: 0x%04x\n", proc_id);
		return crnt_size;
	}

	/* check if patch is for the current family */
	proc_fam = ((proc_fam >> 8) & 0xf) + ((proc_fam >> 20) & 0xff);
	if (proc_fam != c->x86)
		return crnt_size;

	if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) {
		pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n",
			mc_hdr->patch_id);
		return crnt_size;
	}

	ret = verify_patch_size(cpu, patch_size, leftover);
	if (!ret) {
		pr_err("Patch-ID 0x%08x: size mismatch.\n", mc_hdr->patch_id);
		return crnt_size;
	}

	patch = kzalloc(sizeof(*patch), GFP_KERNEL);
	if (!patch) {
		pr_err("Patch allocation failure.\n");
		return -EINVAL;
	}

	patch->data = kzalloc(patch_size, GFP_KERNEL);
	if (!patch->data) {
		pr_err("Patch data allocation failure.\n");
		kfree(patch);
		return -EINVAL;
	}

	/* All looks ok, copy patch... */
	memcpy(patch->data, fw + SECTION_HDR_SIZE, patch_size);
	INIT_LIST_HEAD(&patch->plist);
	patch->patch_id  = mc_hdr->patch_id;
	patch->equiv_cpu = proc_id;

	/* ... and add to cache. */
	update_cache(patch);

	return crnt_size;
}

static enum ucode_state load_microcode_amd(int cpu, const u8 *data, size_t size)
{
	enum ucode_state ret = UCODE_ERROR;
	unsigned int leftover;
	u8 *fw = (u8 *)data;
	int crnt_size = 0;
	int offset;

	offset = install_equiv_cpu_table(data);
	if (offset < 0) {
		pr_err("failed to create equivalent cpu table\n");
		return ret;
	}
	fw += offset;
	leftover = size - offset;

	if (*(u32 *)fw != UCODE_UCODE_TYPE) {
		pr_err("invalid type field in container file section header\n");
		free_equiv_cpu_table();
		return ret;
	}

	while (leftover) {
		crnt_size = verify_and_add_patch(cpu, fw, leftover);
		if (crnt_size < 0)
			return ret;

		fw	 += crnt_size;
		leftover -= crnt_size;
	}

	return UCODE_OK;
}

/*
 * AMD microcode firmware naming convention, up to family 15h they are in
 * the legacy file:
 *
 *    amd-ucode/microcode_amd.bin
 *
 * This legacy file is always smaller than 2K in size.
 *
 * Beginning with family 15h, they are in family-specific firmware files:
 *
 *    amd-ucode/microcode_amd_fam15h.bin
 *    amd-ucode/microcode_amd_fam16h.bin
 *    ...
 *
 * These might be larger than 2K.
 */
static enum ucode_state request_microcode_amd(int cpu, struct device *device,
					      bool refresh_fw)
{
	char fw_name[36] = "amd-ucode/microcode_amd.bin";
	struct cpuinfo_x86 *c = &cpu_data(cpu);
	enum ucode_state ret = UCODE_NFOUND;
	const struct firmware *fw;

	/* reload ucode container only on the boot cpu */
	if (!refresh_fw || c->cpu_index != boot_cpu_data.cpu_index)
		return UCODE_OK;

	if (c->x86 >= 0x15)
		snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86);

	if (request_firmware(&fw, (const char *)fw_name, device)) {
		pr_err("failed to load file %s\n", fw_name);
		goto out;
	}

	ret = UCODE_ERROR;
	if (*(u32 *)fw->data != UCODE_MAGIC) {
		pr_err("invalid magic value (0x%08x)\n", *(u32 *)fw->data);
		goto fw_release;
	}

	/* free old equiv table */
	free_equiv_cpu_table();

	ret = load_microcode_amd(cpu, fw->data, fw->size);
	if (ret != UCODE_OK)
		cleanup();

 fw_release:
	release_firmware(fw);

 out:
	return ret;
}

static enum ucode_state
request_microcode_user(int cpu, const void __user *buf, size_t size)
{
	return UCODE_ERROR;
}

static void microcode_fini_cpu_amd(int cpu)
{
	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;

	uci->mc = NULL;
}

static struct microcode_ops microcode_amd_ops = {
	.request_microcode_user           = request_microcode_user,
	.request_microcode_fw             = request_microcode_amd,
	.collect_cpu_info                 = collect_cpu_info_amd,
	.apply_microcode                  = apply_microcode_amd,
	.microcode_fini_cpu               = microcode_fini_cpu_amd,
};

struct microcode_ops * __init init_amd_microcode(void)
{
	struct cpuinfo_x86 *c = &cpu_data(0);

	if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
		pr_warning("AMD CPU family 0x%x not supported\n", c->x86);
		return NULL;
	}

	return &microcode_amd_ops;
}

void __exit exit_amd_microcode(void)
{
	cleanup();
}
Commit	Line	Data
80cc9f10 PO	1	/*
80cc9f10 PO	2	* AMD CPU Microcode Update Driver for Linux
597e11a3	3	* Copyright (C) 2008-2011 Advanced Micro Devices Inc.
80cc9f10 PO	4	*
	5	* Author: Peter Oruba <peter.oruba@amd.com>
	6	*
	7	* Based on work by:
	8	* Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
	9	*
597e11a3	10	* Maintainers:
943482d0 AH	11	* Andreas Herrmann <herrmann.der.user@googlemail.com>
943482d0 AH	12	* Borislav Petkov <bp@alien8.de>
597e11a3 BP	13	*
	14	* This driver allows to upgrade microcode on F10h AMD
	15	* CPUs and later.
80cc9f10	16	*
2a3282a7	17	* Licensed under the terms of the GNU General Public
80cc9f10	18	* License version 2. See file COPYING for details.
4bae1967	19	*/
f58e1f53 JP	20
	21	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	22
4bae1967	23	#include <linux/firmware.h>
4bae1967 IM	24	#include <linux/pci_ids.h>
	25	#include <linux/uaccess.h>
	26	#include <linux/vmalloc.h>
	27	#include <linux/kernel.h>
	28	#include <linux/module.h>
80cc9f10	29	#include <linux/pci.h>
80cc9f10	30
80cc9f10	31	#include <asm/microcode.h>
4bae1967 IM	32	#include <asm/processor.h>
4bae1967 IM	33	#include <asm/msr.h>
80cc9f10 PO	34
80cc9f10 PO	35	MODULE_DESCRIPTION("AMD Microcode Update Driver");
3c52204b	36	MODULE_AUTHOR("Peter Oruba");
5d7b6052	37	MODULE_LICENSE("GPL v2");
80cc9f10 PO	38
	39	#define UCODE_MAGIC 0x00414d44
	40	#define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
	41	#define UCODE_UCODE_TYPE 0x00000001
	42
18dbc916	43	struct equiv_cpu_entry {
5549b94b AH	44	u32 installed_cpu;
	45	u32 fixed_errata_mask;
	46	u32 fixed_errata_compare;
	47	u16 equiv_cpu;
	48	u16 res;
	49	} __attribute__((packed));
18dbc916 DA	50
18dbc916 DA	51	struct microcode_header_amd {
5549b94b AH	52	u32 data_code;
	53	u32 patch_id;
	54	u16 mc_patch_data_id;
	55	u8 mc_patch_data_len;
	56	u8 init_flag;
	57	u32 mc_patch_data_checksum;
	58	u32 nb_dev_id;
	59	u32 sb_dev_id;
	60	u16 processor_rev_id;
	61	u8 nb_rev_id;
	62	u8 sb_rev_id;
	63	u8 bios_api_rev;
	64	u8 reserved1[3];
	65	u32 match_reg[8];
	66	} __attribute__((packed));
18dbc916 DA	67
18dbc916 DA	68	struct microcode_amd {
4bae1967 IM	69	struct microcode_header_amd hdr;
4bae1967 IM	70	unsigned int mpb[0];
18dbc916 DA	71	};
18dbc916 DA	72
40b7f3df BP	73	#define SECTION_HDR_SIZE 8
40b7f3df BP	74	#define CONTAINER_HDR_SZ 12
80cc9f10	75
a0a29b62	76	static struct equiv_cpu_entry *equiv_cpu_table;
80cc9f10	77
a3eb3b4d BP	78	struct ucode_patch {
	79	struct list_head plist;
	80	void *data;
	81	u32 patch_id;
	82	u16 equiv_cpu;
	83	};
	84
	85	static LIST_HEAD(pcache);
	86
c96d2c09 BP	87	static u16 find_equiv_id(unsigned int cpu)
	88	{
	89	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
	90	int i = 0;
	91
a3eb3b4d BP	92	if (!equiv_cpu_table)
a3eb3b4d BP	93	return 0;
c96d2c09 BP	94
	95	while (equiv_cpu_table[i].installed_cpu != 0) {
	96	if (uci->cpu_sig.sig == equiv_cpu_table[i].installed_cpu)
	97	return equiv_cpu_table[i].equiv_cpu;
	98
	99	i++;
	100	}
	101	return 0;
	102	}
	103
	104	static u32 find_cpu_family_by_equiv_cpu(u16 equiv_cpu)
	105	{
	106	int i = 0;
	107
	108	BUG_ON(!equiv_cpu_table);
	109
	110	while (equiv_cpu_table[i].equiv_cpu != 0) {
	111	if (equiv_cpu == equiv_cpu_table[i].equiv_cpu)
	112	return equiv_cpu_table[i].installed_cpu;
	113	i++;
	114	}
	115	return 0;
	116	}
	117
a3eb3b4d BP	118	/*
	119	* a small, trivial cache of per-family ucode patches
	120	*/
	121	static struct ucode_patch *cache_find_patch(u16 equiv_cpu)
	122	{
	123	struct ucode_patch *p;
	124
	125	list_for_each_entry(p, &pcache, plist)
	126	if (p->equiv_cpu == equiv_cpu)
	127	return p;
	128	return NULL;
	129	}
	130
	131	static void update_cache(struct ucode_patch *new_patch)
	132	{
	133	struct ucode_patch *p;
	134
	135	list_for_each_entry(p, &pcache, plist) {
	136	if (p->equiv_cpu == new_patch->equiv_cpu) {
	137	if (p->patch_id >= new_patch->patch_id)
	138	/* we already have the latest patch */
	139	return;
	140
	141	list_replace(&p->plist, &new_patch->plist);
	142	kfree(p->data);
	143	kfree(p);
	144	return;
	145	}
	146	}
	147	/* no patch found, add it */
	148	list_add_tail(&new_patch->plist, &pcache);
	149	}
	150
	151	static void free_cache(void)
	152	{
2d297480	153	struct ucode_patch p, tmp;
a3eb3b4d	154
2d297480	155	list_for_each_entry_safe(p, tmp, &pcache, plist) {
a3eb3b4d BP	156	__list_del(p->plist.prev, p->plist.next);
	157	kfree(p->data);
	158	kfree(p);
	159	}
	160	}
	161
	162	static struct ucode_patch *find_patch(unsigned int cpu)
	163	{
	164	u16 equiv_id;
	165
	166	equiv_id = find_equiv_id(cpu);
	167	if (!equiv_id)
	168	return NULL;
	169
	170	return cache_find_patch(equiv_id);
	171	}
	172
d45de409	173	static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
80cc9f10	174	{
3b2e3d85	175	struct cpuinfo_x86 *c = &cpu_data(cpu);
80cc9f10	176
5f5b7472	177	csig->sig = cpuid_eax(0x00000001);
bcb80e53	178	csig->rev = c->microcode;
258721ef BP	179	pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);
258721ef BP	180
d45de409	181	return 0;
80cc9f10 PO	182	}
80cc9f10 PO	183
2efb05e8	184	static unsigned int verify_patch_size(int cpu, u32 patch_size,
be62adb4	185	unsigned int size)
80cc9f10	186	{
be62adb4 BP	187	struct cpuinfo_x86 *c = &cpu_data(cpu);
	188	u32 max_size;
	189
	190	#define F1XH_MPB_MAX_SIZE 2048
	191	#define F14H_MPB_MAX_SIZE 1824
	192	#define F15H_MPB_MAX_SIZE 4096
	193
	194	switch (c->x86) {
	195	case 0x14:
	196	max_size = F14H_MPB_MAX_SIZE;
	197	break;
	198	case 0x15:
	199	max_size = F15H_MPB_MAX_SIZE;
	200	break;
	201	default:
	202	max_size = F1XH_MPB_MAX_SIZE;
	203	break;
	204	}
	205
	206	if (patch_size > min_t(u32, size, max_size)) {
	207	pr_err("patch size mismatch\n");
	208	return 0;
	209	}
	210
	211	return patch_size;
	212	}
	213
871b72dd	214	static int apply_microcode_amd(int cpu)
80cc9f10	215	{
bcb80e53	216	struct cpuinfo_x86 *c = &cpu_data(cpu);
2efb05e8 BP	217	struct microcode_amd *mc_amd;
	218	struct ucode_cpu_info *uci;
	219	struct ucode_patch *p;
	220	u32 rev, dummy;
	221
	222	BUG_ON(raw_smp_processor_id() != cpu);
80cc9f10	223
2efb05e8	224	uci = ucode_cpu_info + cpu;
80cc9f10	225
2efb05e8 BP	226	p = find_patch(cpu);
2efb05e8 BP	227	if (!p)
871b72dd	228	return 0;
80cc9f10	229
2efb05e8 BP	230	mc_amd = p->data;
	231	uci->mc = p->data;
	232
29d0887f	233	rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
80cc9f10	234
685ca6d7 BP	235	/* need to apply patch? */
	236	if (rev >= mc_amd->hdr.patch_id) {
	237	c->microcode = rev;
	238	return 0;
	239	}
	240
	241	wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);
	242
	243	/* verify patch application was successful */
	244	rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
18dbc916	245	if (rev != mc_amd->hdr.patch_id) {
258721ef	246	pr_err("CPU%d: update failed for patch_level=0x%08x\n",
f58e1f53	247	cpu, mc_amd->hdr.patch_id);
871b72dd	248	return -1;
80cc9f10 PO	249	}
80cc9f10 PO	250
258721ef	251	pr_info("CPU%d: new patch_level=0x%08x\n", cpu, rev);
d45de409	252	uci->cpu_sig.rev = rev;
bcb80e53	253	c->microcode = rev;
871b72dd DA	254
871b72dd DA	255	return 0;
80cc9f10 PO	256	}
80cc9f10 PO	257
0657d9eb	258	static int install_equiv_cpu_table(const u8 *buf)
80cc9f10	259	{
10de52d6 BP	260	unsigned int ibuf = (unsigned int )buf;
	261	unsigned int type = ibuf[1];
	262	unsigned int size = ibuf[2];
80cc9f10	263
10de52d6	264	if (type != UCODE_EQUIV_CPU_TABLE_TYPE \|\| !size) {
258721ef BP	265	pr_err("empty section/"
258721ef BP	266	"invalid type field in container file section header\n");
10de52d6	267	return -EINVAL;
80cc9f10 PO	268	}
80cc9f10 PO	269
8e5e9521	270	equiv_cpu_table = vmalloc(size);
80cc9f10	271	if (!equiv_cpu_table) {
f58e1f53	272	pr_err("failed to allocate equivalent CPU table\n");
10de52d6	273	return -ENOMEM;
80cc9f10 PO	274	}
80cc9f10 PO	275
e7e632f5	276	memcpy(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size);
80cc9f10	277
40b7f3df BP	278	/* add header length */
40b7f3df BP	279	return size + CONTAINER_HDR_SZ;
80cc9f10 PO	280	}
80cc9f10 PO	281
a0a29b62	282	static void free_equiv_cpu_table(void)
80cc9f10	283	{
aeef50bc F	284	vfree(equiv_cpu_table);
aeef50bc F	285	equiv_cpu_table = NULL;
a0a29b62	286	}
80cc9f10	287
2efb05e8	288	static void cleanup(void)
a0a29b62	289	{
2efb05e8 BP	290	free_equiv_cpu_table();
	291	free_cache();
	292	}
	293
	294	/*
	295	* We return the current size even if some of the checks failed so that
	296	* we can skip over the next patch. If we return a negative value, we
	297	* signal a grave error like a memory allocation has failed and the
	298	* driver cannot continue functioning normally. In such cases, we tear
	299	* down everything we've used up so far and exit.
	300	*/
	301	static int verify_and_add_patch(unsigned int cpu, u8 *fw, unsigned int leftover)
	302	{
	303	struct cpuinfo_x86 *c = &cpu_data(cpu);
	304	struct microcode_header_amd *mc_hdr;
	305	struct ucode_patch *patch;
	306	unsigned int patch_size, crnt_size, ret;
	307	u32 proc_fam;
	308	u16 proc_id;
	309
	310	patch_size = (u32 )(fw + 4);
	311	crnt_size = patch_size + SECTION_HDR_SIZE;
	312	mc_hdr = (struct microcode_header_amd *)(fw + SECTION_HDR_SIZE);
	313	proc_id = mc_hdr->processor_rev_id;
	314
	315	proc_fam = find_cpu_family_by_equiv_cpu(proc_id);
	316	if (!proc_fam) {
	317	pr_err("No patch family for equiv ID: 0x%04x\n", proc_id);
	318	return crnt_size;
	319	}
	320
	321	/* check if patch is for the current family */
	322	proc_fam = ((proc_fam >> 8) & 0xf) + ((proc_fam >> 20) & 0xff);
	323	if (proc_fam != c->x86)
	324	return crnt_size;
	325
	326	if (mc_hdr->nb_dev_id \|\| mc_hdr->sb_dev_id) {
	327	pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n",
	328	mc_hdr->patch_id);
	329	return crnt_size;
	330	}
	331
	332	ret = verify_patch_size(cpu, patch_size, leftover);
	333	if (!ret) {
	334	pr_err("Patch-ID 0x%08x: size mismatch.\n", mc_hdr->patch_id);
	335	return crnt_size;
	336	}
	337
	338	patch = kzalloc(sizeof(*patch), GFP_KERNEL);
	339	if (!patch) {
	340	pr_err("Patch allocation failure.\n");
	341	return -EINVAL;
	342	}
	343
	344	patch->data = kzalloc(patch_size, GFP_KERNEL);
	345	if (!patch->data) {
	346	pr_err("Patch data allocation failure.\n");
	347	kfree(patch);
	348	return -EINVAL;
	349	}
	350
	351	/* All looks ok, copy patch... */
	352	memcpy(patch->data, fw + SECTION_HDR_SIZE, patch_size);
	353	INIT_LIST_HEAD(&patch->plist);
354	patch->patch_id = mc_hdr->patch_id;
355	patch->equiv_cpu = proc_id;
356
357	/* ... and add to cache. */
358	update_cache(patch);
359
360	return crnt_size;
361	}
362
363	static enum ucode_state load_microcode_amd(int cpu, const u8 *data, size_t size)
364	{
365	enum ucode_state ret = UCODE_ERROR;
366	unsigned int leftover;
367	u8 fw = (u8 )data;
368	int crnt_size = 0;
1396fa9c	369	int offset;
80cc9f10	370
2efb05e8	371	offset = install_equiv_cpu_table(data);
10de52d6	372	if (offset < 0) {
f58e1f53	373	pr_err("failed to create equivalent cpu table\n");
2efb05e8	374	return ret;
80cc9f10	375	}
2efb05e8	376	fw += offset;
a0a29b62 DA	377	leftover = size - offset;
a0a29b62 DA	378
2efb05e8	379	if ((u32 )fw != UCODE_UCODE_TYPE) {
be62adb4	380	pr_err("invalid type field in container file section header\n");
2efb05e8 BP	381	free_equiv_cpu_table();
2efb05e8 BP	382	return ret;
be62adb4	383	}
a0a29b62	384
be62adb4	385	while (leftover) {
2efb05e8 BP	386	crnt_size = verify_and_add_patch(cpu, fw, leftover);
	387	if (crnt_size < 0)
	388	return ret;
d733689a	389
2efb05e8 BP	390	fw += crnt_size;
2efb05e8 BP	391	leftover -= crnt_size;
80cc9f10	392	}
a0a29b62	393
2efb05e8	394	return UCODE_OK;
a0a29b62 DA	395	}
a0a29b62 DA	396
5b68edc9 AH	397	/*
	398	* AMD microcode firmware naming convention, up to family 15h they are in
	399	* the legacy file:
	400	*
	401	* amd-ucode/microcode_amd.bin
	402	*
	403	* This legacy file is always smaller than 2K in size.
	404	*
2efb05e8	405	* Beginning with family 15h, they are in family-specific firmware files:
5b68edc9 AH	406	*
	407	* amd-ucode/microcode_amd_fam15h.bin
	408	* amd-ucode/microcode_amd_fam16h.bin
	409	* ...
	410	*
	411	* These might be larger than 2K.
	412	*/
48e30685 BP	413	static enum ucode_state request_microcode_amd(int cpu, struct device *device,
48e30685 BP	414	bool refresh_fw)
a0a29b62	415	{
5b68edc9	416	char fw_name[36] = "amd-ucode/microcode_amd.bin";
5b68edc9	417	struct cpuinfo_x86 *c = &cpu_data(cpu);
2efb05e8 BP	418	enum ucode_state ret = UCODE_NFOUND;
	419	const struct firmware *fw;
	420
	421	/* reload ucode container only on the boot cpu */
	422	if (!refresh_fw \|\| c->cpu_index != boot_cpu_data.cpu_index)
	423	return UCODE_OK;
5b68edc9 AH	424
	425	if (c->x86 >= 0x15)
	426	snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86);
a0a29b62	427
5b68edc9	428	if (request_firmware(&fw, (const char *)fw_name, device)) {
258721ef	429	pr_err("failed to load file %s\n", fw_name);
ffc7e8ac	430	goto out;
3b2e3d85	431	}
a0a29b62	432
ffc7e8ac BP	433	ret = UCODE_ERROR;
ffc7e8ac BP	434	if ((u32 )fw->data != UCODE_MAGIC) {
258721ef	435	pr_err("invalid magic value (0x%08x)\n", (u32 )fw->data);
ffc7e8ac	436	goto fw_release;
506f90ee BP	437	}
506f90ee BP	438
2efb05e8 BP	439	/* free old equiv table */
	440	free_equiv_cpu_table();
	441
	442	ret = load_microcode_amd(cpu, fw->data, fw->size);
	443	if (ret != UCODE_OK)
	444	cleanup();
a0a29b62	445
2efb05e8	446	fw_release:
ffc7e8ac	447	release_firmware(fw);
3b2e3d85	448
2efb05e8	449	out:
a0a29b62 DA	450	return ret;
	451	}
	452
871b72dd DA	453	static enum ucode_state
871b72dd DA	454	request_microcode_user(int cpu, const void __user *buf, size_t size)
a0a29b62	455	{
871b72dd	456	return UCODE_ERROR;
80cc9f10 PO	457	}
80cc9f10 PO	458
80cc9f10 PO	459	static void microcode_fini_cpu_amd(int cpu)
	460	{
	461	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
	462
18dbc916	463	uci->mc = NULL;
80cc9f10 PO	464	}
	465
	466	static struct microcode_ops microcode_amd_ops = {
a0a29b62	467	.request_microcode_user = request_microcode_user,
ffc7e8ac	468	.request_microcode_fw = request_microcode_amd,
80cc9f10 PO	469	.collect_cpu_info = collect_cpu_info_amd,
	470	.apply_microcode = apply_microcode_amd,
	471	.microcode_fini_cpu = microcode_fini_cpu_amd,
	472	};
	473
18dbc916	474	struct microcode_ops * __init init_amd_microcode(void)
80cc9f10	475	{
283c1f25 AH	476	struct cpuinfo_x86 *c = &cpu_data(0);
	477
	478	if (c->x86_vendor != X86_VENDOR_AMD \|\| c->x86 < 0x10) {
	479	pr_warning("AMD CPU family 0x%x not supported\n", c->x86);
	480	return NULL;
	481	}
	482
18dbc916	483	return &microcode_amd_ops;
80cc9f10	484	}
f72c1a57 BP	485
	486	void __exit exit_amd_microcode(void)
	487	{
2efb05e8	488	cleanup();
f72c1a57	489	}