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x86/realmode: Add SEV-ES specific trampoline entry point
[mirror_ubuntu-jammy-kernel.git] / arch / x86 / kernel / sev-es.c
CommitLineData
f980f9c3
JR		 1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * AMD Memory Encryption Support
4 *
5 * Copyright (C) 2019 SUSE
6 *
7 * Author: Joerg Roedel <jroedel@suse.de>
8 */
9
0786138c
TL		 10#define pr_fmt(fmt) "SEV-ES: " fmt
11
1aa9aa8e 12#include <linux/sched/debug.h> /* For show_regs() */
885689e4
TL		 13#include <linux/percpu-defs.h>
14#include <linux/mem_encrypt.h>
0786138c 15#include <linux/lockdep.h>
1aa9aa8e 16#include <linux/printk.h>
885689e4
TL		 17#include <linux/mm_types.h>
18#include <linux/set_memory.h>
19#include <linux/memblock.h>
20#include <linux/kernel.h>
f980f9c3
JR		 21#include <linux/mm.h>
22
02772fb9 23#include <asm/cpu_entry_area.h>
f980f9c3
JR		 24#include <asm/sev-es.h>
25#include <asm/insn-eval.h>
26#include <asm/fpu/internal.h>
27#include <asm/processor.h>
0786138c
TL		 28#include <asm/realmode.h>
29#include <asm/traps.h>
f980f9c3
JR		 30#include <asm/svm.h>
31
479a7bf5
TL		 32#define DR7_RESET_VALUE 0x400
33
1aa9aa8e
JR		 34/* For early boot hypervisor communication in SEV-ES enabled guests */
35static struct ghcb boot_ghcb_page __bss_decrypted __aligned(PAGE_SIZE);
36
37/*
38 * Needs to be in the .data section because we need it NULL before bss is
39 * cleared
40 */
41static struct ghcb __initdata *boot_ghcb;
42
885689e4
TL		 43/* #VC handler runtime per-CPU data */
44struct sev_es_runtime_data {
45 struct ghcb ghcb_page;
02772fb9
JR		 46
47 /* Physical storage for the per-CPU IST stack of the #VC handler */
48 char ist_stack[EXCEPTION_STKSZ] __aligned(PAGE_SIZE);
49
50 /*
51 * Physical storage for the per-CPU fall-back stack of the #VC handler.
52 * The fall-back stack is used when it is not safe to switch back to the
53 * interrupted stack in the #VC entry code.
54 */
55 char fallback_stack[EXCEPTION_STKSZ] __aligned(PAGE_SIZE);
0786138c
TL		 56
57 /*
58 * Reserve one page per CPU as backup storage for the unencrypted GHCB.
59 * It is needed when an NMI happens while the #VC handler uses the real
60 * GHCB, and the NMI handler itself is causing another #VC exception. In
61 * that case the GHCB content of the first handler needs to be backed up
62 * and restored.
63 */
64 struct ghcb backup_ghcb;
65
66 /*
67 * Mark the per-cpu GHCBs as in-use to detect nested #VC exceptions.
68 * There is no need for it to be atomic, because nothing is written to
69 * the GHCB between the read and the write of ghcb_active. So it is safe
70 * to use it when a nested #VC exception happens before the write.
71 *
72 * This is necessary for example in the #VC->NMI->#VC case when the NMI
73 * happens while the first #VC handler uses the GHCB. When the NMI code
74 * raises a second #VC handler it might overwrite the contents of the
75 * GHCB written by the first handler. To avoid this the content of the
76 * GHCB is saved and restored when the GHCB is detected to be in use
77 * already.
78 */
79 bool ghcb_active;
80 bool backup_ghcb_active;
479a7bf5
TL		 81
82 /*
83 * Cached DR7 value - write it on DR7 writes and return it on reads.
84 * That value will never make it to the real hardware DR7 as debugging
85 * is currently unsupported in SEV-ES guests.
86 */
87 unsigned long dr7;
0786138c
TL		 88};
89
90struct ghcb_state {
91 struct ghcb *ghcb;
885689e4
TL		 92};
93
94static DEFINE_PER_CPU(struct sev_es_runtime_data*, runtime_data);
315562c9 95DEFINE_STATIC_KEY_FALSE(sev_es_enable_key);
885689e4 96
0786138c
TL		 97/* Needed in vc_early_forward_exception */
98void do_early_exception(struct pt_regs *regs, int trapnr);
99
02772fb9
JR		 100static void __init setup_vc_stacks(int cpu)
101{
102 struct sev_es_runtime_data *data;
103 struct cpu_entry_area *cea;
104 unsigned long vaddr;
105 phys_addr_t pa;
106
107 data = per_cpu(runtime_data, cpu);
108 cea = get_cpu_entry_area(cpu);
109
110 /* Map #VC IST stack */
111 vaddr = CEA_ESTACK_BOT(&cea->estacks, VC);
112 pa = __pa(data->ist_stack);
113 cea_set_pte((void *)vaddr, pa, PAGE_KERNEL);
114
115 /* Map VC fall-back stack */
116 vaddr = CEA_ESTACK_BOT(&cea->estacks, VC2);
117 pa = __pa(data->fallback_stack);
118 cea_set_pte((void *)vaddr, pa, PAGE_KERNEL);
119}
120
315562c9
JR		 121static __always_inline bool on_vc_stack(unsigned long sp)
122{
123 return ((sp >= __this_cpu_ist_bottom_va(VC)) && (sp < __this_cpu_ist_top_va(VC)));
124}
125
126/*
127 * This function handles the case when an NMI is raised in the #VC exception
128 * handler entry code. In this case, the IST entry for #VC must be adjusted, so
129 * that any subsequent #VC exception will not overwrite the stack contents of the
130 * interrupted #VC handler.
131 *
132 * The IST entry is adjusted unconditionally so that it can be also be
133 * unconditionally adjusted back in sev_es_ist_exit(). Otherwise a nested
134 * sev_es_ist_exit() call may adjust back the IST entry too early.
135 */
136void noinstr __sev_es_ist_enter(struct pt_regs *regs)
137{
138 unsigned long old_ist, new_ist;
139
140 /* Read old IST entry */
141 old_ist = __this_cpu_read(cpu_tss_rw.x86_tss.ist[IST_INDEX_VC]);
142
143 /* Make room on the IST stack */
144 if (on_vc_stack(regs->sp))
145 new_ist = ALIGN_DOWN(regs->sp, 8) - sizeof(old_ist);
146 else
147 new_ist = old_ist - sizeof(old_ist);
148
149 /* Store old IST entry */
150 *(unsigned long *)new_ist = old_ist;
151
152 /* Set new IST entry */
153 this_cpu_write(cpu_tss_rw.x86_tss.ist[IST_INDEX_VC], new_ist);
154}
155
156void noinstr __sev_es_ist_exit(void)
157{
158 unsigned long ist;
159
160 /* Read IST entry */
161 ist = __this_cpu_read(cpu_tss_rw.x86_tss.ist[IST_INDEX_VC]);
162
163 if (WARN_ON(ist == __this_cpu_ist_top_va(VC)))
164 return;
165
166 /* Read back old IST entry and write it to the TSS */
167 this_cpu_write(cpu_tss_rw.x86_tss.ist[IST_INDEX_VC], *(unsigned long *)ist);
168}
169
0786138c
TL		 170static __always_inline struct ghcb *sev_es_get_ghcb(struct ghcb_state *state)
171{
172 struct sev_es_runtime_data *data;
173 struct ghcb *ghcb;
174
175 data = this_cpu_read(runtime_data);
176 ghcb = &data->ghcb_page;
177
178 if (unlikely(data->ghcb_active)) {
179 /* GHCB is already in use - save its contents */
180
181 if (unlikely(data->backup_ghcb_active))
182 return NULL;
183
184 /* Mark backup_ghcb active before writing to it */
185 data->backup_ghcb_active = true;
186
187 state->ghcb = &data->backup_ghcb;
188
189 /* Backup GHCB content */
190 *state->ghcb = *ghcb;
191 } else {
192 state->ghcb = NULL;
193 data->ghcb_active = true;
194 }
195
196 return ghcb;
197}
198
199static __always_inline void sev_es_put_ghcb(struct ghcb_state *state)
200{
201 struct sev_es_runtime_data *data;
202 struct ghcb *ghcb;
203
204 data = this_cpu_read(runtime_data);
205 ghcb = &data->ghcb_page;
206
207 if (state->ghcb) {
208 /* Restore GHCB from Backup */
209 *ghcb = *state->ghcb;
210 data->backup_ghcb_active = false;
211 state->ghcb = NULL;
212 } else {
213 data->ghcb_active = false;
214 }
215}
1aa9aa8e 216
f980f9c3
JR		 217static inline u64 sev_es_rd_ghcb_msr(void)
218{
219 return __rdmsr(MSR_AMD64_SEV_ES_GHCB);
220}
221
222static inline void sev_es_wr_ghcb_msr(u64 val)
223{
224 u32 low, high;
225
226 low = (u32)(val);
227 high = (u32)(val >> 32);
228
229 native_wrmsr(MSR_AMD64_SEV_ES_GHCB, low, high);
230}
231
232static int vc_fetch_insn_kernel(struct es_em_ctxt *ctxt,
233 unsigned char *buffer)
234{
235 return copy_from_kernel_nofault(buffer, (unsigned char *)ctxt->regs->ip, MAX_INSN_SIZE);
236}
237
238static enum es_result vc_decode_insn(struct es_em_ctxt *ctxt)
239{
240 char buffer[MAX_INSN_SIZE];
241 enum es_result ret;
242 int res;
243
5e3427a7
JR		 244 if (user_mode(ctxt->regs)) {
245 res = insn_fetch_from_user(ctxt->regs, buffer);
246 if (!res) {
247 ctxt->fi.vector = X86_TRAP_PF;
248 ctxt->fi.error_code = X86_PF_INSTR | X86_PF_USER;
249 ctxt->fi.cr2 = ctxt->regs->ip;
250 return ES_EXCEPTION;
251 }
252
253 if (!insn_decode(&ctxt->insn, ctxt->regs, buffer, res))
254 return ES_DECODE_FAILED;
255 } else {
256 res = vc_fetch_insn_kernel(ctxt, buffer);
257 if (res) {
258 ctxt->fi.vector = X86_TRAP_PF;
259 ctxt->fi.error_code = X86_PF_INSTR;
260 ctxt->fi.cr2 = ctxt->regs->ip;
261 return ES_EXCEPTION;
262 }
263
264 insn_init(&ctxt->insn, buffer, MAX_INSN_SIZE - res, 1);
265 insn_get_length(&ctxt->insn);
f980f9c3
JR		 266 }
267
f980f9c3
JR		 268 ret = ctxt->insn.immediate.got ? ES_OK : ES_DECODE_FAILED;
269
270 return ret;
271}
272
273static enum es_result vc_write_mem(struct es_em_ctxt *ctxt,
274 char *dst, char *buf, size_t size)
275{
276 unsigned long error_code = X86_PF_PROT | X86_PF_WRITE;
277 char __user *target = (char __user *)dst;
278 u64 d8;
279 u32 d4;
280 u16 d2;
281 u8 d1;
282
283 switch (size) {
284 case 1:
285 memcpy(&d1, buf, 1);
286 if (put_user(d1, target))
287 goto fault;
288 break;
289 case 2:
290 memcpy(&d2, buf, 2);
291 if (put_user(d2, target))
292 goto fault;
293 break;
294 case 4:
295 memcpy(&d4, buf, 4);
296 if (put_user(d4, target))
297 goto fault;
298 break;
299 case 8:
300 memcpy(&d8, buf, 8);
301 if (put_user(d8, target))
302 goto fault;
303 break;
304 default:
305 WARN_ONCE(1, "%s: Invalid size: %zu\n", __func__, size);
306 return ES_UNSUPPORTED;
307 }
308
309 return ES_OK;
310
311fault:
312 if (user_mode(ctxt->regs))
313 error_code |= X86_PF_USER;
314
315 ctxt->fi.vector = X86_TRAP_PF;
316 ctxt->fi.error_code = error_code;
317 ctxt->fi.cr2 = (unsigned long)dst;
318
319 return ES_EXCEPTION;
320}
321
322static enum es_result vc_read_mem(struct es_em_ctxt *ctxt,
323 char *src, char *buf, size_t size)
324{
325 unsigned long error_code = X86_PF_PROT;
326 char __user *s = (char __user *)src;
327 u64 d8;
328 u32 d4;
329 u16 d2;
330 u8 d1;
331
332 switch (size) {
333 case 1:
334 if (get_user(d1, s))
335 goto fault;
336 memcpy(buf, &d1, 1);
337 break;
338 case 2:
339 if (get_user(d2, s))
340 goto fault;
341 memcpy(buf, &d2, 2);
342 break;
343 case 4:
344 if (get_user(d4, s))
345 goto fault;
346 memcpy(buf, &d4, 4);
347 break;
348 case 8:
349 if (get_user(d8, s))
350 goto fault;
351 memcpy(buf, &d8, 8);
352 break;
353 default:
354 WARN_ONCE(1, "%s: Invalid size: %zu\n", __func__, size);
355 return ES_UNSUPPORTED;
356 }
357
358 return ES_OK;
359
360fault:
361 if (user_mode(ctxt->regs))
362 error_code |= X86_PF_USER;
363
364 ctxt->fi.vector = X86_TRAP_PF;
365 ctxt->fi.error_code = error_code;
366 ctxt->fi.cr2 = (unsigned long)src;
367
368 return ES_EXCEPTION;
369}
370
51ee7d6e
TL		 371static bool vc_slow_virt_to_phys(struct ghcb *ghcb, struct es_em_ctxt *ctxt,
372 unsigned long vaddr, phys_addr_t *paddr)
373{
374 unsigned long va = (unsigned long)vaddr;
375 unsigned int level;
376 phys_addr_t pa;
377 pgd_t *pgd;
378 pte_t *pte;
379
380 pgd = __va(read_cr3_pa());
381 pgd = &pgd[pgd_index(va)];
382 pte = lookup_address_in_pgd(pgd, va, &level);
383 if (!pte) {
384 ctxt->fi.vector = X86_TRAP_PF;
385 ctxt->fi.cr2 = vaddr;
386 ctxt->fi.error_code = 0;
387
388 if (user_mode(ctxt->regs))
389 ctxt->fi.error_code |= X86_PF_USER;
390
391 return false;
392 }
393
394 pa = (phys_addr_t)pte_pfn(*pte) << PAGE_SHIFT;
395 pa |= va & ~page_level_mask(level);
396
397 *paddr = pa;
398
399 return true;
400}
401
f980f9c3
JR		 402/* Include code shared with pre-decompression boot stage */
403#include "sev-es-shared.c"
1aa9aa8e 404
a4afa608
TL		 405static enum es_result vc_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt)
406{
407 struct pt_regs *regs = ctxt->regs;
408 enum es_result ret;
409 u64 exit_info_1;
410
411 /* Is it a WRMSR? */
412 exit_info_1 = (ctxt->insn.opcode.bytes[1] == 0x30) ? 1 : 0;
413
414 ghcb_set_rcx(ghcb, regs->cx);
415 if (exit_info_1) {
416 ghcb_set_rax(ghcb, regs->ax);
417 ghcb_set_rdx(ghcb, regs->dx);
418 }
419
420 ret = sev_es_ghcb_hv_call(ghcb, ctxt, SVM_EXIT_MSR, exit_info_1, 0);
421
422 if ((ret == ES_OK) && (!exit_info_1)) {
423 regs->ax = ghcb->save.rax;
424 regs->dx = ghcb->save.rdx;
425 }
426
427 return ret;
428}
429
1aa9aa8e
JR		 430/*
431 * This function runs on the first #VC exception after the kernel
432 * switched to virtual addresses.
433 */
434static bool __init sev_es_setup_ghcb(void)
435{
436 /* First make sure the hypervisor talks a supported protocol. */
437 if (!sev_es_negotiate_protocol())
438 return false;
439
440 /*
441 * Clear the boot_ghcb. The first exception comes in before the bss
442 * section is cleared.
443 */
444 memset(&boot_ghcb_page, 0, PAGE_SIZE);
445
446 /* Alright - Make the boot-ghcb public */
447 boot_ghcb = &boot_ghcb_page;
448
449 return true;
450}
451
885689e4
TL		 452static void __init alloc_runtime_data(int cpu)
453{
454 struct sev_es_runtime_data *data;
455
456 data = memblock_alloc(sizeof(*data), PAGE_SIZE);
457 if (!data)
458 panic("Can't allocate SEV-ES runtime data");
459
460 per_cpu(runtime_data, cpu) = data;
461}
462
463static void __init init_ghcb(int cpu)
464{
465 struct sev_es_runtime_data *data;
466 int err;
467
468 data = per_cpu(runtime_data, cpu);
469
470 err = early_set_memory_decrypted((unsigned long)&data->ghcb_page,
471 sizeof(data->ghcb_page));
472 if (err)
473 panic("Can't map GHCBs unencrypted");
474
475 memset(&data->ghcb_page, 0, sizeof(data->ghcb_page));
0786138c
TL		 476
477 data->ghcb_active = false;
478 data->backup_ghcb_active = false;
885689e4
TL		 479}
480
481void __init sev_es_init_vc_handling(void)
482{
483 int cpu;
484
485 BUILD_BUG_ON(offsetof(struct sev_es_runtime_data, ghcb_page) % PAGE_SIZE);
486
487 if (!sev_es_active())
488 return;
489
315562c9
JR		 490 /* Enable SEV-ES special handling */
491 static_branch_enable(&sev_es_enable_key);
492
885689e4
TL		 493 /* Initialize per-cpu GHCB pages */
494 for_each_possible_cpu(cpu) {
495 alloc_runtime_data(cpu);
496 init_ghcb(cpu);
02772fb9 497 setup_vc_stacks(cpu);
885689e4 498 }
0786138c
TL		 499
500 /* Secondary CPUs use the runtime #VC handler */
501 initial_vc_handler = (unsigned long)safe_stack_exc_vmm_communication;
885689e4
TL		 502}
503
1aa9aa8e
JR		 504static void __init vc_early_forward_exception(struct es_em_ctxt *ctxt)
505{
506 int trapnr = ctxt->fi.vector;
507
508 if (trapnr == X86_TRAP_PF)
509 native_write_cr2(ctxt->fi.cr2);
510
511 ctxt->regs->orig_ax = ctxt->fi.error_code;
512 do_early_exception(ctxt->regs, trapnr);
513}
514
51ee7d6e
TL		 515static long *vc_insn_get_reg(struct es_em_ctxt *ctxt)
516{
517 long *reg_array;
518 int offset;
519
520 reg_array = (long *)ctxt->regs;
521 offset = insn_get_modrm_reg_off(&ctxt->insn, ctxt->regs);
522
523 if (offset < 0)
524 return NULL;
525
526 offset /= sizeof(long);
527
528 return reg_array + offset;
529}
530
479a7bf5
TL		 531static long *vc_insn_get_rm(struct es_em_ctxt *ctxt)
532{
533 long *reg_array;
534 int offset;
535
536 reg_array = (long *)ctxt->regs;
537 offset = insn_get_modrm_rm_off(&ctxt->insn, ctxt->regs);
538
539 if (offset < 0)
540 return NULL;
541
542 offset /= sizeof(long);
543
544 return reg_array + offset;
545}
51ee7d6e
TL		 546static enum es_result vc_do_mmio(struct ghcb *ghcb, struct es_em_ctxt *ctxt,
547 unsigned int bytes, bool read)
548{
549 u64 exit_code, exit_info_1, exit_info_2;
550 unsigned long ghcb_pa = __pa(ghcb);
551 phys_addr_t paddr;
552 void __user *ref;
553
554 ref = insn_get_addr_ref(&ctxt->insn, ctxt->regs);
555 if (ref == (void __user *)-1L)
556 return ES_UNSUPPORTED;
557
558 exit_code = read ? SVM_VMGEXIT_MMIO_READ : SVM_VMGEXIT_MMIO_WRITE;
559
560 if (!vc_slow_virt_to_phys(ghcb, ctxt, (unsigned long)ref, &paddr)) {
561 if (!read)
562 ctxt->fi.error_code |= X86_PF_WRITE;
563
564 return ES_EXCEPTION;
565 }
566
567 exit_info_1 = paddr;
568 /* Can never be greater than 8 */
569 exit_info_2 = bytes;
570
571 ghcb->save.sw_scratch = ghcb_pa + offsetof(struct ghcb, shared_buffer);
572
573 return sev_es_ghcb_hv_call(ghcb, ctxt, exit_code, exit_info_1, exit_info_2);
574}
575
576static enum es_result vc_handle_mmio_twobyte_ops(struct ghcb *ghcb,
577 struct es_em_ctxt *ctxt)
578{
579 struct insn *insn = &ctxt->insn;
580 unsigned int bytes = 0;
581 enum es_result ret;
582 int sign_byte;
583 long *reg_data;
584
585 switch (insn->opcode.bytes[1]) {
586 /* MMIO Read w/ zero-extension */
587 case 0xb6:
588 bytes = 1;
589 fallthrough;
590 case 0xb7:
591 if (!bytes)
592 bytes = 2;
593
594 ret = vc_do_mmio(ghcb, ctxt, bytes, true);
595 if (ret)
596 break;
597
598 /* Zero extend based on operand size */
599 reg_data = vc_insn_get_reg(ctxt);
600 if (!reg_data)
601 return ES_DECODE_FAILED;
602
603 memset(reg_data, 0, insn->opnd_bytes);
604
605 memcpy(reg_data, ghcb->shared_buffer, bytes);
606 break;
607
608 /* MMIO Read w/ sign-extension */
609 case 0xbe:
610 bytes = 1;
611 fallthrough;
612 case 0xbf:
613 if (!bytes)
614 bytes = 2;
615
616 ret = vc_do_mmio(ghcb, ctxt, bytes, true);
617 if (ret)
618 break;
619
620 /* Sign extend based on operand size */
621 reg_data = vc_insn_get_reg(ctxt);
622 if (!reg_data)
623 return ES_DECODE_FAILED;
624
625 if (bytes == 1) {
626 u8 *val = (u8 *)ghcb->shared_buffer;
627
628 sign_byte = (*val & 0x80) ? 0xff : 0x00;
629 } else {
630 u16 *val = (u16 *)ghcb->shared_buffer;
631
632 sign_byte = (*val & 0x8000) ? 0xff : 0x00;
633 }
634 memset(reg_data, sign_byte, insn->opnd_bytes);
635
636 memcpy(reg_data, ghcb->shared_buffer, bytes);
637 break;
638
639 default:
640 ret = ES_UNSUPPORTED;
641 }
642
643 return ret;
644}
645
0118b604
JR		 646/*
647 * The MOVS instruction has two memory operands, which raises the
648 * problem that it is not known whether the access to the source or the
649 * destination caused the #VC exception (and hence whether an MMIO read
650 * or write operation needs to be emulated).
651 *
652 * Instead of playing games with walking page-tables and trying to guess
653 * whether the source or destination is an MMIO range, split the move
654 * into two operations, a read and a write with only one memory operand.
655 * This will cause a nested #VC exception on the MMIO address which can
656 * then be handled.
657 *
658 * This implementation has the benefit that it also supports MOVS where
659 * source _and_ destination are MMIO regions.
660 *
661 * It will slow MOVS on MMIO down a lot, but in SEV-ES guests it is a
662 * rare operation. If it turns out to be a performance problem the split
663 * operations can be moved to memcpy_fromio() and memcpy_toio().
664 */
665static enum es_result vc_handle_mmio_movs(struct es_em_ctxt *ctxt,
666 unsigned int bytes)
667{
668 unsigned long ds_base, es_base;
669 unsigned char *src, *dst;
670 unsigned char buffer[8];
671 enum es_result ret;
672 bool rep;
673 int off;
674
675 ds_base = insn_get_seg_base(ctxt->regs, INAT_SEG_REG_DS);
676 es_base = insn_get_seg_base(ctxt->regs, INAT_SEG_REG_ES);
677
678 if (ds_base == -1L || es_base == -1L) {
679 ctxt->fi.vector = X86_TRAP_GP;
680 ctxt->fi.error_code = 0;
681 return ES_EXCEPTION;
682 }
683
684 src = ds_base + (unsigned char *)ctxt->regs->si;
685 dst = es_base + (unsigned char *)ctxt->regs->di;
686
687 ret = vc_read_mem(ctxt, src, buffer, bytes);
688 if (ret != ES_OK)
689 return ret;
690
691 ret = vc_write_mem(ctxt, dst, buffer, bytes);
692 if (ret != ES_OK)
693 return ret;
694
695 if (ctxt->regs->flags & X86_EFLAGS_DF)
696 off = -bytes;
697 else
698 off = bytes;
699
700 ctxt->regs->si += off;
701 ctxt->regs->di += off;
702
703 rep = insn_has_rep_prefix(&ctxt->insn);
704 if (rep)
705 ctxt->regs->cx -= 1;
706
707 if (!rep || ctxt->regs->cx == 0)
708 return ES_OK;
709 else
710 return ES_RETRY;
711}
712
51ee7d6e
TL		 713static enum es_result vc_handle_mmio(struct ghcb *ghcb,
714 struct es_em_ctxt *ctxt)
715{
716 struct insn *insn = &ctxt->insn;
717 unsigned int bytes = 0;
718 enum es_result ret;
719 long *reg_data;
720
721 switch (insn->opcode.bytes[0]) {
722 /* MMIO Write */
723 case 0x88:
724 bytes = 1;
725 fallthrough;
726 case 0x89:
727 if (!bytes)
728 bytes = insn->opnd_bytes;
729
730 reg_data = vc_insn_get_reg(ctxt);
731 if (!reg_data)
732 return ES_DECODE_FAILED;
733
734 memcpy(ghcb->shared_buffer, reg_data, bytes);
735
736 ret = vc_do_mmio(ghcb, ctxt, bytes, false);
737 break;
738
739 case 0xc6:
740 bytes = 1;
741 fallthrough;
742 case 0xc7:
743 if (!bytes)
744 bytes = insn->opnd_bytes;
745
746 memcpy(ghcb->shared_buffer, insn->immediate1.bytes, bytes);
747
748 ret = vc_do_mmio(ghcb, ctxt, bytes, false);
749 break;
750
751 /* MMIO Read */
752 case 0x8a:
753 bytes = 1;
754 fallthrough;
755 case 0x8b:
756 if (!bytes)
757 bytes = insn->opnd_bytes;
758
759 ret = vc_do_mmio(ghcb, ctxt, bytes, true);
760 if (ret)
761 break;
762
763 reg_data = vc_insn_get_reg(ctxt);
764 if (!reg_data)
765 return ES_DECODE_FAILED;
766
767 /* Zero-extend for 32-bit operation */
768 if (bytes == 4)
769 *reg_data = 0;
770
771 memcpy(reg_data, ghcb->shared_buffer, bytes);
772 break;
773
0118b604
JR		 774 /* MOVS instruction */
775 case 0xa4:
776 bytes = 1;
777 fallthrough;
778 case 0xa5:
779 if (!bytes)
780 bytes = insn->opnd_bytes;
781
782 ret = vc_handle_mmio_movs(ctxt, bytes);
783 break;
51ee7d6e
TL		 784 /* Two-Byte Opcodes */
785 case 0x0f:
786 ret = vc_handle_mmio_twobyte_ops(ghcb, ctxt);
787 break;
788 default:
789 ret = ES_UNSUPPORTED;
790 }
791
792 return ret;
793}
794
479a7bf5
TL		 795static enum es_result vc_handle_dr7_write(struct ghcb *ghcb,
796 struct es_em_ctxt *ctxt)
797{
798 struct sev_es_runtime_data *data = this_cpu_read(runtime_data);
799 long val, *reg = vc_insn_get_rm(ctxt);
800 enum es_result ret;
801
802 if (!reg)
803 return ES_DECODE_FAILED;
804
805 val = *reg;
806
807 /* Upper 32 bits must be written as zeroes */
808 if (val >> 32) {
809 ctxt->fi.vector = X86_TRAP_GP;
810 ctxt->fi.error_code = 0;
811 return ES_EXCEPTION;
812 }
813
814 /* Clear out other reserved bits and set bit 10 */
815 val = (val & 0xffff23ffL) | BIT(10);
816
817 /* Early non-zero writes to DR7 are not supported */
818 if (!data && (val & ~DR7_RESET_VALUE))
819 return ES_UNSUPPORTED;
820
821 /* Using a value of 0 for ExitInfo1 means RAX holds the value */
822 ghcb_set_rax(ghcb, val);
823 ret = sev_es_ghcb_hv_call(ghcb, ctxt, SVM_EXIT_WRITE_DR7, 0, 0);
824 if (ret != ES_OK)
825 return ret;
826
827 if (data)
828 data->dr7 = val;
829
830 return ES_OK;
831}
832
833static enum es_result vc_handle_dr7_read(struct ghcb *ghcb,
834 struct es_em_ctxt *ctxt)
835{
836 struct sev_es_runtime_data *data = this_cpu_read(runtime_data);
837 long *reg = vc_insn_get_rm(ctxt);
838
839 if (!reg)
840 return ES_DECODE_FAILED;
841
842 if (data)
843 *reg = data->dr7;
844 else
845 *reg = DR7_RESET_VALUE;
846
847 return ES_OK;
848}
849
a14a92fc
TL		 850static enum es_result vc_handle_wbinvd(struct ghcb *ghcb,
851 struct es_em_ctxt *ctxt)
852{
853 return sev_es_ghcb_hv_call(ghcb, ctxt, SVM_EXIT_WBINVD, 0, 0);
854}
855
5d55cf78
TL		 856static enum es_result vc_handle_rdpmc(struct ghcb *ghcb, struct es_em_ctxt *ctxt)
857{
858 enum es_result ret;
859
860 ghcb_set_rcx(ghcb, ctxt->regs->cx);
861
862 ret = sev_es_ghcb_hv_call(ghcb, ctxt, SVM_EXIT_RDPMC, 0, 0);
863 if (ret != ES_OK)
864 return ret;
865
866 if (!(ghcb_rax_is_valid(ghcb) && ghcb_rdx_is_valid(ghcb)))
867 return ES_VMM_ERROR;
868
869 ctxt->regs->ax = ghcb->save.rax;
870 ctxt->regs->dx = ghcb->save.rdx;
871
872 return ES_OK;
873}
874
0c2fd2ef
TL		 875static enum es_result vc_handle_monitor(struct ghcb *ghcb,
876 struct es_em_ctxt *ctxt)
877{
878 /*
879 * Treat it as a NOP and do not leak a physical address to the
880 * hypervisor.
881 */
882 return ES_OK;
883}
884
ded476bb
TL		 885static enum es_result vc_handle_mwait(struct ghcb *ghcb,
886 struct es_em_ctxt *ctxt)
887{
888 /* Treat the same as MONITOR/MONITORX */
889 return ES_OK;
890}
891
2eb7dcf0
TL		 892static enum es_result vc_handle_vmmcall(struct ghcb *ghcb,
893 struct es_em_ctxt *ctxt)
894{
895 enum es_result ret;
896
897 ghcb_set_rax(ghcb, ctxt->regs->ax);
898 ghcb_set_cpl(ghcb, user_mode(ctxt->regs) ? 3 : 0);
899
f6a9f8a4
JR		 900 if (x86_platform.hyper.sev_es_hcall_prepare)
901 x86_platform.hyper.sev_es_hcall_prepare(ghcb, ctxt->regs);
902
2eb7dcf0
TL		 903 ret = sev_es_ghcb_hv_call(ghcb, ctxt, SVM_EXIT_VMMCALL, 0, 0);
904 if (ret != ES_OK)
905 return ret;
906
907 if (!ghcb_rax_is_valid(ghcb))
908 return ES_VMM_ERROR;
909
910 ctxt->regs->ax = ghcb->save.rax;
911
f6a9f8a4
JR		 912 /*
913 * Call sev_es_hcall_finish() after regs->ax is already set.
914 * This allows the hypervisor handler to overwrite it again if
915 * necessary.
916 */
917 if (x86_platform.hyper.sev_es_hcall_finish &&
918 !x86_platform.hyper.sev_es_hcall_finish(ghcb, ctxt->regs))
919 return ES_VMM_ERROR;
920
2eb7dcf0
TL		 921 return ES_OK;
922}
923
a2d0171a
JR		 924static enum es_result vc_handle_trap_ac(struct ghcb *ghcb,
925 struct es_em_ctxt *ctxt)
926{
927 /*
928 * Calling ecx_alignment_check() directly does not work, because it
929 * enables IRQs and the GHCB is active. Forward the exception and call
930 * it later from vc_forward_exception().
931 */
932 ctxt->fi.vector = X86_TRAP_AC;
933 ctxt->fi.error_code = 0;
934 return ES_EXCEPTION;
935}
936
cb1ad3ec
JR		 937static __always_inline void vc_handle_trap_db(struct pt_regs *regs)
938{
939 if (user_mode(regs))
940 noist_exc_debug(regs);
941 else
942 exc_debug(regs);
943}
944
1aa9aa8e
JR		 945static enum es_result vc_handle_exitcode(struct es_em_ctxt *ctxt,
946 struct ghcb *ghcb,
947 unsigned long exit_code)
948{
949 enum es_result result;
950
951 switch (exit_code) {
479a7bf5
TL		 952 case SVM_EXIT_READ_DR7:
953 result = vc_handle_dr7_read(ghcb, ctxt);
954 break;
955 case SVM_EXIT_WRITE_DR7:
956 result = vc_handle_dr7_write(ghcb, ctxt);
957 break;
a2d0171a
JR		 958 case SVM_EXIT_EXCP_BASE + X86_TRAP_AC:
959 result = vc_handle_trap_ac(ghcb, ctxt);
960 break;
4711e7ac
TL		 961 case SVM_EXIT_RDTSC:
962 case SVM_EXIT_RDTSCP:
963 result = vc_handle_rdtsc(ghcb, ctxt, exit_code);
964 break;
5d55cf78
TL		 965 case SVM_EXIT_RDPMC:
966 result = vc_handle_rdpmc(ghcb, ctxt);
967 break;
8b4ce837
TL		 968 case SVM_EXIT_INVD:
969 pr_err_ratelimited("#VC exception for INVD??? Seriously???\n");
970 result = ES_UNSUPPORTED;
971 break;
d3529bb7
JR		 972 case SVM_EXIT_CPUID:
973 result = vc_handle_cpuid(ghcb, ctxt);
974 break;
975 case SVM_EXIT_IOIO:
976 result = vc_handle_ioio(ghcb, ctxt);
977 break;
a4afa608
TL		 978 case SVM_EXIT_MSR:
979 result = vc_handle_msr(ghcb, ctxt);
980 break;
2eb7dcf0
TL		 981 case SVM_EXIT_VMMCALL:
982 result = vc_handle_vmmcall(ghcb, ctxt);
983 break;
a14a92fc
TL		 984 case SVM_EXIT_WBINVD:
985 result = vc_handle_wbinvd(ghcb, ctxt);
986 break;
0c2fd2ef
TL		 987 case SVM_EXIT_MONITOR:
988 result = vc_handle_monitor(ghcb, ctxt);
989 break;
ded476bb
TL		 990 case SVM_EXIT_MWAIT:
991 result = vc_handle_mwait(ghcb, ctxt);
992 break;
51ee7d6e
TL		 993 case SVM_EXIT_NPF:
994 result = vc_handle_mmio(ghcb, ctxt);
995 break;
1aa9aa8e
JR		 996 default:
997 /*
998 * Unexpected #VC exception
999 */
1000 result = ES_UNSUPPORTED;
1001 }
1002
1003 return result;
1004}
1005
0786138c
TL		 1006static __always_inline void vc_forward_exception(struct es_em_ctxt *ctxt)
1007{
1008 long error_code = ctxt->fi.error_code;
1009 int trapnr = ctxt->fi.vector;
1010
1011 ctxt->regs->orig_ax = ctxt->fi.error_code;
1012
1013 switch (trapnr) {
1014 case X86_TRAP_GP:
1015 exc_general_protection(ctxt->regs, error_code);
1016 break;
1017 case X86_TRAP_UD:
1018 exc_invalid_op(ctxt->regs);
1019 break;
a2d0171a
JR		 1020 case X86_TRAP_AC:
1021 exc_alignment_check(ctxt->regs, error_code);
1022 break;
0786138c
TL		 1023 default:
1024 pr_emerg("Unsupported exception in #VC instruction emulation - can't continue\n");
1025 BUG();
1026 }
1027}
1028
1029static __always_inline bool on_vc_fallback_stack(struct pt_regs *regs)
1030{
1031 unsigned long sp = (unsigned long)regs;
1032
1033 return (sp >= __this_cpu_ist_bottom_va(VC2) && sp < __this_cpu_ist_top_va(VC2));
1034}
1035
1036/*
1037 * Main #VC exception handler. It is called when the entry code was able to
1038 * switch off the IST to a safe kernel stack.
1039 *
1040 * With the current implementation it is always possible to switch to a safe
1041 * stack because #VC exceptions only happen at known places, like intercepted
1042 * instructions or accesses to MMIO areas/IO ports. They can also happen with
1043 * code instrumentation when the hypervisor intercepts #DB, but the critical
1044 * paths are forbidden to be instrumented, so #DB exceptions currently also
1045 * only happen in safe places.
1046 */
1047DEFINE_IDTENTRY_VC_SAFE_STACK(exc_vmm_communication)
1048{
1049 struct sev_es_runtime_data *data = this_cpu_read(runtime_data);
1050 struct ghcb_state state;
1051 struct es_em_ctxt ctxt;
1052 enum es_result result;
1053 struct ghcb *ghcb;
1054
1055 lockdep_assert_irqs_disabled();
cb1ad3ec
JR		 1056
1057 /*
1058 * Handle #DB before calling into !noinstr code to avoid recursive #DB.
1059 */
1060 if (error_code == SVM_EXIT_EXCP_BASE + X86_TRAP_DB) {
1061 vc_handle_trap_db(regs);
1062 return;
1063 }
1064
0786138c
TL		 1065 instrumentation_begin();
1066
1067 /*
1068 * This is invoked through an interrupt gate, so IRQs are disabled. The
1069 * code below might walk page-tables for user or kernel addresses, so
1070 * keep the IRQs disabled to protect us against concurrent TLB flushes.
1071 */
1072
1073 ghcb = sev_es_get_ghcb(&state);
1074 if (!ghcb) {
1075 /*
1076 * Mark GHCBs inactive so that panic() is able to print the
1077 * message.
1078 */
1079 data->ghcb_active = false;
1080 data->backup_ghcb_active = false;
1081
1082 panic("Unable to handle #VC exception! GHCB and Backup GHCB are already in use");
1083 }
1084
1085 vc_ghcb_invalidate(ghcb);
1086 result = vc_init_em_ctxt(&ctxt, regs, error_code);
1087
1088 if (result == ES_OK)
1089 result = vc_handle_exitcode(&ctxt, ghcb, error_code);
1090
1091 sev_es_put_ghcb(&state);
1092
1093 /* Done - now check the result */
1094 switch (result) {
1095 case ES_OK:
1096 vc_finish_insn(&ctxt);
1097 break;
1098 case ES_UNSUPPORTED:
1099 pr_err_ratelimited("Unsupported exit-code 0x%02lx in early #VC exception (IP: 0x%lx)\n",
1100 error_code, regs->ip);
1101 goto fail;
1102 case ES_VMM_ERROR:
1103 pr_err_ratelimited("Failure in communication with VMM (exit-code 0x%02lx IP: 0x%lx)\n",
1104 error_code, regs->ip);
1105 goto fail;
1106 case ES_DECODE_FAILED:
1107 pr_err_ratelimited("Failed to decode instruction (exit-code 0x%02lx IP: 0x%lx)\n",
1108 error_code, regs->ip);
1109 goto fail;
1110 case ES_EXCEPTION:
1111 vc_forward_exception(&ctxt);
1112 break;
1113 case ES_RETRY:
1114 /* Nothing to do */
1115 break;
1116 default:
1117 pr_emerg("Unknown result in %s():%d\n", __func__, result);
1118 /*
1119 * Emulating the instruction which caused the #VC exception
1120 * failed - can't continue so print debug information
1121 */
1122 BUG();
1123 }
1124
1125out:
1126 instrumentation_end();
1127
1128 return;
1129
1130fail:
1131 if (user_mode(regs)) {
1132 /*
1133 * Do not kill the machine if user-space triggered the
1134 * exception. Send SIGBUS instead and let user-space deal with
1135 * it.
1136 */
1137 force_sig_fault(SIGBUS, BUS_OBJERR, (void __user *)0);
1138 } else {
1139 pr_emerg("PANIC: Unhandled #VC exception in kernel space (result=%d)\n",
1140 result);
1141
1142 /* Show some debug info */
1143 show_regs(regs);
1144
1145 /* Ask hypervisor to sev_es_terminate */
1146 sev_es_terminate(GHCB_SEV_ES_REASON_GENERAL_REQUEST);
1147
1148 /* If that fails and we get here - just panic */
1149 panic("Returned from Terminate-Request to Hypervisor\n");
1150 }
1151
1152 goto out;
1153}
1154
1155/* This handler runs on the #VC fall-back stack. It can cause further #VC exceptions */
1156DEFINE_IDTENTRY_VC_IST(exc_vmm_communication)
1157{
1158 instrumentation_begin();
1159 panic("Can't handle #VC exception from unsupported context\n");
1160 instrumentation_end();
1161}
1162
1163DEFINE_IDTENTRY_VC(exc_vmm_communication)
1164{
1165 if (likely(!on_vc_fallback_stack(regs)))
1166 safe_stack_exc_vmm_communication(regs, error_code);
1167 else
1168 ist_exc_vmm_communication(regs, error_code);
1169}
1170
1aa9aa8e
JR		 1171bool __init handle_vc_boot_ghcb(struct pt_regs *regs)
1172{
1173 unsigned long exit_code = regs->orig_ax;
1174 struct es_em_ctxt ctxt;
1175 enum es_result result;
1176
1177 /* Do initial setup or terminate the guest */
1178 if (unlikely(boot_ghcb == NULL && !sev_es_setup_ghcb()))
1179 sev_es_terminate(GHCB_SEV_ES_REASON_GENERAL_REQUEST);
1180
1181 vc_ghcb_invalidate(boot_ghcb);
1182
1183 result = vc_init_em_ctxt(&ctxt, regs, exit_code);
1184 if (result == ES_OK)
1185 result = vc_handle_exitcode(&ctxt, boot_ghcb, exit_code);
1186
1187 /* Done - now check the result */
1188 switch (result) {
1189 case ES_OK:
1190 vc_finish_insn(&ctxt);
1191 break;
1192 case ES_UNSUPPORTED:
1193 early_printk("PANIC: Unsupported exit-code 0x%02lx in early #VC exception (IP: 0x%lx)\n",
1194 exit_code, regs->ip);
1195 goto fail;
1196 case ES_VMM_ERROR:
1197 early_printk("PANIC: Failure in communication with VMM (exit-code 0x%02lx IP: 0x%lx)\n",
1198 exit_code, regs->ip);
1199 goto fail;
1200 case ES_DECODE_FAILED:
1201 early_printk("PANIC: Failed to decode instruction (exit-code 0x%02lx IP: 0x%lx)\n",
1202 exit_code, regs->ip);
1203 goto fail;
1204 case ES_EXCEPTION:
1205 vc_early_forward_exception(&ctxt);
1206 break;
1207 case ES_RETRY:
1208 /* Nothing to do */
1209 break;
1210 default:
1211 BUG();
1212 }
1213
1214 return true;
1215
1216fail:
1217 show_regs(regs);
1218
1219 while (true)
1220 halt();
1221}
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