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Commit | Line | Data |
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c767a54b | 1 | /* |
4cedb334 GOC |
2 | * x86 SMP booting functions |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 5 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
4cedb334 GOC |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
c767a54b JP |
42 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
43 | ||
68a1c3f8 GC |
44 | #include <linux/init.h> |
45 | #include <linux/smp.h> | |
a355352b | 46 | #include <linux/module.h> |
70708a18 | 47 | #include <linux/sched.h> |
69c18c15 | 48 | #include <linux/percpu.h> |
91718e8d | 49 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
50 | #include <linux/err.h> |
51 | #include <linux/nmi.h> | |
69575d38 | 52 | #include <linux/tboot.h> |
35f720c5 | 53 | #include <linux/stackprotector.h> |
5a0e3ad6 | 54 | #include <linux/gfp.h> |
1a022e3f | 55 | #include <linux/cpuidle.h> |
69c18c15 | 56 | |
8aef135c | 57 | #include <asm/acpi.h> |
cb3c8b90 | 58 | #include <asm/desc.h> |
69c18c15 GC |
59 | #include <asm/nmi.h> |
60 | #include <asm/irq.h> | |
07bbc16a | 61 | #include <asm/idle.h> |
48927bbb | 62 | #include <asm/realmode.h> |
69c18c15 GC |
63 | #include <asm/cpu.h> |
64 | #include <asm/numa.h> | |
cb3c8b90 GOC |
65 | #include <asm/pgtable.h> |
66 | #include <asm/tlbflush.h> | |
67 | #include <asm/mtrr.h> | |
ea530692 | 68 | #include <asm/mwait.h> |
7b6aa335 | 69 | #include <asm/apic.h> |
7167d08e | 70 | #include <asm/io_apic.h> |
644c1541 VP |
71 | #include <asm/i387.h> |
72 | #include <asm/fpu-internal.h> | |
569712b2 | 73 | #include <asm/setup.h> |
bdbcdd48 | 74 | #include <asm/uv/uv.h> |
cb3c8b90 | 75 | #include <linux/mc146818rtc.h> |
b81bb373 | 76 | #include <asm/i8259.h> |
48927bbb | 77 | #include <asm/realmode.h> |
646e29a1 | 78 | #include <asm/misc.h> |
48927bbb | 79 | |
a8db8453 GOC |
80 | /* State of each CPU */ |
81 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
82 | ||
a355352b GC |
83 | /* Number of siblings per CPU package */ |
84 | int smp_num_siblings = 1; | |
85 | EXPORT_SYMBOL(smp_num_siblings); | |
86 | ||
87 | /* Last level cache ID of each logical CPU */ | |
0816b0f0 | 88 | DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; |
a355352b | 89 | |
a355352b | 90 | /* representing HT siblings of each logical CPU */ |
0816b0f0 | 91 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); |
a355352b GC |
92 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
93 | ||
94 | /* representing HT and core siblings of each logical CPU */ | |
0816b0f0 | 95 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); |
a355352b GC |
96 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
97 | ||
0816b0f0 | 98 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); |
b3d7336d | 99 | |
a355352b | 100 | /* Per CPU bogomips and other parameters */ |
2c773dd3 | 101 | DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); |
a355352b | 102 | EXPORT_PER_CPU_SYMBOL(cpu_info); |
768d9505 | 103 | |
2b6163bf | 104 | atomic_t init_deasserted; |
cb3c8b90 | 105 | |
f77aa308 TG |
106 | static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) |
107 | { | |
108 | unsigned long flags; | |
109 | ||
110 | spin_lock_irqsave(&rtc_lock, flags); | |
111 | CMOS_WRITE(0xa, 0xf); | |
112 | spin_unlock_irqrestore(&rtc_lock, flags); | |
113 | local_flush_tlb(); | |
114 | pr_debug("1.\n"); | |
115 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = | |
116 | start_eip >> 4; | |
117 | pr_debug("2.\n"); | |
118 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = | |
119 | start_eip & 0xf; | |
120 | pr_debug("3.\n"); | |
121 | } | |
122 | ||
123 | static inline void smpboot_restore_warm_reset_vector(void) | |
124 | { | |
125 | unsigned long flags; | |
126 | ||
127 | /* | |
128 | * Install writable page 0 entry to set BIOS data area. | |
129 | */ | |
130 | local_flush_tlb(); | |
131 | ||
132 | /* | |
133 | * Paranoid: Set warm reset code and vector here back | |
134 | * to default values. | |
135 | */ | |
136 | spin_lock_irqsave(&rtc_lock, flags); | |
137 | CMOS_WRITE(0, 0xf); | |
138 | spin_unlock_irqrestore(&rtc_lock, flags); | |
139 | ||
140 | *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; | |
141 | } | |
142 | ||
cb3c8b90 | 143 | /* |
30106c17 FY |
144 | * Report back to the Boot Processor during boot time or to the caller processor |
145 | * during CPU online. | |
cb3c8b90 | 146 | */ |
148f9bb8 | 147 | static void smp_callin(void) |
cb3c8b90 GOC |
148 | { |
149 | int cpuid, phys_id; | |
cb3c8b90 GOC |
150 | |
151 | /* | |
152 | * If waken up by an INIT in an 82489DX configuration | |
153 | * we may get here before an INIT-deassert IPI reaches | |
154 | * our local APIC. We have to wait for the IPI or we'll | |
155 | * lock up on an APIC access. | |
e1c467e6 FY |
156 | * |
157 | * Since CPU0 is not wakened up by INIT, it doesn't wait for the IPI. | |
cb3c8b90 | 158 | */ |
e1c467e6 | 159 | cpuid = smp_processor_id(); |
465822cf DR |
160 | if (apic->wait_for_init_deassert && cpuid) |
161 | while (!atomic_read(&init_deasserted)) | |
162 | cpu_relax(); | |
cb3c8b90 GOC |
163 | |
164 | /* | |
165 | * (This works even if the APIC is not enabled.) | |
166 | */ | |
4c9961d5 | 167 | phys_id = read_apic_id(); |
cb3c8b90 GOC |
168 | |
169 | /* | |
170 | * the boot CPU has finished the init stage and is spinning | |
171 | * on callin_map until we finish. We are free to set up this | |
172 | * CPU, first the APIC. (this is probably redundant on most | |
173 | * boards) | |
174 | */ | |
05f7e46d | 175 | apic_ap_setup(); |
cb3c8b90 | 176 | |
9d133e5d SS |
177 | /* |
178 | * Need to setup vector mappings before we enable interrupts. | |
179 | */ | |
36e9e1ea | 180 | setup_vector_irq(smp_processor_id()); |
b565201c JS |
181 | |
182 | /* | |
183 | * Save our processor parameters. Note: this information | |
184 | * is needed for clock calibration. | |
185 | */ | |
186 | smp_store_cpu_info(cpuid); | |
187 | ||
cb3c8b90 GOC |
188 | /* |
189 | * Get our bogomips. | |
b565201c JS |
190 | * Update loops_per_jiffy in cpu_data. Previous call to |
191 | * smp_store_cpu_info() stored a value that is close but not as | |
192 | * accurate as the value just calculated. | |
cb3c8b90 | 193 | */ |
cb3c8b90 | 194 | calibrate_delay(); |
b565201c | 195 | cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; |
cfc1b9a6 | 196 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 | 197 | |
5ef428c4 AK |
198 | /* |
199 | * This must be done before setting cpu_online_mask | |
200 | * or calling notify_cpu_starting. | |
201 | */ | |
202 | set_cpu_sibling_map(raw_smp_processor_id()); | |
203 | wmb(); | |
204 | ||
85257024 PZ |
205 | notify_cpu_starting(cpuid); |
206 | ||
cb3c8b90 GOC |
207 | /* |
208 | * Allow the master to continue. | |
209 | */ | |
c2d1cec1 | 210 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
211 | } |
212 | ||
e1c467e6 FY |
213 | static int cpu0_logical_apicid; |
214 | static int enable_start_cpu0; | |
bbc2ff6a GOC |
215 | /* |
216 | * Activate a secondary processor. | |
217 | */ | |
148f9bb8 | 218 | static void notrace start_secondary(void *unused) |
bbc2ff6a GOC |
219 | { |
220 | /* | |
221 | * Don't put *anything* before cpu_init(), SMP booting is too | |
222 | * fragile that we want to limit the things done here to the | |
223 | * most necessary things. | |
224 | */ | |
b40827fa | 225 | cpu_init(); |
df156f90 | 226 | x86_cpuinit.early_percpu_clock_init(); |
b40827fa BP |
227 | preempt_disable(); |
228 | smp_callin(); | |
fd89a137 | 229 | |
e1c467e6 FY |
230 | enable_start_cpu0 = 0; |
231 | ||
fd89a137 | 232 | #ifdef CONFIG_X86_32 |
b40827fa | 233 | /* switch away from the initial page table */ |
fd89a137 JR |
234 | load_cr3(swapper_pg_dir); |
235 | __flush_tlb_all(); | |
236 | #endif | |
237 | ||
bbc2ff6a GOC |
238 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ |
239 | barrier(); | |
240 | /* | |
241 | * Check TSC synchronization with the BP: | |
242 | */ | |
243 | check_tsc_sync_target(); | |
244 | ||
3891a04a PA |
245 | /* |
246 | * Enable the espfix hack for this CPU | |
247 | */ | |
197725de | 248 | #ifdef CONFIG_X86_ESPFIX64 |
3891a04a PA |
249 | init_espfix_ap(); |
250 | #endif | |
251 | ||
bbc2ff6a | 252 | /* |
d388e5fd EB |
253 | * We need to hold vector_lock so there the set of online cpus |
254 | * does not change while we are assigning vectors to cpus. Holding | |
255 | * this lock ensures we don't half assign or remove an irq from a cpu. | |
bbc2ff6a | 256 | */ |
d388e5fd | 257 | lock_vector_lock(); |
c2d1cec1 | 258 | set_cpu_online(smp_processor_id(), true); |
d388e5fd | 259 | unlock_vector_lock(); |
bbc2ff6a | 260 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
78c06176 | 261 | x86_platform.nmi_init(); |
bbc2ff6a | 262 | |
0cefa5b9 MS |
263 | /* enable local interrupts */ |
264 | local_irq_enable(); | |
265 | ||
35f720c5 JP |
266 | /* to prevent fake stack check failure in clock setup */ |
267 | boot_init_stack_canary(); | |
0cefa5b9 | 268 | |
736decac | 269 | x86_cpuinit.setup_percpu_clockev(); |
bbc2ff6a GOC |
270 | |
271 | wmb(); | |
7d1a9417 | 272 | cpu_startup_entry(CPUHP_ONLINE); |
bbc2ff6a GOC |
273 | } |
274 | ||
30106c17 FY |
275 | void __init smp_store_boot_cpu_info(void) |
276 | { | |
277 | int id = 0; /* CPU 0 */ | |
278 | struct cpuinfo_x86 *c = &cpu_data(id); | |
279 | ||
280 | *c = boot_cpu_data; | |
281 | c->cpu_index = id; | |
282 | } | |
283 | ||
1d89a7f0 GOC |
284 | /* |
285 | * The bootstrap kernel entry code has set these up. Save them for | |
286 | * a given CPU | |
287 | */ | |
148f9bb8 | 288 | void smp_store_cpu_info(int id) |
1d89a7f0 GOC |
289 | { |
290 | struct cpuinfo_x86 *c = &cpu_data(id); | |
291 | ||
b3d7336d | 292 | *c = boot_cpu_data; |
1d89a7f0 | 293 | c->cpu_index = id; |
30106c17 FY |
294 | /* |
295 | * During boot time, CPU0 has this setup already. Save the info when | |
296 | * bringing up AP or offlined CPU0. | |
297 | */ | |
298 | identify_secondary_cpu(c); | |
1d89a7f0 GOC |
299 | } |
300 | ||
cebf15eb DH |
301 | static bool |
302 | topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
303 | { | |
304 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
305 | ||
306 | return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); | |
307 | } | |
308 | ||
148f9bb8 | 309 | static bool |
316ad248 | 310 | topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) |
d4fbe4f0 | 311 | { |
316ad248 PZ |
312 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
313 | ||
cebf15eb | 314 | return !WARN_ONCE(!topology_same_node(c, o), |
316ad248 PZ |
315 | "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " |
316 | "[node: %d != %d]. Ignoring dependency.\n", | |
317 | cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); | |
318 | } | |
319 | ||
320 | #define link_mask(_m, c1, c2) \ | |
321 | do { \ | |
322 | cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \ | |
323 | cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \ | |
324 | } while (0) | |
325 | ||
148f9bb8 | 326 | static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 | 327 | { |
193f3fcb | 328 | if (cpu_has_topoext) { |
316ad248 PZ |
329 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
330 | ||
331 | if (c->phys_proc_id == o->phys_proc_id && | |
332 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) && | |
333 | c->compute_unit_id == o->compute_unit_id) | |
334 | return topology_sane(c, o, "smt"); | |
335 | ||
336 | } else if (c->phys_proc_id == o->phys_proc_id && | |
337 | c->cpu_core_id == o->cpu_core_id) { | |
338 | return topology_sane(c, o, "smt"); | |
339 | } | |
340 | ||
341 | return false; | |
342 | } | |
343 | ||
148f9bb8 | 344 | static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 PZ |
345 | { |
346 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
347 | ||
348 | if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && | |
349 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) | |
350 | return topology_sane(c, o, "llc"); | |
351 | ||
352 | return false; | |
d4fbe4f0 AH |
353 | } |
354 | ||
cebf15eb DH |
355 | /* |
356 | * Unlike the other levels, we do not enforce keeping a | |
357 | * multicore group inside a NUMA node. If this happens, we will | |
358 | * discard the MC level of the topology later. | |
359 | */ | |
360 | static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
316ad248 | 361 | { |
cebf15eb DH |
362 | if (c->phys_proc_id == o->phys_proc_id) |
363 | return true; | |
316ad248 PZ |
364 | return false; |
365 | } | |
1d89a7f0 | 366 | |
cebf15eb DH |
367 | static struct sched_domain_topology_level numa_inside_package_topology[] = { |
368 | #ifdef CONFIG_SCHED_SMT | |
369 | { cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) }, | |
370 | #endif | |
371 | #ifdef CONFIG_SCHED_MC | |
372 | { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) }, | |
373 | #endif | |
374 | { NULL, }, | |
375 | }; | |
376 | /* | |
377 | * set_sched_topology() sets the topology internal to a CPU. The | |
378 | * NUMA topologies are layered on top of it to build the full | |
379 | * system topology. | |
380 | * | |
381 | * If NUMA nodes are observed to occur within a CPU package, this | |
382 | * function should be called. It forces the sched domain code to | |
383 | * only use the SMT level for the CPU portion of the topology. | |
384 | * This essentially falls back to relying on NUMA information | |
385 | * from the SRAT table to describe the entire system topology | |
386 | * (except for hyperthreads). | |
387 | */ | |
388 | static void primarily_use_numa_for_topology(void) | |
389 | { | |
390 | set_sched_topology(numa_inside_package_topology); | |
391 | } | |
392 | ||
148f9bb8 | 393 | void set_cpu_sibling_map(int cpu) |
768d9505 | 394 | { |
316ad248 | 395 | bool has_smt = smp_num_siblings > 1; |
b0bc225d | 396 | bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; |
768d9505 | 397 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
316ad248 PZ |
398 | struct cpuinfo_x86 *o; |
399 | int i; | |
768d9505 | 400 | |
c2d1cec1 | 401 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 | 402 | |
b0bc225d | 403 | if (!has_mp) { |
c2d1cec1 | 404 | cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); |
316ad248 PZ |
405 | cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); |
406 | cpumask_set_cpu(cpu, cpu_core_mask(cpu)); | |
768d9505 GC |
407 | c->booted_cores = 1; |
408 | return; | |
409 | } | |
410 | ||
c2d1cec1 | 411 | for_each_cpu(i, cpu_sibling_setup_mask) { |
316ad248 PZ |
412 | o = &cpu_data(i); |
413 | ||
414 | if ((i == cpu) || (has_smt && match_smt(c, o))) | |
415 | link_mask(sibling, cpu, i); | |
416 | ||
b0bc225d | 417 | if ((i == cpu) || (has_mp && match_llc(c, o))) |
316ad248 PZ |
418 | link_mask(llc_shared, cpu, i); |
419 | ||
ceb1cbac KB |
420 | } |
421 | ||
422 | /* | |
423 | * This needs a separate iteration over the cpus because we rely on all | |
424 | * cpu_sibling_mask links to be set-up. | |
425 | */ | |
426 | for_each_cpu(i, cpu_sibling_setup_mask) { | |
427 | o = &cpu_data(i); | |
428 | ||
cebf15eb | 429 | if ((i == cpu) || (has_mp && match_die(c, o))) { |
316ad248 PZ |
430 | link_mask(core, cpu, i); |
431 | ||
768d9505 GC |
432 | /* |
433 | * Does this new cpu bringup a new core? | |
434 | */ | |
c2d1cec1 | 435 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { |
768d9505 GC |
436 | /* |
437 | * for each core in package, increment | |
438 | * the booted_cores for this new cpu | |
439 | */ | |
c2d1cec1 | 440 | if (cpumask_first(cpu_sibling_mask(i)) == i) |
768d9505 GC |
441 | c->booted_cores++; |
442 | /* | |
443 | * increment the core count for all | |
444 | * the other cpus in this package | |
445 | */ | |
446 | if (i != cpu) | |
447 | cpu_data(i).booted_cores++; | |
448 | } else if (i != cpu && !c->booted_cores) | |
449 | c->booted_cores = cpu_data(i).booted_cores; | |
450 | } | |
728e5653 | 451 | if (match_die(c, o) && !topology_same_node(c, o)) |
cebf15eb | 452 | primarily_use_numa_for_topology(); |
768d9505 GC |
453 | } |
454 | } | |
455 | ||
70708a18 | 456 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 457 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 | 458 | { |
9f646389 | 459 | return cpu_llc_shared_mask(cpu); |
030bb203 RR |
460 | } |
461 | ||
a4928cff | 462 | static void impress_friends(void) |
904541e2 GOC |
463 | { |
464 | int cpu; | |
465 | unsigned long bogosum = 0; | |
466 | /* | |
467 | * Allow the user to impress friends. | |
468 | */ | |
c767a54b | 469 | pr_debug("Before bogomips\n"); |
904541e2 | 470 | for_each_possible_cpu(cpu) |
c2d1cec1 | 471 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 | 472 | bogosum += cpu_data(cpu).loops_per_jiffy; |
c767a54b | 473 | pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", |
f68e00a3 | 474 | num_online_cpus(), |
904541e2 GOC |
475 | bogosum/(500000/HZ), |
476 | (bogosum/(5000/HZ))%100); | |
477 | ||
c767a54b | 478 | pr_debug("Before bogocount - setting activated=1\n"); |
904541e2 GOC |
479 | } |
480 | ||
569712b2 | 481 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
482 | { |
483 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
a6c23905 | 484 | const char * const names[] = { "ID", "VERSION", "SPIV" }; |
cb3c8b90 GOC |
485 | int timeout; |
486 | u32 status; | |
487 | ||
c767a54b | 488 | pr_info("Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
489 | |
490 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
c767a54b | 491 | pr_info("... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
492 | |
493 | /* | |
494 | * Wait for idle. | |
495 | */ | |
496 | status = safe_apic_wait_icr_idle(); | |
497 | if (status) | |
c767a54b | 498 | pr_cont("a previous APIC delivery may have failed\n"); |
cb3c8b90 | 499 | |
1b374e4d | 500 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
501 | |
502 | timeout = 0; | |
503 | do { | |
504 | udelay(100); | |
505 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
506 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
507 | ||
508 | switch (status) { | |
509 | case APIC_ICR_RR_VALID: | |
510 | status = apic_read(APIC_RRR); | |
c767a54b | 511 | pr_cont("%08x\n", status); |
cb3c8b90 GOC |
512 | break; |
513 | default: | |
c767a54b | 514 | pr_cont("failed\n"); |
cb3c8b90 GOC |
515 | } |
516 | } | |
517 | } | |
518 | ||
cb3c8b90 GOC |
519 | /* |
520 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
521 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
522 | * won't ... remember to clear down the APIC, etc later. | |
523 | */ | |
148f9bb8 | 524 | int |
e1c467e6 | 525 | wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) |
cb3c8b90 GOC |
526 | { |
527 | unsigned long send_status, accept_status = 0; | |
528 | int maxlvt; | |
529 | ||
530 | /* Target chip */ | |
cb3c8b90 GOC |
531 | /* Boot on the stack */ |
532 | /* Kick the second */ | |
e1c467e6 | 533 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); |
cb3c8b90 | 534 | |
cfc1b9a6 | 535 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
536 | send_status = safe_apic_wait_icr_idle(); |
537 | ||
538 | /* | |
539 | * Give the other CPU some time to accept the IPI. | |
540 | */ | |
541 | udelay(200); | |
569712b2 | 542 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
59ef48a5 CG |
543 | maxlvt = lapic_get_maxlvt(); |
544 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
545 | apic_write(APIC_ESR, 0); | |
546 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
547 | } | |
c767a54b | 548 | pr_debug("NMI sent\n"); |
cb3c8b90 GOC |
549 | |
550 | if (send_status) | |
c767a54b | 551 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 552 | if (accept_status) |
c767a54b | 553 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
554 | |
555 | return (send_status | accept_status); | |
556 | } | |
cb3c8b90 | 557 | |
148f9bb8 | 558 | static int |
569712b2 | 559 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 GOC |
560 | { |
561 | unsigned long send_status, accept_status = 0; | |
562 | int maxlvt, num_starts, j; | |
563 | ||
593f4a78 MR |
564 | maxlvt = lapic_get_maxlvt(); |
565 | ||
cb3c8b90 GOC |
566 | /* |
567 | * Be paranoid about clearing APIC errors. | |
568 | */ | |
569 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
593f4a78 MR |
570 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
571 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
572 | apic_read(APIC_ESR); |
573 | } | |
574 | ||
c767a54b | 575 | pr_debug("Asserting INIT\n"); |
cb3c8b90 GOC |
576 | |
577 | /* | |
578 | * Turn INIT on target chip | |
579 | */ | |
cb3c8b90 GOC |
580 | /* |
581 | * Send IPI | |
582 | */ | |
1b374e4d SS |
583 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
584 | phys_apicid); | |
cb3c8b90 | 585 | |
cfc1b9a6 | 586 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
587 | send_status = safe_apic_wait_icr_idle(); |
588 | ||
589 | mdelay(10); | |
590 | ||
c767a54b | 591 | pr_debug("Deasserting INIT\n"); |
cb3c8b90 GOC |
592 | |
593 | /* Target chip */ | |
cb3c8b90 | 594 | /* Send IPI */ |
1b374e4d | 595 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 596 | |
cfc1b9a6 | 597 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
598 | send_status = safe_apic_wait_icr_idle(); |
599 | ||
600 | mb(); | |
601 | atomic_set(&init_deasserted, 1); | |
602 | ||
603 | /* | |
604 | * Should we send STARTUP IPIs ? | |
605 | * | |
606 | * Determine this based on the APIC version. | |
607 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
608 | */ | |
609 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
610 | num_starts = 2; | |
611 | else | |
612 | num_starts = 0; | |
613 | ||
614 | /* | |
615 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
616 | * target processor state. | |
617 | */ | |
618 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
11d4c3f9 | 619 | stack_start); |
cb3c8b90 GOC |
620 | |
621 | /* | |
622 | * Run STARTUP IPI loop. | |
623 | */ | |
c767a54b | 624 | pr_debug("#startup loops: %d\n", num_starts); |
cb3c8b90 | 625 | |
cb3c8b90 | 626 | for (j = 1; j <= num_starts; j++) { |
c767a54b | 627 | pr_debug("Sending STARTUP #%d\n", j); |
593f4a78 MR |
628 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
629 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 630 | apic_read(APIC_ESR); |
c767a54b | 631 | pr_debug("After apic_write\n"); |
cb3c8b90 GOC |
632 | |
633 | /* | |
634 | * STARTUP IPI | |
635 | */ | |
636 | ||
637 | /* Target chip */ | |
cb3c8b90 GOC |
638 | /* Boot on the stack */ |
639 | /* Kick the second */ | |
1b374e4d SS |
640 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
641 | phys_apicid); | |
cb3c8b90 GOC |
642 | |
643 | /* | |
644 | * Give the other CPU some time to accept the IPI. | |
645 | */ | |
646 | udelay(300); | |
647 | ||
c767a54b | 648 | pr_debug("Startup point 1\n"); |
cb3c8b90 | 649 | |
cfc1b9a6 | 650 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
651 | send_status = safe_apic_wait_icr_idle(); |
652 | ||
653 | /* | |
654 | * Give the other CPU some time to accept the IPI. | |
655 | */ | |
656 | udelay(200); | |
593f4a78 | 657 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 658 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
659 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
660 | if (send_status || accept_status) | |
661 | break; | |
662 | } | |
c767a54b | 663 | pr_debug("After Startup\n"); |
cb3c8b90 GOC |
664 | |
665 | if (send_status) | |
c767a54b | 666 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 667 | if (accept_status) |
c767a54b | 668 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
669 | |
670 | return (send_status | accept_status); | |
671 | } | |
cb3c8b90 | 672 | |
a17bce4d BP |
673 | void smp_announce(void) |
674 | { | |
675 | int num_nodes = num_online_nodes(); | |
676 | ||
677 | printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n", | |
678 | num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus()); | |
679 | } | |
680 | ||
2eaad1fd | 681 | /* reduce the number of lines printed when booting a large cpu count system */ |
148f9bb8 | 682 | static void announce_cpu(int cpu, int apicid) |
2eaad1fd MT |
683 | { |
684 | static int current_node = -1; | |
4adc8b71 | 685 | int node = early_cpu_to_node(cpu); |
a17bce4d | 686 | static int width, node_width; |
646e29a1 BP |
687 | |
688 | if (!width) | |
689 | width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ | |
2eaad1fd | 690 | |
a17bce4d BP |
691 | if (!node_width) |
692 | node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ | |
693 | ||
694 | if (cpu == 1) | |
695 | printk(KERN_INFO "x86: Booting SMP configuration:\n"); | |
696 | ||
2eaad1fd MT |
697 | if (system_state == SYSTEM_BOOTING) { |
698 | if (node != current_node) { | |
699 | if (current_node > (-1)) | |
a17bce4d | 700 | pr_cont("\n"); |
2eaad1fd | 701 | current_node = node; |
a17bce4d BP |
702 | |
703 | printk(KERN_INFO ".... node %*s#%d, CPUs: ", | |
704 | node_width - num_digits(node), " ", node); | |
2eaad1fd | 705 | } |
646e29a1 BP |
706 | |
707 | /* Add padding for the BSP */ | |
708 | if (cpu == 1) | |
709 | pr_cont("%*s", width + 1, " "); | |
710 | ||
711 | pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); | |
712 | ||
2eaad1fd MT |
713 | } else |
714 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", | |
715 | node, cpu, apicid); | |
716 | } | |
717 | ||
e1c467e6 FY |
718 | static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) |
719 | { | |
720 | int cpu; | |
721 | ||
722 | cpu = smp_processor_id(); | |
723 | if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) | |
724 | return NMI_HANDLED; | |
725 | ||
726 | return NMI_DONE; | |
727 | } | |
728 | ||
729 | /* | |
730 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
731 | * | |
732 | * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS | |
733 | * boot-strap code which is not a desired behavior for waking up BSP. To | |
734 | * void the boot-strap code, wake up CPU0 by NMI instead. | |
735 | * | |
736 | * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined | |
737 | * (i.e. physically hot removed and then hot added), NMI won't wake it up. | |
738 | * We'll change this code in the future to wake up hard offlined CPU0 if | |
739 | * real platform and request are available. | |
740 | */ | |
148f9bb8 | 741 | static int |
e1c467e6 FY |
742 | wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, |
743 | int *cpu0_nmi_registered) | |
744 | { | |
745 | int id; | |
746 | int boot_error; | |
747 | ||
ea7bdc65 JK |
748 | preempt_disable(); |
749 | ||
e1c467e6 FY |
750 | /* |
751 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
752 | */ | |
ea7bdc65 JK |
753 | if (cpu) { |
754 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); | |
755 | goto out; | |
756 | } | |
e1c467e6 FY |
757 | |
758 | /* | |
759 | * Wake up BSP by nmi. | |
760 | * | |
761 | * Register a NMI handler to help wake up CPU0. | |
762 | */ | |
763 | boot_error = register_nmi_handler(NMI_LOCAL, | |
764 | wakeup_cpu0_nmi, 0, "wake_cpu0"); | |
765 | ||
766 | if (!boot_error) { | |
767 | enable_start_cpu0 = 1; | |
768 | *cpu0_nmi_registered = 1; | |
769 | if (apic->dest_logical == APIC_DEST_LOGICAL) | |
770 | id = cpu0_logical_apicid; | |
771 | else | |
772 | id = apicid; | |
773 | boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); | |
774 | } | |
ea7bdc65 JK |
775 | |
776 | out: | |
777 | preempt_enable(); | |
e1c467e6 FY |
778 | |
779 | return boot_error; | |
780 | } | |
781 | ||
cb3c8b90 GOC |
782 | /* |
783 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
784 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
785 | * Returns zero if CPU booted OK, else error code from |
786 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 787 | */ |
148f9bb8 | 788 | static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) |
cb3c8b90 | 789 | { |
48927bbb | 790 | volatile u32 *trampoline_status = |
b429dbf6 | 791 | (volatile u32 *) __va(real_mode_header->trampoline_status); |
48927bbb | 792 | /* start_ip had better be page-aligned! */ |
f37240f1 | 793 | unsigned long start_ip = real_mode_header->trampoline_start; |
48927bbb | 794 | |
cb3c8b90 | 795 | unsigned long boot_error = 0; |
e1c467e6 | 796 | int cpu0_nmi_registered = 0; |
ce4b1b16 | 797 | unsigned long timeout; |
cb3c8b90 | 798 | |
816afe4f RR |
799 | /* Just in case we booted with a single CPU. */ |
800 | alternatives_enable_smp(); | |
cb3c8b90 | 801 | |
7eb43a6d TG |
802 | idle->thread.sp = (unsigned long) (((struct pt_regs *) |
803 | (THREAD_SIZE + task_stack_page(idle))) - 1); | |
804 | per_cpu(current_task, cpu) = idle; | |
cb3c8b90 | 805 | |
c6f5e0ac | 806 | #ifdef CONFIG_X86_32 |
cb3c8b90 | 807 | /* Stack for startup_32 can be just as for start_secondary onwards */ |
cb3c8b90 GOC |
808 | irq_ctx_init(cpu); |
809 | #else | |
7eb43a6d | 810 | clear_tsk_thread_flag(idle, TIF_FORK); |
004aa322 | 811 | initial_gs = per_cpu_offset(cpu); |
198d208d | 812 | #endif |
9af45651 | 813 | per_cpu(kernel_stack, cpu) = |
7eb43a6d | 814 | (unsigned long)task_stack_page(idle) - |
9af45651 | 815 | KERNEL_STACK_OFFSET + THREAD_SIZE; |
a939098a | 816 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
3e970473 | 817 | initial_code = (unsigned long)start_secondary; |
7eb43a6d | 818 | stack_start = idle->thread.sp; |
cb3c8b90 | 819 | |
2eaad1fd MT |
820 | /* So we see what's up */ |
821 | announce_cpu(cpu, apicid); | |
cb3c8b90 GOC |
822 | |
823 | /* | |
824 | * This grunge runs the startup process for | |
825 | * the targeted processor. | |
826 | */ | |
827 | ||
828 | atomic_set(&init_deasserted, 0); | |
829 | ||
34d05591 | 830 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 831 | |
cfc1b9a6 | 832 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 833 | |
34d05591 JS |
834 | smpboot_setup_warm_reset_vector(start_ip); |
835 | /* | |
836 | * Be paranoid about clearing APIC errors. | |
db96b0a0 CG |
837 | */ |
838 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
839 | apic_write(APIC_ESR, 0); | |
840 | apic_read(APIC_ESR); | |
841 | } | |
34d05591 | 842 | } |
cb3c8b90 | 843 | |
ce4b1b16 IM |
844 | /* |
845 | * AP might wait on cpu_callout_mask in cpu_init() with | |
846 | * cpu_initialized_mask set if previous attempt to online | |
847 | * it timed-out. Clear cpu_initialized_mask so that after | |
848 | * INIT/SIPI it could start with a clean state. | |
849 | */ | |
850 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
851 | smp_mb(); | |
852 | ||
cb3c8b90 | 853 | /* |
e1c467e6 FY |
854 | * Wake up a CPU in difference cases: |
855 | * - Use the method in the APIC driver if it's defined | |
856 | * Otherwise, | |
857 | * - Use an INIT boot APIC message for APs or NMI for BSP. | |
cb3c8b90 | 858 | */ |
1f5bcabf IM |
859 | if (apic->wakeup_secondary_cpu) |
860 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
861 | else | |
e1c467e6 FY |
862 | boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, |
863 | &cpu0_nmi_registered); | |
cb3c8b90 GOC |
864 | |
865 | if (!boot_error) { | |
866 | /* | |
ce4b1b16 | 867 | * Wait 10s total for a response from AP |
cb3c8b90 | 868 | */ |
ce4b1b16 IM |
869 | boot_error = -1; |
870 | timeout = jiffies + 10*HZ; | |
871 | while (time_before(jiffies, timeout)) { | |
872 | if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { | |
873 | /* | |
874 | * Tell AP to proceed with initialization | |
875 | */ | |
876 | cpumask_set_cpu(cpu, cpu_callout_mask); | |
877 | boot_error = 0; | |
878 | break; | |
879 | } | |
880 | udelay(100); | |
881 | schedule(); | |
882 | } | |
883 | } | |
cb3c8b90 | 884 | |
ce4b1b16 | 885 | if (!boot_error) { |
cb3c8b90 | 886 | /* |
ce4b1b16 | 887 | * Wait till AP completes initial initialization |
cb3c8b90 | 888 | */ |
ce4b1b16 | 889 | while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { |
68f202e4 SS |
890 | /* |
891 | * Allow other tasks to run while we wait for the | |
892 | * AP to come online. This also gives a chance | |
893 | * for the MTRR work(triggered by the AP coming online) | |
894 | * to be completed in the stop machine context. | |
895 | */ | |
ce4b1b16 | 896 | udelay(100); |
68f202e4 | 897 | schedule(); |
cb3c8b90 | 898 | } |
cb3c8b90 GOC |
899 | } |
900 | ||
901 | /* mark "stuck" area as not stuck */ | |
48927bbb | 902 | *trampoline_status = 0; |
cb3c8b90 | 903 | |
02421f98 YL |
904 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
905 | /* | |
906 | * Cleanup possible dangling ends... | |
907 | */ | |
908 | smpboot_restore_warm_reset_vector(); | |
909 | } | |
e1c467e6 FY |
910 | /* |
911 | * Clean up the nmi handler. Do this after the callin and callout sync | |
912 | * to avoid impact of possible long unregister time. | |
913 | */ | |
914 | if (cpu0_nmi_registered) | |
915 | unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); | |
916 | ||
cb3c8b90 GOC |
917 | return boot_error; |
918 | } | |
919 | ||
148f9bb8 | 920 | int native_cpu_up(unsigned int cpu, struct task_struct *tidle) |
cb3c8b90 | 921 | { |
a21769a4 | 922 | int apicid = apic->cpu_present_to_apicid(cpu); |
cb3c8b90 GOC |
923 | unsigned long flags; |
924 | int err; | |
925 | ||
926 | WARN_ON(irqs_disabled()); | |
927 | ||
cfc1b9a6 | 928 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 | 929 | |
30106c17 | 930 | if (apicid == BAD_APICID || |
c284b42a | 931 | !physid_isset(apicid, phys_cpu_present_map) || |
fa63030e | 932 | !apic->apic_id_valid(apicid)) { |
c767a54b | 933 | pr_err("%s: bad cpu %d\n", __func__, cpu); |
cb3c8b90 GOC |
934 | return -EINVAL; |
935 | } | |
936 | ||
937 | /* | |
938 | * Already booted CPU? | |
939 | */ | |
c2d1cec1 | 940 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 941 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
942 | return -ENOSYS; |
943 | } | |
944 | ||
945 | /* | |
946 | * Save current MTRR state in case it was changed since early boot | |
947 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
948 | */ | |
949 | mtrr_save_state(); | |
950 | ||
951 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
952 | ||
644c1541 VP |
953 | /* the FPU context is blank, nobody can own it */ |
954 | __cpu_disable_lazy_restore(cpu); | |
955 | ||
7eb43a6d | 956 | err = do_boot_cpu(apicid, cpu, tidle); |
61165d7a | 957 | if (err) { |
feef1e8e | 958 | pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); |
61165d7a | 959 | return -EIO; |
cb3c8b90 GOC |
960 | } |
961 | ||
962 | /* | |
963 | * Check TSC synchronization with the AP (keep irqs disabled | |
964 | * while doing so): | |
965 | */ | |
966 | local_irq_save(flags); | |
967 | check_tsc_sync_source(cpu); | |
968 | local_irq_restore(flags); | |
969 | ||
7c04e64a | 970 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
971 | cpu_relax(); |
972 | touch_nmi_watchdog(); | |
973 | } | |
974 | ||
975 | return 0; | |
976 | } | |
977 | ||
7167d08e HK |
978 | /** |
979 | * arch_disable_smp_support() - disables SMP support for x86 at runtime | |
980 | */ | |
981 | void arch_disable_smp_support(void) | |
982 | { | |
983 | disable_ioapic_support(); | |
984 | } | |
985 | ||
8aef135c GOC |
986 | /* |
987 | * Fall back to non SMP mode after errors. | |
988 | * | |
989 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
990 | */ | |
991 | static __init void disable_smp(void) | |
992 | { | |
613c25ef TG |
993 | pr_info("SMP disabled\n"); |
994 | ||
ef4c59a4 TG |
995 | disable_ioapic_support(); |
996 | ||
4f062896 RR |
997 | init_cpu_present(cpumask_of(0)); |
998 | init_cpu_possible(cpumask_of(0)); | |
0f385d1d | 999 | |
8aef135c | 1000 | if (smp_found_config) |
b6df1b8b | 1001 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 1002 | else |
b6df1b8b | 1003 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
c2d1cec1 MT |
1004 | cpumask_set_cpu(0, cpu_sibling_mask(0)); |
1005 | cpumask_set_cpu(0, cpu_core_mask(0)); | |
8aef135c GOC |
1006 | } |
1007 | ||
613c25ef TG |
1008 | enum { |
1009 | SMP_OK, | |
1010 | SMP_NO_CONFIG, | |
1011 | SMP_NO_APIC, | |
1012 | SMP_FORCE_UP, | |
1013 | }; | |
1014 | ||
8aef135c GOC |
1015 | /* |
1016 | * Various sanity checks. | |
1017 | */ | |
1018 | static int __init smp_sanity_check(unsigned max_cpus) | |
1019 | { | |
ac23d4ee | 1020 | preempt_disable(); |
a58f03b0 | 1021 | |
1ff2f20d | 1022 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
1023 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
1024 | unsigned int cpu; | |
1025 | unsigned nr; | |
1026 | ||
c767a54b JP |
1027 | pr_warn("More than 8 CPUs detected - skipping them\n" |
1028 | "Use CONFIG_X86_BIGSMP\n"); | |
a58f03b0 YL |
1029 | |
1030 | nr = 0; | |
1031 | for_each_present_cpu(cpu) { | |
1032 | if (nr >= 8) | |
c2d1cec1 | 1033 | set_cpu_present(cpu, false); |
a58f03b0 YL |
1034 | nr++; |
1035 | } | |
1036 | ||
1037 | nr = 0; | |
1038 | for_each_possible_cpu(cpu) { | |
1039 | if (nr >= 8) | |
c2d1cec1 | 1040 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
1041 | nr++; |
1042 | } | |
1043 | ||
1044 | nr_cpu_ids = 8; | |
1045 | } | |
1046 | #endif | |
1047 | ||
8aef135c | 1048 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
c767a54b | 1049 | pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", |
55c395b4 MT |
1050 | hard_smp_processor_id()); |
1051 | ||
8aef135c GOC |
1052 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1053 | } | |
1054 | ||
1055 | /* | |
1056 | * If we couldn't find an SMP configuration at boot time, | |
1057 | * get out of here now! | |
1058 | */ | |
1059 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 1060 | preempt_enable(); |
c767a54b | 1061 | pr_notice("SMP motherboard not detected\n"); |
613c25ef | 1062 | return SMP_NO_CONFIG; |
8aef135c GOC |
1063 | } |
1064 | ||
1065 | /* | |
1066 | * Should not be necessary because the MP table should list the boot | |
1067 | * CPU too, but we do it for the sake of robustness anyway. | |
1068 | */ | |
a27a6210 | 1069 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
c767a54b JP |
1070 | pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", |
1071 | boot_cpu_physical_apicid); | |
8aef135c GOC |
1072 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1073 | } | |
ac23d4ee | 1074 | preempt_enable(); |
8aef135c GOC |
1075 | |
1076 | /* | |
1077 | * If we couldn't find a local APIC, then get out of here now! | |
1078 | */ | |
1079 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && | |
1080 | !cpu_has_apic) { | |
103428e5 CG |
1081 | if (!disable_apic) { |
1082 | pr_err("BIOS bug, local APIC #%d not detected!...\n", | |
1083 | boot_cpu_physical_apicid); | |
c767a54b | 1084 | pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); |
103428e5 | 1085 | } |
613c25ef | 1086 | return SMP_NO_APIC; |
8aef135c GOC |
1087 | } |
1088 | ||
1089 | verify_local_APIC(); | |
1090 | ||
1091 | /* | |
1092 | * If SMP should be disabled, then really disable it! | |
1093 | */ | |
1094 | if (!max_cpus) { | |
c767a54b | 1095 | pr_info("SMP mode deactivated\n"); |
613c25ef | 1096 | return SMP_FORCE_UP; |
8aef135c GOC |
1097 | } |
1098 | ||
613c25ef | 1099 | return SMP_OK; |
8aef135c GOC |
1100 | } |
1101 | ||
1102 | static void __init smp_cpu_index_default(void) | |
1103 | { | |
1104 | int i; | |
1105 | struct cpuinfo_x86 *c; | |
1106 | ||
7c04e64a | 1107 | for_each_possible_cpu(i) { |
8aef135c GOC |
1108 | c = &cpu_data(i); |
1109 | /* mark all to hotplug */ | |
9628937d | 1110 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1111 | } |
1112 | } | |
1113 | ||
1114 | /* | |
1115 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1116 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1117 | */ | |
1118 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1119 | { | |
7ad728f9 RR |
1120 | unsigned int i; |
1121 | ||
8aef135c | 1122 | smp_cpu_index_default(); |
792363d2 | 1123 | |
8aef135c GOC |
1124 | /* |
1125 | * Setup boot CPU information | |
1126 | */ | |
30106c17 | 1127 | smp_store_boot_cpu_info(); /* Final full version of the data */ |
792363d2 YL |
1128 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
1129 | mb(); | |
bd22a2f1 | 1130 | |
8aef135c | 1131 | current_thread_info()->cpu = 0; /* needed? */ |
7ad728f9 | 1132 | for_each_possible_cpu(i) { |
79f55997 LZ |
1133 | zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); |
1134 | zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); | |
b3d7336d | 1135 | zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); |
7ad728f9 | 1136 | } |
8aef135c GOC |
1137 | set_cpu_sibling_map(0); |
1138 | ||
613c25ef TG |
1139 | switch (smp_sanity_check(max_cpus)) { |
1140 | case SMP_NO_CONFIG: | |
8aef135c | 1141 | disable_smp(); |
613c25ef TG |
1142 | if (APIC_init_uniprocessor()) |
1143 | pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); | |
1144 | return; | |
1145 | case SMP_NO_APIC: | |
1146 | disable_smp(); | |
1147 | return; | |
1148 | case SMP_FORCE_UP: | |
1149 | disable_smp(); | |
374aab33 | 1150 | apic_bsp_setup(false); |
250a1ac6 | 1151 | return; |
613c25ef TG |
1152 | case SMP_OK: |
1153 | break; | |
8aef135c GOC |
1154 | } |
1155 | ||
fa47f7e5 SS |
1156 | default_setup_apic_routing(); |
1157 | ||
4c9961d5 | 1158 | if (read_apic_id() != boot_cpu_physical_apicid) { |
8aef135c | 1159 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
4c9961d5 | 1160 | read_apic_id(), boot_cpu_physical_apicid); |
8aef135c GOC |
1161 | /* Or can we switch back to PIC here? */ |
1162 | } | |
1163 | ||
374aab33 | 1164 | cpu0_logical_apicid = apic_bsp_setup(false); |
ef4c59a4 | 1165 | |
c767a54b | 1166 | pr_info("CPU%d: ", 0); |
8aef135c | 1167 | print_cpu_info(&cpu_data(0)); |
c4bd1fda MS |
1168 | |
1169 | if (is_uv_system()) | |
1170 | uv_system_init(); | |
d0af9eed SS |
1171 | |
1172 | set_mtrr_aps_delayed_init(); | |
8aef135c | 1173 | } |
d0af9eed SS |
1174 | |
1175 | void arch_enable_nonboot_cpus_begin(void) | |
1176 | { | |
1177 | set_mtrr_aps_delayed_init(); | |
1178 | } | |
1179 | ||
1180 | void arch_enable_nonboot_cpus_end(void) | |
1181 | { | |
1182 | mtrr_aps_init(); | |
1183 | } | |
1184 | ||
a8db8453 GOC |
1185 | /* |
1186 | * Early setup to make printk work. | |
1187 | */ | |
1188 | void __init native_smp_prepare_boot_cpu(void) | |
1189 | { | |
1190 | int me = smp_processor_id(); | |
552be871 | 1191 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1192 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1193 | cpumask_set_cpu(me, cpu_callout_mask); | |
a8db8453 GOC |
1194 | per_cpu(cpu_state, me) = CPU_ONLINE; |
1195 | } | |
1196 | ||
83f7eb9c GOC |
1197 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1198 | { | |
c767a54b | 1199 | pr_debug("Boot done\n"); |
83f7eb9c | 1200 | |
99e8b9ca | 1201 | nmi_selftest(); |
83f7eb9c | 1202 | impress_friends(); |
83f7eb9c | 1203 | setup_ioapic_dest(); |
d0af9eed | 1204 | mtrr_aps_init(); |
83f7eb9c GOC |
1205 | } |
1206 | ||
3b11ce7f MT |
1207 | static int __initdata setup_possible_cpus = -1; |
1208 | static int __init _setup_possible_cpus(char *str) | |
1209 | { | |
1210 | get_option(&str, &setup_possible_cpus); | |
1211 | return 0; | |
1212 | } | |
1213 | early_param("possible_cpus", _setup_possible_cpus); | |
1214 | ||
1215 | ||
68a1c3f8 | 1216 | /* |
4f062896 | 1217 | * cpu_possible_mask should be static, it cannot change as cpu's |
68a1c3f8 GC |
1218 | * are onlined, or offlined. The reason is per-cpu data-structures |
1219 | * are allocated by some modules at init time, and dont expect to | |
1220 | * do this dynamically on cpu arrival/departure. | |
4f062896 | 1221 | * cpu_present_mask on the other hand can change dynamically. |
68a1c3f8 GC |
1222 | * In case when cpu_hotplug is not compiled, then we resort to current |
1223 | * behaviour, which is cpu_possible == cpu_present. | |
1224 | * - Ashok Raj | |
1225 | * | |
1226 | * Three ways to find out the number of additional hotplug CPUs: | |
1227 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1228 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1229 | * - Otherwise don't reserve additional CPUs. |
1230 | * We do this because additional CPUs waste a lot of memory. | |
1231 | * -AK | |
1232 | */ | |
1233 | __init void prefill_possible_map(void) | |
1234 | { | |
cb48bb59 | 1235 | int i, possible; |
68a1c3f8 | 1236 | |
329513a3 YL |
1237 | /* no processor from mptable or madt */ |
1238 | if (!num_processors) | |
1239 | num_processors = 1; | |
1240 | ||
5f2eb550 JB |
1241 | i = setup_max_cpus ?: 1; |
1242 | if (setup_possible_cpus == -1) { | |
1243 | possible = num_processors; | |
1244 | #ifdef CONFIG_HOTPLUG_CPU | |
1245 | if (setup_max_cpus) | |
1246 | possible += disabled_cpus; | |
1247 | #else | |
1248 | if (possible > i) | |
1249 | possible = i; | |
1250 | #endif | |
1251 | } else | |
3b11ce7f MT |
1252 | possible = setup_possible_cpus; |
1253 | ||
730cf272 MT |
1254 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1255 | ||
2b633e3f YL |
1256 | /* nr_cpu_ids could be reduced via nr_cpus= */ |
1257 | if (possible > nr_cpu_ids) { | |
c767a54b | 1258 | pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", |
2b633e3f YL |
1259 | possible, nr_cpu_ids); |
1260 | possible = nr_cpu_ids; | |
3b11ce7f | 1261 | } |
68a1c3f8 | 1262 | |
5f2eb550 JB |
1263 | #ifdef CONFIG_HOTPLUG_CPU |
1264 | if (!setup_max_cpus) | |
1265 | #endif | |
1266 | if (possible > i) { | |
c767a54b | 1267 | pr_warn("%d Processors exceeds max_cpus limit of %u\n", |
5f2eb550 JB |
1268 | possible, setup_max_cpus); |
1269 | possible = i; | |
1270 | } | |
1271 | ||
c767a54b | 1272 | pr_info("Allowing %d CPUs, %d hotplug CPUs\n", |
68a1c3f8 GC |
1273 | possible, max_t(int, possible - num_processors, 0)); |
1274 | ||
1275 | for (i = 0; i < possible; i++) | |
c2d1cec1 | 1276 | set_cpu_possible(i, true); |
5f2eb550 JB |
1277 | for (; i < NR_CPUS; i++) |
1278 | set_cpu_possible(i, false); | |
3461b0af MT |
1279 | |
1280 | nr_cpu_ids = possible; | |
68a1c3f8 | 1281 | } |
69c18c15 | 1282 | |
14adf855 CE |
1283 | #ifdef CONFIG_HOTPLUG_CPU |
1284 | ||
1285 | static void remove_siblinginfo(int cpu) | |
1286 | { | |
1287 | int sibling; | |
1288 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1289 | ||
c2d1cec1 MT |
1290 | for_each_cpu(sibling, cpu_core_mask(cpu)) { |
1291 | cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); | |
14adf855 CE |
1292 | /*/ |
1293 | * last thread sibling in this cpu core going down | |
1294 | */ | |
c2d1cec1 | 1295 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) |
14adf855 CE |
1296 | cpu_data(sibling).booted_cores--; |
1297 | } | |
1298 | ||
c2d1cec1 MT |
1299 | for_each_cpu(sibling, cpu_sibling_mask(cpu)) |
1300 | cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); | |
03bd4e1f WL |
1301 | for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) |
1302 | cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); | |
1303 | cpumask_clear(cpu_llc_shared_mask(cpu)); | |
c2d1cec1 MT |
1304 | cpumask_clear(cpu_sibling_mask(cpu)); |
1305 | cpumask_clear(cpu_core_mask(cpu)); | |
14adf855 CE |
1306 | c->phys_proc_id = 0; |
1307 | c->cpu_core_id = 0; | |
c2d1cec1 | 1308 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
14adf855 CE |
1309 | } |
1310 | ||
69c18c15 GC |
1311 | static void __ref remove_cpu_from_maps(int cpu) |
1312 | { | |
c2d1cec1 MT |
1313 | set_cpu_online(cpu, false); |
1314 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1315 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1316 | /* was set by cpu_init() */ |
c2d1cec1 | 1317 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1318 | numa_remove_cpu(cpu); |
69c18c15 GC |
1319 | } |
1320 | ||
54279552 BO |
1321 | static DEFINE_PER_CPU(struct completion, die_complete); |
1322 | ||
8227dce7 | 1323 | void cpu_disable_common(void) |
69c18c15 GC |
1324 | { |
1325 | int cpu = smp_processor_id(); | |
69c18c15 | 1326 | |
54279552 BO |
1327 | init_completion(&per_cpu(die_complete, smp_processor_id())); |
1328 | ||
69c18c15 GC |
1329 | remove_siblinginfo(cpu); |
1330 | ||
1331 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1332 | lock_vector_lock(); |
69c18c15 | 1333 | remove_cpu_from_maps(cpu); |
d388e5fd | 1334 | unlock_vector_lock(); |
d7b381bb | 1335 | fixup_irqs(); |
8227dce7 AN |
1336 | } |
1337 | ||
1338 | int native_cpu_disable(void) | |
1339 | { | |
da6139e4 PB |
1340 | int ret; |
1341 | ||
1342 | ret = check_irq_vectors_for_cpu_disable(); | |
1343 | if (ret) | |
1344 | return ret; | |
1345 | ||
8227dce7 | 1346 | clear_local_APIC(); |
8227dce7 | 1347 | cpu_disable_common(); |
2ed53c0d | 1348 | |
69c18c15 GC |
1349 | return 0; |
1350 | } | |
1351 | ||
54279552 BO |
1352 | void cpu_die_common(unsigned int cpu) |
1353 | { | |
1354 | wait_for_completion_timeout(&per_cpu(die_complete, cpu), HZ); | |
1355 | } | |
1356 | ||
93be71b6 | 1357 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1358 | { |
1359 | /* We don't do anything here: idle task is faking death itself. */ | |
54279552 BO |
1360 | |
1361 | cpu_die_common(cpu); | |
2ed53c0d LT |
1362 | |
1363 | /* They ack this in play_dead() by setting CPU_DEAD */ | |
1364 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { | |
1365 | if (system_state == SYSTEM_RUNNING) | |
1366 | pr_info("CPU %u is now offline\n", cpu); | |
1367 | } else { | |
1368 | pr_err("CPU %u didn't die...\n", cpu); | |
69c18c15 | 1369 | } |
69c18c15 | 1370 | } |
a21f5d88 AN |
1371 | |
1372 | void play_dead_common(void) | |
1373 | { | |
1374 | idle_task_exit(); | |
1375 | reset_lazy_tlbstate(); | |
02c68a02 | 1376 | amd_e400_remove_cpu(raw_smp_processor_id()); |
a21f5d88 AN |
1377 | |
1378 | mb(); | |
1379 | /* Ack it */ | |
0a3aee0d | 1380 | __this_cpu_write(cpu_state, CPU_DEAD); |
2ed53c0d | 1381 | complete(&per_cpu(die_complete, smp_processor_id())); |
a21f5d88 AN |
1382 | |
1383 | /* | |
1384 | * With physical CPU hotplug, we should halt the cpu | |
1385 | */ | |
1386 | local_irq_disable(); | |
1387 | } | |
1388 | ||
e1c467e6 FY |
1389 | static bool wakeup_cpu0(void) |
1390 | { | |
1391 | if (smp_processor_id() == 0 && enable_start_cpu0) | |
1392 | return true; | |
1393 | ||
1394 | return false; | |
1395 | } | |
1396 | ||
ea530692 PA |
1397 | /* |
1398 | * We need to flush the caches before going to sleep, lest we have | |
1399 | * dirty data in our caches when we come back up. | |
1400 | */ | |
1401 | static inline void mwait_play_dead(void) | |
1402 | { | |
1403 | unsigned int eax, ebx, ecx, edx; | |
1404 | unsigned int highest_cstate = 0; | |
1405 | unsigned int highest_subcstate = 0; | |
ce5f6824 | 1406 | void *mwait_ptr; |
576cfb40 | 1407 | int i; |
ea530692 | 1408 | |
69fb3676 | 1409 | if (!this_cpu_has(X86_FEATURE_MWAIT)) |
ea530692 | 1410 | return; |
840d2830 | 1411 | if (!this_cpu_has(X86_FEATURE_CLFLUSH)) |
ce5f6824 | 1412 | return; |
7b543a53 | 1413 | if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) |
ea530692 PA |
1414 | return; |
1415 | ||
1416 | eax = CPUID_MWAIT_LEAF; | |
1417 | ecx = 0; | |
1418 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
1419 | ||
1420 | /* | |
1421 | * eax will be 0 if EDX enumeration is not valid. | |
1422 | * Initialized below to cstate, sub_cstate value when EDX is valid. | |
1423 | */ | |
1424 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { | |
1425 | eax = 0; | |
1426 | } else { | |
1427 | edx >>= MWAIT_SUBSTATE_SIZE; | |
1428 | for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { | |
1429 | if (edx & MWAIT_SUBSTATE_MASK) { | |
1430 | highest_cstate = i; | |
1431 | highest_subcstate = edx & MWAIT_SUBSTATE_MASK; | |
1432 | } | |
1433 | } | |
1434 | eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | | |
1435 | (highest_subcstate - 1); | |
1436 | } | |
1437 | ||
ce5f6824 PA |
1438 | /* |
1439 | * This should be a memory location in a cache line which is | |
1440 | * unlikely to be touched by other processors. The actual | |
1441 | * content is immaterial as it is not actually modified in any way. | |
1442 | */ | |
1443 | mwait_ptr = ¤t_thread_info()->flags; | |
1444 | ||
a68e5c94 PA |
1445 | wbinvd(); |
1446 | ||
ea530692 | 1447 | while (1) { |
ce5f6824 PA |
1448 | /* |
1449 | * The CLFLUSH is a workaround for erratum AAI65 for | |
1450 | * the Xeon 7400 series. It's not clear it is actually | |
1451 | * needed, but it should be harmless in either case. | |
1452 | * The WBINVD is insufficient due to the spurious-wakeup | |
1453 | * case where we return around the loop. | |
1454 | */ | |
7d590cca | 1455 | mb(); |
ce5f6824 | 1456 | clflush(mwait_ptr); |
7d590cca | 1457 | mb(); |
ce5f6824 | 1458 | __monitor(mwait_ptr, 0, 0); |
ea530692 PA |
1459 | mb(); |
1460 | __mwait(eax, 0); | |
e1c467e6 FY |
1461 | /* |
1462 | * If NMI wants to wake up CPU0, start CPU0. | |
1463 | */ | |
1464 | if (wakeup_cpu0()) | |
1465 | start_cpu0(); | |
ea530692 PA |
1466 | } |
1467 | } | |
1468 | ||
1469 | static inline void hlt_play_dead(void) | |
1470 | { | |
7b543a53 | 1471 | if (__this_cpu_read(cpu_info.x86) >= 4) |
a68e5c94 PA |
1472 | wbinvd(); |
1473 | ||
ea530692 | 1474 | while (1) { |
ea530692 | 1475 | native_halt(); |
e1c467e6 FY |
1476 | /* |
1477 | * If NMI wants to wake up CPU0, start CPU0. | |
1478 | */ | |
1479 | if (wakeup_cpu0()) | |
1480 | start_cpu0(); | |
ea530692 PA |
1481 | } |
1482 | } | |
1483 | ||
a21f5d88 AN |
1484 | void native_play_dead(void) |
1485 | { | |
1486 | play_dead_common(); | |
86886e55 | 1487 | tboot_shutdown(TB_SHUTDOWN_WFS); |
ea530692 PA |
1488 | |
1489 | mwait_play_dead(); /* Only returns on failure */ | |
1a022e3f BO |
1490 | if (cpuidle_play_dead()) |
1491 | hlt_play_dead(); | |
a21f5d88 AN |
1492 | } |
1493 | ||
69c18c15 | 1494 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1495 | int native_cpu_disable(void) |
69c18c15 GC |
1496 | { |
1497 | return -ENOSYS; | |
1498 | } | |
1499 | ||
93be71b6 | 1500 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1501 | { |
1502 | /* We said "no" in __cpu_disable */ | |
1503 | BUG(); | |
1504 | } | |
a21f5d88 AN |
1505 | |
1506 | void native_play_dead(void) | |
1507 | { | |
1508 | BUG(); | |
1509 | } | |
1510 | ||
68a1c3f8 | 1511 | #endif |