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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
17ce265d SR |
2 | /* |
3 | * ld script for the x86 kernel | |
4 | * | |
5 | * Historic 32-bit version written by Martin Mares <mj@atrey.karlin.mff.cuni.cz> | |
6 | * | |
91fd7fe8 IM |
7 | * Modernisation, unification and other changes and fixes: |
8 | * Copyright (C) 2007-2009 Sam Ravnborg <sam@ravnborg.org> | |
17ce265d SR |
9 | * |
10 | * | |
11 | * Don't define absolute symbols until and unless you know that symbol | |
12 | * value is should remain constant even if kernel image is relocated | |
13 | * at run time. Absolute symbols are not relocated. If symbol value should | |
14 | * change if kernel is relocated, make the symbol section relative and | |
15 | * put it inside the section definition. | |
16 | */ | |
17 | ||
18 | #ifdef CONFIG_X86_32 | |
19 | #define LOAD_OFFSET __PAGE_OFFSET | |
20 | #else | |
21 | #define LOAD_OFFSET __START_KERNEL_map | |
22 | #endif | |
23 | ||
24 | #include <asm-generic/vmlinux.lds.h> | |
25 | #include <asm/asm-offsets.h> | |
26 | #include <asm/thread_info.h> | |
27 | #include <asm/page_types.h> | |
ee9f8fce | 28 | #include <asm/orc_lookup.h> |
17ce265d SR |
29 | #include <asm/cache.h> |
30 | #include <asm/boot.h> | |
31 | ||
32 | #undef i386 /* in case the preprocessor is a 32bit one */ | |
33 | ||
34 | OUTPUT_FORMAT(CONFIG_OUTPUT_FORMAT, CONFIG_OUTPUT_FORMAT, CONFIG_OUTPUT_FORMAT) | |
35 | ||
36 | #ifdef CONFIG_X86_32 | |
37 | OUTPUT_ARCH(i386) | |
38 | ENTRY(phys_startup_32) | |
6b35eb9d | 39 | jiffies = jiffies_64; |
17ce265d SR |
40 | #else |
41 | OUTPUT_ARCH(i386:x86-64) | |
42 | ENTRY(phys_startup_64) | |
6b35eb9d | 43 | jiffies_64 = jiffies; |
17ce265d SR |
44 | #endif |
45 | ||
9ccaf77c | 46 | #if defined(CONFIG_X86_64) |
d6cc1c3a | 47 | /* |
9ccaf77c KC |
48 | * On 64-bit, align RODATA to 2MB so we retain large page mappings for |
49 | * boundaries spanning kernel text, rodata and data sections. | |
d6cc1c3a SS |
50 | * |
51 | * However, kernel identity mappings will have different RWX permissions | |
52 | * to the pages mapping to text and to the pages padding (which are freed) the | |
53 | * text section. Hence kernel identity mappings will be broken to smaller | |
54 | * pages. For 64-bit, kernel text and kernel identity mappings are different, | |
9ccaf77c KC |
55 | * so we can enable protection checks as well as retain 2MB large page |
56 | * mappings for kernel text. | |
d6cc1c3a | 57 | */ |
9ccaf77c | 58 | #define X64_ALIGN_RODATA_BEGIN . = ALIGN(HPAGE_SIZE); |
74e08179 | 59 | |
9ccaf77c | 60 | #define X64_ALIGN_RODATA_END \ |
74e08179 SS |
61 | . = ALIGN(HPAGE_SIZE); \ |
62 | __end_rodata_hpage_align = .; | |
63 | ||
2f7412ba TG |
64 | #define ALIGN_ENTRY_TEXT_BEGIN . = ALIGN(PMD_SIZE); |
65 | #define ALIGN_ENTRY_TEXT_END . = ALIGN(PMD_SIZE); | |
66 | ||
74e08179 SS |
67 | #else |
68 | ||
9ccaf77c KC |
69 | #define X64_ALIGN_RODATA_BEGIN |
70 | #define X64_ALIGN_RODATA_END | |
74e08179 | 71 | |
2f7412ba TG |
72 | #define ALIGN_ENTRY_TEXT_BEGIN |
73 | #define ALIGN_ENTRY_TEXT_END | |
74 | ||
74e08179 SS |
75 | #endif |
76 | ||
afb8095a SR |
77 | PHDRS { |
78 | text PT_LOAD FLAGS(5); /* R_E */ | |
5bd5a452 | 79 | data PT_LOAD FLAGS(6); /* RW_ */ |
afb8095a | 80 | #ifdef CONFIG_X86_64 |
afb8095a | 81 | #ifdef CONFIG_SMP |
8d0cc631 | 82 | percpu PT_LOAD FLAGS(6); /* RW_ */ |
afb8095a | 83 | #endif |
c62e4320 | 84 | init PT_LOAD FLAGS(7); /* RWE */ |
afb8095a SR |
85 | #endif |
86 | note PT_NOTE FLAGS(0); /* ___ */ | |
87 | } | |
17ce265d | 88 | |
444e0ae4 SR |
89 | SECTIONS |
90 | { | |
91 | #ifdef CONFIG_X86_32 | |
142b9e6c AB |
92 | . = LOAD_OFFSET + LOAD_PHYSICAL_ADDR; |
93 | phys_startup_32 = ABSOLUTE(startup_32 - LOAD_OFFSET); | |
444e0ae4 | 94 | #else |
142b9e6c AB |
95 | . = __START_KERNEL; |
96 | phys_startup_64 = ABSOLUTE(startup_64 - LOAD_OFFSET); | |
444e0ae4 SR |
97 | #endif |
98 | ||
dfc20895 | 99 | /* Text and read-only data */ |
dfc20895 | 100 | .text : AT(ADDR(.text) - LOAD_OFFSET) { |
4ae59b91 | 101 | _text = .; |
e728f61c | 102 | _stext = .; |
4ae59b91 TA |
103 | /* bootstrapping code */ |
104 | HEAD_TEXT | |
dfc20895 | 105 | . = ALIGN(8); |
dfc20895 SR |
106 | TEXT_TEXT |
107 | SCHED_TEXT | |
6727ad9e | 108 | CPUIDLE_TEXT |
dfc20895 SR |
109 | LOCK_TEXT |
110 | KPROBES_TEXT | |
2f7412ba | 111 | ALIGN_ENTRY_TEXT_BEGIN |
ea714547 | 112 | ENTRY_TEXT |
dfc20895 | 113 | IRQENTRY_TEXT |
2f7412ba | 114 | ALIGN_ENTRY_TEXT_END |
be7635e7 | 115 | SOFTIRQENTRY_TEXT |
dfc20895 SR |
116 | *(.fixup) |
117 | *(.gnu.warning) | |
3386bc8a AL |
118 | |
119 | #ifdef CONFIG_X86_64 | |
120 | . = ALIGN(PAGE_SIZE); | |
121 | _entry_trampoline = .; | |
122 | *(.entry_trampoline) | |
123 | . = ALIGN(PAGE_SIZE); | |
124 | ASSERT(. - _entry_trampoline == PAGE_SIZE, "entry trampoline is too big"); | |
125 | #endif | |
126 | ||
736e80a4 MH |
127 | #ifdef CONFIG_RETPOLINE |
128 | __indirect_thunk_start = .; | |
129 | *(.text.__x86.indirect_thunk) | |
130 | __indirect_thunk_end = .; | |
131 | #endif | |
132 | ||
dfc20895 SR |
133 | /* End of text section */ |
134 | _etext = .; | |
135 | } :text = 0x9090 | |
136 | ||
137 | NOTES :text :note | |
138 | ||
123f3e1d | 139 | EXCEPTION_TABLE(16) :text = 0x9090 |
448bc3ab | 140 | |
5bd5a452 MC |
141 | /* .text should occupy whole number of pages */ |
142 | . = ALIGN(PAGE_SIZE); | |
9ccaf77c | 143 | X64_ALIGN_RODATA_BEGIN |
c62e4320 | 144 | RO_DATA(PAGE_SIZE) |
9ccaf77c | 145 | X64_ALIGN_RODATA_END |
448bc3ab | 146 | |
1f6397ba | 147 | /* Data */ |
1f6397ba | 148 | .data : AT(ADDR(.data) - LOAD_OFFSET) { |
1260866a CM |
149 | /* Start of data section */ |
150 | _sdata = .; | |
c62e4320 JB |
151 | |
152 | /* init_task */ | |
153 | INIT_TASK_DATA(THREAD_SIZE) | |
1f6397ba SR |
154 | |
155 | #ifdef CONFIG_X86_32 | |
c62e4320 JB |
156 | /* 32 bit has nosave before _edata */ |
157 | NOSAVE_DATA | |
1f6397ba SR |
158 | #endif |
159 | ||
c62e4320 | 160 | PAGE_ALIGNED_DATA(PAGE_SIZE) |
1f6397ba | 161 | |
350f8f56 | 162 | CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES) |
1f6397ba | 163 | |
c62e4320 JB |
164 | DATA_DATA |
165 | CONSTRUCTORS | |
166 | ||
167 | /* rarely changed data like cpu maps */ | |
350f8f56 | 168 | READ_MOSTLY_DATA(INTERNODE_CACHE_BYTES) |
1f6397ba | 169 | |
1f6397ba SR |
170 | /* End of data section */ |
171 | _edata = .; | |
c62e4320 | 172 | } :data |
1f6397ba | 173 | |
b5effd38 | 174 | BUG_TABLE |
ff6f87e1 | 175 | |
ee9f8fce JP |
176 | ORC_UNWIND_TABLE |
177 | ||
9c40818d AL |
178 | . = ALIGN(PAGE_SIZE); |
179 | __vvar_page = .; | |
180 | ||
181 | .vvar : AT(ADDR(.vvar) - LOAD_OFFSET) { | |
f670bb76 AL |
182 | /* work around gold bug 13023 */ |
183 | __vvar_beginning_hack = .; | |
9c40818d | 184 | |
f670bb76 AL |
185 | /* Place all vvars at the offsets in asm/vvar.h. */ |
186 | #define EMIT_VVAR(name, offset) \ | |
187 | . = __vvar_beginning_hack + offset; \ | |
9c40818d AL |
188 | *(.vvar_ ## name) |
189 | #define __VVAR_KERNEL_LDS | |
190 | #include <asm/vvar.h> | |
191 | #undef __VVAR_KERNEL_LDS | |
192 | #undef EMIT_VVAR | |
193 | ||
309944be AL |
194 | /* |
195 | * Pad the rest of the page with zeros. Otherwise the loader | |
196 | * can leave garbage here. | |
197 | */ | |
198 | . = __vvar_beginning_hack + PAGE_SIZE; | |
9c40818d AL |
199 | } :data |
200 | ||
201 | . = ALIGN(__vvar_page + PAGE_SIZE, PAGE_SIZE); | |
202 | ||
c62e4320 JB |
203 | /* Init code and data - will be freed after init */ |
204 | . = ALIGN(PAGE_SIZE); | |
205 | .init.begin : AT(ADDR(.init.begin) - LOAD_OFFSET) { | |
206 | __init_begin = .; /* paired with __init_end */ | |
e58bdaa8 | 207 | } |
e58bdaa8 | 208 | |
c62e4320 | 209 | #if defined(CONFIG_X86_64) && defined(CONFIG_SMP) |
e58bdaa8 | 210 | /* |
c62e4320 JB |
211 | * percpu offsets are zero-based on SMP. PERCPU_VADDR() changes the |
212 | * output PHDR, so the next output section - .init.text - should | |
213 | * start another segment - init. | |
e58bdaa8 | 214 | */ |
19df0c2f | 215 | PERCPU_VADDR(INTERNODE_CACHE_BYTES, 0, :percpu) |
97b67ae5 JB |
216 | ASSERT(SIZEOF(.data..percpu) < CONFIG_PHYSICAL_START, |
217 | "per-CPU data too large - increase CONFIG_PHYSICAL_START") | |
c62e4320 | 218 | #endif |
e58bdaa8 | 219 | |
123f3e1d | 220 | INIT_TEXT_SECTION(PAGE_SIZE) |
c62e4320 JB |
221 | #ifdef CONFIG_X86_64 |
222 | :init | |
223 | #endif | |
e58bdaa8 | 224 | |
337e4cc8 BP |
225 | /* |
226 | * Section for code used exclusively before alternatives are run. All | |
227 | * references to such code must be patched out by alternatives, normally | |
228 | * by using X86_FEATURE_ALWAYS CPU feature bit. | |
229 | * | |
230 | * See static_cpu_has() for an example. | |
231 | */ | |
232 | .altinstr_aux : AT(ADDR(.altinstr_aux) - LOAD_OFFSET) { | |
233 | *(.altinstr_aux) | |
234 | } | |
235 | ||
123f3e1d | 236 | INIT_DATA_SECTION(16) |
e58bdaa8 SR |
237 | |
238 | .x86_cpu_dev.init : AT(ADDR(.x86_cpu_dev.init) - LOAD_OFFSET) { | |
239 | __x86_cpu_dev_start = .; | |
240 | *(.x86_cpu_dev.init) | |
241 | __x86_cpu_dev_end = .; | |
242 | } | |
243 | ||
66ac5013 DC |
244 | #ifdef CONFIG_X86_INTEL_MID |
245 | .x86_intel_mid_dev.init : AT(ADDR(.x86_intel_mid_dev.init) - \ | |
246 | LOAD_OFFSET) { | |
247 | __x86_intel_mid_dev_start = .; | |
248 | *(.x86_intel_mid_dev.init) | |
249 | __x86_intel_mid_dev_end = .; | |
250 | } | |
251 | #endif | |
252 | ||
6f44d033 KRW |
253 | /* |
254 | * start address and size of operations which during runtime | |
255 | * can be patched with virtualization friendly instructions or | |
256 | * baremetal native ones. Think page table operations. | |
257 | * Details in paravirt_types.h | |
258 | */ | |
ae618362 SR |
259 | . = ALIGN(8); |
260 | .parainstructions : AT(ADDR(.parainstructions) - LOAD_OFFSET) { | |
261 | __parainstructions = .; | |
262 | *(.parainstructions) | |
263 | __parainstructions_end = .; | |
264 | } | |
265 | ||
6f44d033 KRW |
266 | /* |
267 | * struct alt_inst entries. From the header (alternative.h): | |
268 | * "Alternative instructions for different CPU types or capabilities" | |
269 | * Think locking instructions on spinlocks. | |
270 | */ | |
ae618362 SR |
271 | . = ALIGN(8); |
272 | .altinstructions : AT(ADDR(.altinstructions) - LOAD_OFFSET) { | |
273 | __alt_instructions = .; | |
274 | *(.altinstructions) | |
275 | __alt_instructions_end = .; | |
276 | } | |
277 | ||
6f44d033 KRW |
278 | /* |
279 | * And here are the replacement instructions. The linker sticks | |
280 | * them as binary blobs. The .altinstructions has enough data to | |
281 | * get the address and the length of them to patch the kernel safely. | |
282 | */ | |
ae618362 SR |
283 | .altinstr_replacement : AT(ADDR(.altinstr_replacement) - LOAD_OFFSET) { |
284 | *(.altinstr_replacement) | |
285 | } | |
286 | ||
6f44d033 KRW |
287 | /* |
288 | * struct iommu_table_entry entries are injected in this section. | |
289 | * It is an array of IOMMUs which during run time gets sorted depending | |
290 | * on its dependency order. After rootfs_initcall is complete | |
291 | * this section can be safely removed. | |
292 | */ | |
0444ad93 KRW |
293 | .iommu_table : AT(ADDR(.iommu_table) - LOAD_OFFSET) { |
294 | __iommu_table = .; | |
295 | *(.iommu_table) | |
0444ad93 KRW |
296 | __iommu_table_end = .; |
297 | } | |
4822b7fc | 298 | |
107e0e0c SS |
299 | . = ALIGN(8); |
300 | .apicdrivers : AT(ADDR(.apicdrivers) - LOAD_OFFSET) { | |
301 | __apicdrivers = .; | |
302 | *(.apicdrivers); | |
303 | __apicdrivers_end = .; | |
304 | } | |
305 | ||
7ac41ccf | 306 | . = ALIGN(8); |
bf6a5741 SR |
307 | /* |
308 | * .exit.text is discard at runtime, not link time, to deal with | |
309 | * references from .altinstructions and .eh_frame | |
310 | */ | |
311 | .exit.text : AT(ADDR(.exit.text) - LOAD_OFFSET) { | |
312 | EXIT_TEXT | |
313 | } | |
314 | ||
315 | .exit.data : AT(ADDR(.exit.data) - LOAD_OFFSET) { | |
316 | EXIT_DATA | |
317 | } | |
318 | ||
c62e4320 | 319 | #if !defined(CONFIG_X86_64) || !defined(CONFIG_SMP) |
0415b00d | 320 | PERCPU_SECTION(INTERNODE_CACHE_BYTES) |
9d16e783 SR |
321 | #endif |
322 | ||
323 | . = ALIGN(PAGE_SIZE); | |
fd073194 | 324 | |
9d16e783 | 325 | /* freed after init ends here */ |
fd073194 IM |
326 | .init.end : AT(ADDR(.init.end) - LOAD_OFFSET) { |
327 | __init_end = .; | |
328 | } | |
9d16e783 | 329 | |
c62e4320 JB |
330 | /* |
331 | * smp_locks might be freed after init | |
332 | * start/end must be page aligned | |
333 | */ | |
334 | . = ALIGN(PAGE_SIZE); | |
335 | .smp_locks : AT(ADDR(.smp_locks) - LOAD_OFFSET) { | |
336 | __smp_locks = .; | |
337 | *(.smp_locks) | |
c62e4320 | 338 | . = ALIGN(PAGE_SIZE); |
596b711e | 339 | __smp_locks_end = .; |
c62e4320 JB |
340 | } |
341 | ||
9d16e783 SR |
342 | #ifdef CONFIG_X86_64 |
343 | .data_nosave : AT(ADDR(.data_nosave) - LOAD_OFFSET) { | |
c62e4320 JB |
344 | NOSAVE_DATA |
345 | } | |
9d16e783 SR |
346 | #endif |
347 | ||
091e52c3 SR |
348 | /* BSS */ |
349 | . = ALIGN(PAGE_SIZE); | |
350 | .bss : AT(ADDR(.bss) - LOAD_OFFSET) { | |
351 | __bss_start = .; | |
7c74df07 | 352 | *(.bss..page_aligned) |
091e52c3 | 353 | *(.bss) |
5bd5a452 | 354 | . = ALIGN(PAGE_SIZE); |
091e52c3 SR |
355 | __bss_stop = .; |
356 | } | |
9d16e783 | 357 | |
091e52c3 SR |
358 | . = ALIGN(PAGE_SIZE); |
359 | .brk : AT(ADDR(.brk) - LOAD_OFFSET) { | |
360 | __brk_base = .; | |
361 | . += 64 * 1024; /* 64k alignment slop space */ | |
362 | *(.brk_reservation) /* areas brk users have reserved */ | |
363 | __brk_limit = .; | |
364 | } | |
365 | ||
974f221c | 366 | . = ALIGN(PAGE_SIZE); /* keep VO_INIT_SIZE page aligned */ |
873b5271 | 367 | _end = .; |
091e52c3 | 368 | |
444e0ae4 SR |
369 | STABS_DEBUG |
370 | DWARF_DEBUG | |
023bf6f1 TH |
371 | |
372 | /* Sections to be discarded */ | |
373 | DISCARDS | |
9a99417a JP |
374 | /DISCARD/ : { |
375 | *(.eh_frame) | |
9a99417a | 376 | } |
444e0ae4 SR |
377 | } |
378 | ||
17ce265d SR |
379 | |
380 | #ifdef CONFIG_X86_32 | |
a5912f6b IM |
381 | /* |
382 | * The ASSERT() sink to . is intentional, for binutils 2.14 compatibility: | |
383 | */ | |
d2ba8b21 PA |
384 | . = ASSERT((_end - LOAD_OFFSET <= KERNEL_IMAGE_SIZE), |
385 | "kernel image bigger than KERNEL_IMAGE_SIZE"); | |
17ce265d SR |
386 | #else |
387 | /* | |
388 | * Per-cpu symbols which need to be offset from __per_cpu_load | |
389 | * for the boot processor. | |
390 | */ | |
dd17c8f7 | 391 | #define INIT_PER_CPU(x) init_per_cpu__##x = x + __per_cpu_load |
17ce265d SR |
392 | INIT_PER_CPU(gdt_page); |
393 | INIT_PER_CPU(irq_stack_union); | |
394 | ||
395 | /* | |
396 | * Build-time check on the image size: | |
397 | */ | |
d2ba8b21 PA |
398 | . = ASSERT((_end - _text <= KERNEL_IMAGE_SIZE), |
399 | "kernel image bigger than KERNEL_IMAGE_SIZE"); | |
17ce265d SR |
400 | |
401 | #ifdef CONFIG_SMP | |
dd17c8f7 | 402 | . = ASSERT((irq_stack_union == 0), |
d2ba8b21 | 403 | "irq_stack_union is not at start of per-cpu area"); |
17ce265d SR |
404 | #endif |
405 | ||
406 | #endif /* CONFIG_X86_32 */ | |
407 | ||
2965faa5 | 408 | #ifdef CONFIG_KEXEC_CORE |
17ce265d SR |
409 | #include <asm/kexec.h> |
410 | ||
d2ba8b21 PA |
411 | . = ASSERT(kexec_control_code_size <= KEXEC_CONTROL_CODE_MAX_SIZE, |
412 | "kexec control code size is too big"); | |
17ce265d SR |
413 | #endif |
414 |