[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / i8259.c

/*
 * 8259 interrupt controller emulation
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 * Copyright (c) 2007 Intel Corporation
 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 * Authors:
 *   Yaozu (Eddie) Dong <Eddie.dong@intel.com>
 *   Port from Qemu.
 */
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/bitops.h>
#include "irq.h"

#include <linux/kvm_host.h>
#include "trace.h"

static void pic_irq_request(struct kvm *kvm, int level);

static void pic_lock(struct kvm_pic *s)
	__acquires(&s->lock)
{
	spin_lock(&s->lock);
}

static void pic_unlock(struct kvm_pic *s)
	__releases(&s->lock)
{
	bool wakeup = s->wakeup_needed;
	struct kvm_vcpu *vcpu, *found = NULL;
	int i;

	s->wakeup_needed = false;

	spin_unlock(&s->lock);

	if (wakeup) {
		kvm_for_each_vcpu(i, vcpu, s->kvm) {
			if (kvm_apic_accept_pic_intr(vcpu)) {
				found = vcpu;
				break;
			}
		}

		if (!found)
			return;

		kvm_make_request(KVM_REQ_EVENT, found);
		kvm_vcpu_kick(found);
	}
}

static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
{
	s->isr &= ~(1 << irq);
	if (s != &s->pics_state->pics[0])
		irq += 8;
	/*
	 * We are dropping lock while calling ack notifiers since ack
	 * notifier callbacks for assigned devices call into PIC recursively.
	 * Other interrupt may be delivered to PIC while lock is dropped but
	 * it should be safe since PIC state is already updated at this stage.
	 */
	pic_unlock(s->pics_state);
	kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq);
	pic_lock(s->pics_state);
}

/*
 * set irq level. If an edge is detected, then the IRR is set to 1
 */
static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
{
	int mask, ret = 1;
	mask = 1 << irq;
	if (s->elcr & mask)	/* level triggered */
		if (level) {
			ret = !(s->irr & mask);
			s->irr |= mask;
			s->last_irr |= mask;
		} else {
			s->irr &= ~mask;
			s->last_irr &= ~mask;
		}
	else	/* edge triggered */
		if (level) {
			if ((s->last_irr & mask) == 0) {
				ret = !(s->irr & mask);
				s->irr |= mask;
			}
			s->last_irr |= mask;
		} else
			s->last_irr &= ~mask;

	return (s->imr & mask) ? -1 : ret;
}

/*
 * return the highest priority found in mask (highest = smallest
 * number). Return 8 if no irq
 */
static inline int get_priority(struct kvm_kpic_state *s, int mask)
{
	int priority;
	if (mask == 0)
		return 8;
	priority = 0;
	while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
		priority++;
	return priority;
}

/*
 * return the pic wanted interrupt. return -1 if none
 */
static int pic_get_irq(struct kvm_kpic_state *s)
{
	int mask, cur_priority, priority;

	mask = s->irr & ~s->imr;
	priority = get_priority(s, mask);
	if (priority == 8)
		return -1;
	/*
	 * compute current priority. If special fully nested mode on the
	 * master, the IRQ coming from the slave is not taken into account
	 * for the priority computation.
	 */
	mask = s->isr;
	if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
		mask &= ~(1 << 2);
	cur_priority = get_priority(s, mask);
	if (priority < cur_priority)
		/*
		 * higher priority found: an irq should be generated
		 */
		return (priority + s->priority_add) & 7;
	else
		return -1;
}

/*
 * raise irq to CPU if necessary. must be called every time the active
 * irq may change
 */
static void pic_update_irq(struct kvm_pic *s)
{
	int irq2, irq;

	irq2 = pic_get_irq(&s->pics[1]);
	if (irq2 >= 0) {
		/*
		 * if irq request by slave pic, signal master PIC
		 */
		pic_set_irq1(&s->pics[0], 2, 1);
		pic_set_irq1(&s->pics[0], 2, 0);
	}
	irq = pic_get_irq(&s->pics[0]);
	pic_irq_request(s->kvm, irq >= 0);
}

void kvm_pic_update_irq(struct kvm_pic *s)
{
	pic_lock(s);
	pic_update_irq(s);
	pic_unlock(s);
}

int kvm_pic_set_irq(void *opaque, int irq, int level)
{
	struct kvm_pic *s = opaque;
	int ret = -1;

	pic_lock(s);
	if (irq >= 0 && irq < PIC_NUM_PINS) {
		ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
		pic_update_irq(s);
		trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,
				      s->pics[irq >> 3].imr, ret == 0);
	}
	pic_unlock(s);

	return ret;
}

/*
 * acknowledge interrupt 'irq'
 */
static inline void pic_intack(struct kvm_kpic_state *s, int irq)
{
	s->isr |= 1 << irq;
	/*
	 * We don't clear a level sensitive interrupt here
	 */
	if (!(s->elcr & (1 << irq)))
		s->irr &= ~(1 << irq);

	if (s->auto_eoi) {
		if (s->rotate_on_auto_eoi)
			s->priority_add = (irq + 1) & 7;
		pic_clear_isr(s, irq);
	}

}

int kvm_pic_read_irq(struct kvm *kvm)
{
	int irq, irq2, intno;
	struct kvm_pic *s = pic_irqchip(kvm);

	pic_lock(s);
	irq = pic_get_irq(&s->pics[0]);
	if (irq >= 0) {
		pic_intack(&s->pics[0], irq);
		if (irq == 2) {
			irq2 = pic_get_irq(&s->pics[1]);
			if (irq2 >= 0)
				pic_intack(&s->pics[1], irq2);
			else
				/*
				 * spurious IRQ on slave controller
				 */
				irq2 = 7;
			intno = s->pics[1].irq_base + irq2;
			irq = irq2 + 8;
		} else
			intno = s->pics[0].irq_base + irq;
	} else {
		/*
		 * spurious IRQ on host controller
		 */
		irq = 7;
		intno = s->pics[0].irq_base + irq;
	}
	pic_update_irq(s);
	pic_unlock(s);

	return intno;
}

void kvm_pic_reset(struct kvm_kpic_state *s)
{
	int irq;
	struct kvm_vcpu *vcpu0 = s->pics_state->kvm->bsp_vcpu;
	u8 irr = s->irr, isr = s->imr;

	s->last_irr = 0;
	s->irr = 0;
	s->imr = 0;
	s->isr = 0;
	s->priority_add = 0;
	s->irq_base = 0;
	s->read_reg_select = 0;
	s->poll = 0;
	s->special_mask = 0;
	s->init_state = 0;
	s->auto_eoi = 0;
	s->rotate_on_auto_eoi = 0;
	s->special_fully_nested_mode = 0;
	s->init4 = 0;

	for (irq = 0; irq < PIC_NUM_PINS/2; irq++) {
		if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0))
			if (irr & (1 << irq) || isr & (1 << irq)) {
				pic_clear_isr(s, irq);
			}
	}
}

static void pic_ioport_write(void *opaque, u32 addr, u32 val)
{
	struct kvm_kpic_state *s = opaque;
	int priority, cmd, irq;

	addr &= 1;
	if (addr == 0) {
		if (val & 0x10) {
			s->init4 = val & 1;
			s->last_irr = 0;
			s->imr = 0;
			s->priority_add = 0;
			s->special_mask = 0;
			s->read_reg_select = 0;
			if (!s->init4) {
				s->special_fully_nested_mode = 0;
				s->auto_eoi = 0;
			}
			s->init_state = 1;
			if (val & 0x02)
				printk(KERN_ERR "single mode not supported");
			if (val & 0x08)
				printk(KERN_ERR
				       "level sensitive irq not supported");
		} else if (val & 0x08) {
			if (val & 0x04)
				s->poll = 1;
			if (val & 0x02)
				s->read_reg_select = val & 1;
			if (val & 0x40)
				s->special_mask = (val >> 5) & 1;
		} else {
			cmd = val >> 5;
			switch (cmd) {
			case 0:
			case 4:
				s->rotate_on_auto_eoi = cmd >> 2;
				break;
			case 1:	/* end of interrupt */
			case 5:
				priority = get_priority(s, s->isr);
				if (priority != 8) {
					irq = (priority + s->priority_add) & 7;
					if (cmd == 5)
						s->priority_add = (irq + 1) & 7;
					pic_clear_isr(s, irq);
					pic_update_irq(s->pics_state);
				}
				break;
			case 3:
				irq = val & 7;
				pic_clear_isr(s, irq);
				pic_update_irq(s->pics_state);
				break;
			case 6:
				s->priority_add = (val + 1) & 7;
				pic_update_irq(s->pics_state);
				break;
			case 7:
				irq = val & 7;
				s->priority_add = (irq + 1) & 7;
				pic_clear_isr(s, irq);
				pic_update_irq(s->pics_state);
				break;
			default:
				break;	/* no operation */
			}
		}
	} else
		switch (s->init_state) {
		case 0: { /* normal mode */
			u8 imr_diff = s->imr ^ val,
				off = (s == &s->pics_state->pics[0]) ? 0 : 8;
			s->imr = val;
			for (irq = 0; irq < PIC_NUM_PINS/2; irq++)
				if (imr_diff & (1 << irq))
					kvm_fire_mask_notifiers(
						s->pics_state->kvm,
						SELECT_PIC(irq + off),
						irq + off,
						!!(s->imr & (1 << irq)));
			pic_update_irq(s->pics_state);
			break;
		}
		case 1:
			s->irq_base = val & 0xf8;
			s->init_state = 2;
			break;
		case 2:
			if (s->init4)
				s->init_state = 3;
			else
				s->init_state = 0;
			break;
		case 3:
			s->special_fully_nested_mode = (val >> 4) & 1;
			s->auto_eoi = (val >> 1) & 1;
			s->init_state = 0;
			break;
		}
}

static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
{
	int ret;

	ret = pic_get_irq(s);
	if (ret >= 0) {
		if (addr1 >> 7) {
			s->pics_state->pics[0].isr &= ~(1 << 2);
			s->pics_state->pics[0].irr &= ~(1 << 2);
		}
		s->irr &= ~(1 << ret);
		pic_clear_isr(s, ret);
		if (addr1 >> 7 || ret != 2)
			pic_update_irq(s->pics_state);
	} else {
		ret = 0x07;
		pic_update_irq(s->pics_state);
	}

	return ret;
}

static u32 pic_ioport_read(void *opaque, u32 addr1)
{
	struct kvm_kpic_state *s = opaque;
	unsigned int addr;
	int ret;

	addr = addr1;
	addr &= 1;
	if (s->poll) {
		ret = pic_poll_read(s, addr1);
		s->poll = 0;
	} else
		if (addr == 0)
			if (s->read_reg_select)
				ret = s->isr;
			else
				ret = s->irr;
		else
			ret = s->imr;
	return ret;
}

static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
{
	struct kvm_kpic_state *s = opaque;
	s->elcr = val & s->elcr_mask;
}

static u32 elcr_ioport_read(void *opaque, u32 addr1)
{
	struct kvm_kpic_state *s = opaque;
	return s->elcr;
}

static int picdev_in_range(gpa_t addr)
{
	switch (addr) {
	case 0x20:
	case 0x21:
	case 0xa0:
	case 0xa1:
	case 0x4d0:
	case 0x4d1:
		return 1;
	default:
		return 0;
	}
}

static int picdev_write(struct kvm_pic *s,
			 gpa_t addr, int len, const void *val)
{
	unsigned char data = *(unsigned char *)val;
	if (!picdev_in_range(addr))
		return -EOPNOTSUPP;

	if (len != 1) {
		if (printk_ratelimit())
			printk(KERN_ERR "PIC: non byte write\n");
		return 0;
	}
	pic_lock(s);
	switch (addr) {
	case 0x20:
	case 0x21:
	case 0xa0:
	case 0xa1:
		pic_ioport_write(&s->pics[addr >> 7], addr, data);
		break;
	case 0x4d0:
	case 0x4d1:
		elcr_ioport_write(&s->pics[addr & 1], addr, data);
		break;
	}
	pic_unlock(s);
	return 0;
}

static int picdev_read(struct kvm_pic *s,
		       gpa_t addr, int len, void *val)
{
	unsigned char data = 0;
	if (!picdev_in_range(addr))
		return -EOPNOTSUPP;

	if (len != 1) {
		if (printk_ratelimit())
			printk(KERN_ERR "PIC: non byte read\n");
		return 0;
	}
	pic_lock(s);
	switch (addr) {
	case 0x20:
	case 0x21:
	case 0xa0:
	case 0xa1:
		data = pic_ioport_read(&s->pics[addr >> 7], addr);
		break;
	case 0x4d0:
	case 0x4d1:
		data = elcr_ioport_read(&s->pics[addr & 1], addr);
		break;
	}
	*(unsigned char *)val = data;
	pic_unlock(s);
	return 0;
}

static int picdev_master_write(struct kvm_io_device *dev,
			       gpa_t addr, int len, const void *val)
{
	return picdev_write(container_of(dev, struct kvm_pic, dev_master),
			    addr, len, val);
}

static int picdev_master_read(struct kvm_io_device *dev,
			      gpa_t addr, int len, void *val)
{
	return picdev_read(container_of(dev, struct kvm_pic, dev_master),
			    addr, len, val);
}

static int picdev_slave_write(struct kvm_io_device *dev,
			      gpa_t addr, int len, const void *val)
{
	return picdev_write(container_of(dev, struct kvm_pic, dev_slave),
			    addr, len, val);
}

static int picdev_slave_read(struct kvm_io_device *dev,
			     gpa_t addr, int len, void *val)
{
	return picdev_read(container_of(dev, struct kvm_pic, dev_slave),
			    addr, len, val);
}

static int picdev_eclr_write(struct kvm_io_device *dev,
			     gpa_t addr, int len, const void *val)
{
	return picdev_write(container_of(dev, struct kvm_pic, dev_eclr),
			    addr, len, val);
}

static int picdev_eclr_read(struct kvm_io_device *dev,
			    gpa_t addr, int len, void *val)
{
	return picdev_read(container_of(dev, struct kvm_pic, dev_eclr),
			    addr, len, val);
}

/*
 * callback when PIC0 irq status changed
 */
static void pic_irq_request(struct kvm *kvm, int level)
{
	struct kvm_pic *s = pic_irqchip(kvm);

	if (!s->output)
		s->wakeup_needed = true;
	s->output = level;
}

static const struct kvm_io_device_ops picdev_master_ops = {
	.read     = picdev_master_read,
	.write    = picdev_master_write,
};

static const struct kvm_io_device_ops picdev_slave_ops = {
	.read     = picdev_slave_read,
	.write    = picdev_slave_write,
};

static const struct kvm_io_device_ops picdev_eclr_ops = {
	.read     = picdev_eclr_read,
	.write    = picdev_eclr_write,
};

struct kvm_pic *kvm_create_pic(struct kvm *kvm)
{
	struct kvm_pic *s;
	int ret;

	s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
	if (!s)
		return NULL;
	spin_lock_init(&s->lock);
	s->kvm = kvm;
	s->pics[0].elcr_mask = 0xf8;
	s->pics[1].elcr_mask = 0xde;
	s->pics[0].pics_state = s;
	s->pics[1].pics_state = s;

	/*
	 * Initialize PIO device
	 */
	kvm_iodevice_init(&s->dev_master, &picdev_master_ops);
	kvm_iodevice_init(&s->dev_slave, &picdev_slave_ops);
	kvm_iodevice_init(&s->dev_eclr, &picdev_eclr_ops);
	mutex_lock(&kvm->slots_lock);
	ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0x20, 2,
				      &s->dev_master);
	if (ret < 0)
		goto fail_unlock;

	ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0xa0, 2, &s->dev_slave);
	if (ret < 0)
		goto fail_unreg_2;

	ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0x4d0, 2, &s->dev_eclr);
	if (ret < 0)
		goto fail_unreg_1;

	mutex_unlock(&kvm->slots_lock);

	return s;

fail_unreg_1:
	kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &s->dev_slave);

fail_unreg_2:
	kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &s->dev_master);

fail_unlock:
	mutex_unlock(&kvm->slots_lock);

	kfree(s);

	return NULL;
}

void kvm_destroy_pic(struct kvm *kvm)
{
	struct kvm_pic *vpic = kvm->arch.vpic;

	if (vpic) {
		kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &vpic->dev_master);
		kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &vpic->dev_slave);
		kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &vpic->dev_eclr);
		kvm->arch.vpic = NULL;
		kfree(vpic);
	}
}
Commit	Line	Data
85f455f7 ED	1	/*
	2	* 8259 interrupt controller emulation
	3	*
	4	* Copyright (c) 2003-2004 Fabrice Bellard
	5	* Copyright (c) 2007 Intel Corporation
9611c187	6	* Copyright 2009 Red Hat, Inc. and/or its affiliates.
85f455f7 ED	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	* Authors:
	26	* Yaozu (Eddie) Dong <Eddie.dong@intel.com>
	27	* Port from Qemu.
	28	*/
	29	#include <linux/mm.h>
5a0e3ad6	30	#include <linux/slab.h>
3f353858	31	#include <linux/bitops.h>
85f455f7	32	#include "irq.h"
edf88417 AK	33
edf88417 AK	34	#include <linux/kvm_host.h>
1000ff8d	35	#include "trace.h"
85f455f7	36
073d4613 AK	37	static void pic_irq_request(struct kvm *kvm, int level);
073d4613 AK	38
50a085bd JK	39	static void pic_lock(struct kvm_pic *s)
	40	__acquires(&s->lock)
	41	{
f4f51050	42	spin_lock(&s->lock);
50a085bd JK	43	}
	44
	45	static void pic_unlock(struct kvm_pic *s)
	46	__releases(&s->lock)
	47	{
	48	bool wakeup = s->wakeup_needed;
529df65e CL	49	struct kvm_vcpu vcpu, found = NULL;
529df65e CL	50	int i;
50a085bd JK	51
	52	s->wakeup_needed = false;
	53
f4f51050	54	spin_unlock(&s->lock);
50a085bd JK	55
50a085bd JK	56	if (wakeup) {
529df65e CL	57	kvm_for_each_vcpu(i, vcpu, s->kvm) {
	58	if (kvm_apic_accept_pic_intr(vcpu)) {
	59	found = vcpu;
	60	break;
	61	}
	62	}
	63
ae0635b3 AK	64	if (!found)
	65	return;
	66
3842d135	67	kvm_make_request(KVM_REQ_EVENT, found);
529df65e	68	kvm_vcpu_kick(found);
50a085bd JK	69	}
	70	}
	71
7edd0ce0 AK	72	static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
	73	{
	74	s->isr &= ~(1 << irq);
938396a2 GN	75	if (s != &s->pics_state->pics[0])
938396a2 GN	76	irq += 8;
eba0226b GN	77	/*
	78	* We are dropping lock while calling ack notifiers since ack
	79	* notifier callbacks for assigned devices call into PIC recursively.
	80	* Other interrupt may be delivered to PIC while lock is dropped but
	81	* it should be safe since PIC state is already updated at this stage.
	82	*/
50a085bd	83	pic_unlock(s->pics_state);
938396a2	84	kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq);
50a085bd	85	pic_lock(s->pics_state);
e4825800 MT	86	}
e4825800 MT	87
85f455f7 ED	88	/*
	89	* set irq level. If an edge is detected, then the IRR is set to 1
	90	*/
4925663a	91	static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
85f455f7	92	{
4925663a	93	int mask, ret = 1;
85f455f7 ED	94	mask = 1 << irq;
	95	if (s->elcr & mask) /* level triggered */
	96	if (level) {
4925663a	97	ret = !(s->irr & mask);
85f455f7 ED	98	s->irr \|= mask;
	99	s->last_irr \|= mask;
	100	} else {
	101	s->irr &= ~mask;
	102	s->last_irr &= ~mask;
	103	}
	104	else /* edge triggered */
	105	if (level) {
4925663a GN	106	if ((s->last_irr & mask) == 0) {
4925663a GN	107	ret = !(s->irr & mask);
85f455f7	108	s->irr \|= mask;
4925663a	109	}
85f455f7 ED	110	s->last_irr \|= mask;
	111	} else
	112	s->last_irr &= ~mask;
4925663a GN	113
4925663a GN	114	return (s->imr & mask) ? -1 : ret;
85f455f7 ED	115	}
	116
	117	/*
	118	* return the highest priority found in mask (highest = smallest
	119	* number). Return 8 if no irq
	120	*/
	121	static inline int get_priority(struct kvm_kpic_state *s, int mask)
	122	{
	123	int priority;
	124	if (mask == 0)
	125	return 8;
	126	priority = 0;
	127	while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
	128	priority++;
	129	return priority;
	130	}
	131
	132	/*
	133	* return the pic wanted interrupt. return -1 if none
	134	*/
	135	static int pic_get_irq(struct kvm_kpic_state *s)
	136	{
	137	int mask, cur_priority, priority;
	138
	139	mask = s->irr & ~s->imr;
	140	priority = get_priority(s, mask);
	141	if (priority == 8)
	142	return -1;
	143	/*
	144	* compute current priority. If special fully nested mode on the
	145	* master, the IRQ coming from the slave is not taken into account
	146	* for the priority computation.
	147	*/
	148	mask = s->isr;
	149	if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
	150	mask &= ~(1 << 2);
	151	cur_priority = get_priority(s, mask);
	152	if (priority < cur_priority)
	153	/*
	154	* higher priority found: an irq should be generated
	155	*/
	156	return (priority + s->priority_add) & 7;
	157	else
	158	return -1;
	159	}
	160
	161	/*
	162	* raise irq to CPU if necessary. must be called every time the active
	163	* irq may change
	164	*/
	165	static void pic_update_irq(struct kvm_pic *s)
	166	{
	167	int irq2, irq;
	168
	169	irq2 = pic_get_irq(&s->pics[1]);
	170	if (irq2 >= 0) {
	171	/*
	172	* if irq request by slave pic, signal master PIC
	173	*/
	174	pic_set_irq1(&s->pics[0], 2, 1);
	175	pic_set_irq1(&s->pics[0], 2, 0);
	176	}
	177	irq = pic_get_irq(&s->pics[0]);
36633f32	178	pic_irq_request(s->kvm, irq >= 0);
85f455f7 ED	179	}
85f455f7 ED	180
6ceb9d79 HQ	181	void kvm_pic_update_irq(struct kvm_pic *s)
6ceb9d79 HQ	182	{
50a085bd	183	pic_lock(s);
6ceb9d79	184	pic_update_irq(s);
50a085bd	185	pic_unlock(s);
6ceb9d79 HQ	186	}
6ceb9d79 HQ	187
4925663a	188	int kvm_pic_set_irq(void *opaque, int irq, int level)
85f455f7 ED	189	{
85f455f7 ED	190	struct kvm_pic *s = opaque;
4925663a	191	int ret = -1;
85f455f7	192
50a085bd	193	pic_lock(s);
c65bbfa1	194	if (irq >= 0 && irq < PIC_NUM_PINS) {
4925663a	195	ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
c65bbfa1	196	pic_update_irq(s);
1000ff8d GN	197	trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,
1000ff8d GN	198	s->pics[irq >> 3].imr, ret == 0);
c65bbfa1	199	}
50a085bd	200	pic_unlock(s);
4925663a GN	201
4925663a GN	202	return ret;
85f455f7 ED	203	}
	204
	205	/*
	206	* acknowledge interrupt 'irq'
	207	*/
	208	static inline void pic_intack(struct kvm_kpic_state *s, int irq)
	209	{
7edd0ce0	210	s->isr \|= 1 << irq;
85f455f7 ED	211	/*
	212	* We don't clear a level sensitive interrupt here
	213	*/
	214	if (!(s->elcr & (1 << irq)))
	215	s->irr &= ~(1 << irq);
eba0226b GN	216
	217	if (s->auto_eoi) {
	218	if (s->rotate_on_auto_eoi)
	219	s->priority_add = (irq + 1) & 7;
	220	pic_clear_isr(s, irq);
	221	}
	222
85f455f7 ED	223	}
85f455f7 ED	224
f5244726	225	int kvm_pic_read_irq(struct kvm *kvm)
85f455f7 ED	226	{
85f455f7 ED	227	int irq, irq2, intno;
f5244726	228	struct kvm_pic *s = pic_irqchip(kvm);
85f455f7	229
50a085bd	230	pic_lock(s);
85f455f7 ED	231	irq = pic_get_irq(&s->pics[0]);
	232	if (irq >= 0) {
	233	pic_intack(&s->pics[0], irq);
	234	if (irq == 2) {
	235	irq2 = pic_get_irq(&s->pics[1]);
	236	if (irq2 >= 0)
	237	pic_intack(&s->pics[1], irq2);
	238	else
	239	/*
	240	* spurious IRQ on slave controller
	241	*/
	242	irq2 = 7;
	243	intno = s->pics[1].irq_base + irq2;
	244	irq = irq2 + 8;
	245	} else
	246	intno = s->pics[0].irq_base + irq;
	247	} else {
	248	/*
	249	* spurious IRQ on host controller
	250	*/
	251	irq = 7;
	252	intno = s->pics[0].irq_base + irq;
	253	}
	254	pic_update_irq(s);
50a085bd	255	pic_unlock(s);
85f455f7 ED	256
	257	return intno;
	258	}
	259
2fcceae1	260	void kvm_pic_reset(struct kvm_kpic_state *s)
85f455f7	261	{
79c727d4	262	int irq;
073d4613	263	struct kvm_vcpu *vcpu0 = s->pics_state->kvm->bsp_vcpu;
79c727d4	264	u8 irr = s->irr, isr = s->imr;
f5244726	265
85f455f7 ED	266	s->last_irr = 0;
	267	s->irr = 0;
	268	s->imr = 0;
	269	s->isr = 0;
	270	s->priority_add = 0;
	271	s->irq_base = 0;
	272	s->read_reg_select = 0;
	273	s->poll = 0;
	274	s->special_mask = 0;
	275	s->init_state = 0;
	276	s->auto_eoi = 0;
	277	s->rotate_on_auto_eoi = 0;
	278	s->special_fully_nested_mode = 0;
	279	s->init4 = 0;
79c727d4 GN	280
	281	for (irq = 0; irq < PIC_NUM_PINS/2; irq++) {
	282	if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0))
	283	if (irr & (1 << irq) \|\| isr & (1 << irq)) {
	284	pic_clear_isr(s, irq);
	285	}
	286	}
85f455f7 ED	287	}
	288
	289	static void pic_ioport_write(void *opaque, u32 addr, u32 val)
	290	{
	291	struct kvm_kpic_state *s = opaque;
	292	int priority, cmd, irq;
	293
	294	addr &= 1;
	295	if (addr == 0) {
	296	if (val & 0x10) {
85f455f7	297	s->init4 = val & 1;
9ed049c3 AK	298	s->last_irr = 0;
	299	s->imr = 0;
	300	s->priority_add = 0;
	301	s->special_mask = 0;
	302	s->read_reg_select = 0;
	303	if (!s->init4) {
	304	s->special_fully_nested_mode = 0;
	305	s->auto_eoi = 0;
	306	}
	307	s->init_state = 1;
85f455f7 ED	308	if (val & 0x02)
	309	printk(KERN_ERR "single mode not supported");
	310	if (val & 0x08)
	311	printk(KERN_ERR
	312	"level sensitive irq not supported");
	313	} else if (val & 0x08) {
	314	if (val & 0x04)
	315	s->poll = 1;
	316	if (val & 0x02)
	317	s->read_reg_select = val & 1;
	318	if (val & 0x40)
	319	s->special_mask = (val >> 5) & 1;
	320	} else {
	321	cmd = val >> 5;
	322	switch (cmd) {
	323	case 0:
	324	case 4:
	325	s->rotate_on_auto_eoi = cmd >> 2;
	326	break;
	327	case 1: /* end of interrupt */
	328	case 5:
	329	priority = get_priority(s, s->isr);
	330	if (priority != 8) {
	331	irq = (priority + s->priority_add) & 7;
85f455f7 ED	332	if (cmd == 5)
85f455f7 ED	333	s->priority_add = (irq + 1) & 7;
eba0226b	334	pic_clear_isr(s, irq);
85f455f7 ED	335	pic_update_irq(s->pics_state);
	336	}
	337	break;
	338	case 3:
	339	irq = val & 7;
7edd0ce0	340	pic_clear_isr(s, irq);
85f455f7 ED	341	pic_update_irq(s->pics_state);
	342	break;
	343	case 6:
	344	s->priority_add = (val + 1) & 7;
	345	pic_update_irq(s->pics_state);
	346	break;
	347	case 7:
	348	irq = val & 7;
85f455f7	349	s->priority_add = (irq + 1) & 7;
7edd0ce0	350	pic_clear_isr(s, irq);
85f455f7 ED	351	pic_update_irq(s->pics_state);
	352	break;
	353	default:
	354	break; /* no operation */
	355	}
	356	}
	357	} else
	358	switch (s->init_state) {
9195c4da GN	359	case 0: { /* normal mode */
	360	u8 imr_diff = s->imr ^ val,
	361	off = (s == &s->pics_state->pics[0]) ? 0 : 8;
85f455f7	362	s->imr = val;
9195c4da GN	363	for (irq = 0; irq < PIC_NUM_PINS/2; irq++)
	364	if (imr_diff & (1 << irq))
	365	kvm_fire_mask_notifiers(
	366	s->pics_state->kvm,
	367	SELECT_PIC(irq + off),
	368	irq + off,
	369	!!(s->imr & (1 << irq)));
85f455f7 ED	370	pic_update_irq(s->pics_state);
85f455f7 ED	371	break;
9195c4da	372	}
85f455f7 ED	373	case 1:
	374	s->irq_base = val & 0xf8;
	375	s->init_state = 2;
	376	break;
	377	case 2:
	378	if (s->init4)
	379	s->init_state = 3;
	380	else
	381	s->init_state = 0;
	382	break;
	383	case 3:
	384	s->special_fully_nested_mode = (val >> 4) & 1;
	385	s->auto_eoi = (val >> 1) & 1;
	386	s->init_state = 0;
	387	break;
	388	}
	389	}
	390
	391	static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
	392	{
	393	int ret;
	394
	395	ret = pic_get_irq(s);
	396	if (ret >= 0) {
	397	if (addr1 >> 7) {
	398	s->pics_state->pics[0].isr &= ~(1 << 2);
	399	s->pics_state->pics[0].irr &= ~(1 << 2);
	400	}
	401	s->irr &= ~(1 << ret);
7edd0ce0	402	pic_clear_isr(s, ret);
85f455f7 ED	403	if (addr1 >> 7 \|\| ret != 2)
	404	pic_update_irq(s->pics_state);
	405	} else {
	406	ret = 0x07;
	407	pic_update_irq(s->pics_state);
	408	}
	409
	410	return ret;
	411	}
	412
	413	static u32 pic_ioport_read(void *opaque, u32 addr1)
	414	{
	415	struct kvm_kpic_state *s = opaque;
	416	unsigned int addr;
	417	int ret;
	418
	419	addr = addr1;
	420	addr &= 1;
	421	if (s->poll) {
	422	ret = pic_poll_read(s, addr1);
	423	s->poll = 0;
	424	} else
	425	if (addr == 0)
	426	if (s->read_reg_select)
	427	ret = s->isr;
	428	else
	429	ret = s->irr;
	430	else
	431	ret = s->imr;
	432	return ret;
	433	}
	434
	435	static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
	436	{
	437	struct kvm_kpic_state *s = opaque;
	438	s->elcr = val & s->elcr_mask;
	439	}
	440
	441	static u32 elcr_ioport_read(void *opaque, u32 addr1)
	442	{
	443	struct kvm_kpic_state *s = opaque;
	444	return s->elcr;
	445	}
	446
bda9020e	447	static int picdev_in_range(gpa_t addr)
85f455f7 ED	448	{
	449	switch (addr) {
	450	case 0x20:
	451	case 0x21:
	452	case 0xa0:
	453	case 0xa1:
	454	case 0x4d0:
	455	case 0x4d1:
	456	return 1;
	457	default:
	458	return 0;
	459	}
	460	}
	461
743eeb0b	462	static int picdev_write(struct kvm_pic *s,
85f455f7 ED	463	gpa_t addr, int len, const void *val)
85f455f7 ED	464	{
85f455f7	465	unsigned char data = (unsigned char )val;
bda9020e MT	466	if (!picdev_in_range(addr))
bda9020e MT	467	return -EOPNOTSUPP;
85f455f7 ED	468
	469	if (len != 1) {
	470	if (printk_ratelimit())
	471	printk(KERN_ERR "PIC: non byte write\n");
bda9020e	472	return 0;
85f455f7	473	}
50a085bd	474	pic_lock(s);
85f455f7 ED	475	switch (addr) {
	476	case 0x20:
	477	case 0x21:
	478	case 0xa0:
	479	case 0xa1:
	480	pic_ioport_write(&s->pics[addr >> 7], addr, data);
	481	break;
	482	case 0x4d0:
	483	case 0x4d1:
	484	elcr_ioport_write(&s->pics[addr & 1], addr, data);
	485	break;
	486	}
50a085bd	487	pic_unlock(s);
bda9020e	488	return 0;
85f455f7 ED	489	}
85f455f7 ED	490
743eeb0b	491	static int picdev_read(struct kvm_pic *s,
bda9020e	492	gpa_t addr, int len, void *val)
85f455f7	493	{
85f455f7	494	unsigned char data = 0;
bda9020e MT	495	if (!picdev_in_range(addr))
bda9020e MT	496	return -EOPNOTSUPP;
85f455f7 ED	497
	498	if (len != 1) {
	499	if (printk_ratelimit())
	500	printk(KERN_ERR "PIC: non byte read\n");
bda9020e	501	return 0;
85f455f7	502	}
50a085bd	503	pic_lock(s);
85f455f7 ED	504	switch (addr) {
	505	case 0x20:
	506	case 0x21:
	507	case 0xa0:
	508	case 0xa1:
	509	data = pic_ioport_read(&s->pics[addr >> 7], addr);
	510	break;
	511	case 0x4d0:
	512	case 0x4d1:
	513	data = elcr_ioport_read(&s->pics[addr & 1], addr);
	514	break;
	515	}
	516	(unsigned char )val = data;
50a085bd	517	pic_unlock(s);
bda9020e	518	return 0;
85f455f7 ED	519	}
85f455f7 ED	520
743eeb0b SL	521	static int picdev_master_write(struct kvm_io_device *dev,
	522	gpa_t addr, int len, const void *val)
	523	{
	524	return picdev_write(container_of(dev, struct kvm_pic, dev_master),
	525	addr, len, val);
	526	}
	527
	528	static int picdev_master_read(struct kvm_io_device *dev,
	529	gpa_t addr, int len, void *val)
	530	{
	531	return picdev_read(container_of(dev, struct kvm_pic, dev_master),
	532	addr, len, val);
	533	}
	534
	535	static int picdev_slave_write(struct kvm_io_device *dev,
	536	gpa_t addr, int len, const void *val)
	537	{
	538	return picdev_write(container_of(dev, struct kvm_pic, dev_slave),
	539	addr, len, val);
	540	}
	541
	542	static int picdev_slave_read(struct kvm_io_device *dev,
	543	gpa_t addr, int len, void *val)
	544	{
	545	return picdev_read(container_of(dev, struct kvm_pic, dev_slave),
	546	addr, len, val);
	547	}
	548
	549	static int picdev_eclr_write(struct kvm_io_device *dev,
	550	gpa_t addr, int len, const void *val)
	551	{
	552	return picdev_write(container_of(dev, struct kvm_pic, dev_eclr),
	553	addr, len, val);
	554	}
	555
	556	static int picdev_eclr_read(struct kvm_io_device *dev,
	557	gpa_t addr, int len, void *val)
	558	{
	559	return picdev_read(container_of(dev, struct kvm_pic, dev_eclr),
	560	addr, len, val);
	561	}
	562
85f455f7 ED	563	/*
	564	* callback when PIC0 irq status changed
	565	*/
073d4613	566	static void pic_irq_request(struct kvm *kvm, int level)
85f455f7	567	{
e4825800	568	struct kvm_pic *s = pic_irqchip(kvm);
85f455f7	569
7049467b	570	if (!s->output)
50a085bd	571	s->wakeup_needed = true;
7049467b	572	s->output = level;
85f455f7 ED	573	}
85f455f7 ED	574
743eeb0b SL	575	static const struct kvm_io_device_ops picdev_master_ops = {
	576	.read = picdev_master_read,
	577	.write = picdev_master_write,
	578	};
	579
	580	static const struct kvm_io_device_ops picdev_slave_ops = {
	581	.read = picdev_slave_read,
	582	.write = picdev_slave_write,
	583	};
	584
	585	static const struct kvm_io_device_ops picdev_eclr_ops = {
	586	.read = picdev_eclr_read,
	587	.write = picdev_eclr_write,
d76685c4 GH	588	};
d76685c4 GH	589
85f455f7 ED	590	struct kvm_pic kvm_create_pic(struct kvm kvm)
	591	{
	592	struct kvm_pic *s;
090b7aff GH	593	int ret;
090b7aff GH	594
85f455f7 ED	595	s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
	596	if (!s)
	597	return NULL;
f4f51050	598	spin_lock_init(&s->lock);
3f353858	599	s->kvm = kvm;
85f455f7 ED	600	s->pics[0].elcr_mask = 0xf8;
85f455f7 ED	601	s->pics[1].elcr_mask = 0xde;
85f455f7 ED	602	s->pics[0].pics_state = s;
	603	s->pics[1].pics_state = s;
	604
	605	/*
	606	* Initialize PIO device
	607	*/
743eeb0b SL	608	kvm_iodevice_init(&s->dev_master, &picdev_master_ops);
	609	kvm_iodevice_init(&s->dev_slave, &picdev_slave_ops);
	610	kvm_iodevice_init(&s->dev_eclr, &picdev_eclr_ops);
79fac95e	611	mutex_lock(&kvm->slots_lock);
743eeb0b SL	612	ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0x20, 2,
	613	&s->dev_master);
	614	if (ret < 0)
	615	goto fail_unlock;
	616
	617	ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0xa0, 2, &s->dev_slave);
	618	if (ret < 0)
	619	goto fail_unreg_2;
	620
	621	ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0x4d0, 2, &s->dev_eclr);
	622	if (ret < 0)
	623	goto fail_unreg_1;
	624
79fac95e	625	mutex_unlock(&kvm->slots_lock);
090b7aff	626
85f455f7	627	return s;
743eeb0b SL	628
	629	fail_unreg_1:
	630	kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &s->dev_slave);
	631
	632	fail_unreg_2:
	633	kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &s->dev_master);
	634
	635	fail_unlock:
	636	mutex_unlock(&kvm->slots_lock);
	637
	638	kfree(s);
	639
	640	return NULL;
85f455f7	641	}
72bb2fcd WY	642
	643	void kvm_destroy_pic(struct kvm *kvm)
	644	{
	645	struct kvm_pic *vpic = kvm->arch.vpic;
	646
	647	if (vpic) {
743eeb0b SL	648	kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &vpic->dev_master);
	649	kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &vpic->dev_slave);
	650	kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &vpic->dev_eclr);
72bb2fcd WY	651	kvm->arch.vpic = NULL;
	652	kfree(vpic);
	653	}
	654	}