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KVM: ia64: add a dummy irq ack notification
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / lapic.c
CommitLineData
97222cc8
ED		 1
2/*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 *
9 * Authors:
10 * Dor Laor <dor.laor@qumranet.com>
11 * Gregory Haskins <ghaskins@novell.com>
12 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
13 *
14 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 */
19
edf88417 20#include <linux/kvm_host.h>
97222cc8
ED		 21#include <linux/kvm.h>
22#include <linux/mm.h>
23#include <linux/highmem.h>
24#include <linux/smp.h>
25#include <linux/hrtimer.h>
26#include <linux/io.h>
27#include <linux/module.h>
6f6d6a1a 28#include <linux/math64.h>
97222cc8
ED		 29#include <asm/processor.h>
30#include <asm/msr.h>
31#include <asm/page.h>
32#include <asm/current.h>
33#include <asm/apicdef.h>
34#include <asm/atomic.h>
5fdbf976 35#include "kvm_cache_regs.h"
97222cc8
ED		 36#include "irq.h"
37
38#define PRId64 "d"
39#define PRIx64 "llx"
40#define PRIu64 "u"
41#define PRIo64 "o"
42
43#define APIC_BUS_CYCLE_NS 1
44
45/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
46#define apic_debug(fmt, arg...)
47
48#define APIC_LVT_NUM 6
49/* 14 is the version for Xeon and Pentium 8.4.8*/
50#define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
51#define LAPIC_MMIO_LENGTH (1 << 12)
52/* followed define is not in apicdef.h */
53#define APIC_SHORT_MASK 0xc0000
54#define APIC_DEST_NOSHORT 0x0
55#define APIC_DEST_MASK 0x800
56#define MAX_APIC_VECTOR 256
57
58#define VEC_POS(v) ((v) & (32 - 1))
59#define REG_POS(v) (((v) >> 5) << 4)
ad312c7c 60
97222cc8
ED		 61static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
62{
63 return *((u32 *) (apic->regs + reg_off));
64}
65
66static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
67{
68 *((u32 *) (apic->regs + reg_off)) = val;
69}
70
71static inline int apic_test_and_set_vector(int vec, void *bitmap)
72{
73 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
74}
75
76static inline int apic_test_and_clear_vector(int vec, void *bitmap)
77{
78 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
79}
80
81static inline void apic_set_vector(int vec, void *bitmap)
82{
83 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
84}
85
86static inline void apic_clear_vector(int vec, void *bitmap)
87{
88 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
89}
90
91static inline int apic_hw_enabled(struct kvm_lapic *apic)
92{
ad312c7c 93 return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
97222cc8
ED		 94}
95
96static inline int apic_sw_enabled(struct kvm_lapic *apic)
97{
98 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
99}
100
101static inline int apic_enabled(struct kvm_lapic *apic)
102{
103 return apic_sw_enabled(apic) && apic_hw_enabled(apic);
104}
105
106#define LVT_MASK \
107 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
108
109#define LINT_MASK \
110 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
111 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
112
113static inline int kvm_apic_id(struct kvm_lapic *apic)
114{
115 return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
116}
117
118static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
119{
120 return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
121}
122
123static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
124{
125 return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
126}
127
128static inline int apic_lvtt_period(struct kvm_lapic *apic)
129{
130 return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
131}
132
133static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
134 LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */
135 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
136 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
137 LINT_MASK, LINT_MASK, /* LVT0-1 */
138 LVT_MASK /* LVTERR */
139};
140
141static int find_highest_vector(void *bitmap)
142{
143 u32 *word = bitmap;
144 int word_offset = MAX_APIC_VECTOR >> 5;
145
146 while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
147 continue;
148
149 if (likely(!word_offset && !word[0]))
150 return -1;
151 else
152 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
153}
154
155static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
156{
157 return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
158}
159
160static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
161{
162 apic_clear_vector(vec, apic->regs + APIC_IRR);
163}
164
165static inline int apic_find_highest_irr(struct kvm_lapic *apic)
166{
167 int result;
168
169 result = find_highest_vector(apic->regs + APIC_IRR);
170 ASSERT(result == -1 || result >= 16);
171
172 return result;
173}
174
6e5d865c
YS		 175int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
176{
ad312c7c 177 struct kvm_lapic *apic = vcpu->arch.apic;
6e5d865c
YS		 178 int highest_irr;
179
180 if (!apic)
181 return 0;
182 highest_irr = apic_find_highest_irr(apic);
183
184 return highest_irr;
185}
186EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
187
8be5453f 188int kvm_apic_set_irq(struct kvm_vcpu *vcpu, u8 vec, u8 trig)
97222cc8 189{
ad312c7c 190 struct kvm_lapic *apic = vcpu->arch.apic;
8be5453f 191
97222cc8
ED		 192 if (!apic_test_and_set_irr(vec, apic)) {
193 /* a new pending irq is set in IRR */
194 if (trig)
195 apic_set_vector(vec, apic->regs + APIC_TMR);
196 else
197 apic_clear_vector(vec, apic->regs + APIC_TMR);
198 kvm_vcpu_kick(apic->vcpu);
199 return 1;
200 }
201 return 0;
202}
203
204static inline int apic_find_highest_isr(struct kvm_lapic *apic)
205{
206 int result;
207
208 result = find_highest_vector(apic->regs + APIC_ISR);
209 ASSERT(result == -1 || result >= 16);
210
211 return result;
212}
213
214static void apic_update_ppr(struct kvm_lapic *apic)
215{
216 u32 tpr, isrv, ppr;
217 int isr;
218
219 tpr = apic_get_reg(apic, APIC_TASKPRI);
220 isr = apic_find_highest_isr(apic);
221 isrv = (isr != -1) ? isr : 0;
222
223 if ((tpr & 0xf0) >= (isrv & 0xf0))
224 ppr = tpr & 0xff;
225 else
226 ppr = isrv & 0xf0;
227
228 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
229 apic, ppr, isr, isrv);
230
231 apic_set_reg(apic, APIC_PROCPRI, ppr);
232}
233
234static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
235{
236 apic_set_reg(apic, APIC_TASKPRI, tpr);
237 apic_update_ppr(apic);
238}
239
240int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
241{
242 return kvm_apic_id(apic) == dest;
243}
244
245int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
246{
247 int result = 0;
248 u8 logical_id;
249
250 logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
251
252 switch (apic_get_reg(apic, APIC_DFR)) {
253 case APIC_DFR_FLAT:
254 if (logical_id & mda)
255 result = 1;
256 break;
257 case APIC_DFR_CLUSTER:
258 if (((logical_id >> 4) == (mda >> 0x4))
259 && (logical_id & mda & 0xf))
260 result = 1;
261 break;
262 default:
263 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
264 apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
265 break;
266 }
267
268 return result;
269}
270
271static int apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
272 int short_hand, int dest, int dest_mode)
273{
274 int result = 0;
ad312c7c 275 struct kvm_lapic *target = vcpu->arch.apic;
97222cc8
ED		 276
277 apic_debug("target %p, source %p, dest 0x%x, "
278 "dest_mode 0x%x, short_hand 0x%x",
279 target, source, dest, dest_mode, short_hand);
280
281 ASSERT(!target);
282 switch (short_hand) {
283 case APIC_DEST_NOSHORT:
284 if (dest_mode == 0) {
285 /* Physical mode. */
286 if ((dest == 0xFF) || (dest == kvm_apic_id(target)))
287 result = 1;
288 } else
289 /* Logical mode. */
290 result = kvm_apic_match_logical_addr(target, dest);
291 break;
292 case APIC_DEST_SELF:
293 if (target == source)
294 result = 1;
295 break;
296 case APIC_DEST_ALLINC:
297 result = 1;
298 break;
299 case APIC_DEST_ALLBUT:
300 if (target != source)
301 result = 1;
302 break;
303 default:
304 printk(KERN_WARNING "Bad dest shorthand value %x\n",
305 short_hand);
306 break;
307 }
308
309 return result;
310}
311
312/*
313 * Add a pending IRQ into lapic.
314 * Return 1 if successfully added and 0 if discarded.
315 */
316static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
317 int vector, int level, int trig_mode)
318{
c5ec1534
HQ		 319 int orig_irr, result = 0;
320 struct kvm_vcpu *vcpu = apic->vcpu;
97222cc8
ED		 321
322 switch (delivery_mode) {
323 case APIC_DM_FIXED:
324 case APIC_DM_LOWEST:
325 /* FIXME add logic for vcpu on reset */
326 if (unlikely(!apic_enabled(apic)))
327 break;
328
1b9778da
ED		 329 orig_irr = apic_test_and_set_irr(vector, apic);
330 if (orig_irr && trig_mode) {
97222cc8
ED		 331 apic_debug("level trig mode repeatedly for vector %d",
332 vector);
333 break;
334 }
335
336 if (trig_mode) {
337 apic_debug("level trig mode for vector %d", vector);
338 apic_set_vector(vector, apic->regs + APIC_TMR);
339 } else
340 apic_clear_vector(vector, apic->regs + APIC_TMR);
341
a4535290 342 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
c5ec1534 343 kvm_vcpu_kick(vcpu);
a4535290
AK		 344 else if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) {
345 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
c5ec1534
HQ		 346 if (waitqueue_active(&vcpu->wq))
347 wake_up_interruptible(&vcpu->wq);
348 }
97222cc8 349
1b9778da 350 result = (orig_irr == 0);
97222cc8
ED		 351 break;
352
353 case APIC_DM_REMRD:
354 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
355 break;
356
357 case APIC_DM_SMI:
358 printk(KERN_DEBUG "Ignoring guest SMI\n");
359 break;
3419ffc8 360
97222cc8 361 case APIC_DM_NMI:
3419ffc8 362 kvm_inject_nmi(vcpu);
97222cc8
ED		 363 break;
364
365 case APIC_DM_INIT:
c5ec1534 366 if (level) {
a4535290 367 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
c5ec1534
HQ		 368 printk(KERN_DEBUG
369 "INIT on a runnable vcpu %d\n",
370 vcpu->vcpu_id);
a4535290 371 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
c5ec1534
HQ		 372 kvm_vcpu_kick(vcpu);
373 } else {
374 printk(KERN_DEBUG
375 "Ignoring de-assert INIT to vcpu %d\n",
376 vcpu->vcpu_id);
377 }
378
97222cc8
ED		 379 break;
380
381 case APIC_DM_STARTUP:
c5ec1534
HQ		 382 printk(KERN_DEBUG "SIPI to vcpu %d vector 0x%02x\n",
383 vcpu->vcpu_id, vector);
a4535290 384 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
ad312c7c 385 vcpu->arch.sipi_vector = vector;
a4535290 386 vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
c5ec1534
HQ		 387 if (waitqueue_active(&vcpu->wq))
388 wake_up_interruptible(&vcpu->wq);
389 }
97222cc8
ED		 390 break;
391
392 default:
393 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
394 delivery_mode);
395 break;
396 }
397 return result;
398}
399
8be5453f 400static struct kvm_lapic *kvm_apic_round_robin(struct kvm *kvm, u8 vector,
97222cc8
ED		 401 unsigned long bitmap)
402{
932f72ad
HQ		 403 int last;
404 int next;
e4d47f40 405 struct kvm_lapic *apic = NULL;
932f72ad 406
bfc6d222 407 last = kvm->arch.round_robin_prev_vcpu;
932f72ad
HQ		 408 next = last;
409
410 do {
411 if (++next == KVM_MAX_VCPUS)
412 next = 0;
413 if (kvm->vcpus[next] == NULL || !test_bit(next, &bitmap))
414 continue;
ad312c7c 415 apic = kvm->vcpus[next]->arch.apic;
932f72ad
HQ		 416 if (apic && apic_enabled(apic))
417 break;
418 apic = NULL;
419 } while (next != last);
bfc6d222 420 kvm->arch.round_robin_prev_vcpu = next;
932f72ad 421
e4d47f40
QH		 422 if (!apic)
423 printk(KERN_DEBUG "vcpu not ready for apic_round_robin\n");
97222cc8 424
932f72ad 425 return apic;
97222cc8
ED		 426}
427
8be5453f
ZX		 428struct kvm_vcpu *kvm_get_lowest_prio_vcpu(struct kvm *kvm, u8 vector,
429 unsigned long bitmap)
430{
431 struct kvm_lapic *apic;
432
433 apic = kvm_apic_round_robin(kvm, vector, bitmap);
434 if (apic)
435 return apic->vcpu;
436 return NULL;
437}
438
97222cc8
ED		 439static void apic_set_eoi(struct kvm_lapic *apic)
440{
441 int vector = apic_find_highest_isr(apic);
f5244726 442 int trigger_mode;
97222cc8
ED		 443 /*
444 * Not every write EOI will has corresponding ISR,
445 * one example is when Kernel check timer on setup_IO_APIC
446 */
447 if (vector == -1)
448 return;
449
450 apic_clear_vector(vector, apic->regs + APIC_ISR);
451 apic_update_ppr(apic);
452
453 if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
f5244726
MT		 454 trigger_mode = IOAPIC_LEVEL_TRIG;
455 else
456 trigger_mode = IOAPIC_EDGE_TRIG;
457 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
97222cc8
ED		 458}
459
460static void apic_send_ipi(struct kvm_lapic *apic)
461{
462 u32 icr_low = apic_get_reg(apic, APIC_ICR);
463 u32 icr_high = apic_get_reg(apic, APIC_ICR2);
464
465 unsigned int dest = GET_APIC_DEST_FIELD(icr_high);
466 unsigned int short_hand = icr_low & APIC_SHORT_MASK;
467 unsigned int trig_mode = icr_low & APIC_INT_LEVELTRIG;
468 unsigned int level = icr_low & APIC_INT_ASSERT;
469 unsigned int dest_mode = icr_low & APIC_DEST_MASK;
470 unsigned int delivery_mode = icr_low & APIC_MODE_MASK;
471 unsigned int vector = icr_low & APIC_VECTOR_MASK;
472
8be5453f 473 struct kvm_vcpu *target;
97222cc8
ED		 474 struct kvm_vcpu *vcpu;
475 unsigned long lpr_map = 0;
476 int i;
477
478 apic_debug("icr_high 0x%x, icr_low 0x%x, "
479 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
480 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
481 icr_high, icr_low, short_hand, dest,
482 trig_mode, level, dest_mode, delivery_mode, vector);
483
484 for (i = 0; i < KVM_MAX_VCPUS; i++) {
485 vcpu = apic->vcpu->kvm->vcpus[i];
486 if (!vcpu)
487 continue;
488
ad312c7c 489 if (vcpu->arch.apic &&
97222cc8
ED		 490 apic_match_dest(vcpu, apic, short_hand, dest, dest_mode)) {
491 if (delivery_mode == APIC_DM_LOWEST)
492 set_bit(vcpu->vcpu_id, &lpr_map);
493 else
ad312c7c 494 __apic_accept_irq(vcpu->arch.apic, delivery_mode,
97222cc8
ED		 495 vector, level, trig_mode);
496 }
497 }
498
499 if (delivery_mode == APIC_DM_LOWEST) {
8be5453f 500 target = kvm_get_lowest_prio_vcpu(vcpu->kvm, vector, lpr_map);
97222cc8 501 if (target != NULL)
ad312c7c 502 __apic_accept_irq(target->arch.apic, delivery_mode,
97222cc8
ED		 503 vector, level, trig_mode);
504 }
505}
506
507static u32 apic_get_tmcct(struct kvm_lapic *apic)
508{
9da8f4e8
KP		 509 u64 counter_passed;
510 ktime_t passed, now;
511 u32 tmcct;
97222cc8
ED		 512
513 ASSERT(apic != NULL);
514
9da8f4e8
KP		 515 now = apic->timer.dev.base->get_time();
516 tmcct = apic_get_reg(apic, APIC_TMICT);
517
518 /* if initial count is 0, current count should also be 0 */
519 if (tmcct == 0)
520 return 0;
521
97222cc8
ED		 522 if (unlikely(ktime_to_ns(now) <=
523 ktime_to_ns(apic->timer.last_update))) {
524 /* Wrap around */
525 passed = ktime_add(( {
526 (ktime_t) {
527 .tv64 = KTIME_MAX -
528 (apic->timer.last_update).tv64}; }
529 ), now);
530 apic_debug("time elapsed\n");
531 } else
532 passed = ktime_sub(now, apic->timer.last_update);
533
6f6d6a1a
RZ		 534 counter_passed = div64_u64(ktime_to_ns(passed),
535 (APIC_BUS_CYCLE_NS * apic->timer.divide_count));
97222cc8 536
9da8f4e8
KP		 537 if (counter_passed > tmcct) {
538 if (unlikely(!apic_lvtt_period(apic))) {
539 /* one-shot timers stick at 0 until reset */
97222cc8 540 tmcct = 0;
9da8f4e8
KP		 541 } else {
542 /*
543 * periodic timers reset to APIC_TMICT when they
544 * hit 0. The while loop simulates this happening N
545 * times. (counter_passed %= tmcct) would also work,
546 * but might be slower or not work on 32-bit??
547 */
548 while (counter_passed > tmcct)
549 counter_passed -= tmcct;
550 tmcct -= counter_passed;
551 }
552 } else {
553 tmcct -= counter_passed;
97222cc8
ED		 554 }
555
556 return tmcct;
557}
558
b209749f
AK		 559static void __report_tpr_access(struct kvm_lapic *apic, bool write)
560{
561 struct kvm_vcpu *vcpu = apic->vcpu;
562 struct kvm_run *run = vcpu->run;
563
564 set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests);
5fdbf976 565 run->tpr_access.rip = kvm_rip_read(vcpu);
b209749f
AK		 566 run->tpr_access.is_write = write;
567}
568
569static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
570{
571 if (apic->vcpu->arch.tpr_access_reporting)
572 __report_tpr_access(apic, write);
573}
574
97222cc8
ED		 575static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
576{
577 u32 val = 0;
578
c7bf23ba
JR		 579 KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
580
97222cc8
ED		 581 if (offset >= LAPIC_MMIO_LENGTH)
582 return 0;
583
584 switch (offset) {
585 case APIC_ARBPRI:
586 printk(KERN_WARNING "Access APIC ARBPRI register "
587 "which is for P6\n");
588 break;
589
590 case APIC_TMCCT: /* Timer CCR */
591 val = apic_get_tmcct(apic);
592 break;
593
b209749f
AK		 594 case APIC_TASKPRI:
595 report_tpr_access(apic, false);
596 /* fall thru */
97222cc8 597 default:
6e5d865c 598 apic_update_ppr(apic);
97222cc8
ED		 599 val = apic_get_reg(apic, offset);
600 break;
601 }
602
603 return val;
604}
605
606static void apic_mmio_read(struct kvm_io_device *this,
607 gpa_t address, int len, void *data)
608{
609 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
610 unsigned int offset = address - apic->base_address;
611 unsigned char alignment = offset & 0xf;
612 u32 result;
613
614 if ((alignment + len) > 4) {
615 printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
616 (unsigned long)address, len);
617 return;
618 }
619 result = __apic_read(apic, offset & ~0xf);
620
621 switch (len) {
622 case 1:
623 case 2:
624 case 4:
625 memcpy(data, (char *)&result + alignment, len);
626 break;
627 default:
628 printk(KERN_ERR "Local APIC read with len = %x, "
629 "should be 1,2, or 4 instead\n", len);
630 break;
631 }
632}
633
634static void update_divide_count(struct kvm_lapic *apic)
635{
636 u32 tmp1, tmp2, tdcr;
637
638 tdcr = apic_get_reg(apic, APIC_TDCR);
639 tmp1 = tdcr & 0xf;
640 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
641 apic->timer.divide_count = 0x1 << (tmp2 & 0x7);
642
643 apic_debug("timer divide count is 0x%x\n",
644 apic->timer.divide_count);
645}
646
647static void start_apic_timer(struct kvm_lapic *apic)
648{
649 ktime_t now = apic->timer.dev.base->get_time();
650
651 apic->timer.last_update = now;
652
653 apic->timer.period = apic_get_reg(apic, APIC_TMICT) *
654 APIC_BUS_CYCLE_NS * apic->timer.divide_count;
655 atomic_set(&apic->timer.pending, 0);
0b975a3c
AK		 656
657 if (!apic->timer.period)
658 return;
659
97222cc8
ED		 660 hrtimer_start(&apic->timer.dev,
661 ktime_add_ns(now, apic->timer.period),
662 HRTIMER_MODE_ABS);
663
664 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
665 PRIx64 ", "
666 "timer initial count 0x%x, period %lldns, "
b8688d51 667 "expire @ 0x%016" PRIx64 ".\n", __func__,
97222cc8
ED		 668 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
669 apic_get_reg(apic, APIC_TMICT),
670 apic->timer.period,
671 ktime_to_ns(ktime_add_ns(now,
672 apic->timer.period)));
673}
674
675static void apic_mmio_write(struct kvm_io_device *this,
676 gpa_t address, int len, const void *data)
677{
678 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
679 unsigned int offset = address - apic->base_address;
680 unsigned char alignment = offset & 0xf;
681 u32 val;
682
683 /*
684 * APIC register must be aligned on 128-bits boundary.
685 * 32/64/128 bits registers must be accessed thru 32 bits.
686 * Refer SDM 8.4.1
687 */
688 if (len != 4 || alignment) {
689 if (printk_ratelimit())
690 printk(KERN_ERR "apic write: bad size=%d %lx\n",
691 len, (long)address);
692 return;
693 }
694
695 val = *(u32 *) data;
696
697 /* too common printing */
698 if (offset != APIC_EOI)
699 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
b8688d51 700 "0x%x\n", __func__, offset, len, val);
97222cc8
ED		 701
702 offset &= 0xff0;
703
c7bf23ba
JR		 704 KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
705
97222cc8
ED		 706 switch (offset) {
707 case APIC_ID: /* Local APIC ID */
708 apic_set_reg(apic, APIC_ID, val);
709 break;
710
711 case APIC_TASKPRI:
b209749f 712 report_tpr_access(apic, true);
97222cc8
ED		 713 apic_set_tpr(apic, val & 0xff);
714 break;
715
716 case APIC_EOI:
717 apic_set_eoi(apic);
718 break;
719
720 case APIC_LDR:
721 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
722 break;
723
724 case APIC_DFR:
725 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
726 break;
727
728 case APIC_SPIV:
729 apic_set_reg(apic, APIC_SPIV, val & 0x3ff);
730 if (!(val & APIC_SPIV_APIC_ENABLED)) {
731 int i;
732 u32 lvt_val;
733
734 for (i = 0; i < APIC_LVT_NUM; i++) {
735 lvt_val = apic_get_reg(apic,
736 APIC_LVTT + 0x10 * i);
737 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
738 lvt_val | APIC_LVT_MASKED);
739 }
740 atomic_set(&apic->timer.pending, 0);
741
742 }
743 break;
744
745 case APIC_ICR:
746 /* No delay here, so we always clear the pending bit */
747 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
748 apic_send_ipi(apic);
749 break;
750
751 case APIC_ICR2:
752 apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
753 break;
754
755 case APIC_LVTT:
756 case APIC_LVTTHMR:
757 case APIC_LVTPC:
758 case APIC_LVT0:
759 case APIC_LVT1:
760 case APIC_LVTERR:
761 /* TODO: Check vector */
762 if (!apic_sw_enabled(apic))
763 val |= APIC_LVT_MASKED;
764
765 val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
766 apic_set_reg(apic, offset, val);
767
768 break;
769
770 case APIC_TMICT:
771 hrtimer_cancel(&apic->timer.dev);
772 apic_set_reg(apic, APIC_TMICT, val);
773 start_apic_timer(apic);
774 return;
775
776 case APIC_TDCR:
777 if (val & 4)
778 printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
779 apic_set_reg(apic, APIC_TDCR, val);
780 update_divide_count(apic);
781 break;
782
783 default:
784 apic_debug("Local APIC Write to read-only register %x\n",
785 offset);
786 break;
787 }
788
789}
790
92760499
LV		 791static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr,
792 int len, int size)
97222cc8
ED		 793{
794 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
795 int ret = 0;
796
797
798 if (apic_hw_enabled(apic) &&
799 (addr >= apic->base_address) &&
800 (addr < (apic->base_address + LAPIC_MMIO_LENGTH)))
801 ret = 1;
802
803 return ret;
804}
805
d589444e 806void kvm_free_lapic(struct kvm_vcpu *vcpu)
97222cc8 807{
ad312c7c 808 if (!vcpu->arch.apic)
97222cc8
ED		 809 return;
810
ad312c7c 811 hrtimer_cancel(&vcpu->arch.apic->timer.dev);
97222cc8 812
ad312c7c
ZX		 813 if (vcpu->arch.apic->regs_page)
814 __free_page(vcpu->arch.apic->regs_page);
97222cc8 815
ad312c7c 816 kfree(vcpu->arch.apic);
97222cc8
ED		 817}
818
819/*
820 *----------------------------------------------------------------------
821 * LAPIC interface
822 *----------------------------------------------------------------------
823 */
824
825void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
826{
ad312c7c 827 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 828
829 if (!apic)
830 return;
b93463aa
AK		 831 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
832 | (apic_get_reg(apic, APIC_TASKPRI) & 4));
97222cc8 833}
ec7cf690 834EXPORT_SYMBOL_GPL(kvm_lapic_set_tpr);
97222cc8
ED		 835
836u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
837{
ad312c7c 838 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 839 u64 tpr;
840
841 if (!apic)
842 return 0;
843 tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
844
845 return (tpr & 0xf0) >> 4;
846}
6e5d865c 847EXPORT_SYMBOL_GPL(kvm_lapic_get_cr8);
97222cc8
ED		 848
849void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
850{
ad312c7c 851 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 852
853 if (!apic) {
854 value |= MSR_IA32_APICBASE_BSP;
ad312c7c 855 vcpu->arch.apic_base = value;
97222cc8
ED		 856 return;
857 }
858 if (apic->vcpu->vcpu_id)
859 value &= ~MSR_IA32_APICBASE_BSP;
860
ad312c7c
ZX		 861 vcpu->arch.apic_base = value;
862 apic->base_address = apic->vcpu->arch.apic_base &
97222cc8
ED		 863 MSR_IA32_APICBASE_BASE;
864
865 /* with FSB delivery interrupt, we can restart APIC functionality */
866 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
ad312c7c 867 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 868
869}
870
871u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu)
872{
ad312c7c 873 return vcpu->arch.apic_base;
97222cc8
ED		 874}
875EXPORT_SYMBOL_GPL(kvm_lapic_get_base);
876
c5ec1534 877void kvm_lapic_reset(struct kvm_vcpu *vcpu)
97222cc8
ED		 878{
879 struct kvm_lapic *apic;
880 int i;
881
b8688d51 882 apic_debug("%s\n", __func__);
97222cc8
ED		 883
884 ASSERT(vcpu);
ad312c7c 885 apic = vcpu->arch.apic;
97222cc8
ED		 886 ASSERT(apic != NULL);
887
888 /* Stop the timer in case it's a reset to an active apic */
889 hrtimer_cancel(&apic->timer.dev);
890
891 apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
892 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
893
894 for (i = 0; i < APIC_LVT_NUM; i++)
895 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
40487c68
QH		 896 apic_set_reg(apic, APIC_LVT0,
897 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
97222cc8
ED		 898
899 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
900 apic_set_reg(apic, APIC_SPIV, 0xff);
901 apic_set_reg(apic, APIC_TASKPRI, 0);
902 apic_set_reg(apic, APIC_LDR, 0);
903 apic_set_reg(apic, APIC_ESR, 0);
904 apic_set_reg(apic, APIC_ICR, 0);
905 apic_set_reg(apic, APIC_ICR2, 0);
906 apic_set_reg(apic, APIC_TDCR, 0);
907 apic_set_reg(apic, APIC_TMICT, 0);
908 for (i = 0; i < 8; i++) {
909 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
910 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
911 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
912 }
b33ac88b 913 update_divide_count(apic);
97222cc8
ED		 914 atomic_set(&apic->timer.pending, 0);
915 if (vcpu->vcpu_id == 0)
ad312c7c 916 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
97222cc8
ED		 917 apic_update_ppr(apic);
918
919 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
b8688d51 920 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
97222cc8 921 vcpu, kvm_apic_id(apic),
ad312c7c 922 vcpu->arch.apic_base, apic->base_address);
97222cc8 923}
c5ec1534 924EXPORT_SYMBOL_GPL(kvm_lapic_reset);
97222cc8
ED		 925
926int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
927{
ad312c7c 928 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 929 int ret = 0;
930
931 if (!apic)
932 return 0;
933 ret = apic_enabled(apic);
934
935 return ret;
936}
6e5d865c 937EXPORT_SYMBOL_GPL(kvm_lapic_enabled);
97222cc8
ED		 938
939/*
940 *----------------------------------------------------------------------
941 * timer interface
942 *----------------------------------------------------------------------
943 */
1b9778da
ED		 944
945/* TODO: make sure __apic_timer_fn runs in current pCPU */
97222cc8
ED		 946static int __apic_timer_fn(struct kvm_lapic *apic)
947{
97222cc8 948 int result = 0;
1b9778da 949 wait_queue_head_t *q = &apic->vcpu->wq;
97222cc8 950
622395a9
MT		 951 if(!atomic_inc_and_test(&apic->timer.pending))
952 set_bit(KVM_REQ_PENDING_TIMER, &apic->vcpu->requests);
d77c26fc 953 if (waitqueue_active(q)) {
a4535290 954 apic->vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1b9778da 955 wake_up_interruptible(q);
c5ec1534 956 }
97222cc8 957 if (apic_lvtt_period(apic)) {
97222cc8
ED		 958 result = 1;
959 apic->timer.dev.expires = ktime_add_ns(
960 apic->timer.dev.expires,
961 apic->timer.period);
962 }
97222cc8
ED		 963 return result;
964}
965
3d80840d
MT		 966int apic_has_pending_timer(struct kvm_vcpu *vcpu)
967{
968 struct kvm_lapic *lapic = vcpu->arch.apic;
969
54aaacee 970 if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
3d80840d
MT		 971 return atomic_read(&lapic->timer.pending);
972
973 return 0;
974}
975
1b9778da
ED		 976static int __inject_apic_timer_irq(struct kvm_lapic *apic)
977{
978 int vector;
979
980 vector = apic_lvt_vector(apic, APIC_LVTT);
981 return __apic_accept_irq(apic, APIC_DM_FIXED, vector, 1, 0);
982}
983
97222cc8
ED		 984static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
985{
986 struct kvm_lapic *apic;
987 int restart_timer = 0;
988
989 apic = container_of(data, struct kvm_lapic, timer.dev);
990
991 restart_timer = __apic_timer_fn(apic);
992
993 if (restart_timer)
994 return HRTIMER_RESTART;
995 else
996 return HRTIMER_NORESTART;
997}
998
999int kvm_create_lapic(struct kvm_vcpu *vcpu)
1000{
1001 struct kvm_lapic *apic;
1002
1003 ASSERT(vcpu != NULL);
1004 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1005
1006 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1007 if (!apic)
1008 goto nomem;
1009
ad312c7c 1010 vcpu->arch.apic = apic;
97222cc8
ED		 1011
1012 apic->regs_page = alloc_page(GFP_KERNEL);
1013 if (apic->regs_page == NULL) {
1014 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1015 vcpu->vcpu_id);
d589444e 1016 goto nomem_free_apic;
97222cc8
ED		 1017 }
1018 apic->regs = page_address(apic->regs_page);
1019 memset(apic->regs, 0, PAGE_SIZE);
1020 apic->vcpu = vcpu;
1021
1022 hrtimer_init(&apic->timer.dev, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
1023 apic->timer.dev.function = apic_timer_fn;
1024 apic->base_address = APIC_DEFAULT_PHYS_BASE;
ad312c7c 1025 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
97222cc8 1026
c5ec1534 1027 kvm_lapic_reset(vcpu);
97222cc8
ED		 1028 apic->dev.read = apic_mmio_read;
1029 apic->dev.write = apic_mmio_write;
1030 apic->dev.in_range = apic_mmio_range;
1031 apic->dev.private = apic;
1032
1033 return 0;
d589444e
RR		 1034nomem_free_apic:
1035 kfree(apic);
97222cc8 1036nomem:
97222cc8
ED		 1037 return -ENOMEM;
1038}
1039EXPORT_SYMBOL_GPL(kvm_create_lapic);
1040
1041int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1042{
ad312c7c 1043 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1044 int highest_irr;
1045
1046 if (!apic || !apic_enabled(apic))
1047 return -1;
1048
6e5d865c 1049 apic_update_ppr(apic);
97222cc8
ED		 1050 highest_irr = apic_find_highest_irr(apic);
1051 if ((highest_irr == -1) ||
1052 ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1053 return -1;
1054 return highest_irr;
1055}
1056
40487c68
QH		 1057int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1058{
ad312c7c 1059 u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
40487c68
QH		 1060 int r = 0;
1061
1062 if (vcpu->vcpu_id == 0) {
ad312c7c 1063 if (!apic_hw_enabled(vcpu->arch.apic))
40487c68
QH		 1064 r = 1;
1065 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1066 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1067 r = 1;
1068 }
1069 return r;
1070}
1071
1b9778da
ED		 1072void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1073{
ad312c7c 1074 struct kvm_lapic *apic = vcpu->arch.apic;
1b9778da
ED		 1075
1076 if (apic && apic_lvt_enabled(apic, APIC_LVTT) &&
1077 atomic_read(&apic->timer.pending) > 0) {
1078 if (__inject_apic_timer_irq(apic))
1079 atomic_dec(&apic->timer.pending);
1080 }
1081}
1082
1083void kvm_apic_timer_intr_post(struct kvm_vcpu *vcpu, int vec)
1084{
ad312c7c 1085 struct kvm_lapic *apic = vcpu->arch.apic;
1b9778da
ED		 1086
1087 if (apic && apic_lvt_vector(apic, APIC_LVTT) == vec)
1088 apic->timer.last_update = ktime_add_ns(
1089 apic->timer.last_update,
1090 apic->timer.period);
1091}
1092
97222cc8
ED		 1093int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1094{
1095 int vector = kvm_apic_has_interrupt(vcpu);
ad312c7c 1096 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1097
1098 if (vector == -1)
1099 return -1;
1100
1101 apic_set_vector(vector, apic->regs + APIC_ISR);
1102 apic_update_ppr(apic);
1103 apic_clear_irr(vector, apic);
1104 return vector;
1105}
96ad2cc6
ED		 1106
1107void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1108{
ad312c7c 1109 struct kvm_lapic *apic = vcpu->arch.apic;
96ad2cc6 1110
ad312c7c 1111 apic->base_address = vcpu->arch.apic_base &
96ad2cc6
ED		 1112 MSR_IA32_APICBASE_BASE;
1113 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
1114 apic_update_ppr(apic);
1115 hrtimer_cancel(&apic->timer.dev);
1116 update_divide_count(apic);
1117 start_apic_timer(apic);
1118}
a3d7f85f 1119
2f52d58c 1120void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
a3d7f85f 1121{
ad312c7c 1122 struct kvm_lapic *apic = vcpu->arch.apic;
a3d7f85f
ED		 1123 struct hrtimer *timer;
1124
1125 if (!apic)
1126 return;
1127
1128 timer = &apic->timer.dev;
1129 if (hrtimer_cancel(timer))
1130 hrtimer_start(timer, timer->expires, HRTIMER_MODE_ABS);
1131}
b93463aa
AK		 1132
1133void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1134{
1135 u32 data;
1136 void *vapic;
1137
1138 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1139 return;
1140
1141 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1142 data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1143 kunmap_atomic(vapic, KM_USER0);
1144
1145 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1146}
1147
1148void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1149{
1150 u32 data, tpr;
1151 int max_irr, max_isr;
1152 struct kvm_lapic *apic;
1153 void *vapic;
1154
1155 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1156 return;
1157
1158 apic = vcpu->arch.apic;
1159 tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1160 max_irr = apic_find_highest_irr(apic);
1161 if (max_irr < 0)
1162 max_irr = 0;
1163 max_isr = apic_find_highest_isr(apic);
1164 if (max_isr < 0)
1165 max_isr = 0;
1166 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1167
1168 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1169 *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1170 kunmap_atomic(vapic, KM_USER0);
1171}
1172
1173void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1174{
1175 if (!irqchip_in_kernel(vcpu->kvm))
1176 return;
1177
1178 vcpu->arch.apic->vapic_addr = vapic_addr;
1179}
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