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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
6aa8b732 AK |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * This module enables machines with Intel VT-x extensions to run virtual | |
6 | * machines without emulation or binary translation. | |
7 | * | |
8 | * MMU support | |
9 | * | |
10 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 11 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
12 | * |
13 | * Authors: | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
15 | * Avi Kivity <avi@qumranet.com> | |
6aa8b732 | 16 | */ |
e495606d | 17 | |
af585b92 | 18 | #include "irq.h" |
88197e6a | 19 | #include "ioapic.h" |
1d737c8a | 20 | #include "mmu.h" |
6ca9a6f3 | 21 | #include "mmu_internal.h" |
fe5db27d | 22 | #include "tdp_mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
2f728d66 | 25 | #include "kvm_emulate.h" |
5f7dde7b | 26 | #include "cpuid.h" |
5a9624af | 27 | #include "spte.h" |
e495606d | 28 | |
edf88417 | 29 | #include <linux/kvm_host.h> |
6aa8b732 AK |
30 | #include <linux/types.h> |
31 | #include <linux/string.h> | |
6aa8b732 AK |
32 | #include <linux/mm.h> |
33 | #include <linux/highmem.h> | |
1767e931 PG |
34 | #include <linux/moduleparam.h> |
35 | #include <linux/export.h> | |
448353ca | 36 | #include <linux/swap.h> |
05da4558 | 37 | #include <linux/hugetlb.h> |
2f333bcb | 38 | #include <linux/compiler.h> |
bc6678a3 | 39 | #include <linux/srcu.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
3f07c014 | 41 | #include <linux/sched/signal.h> |
bf998156 | 42 | #include <linux/uaccess.h> |
114df303 | 43 | #include <linux/hash.h> |
f160c7b7 | 44 | #include <linux/kern_levels.h> |
1aa9b957 | 45 | #include <linux/kthread.h> |
6aa8b732 | 46 | |
e495606d | 47 | #include <asm/page.h> |
eb243d1d | 48 | #include <asm/memtype.h> |
e495606d | 49 | #include <asm/cmpxchg.h> |
4e542370 | 50 | #include <asm/io.h> |
13673a90 | 51 | #include <asm/vmx.h> |
3d0c27ad | 52 | #include <asm/kvm_page_track.h> |
1261bfa3 | 53 | #include "trace.h" |
6aa8b732 | 54 | |
b8e8c830 PB |
55 | extern bool itlb_multihit_kvm_mitigation; |
56 | ||
57 | static int __read_mostly nx_huge_pages = -1; | |
13fb5927 PB |
58 | #ifdef CONFIG_PREEMPT_RT |
59 | /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */ | |
60 | static uint __read_mostly nx_huge_pages_recovery_ratio = 0; | |
61 | #else | |
1aa9b957 | 62 | static uint __read_mostly nx_huge_pages_recovery_ratio = 60; |
13fb5927 | 63 | #endif |
b8e8c830 PB |
64 | |
65 | static int set_nx_huge_pages(const char *val, const struct kernel_param *kp); | |
1aa9b957 | 66 | static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp); |
b8e8c830 | 67 | |
d5d6c18d | 68 | static const struct kernel_param_ops nx_huge_pages_ops = { |
b8e8c830 PB |
69 | .set = set_nx_huge_pages, |
70 | .get = param_get_bool, | |
71 | }; | |
72 | ||
d5d6c18d | 73 | static const struct kernel_param_ops nx_huge_pages_recovery_ratio_ops = { |
1aa9b957 JS |
74 | .set = set_nx_huge_pages_recovery_ratio, |
75 | .get = param_get_uint, | |
76 | }; | |
77 | ||
b8e8c830 PB |
78 | module_param_cb(nx_huge_pages, &nx_huge_pages_ops, &nx_huge_pages, 0644); |
79 | __MODULE_PARM_TYPE(nx_huge_pages, "bool"); | |
1aa9b957 JS |
80 | module_param_cb(nx_huge_pages_recovery_ratio, &nx_huge_pages_recovery_ratio_ops, |
81 | &nx_huge_pages_recovery_ratio, 0644); | |
82 | __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio, "uint"); | |
b8e8c830 | 83 | |
71fe7013 SC |
84 | static bool __read_mostly force_flush_and_sync_on_reuse; |
85 | module_param_named(flush_on_reuse, force_flush_and_sync_on_reuse, bool, 0644); | |
86 | ||
18552672 JR |
87 | /* |
88 | * When setting this variable to true it enables Two-Dimensional-Paging | |
89 | * where the hardware walks 2 page tables: | |
90 | * 1. the guest-virtual to guest-physical | |
91 | * 2. while doing 1. it walks guest-physical to host-physical | |
92 | * If the hardware supports that we don't need to do shadow paging. | |
93 | */ | |
2f333bcb | 94 | bool tdp_enabled = false; |
18552672 | 95 | |
1d92d2e8 | 96 | static int max_huge_page_level __read_mostly; |
83013059 | 97 | static int max_tdp_level __read_mostly; |
703c335d | 98 | |
8b1fe17c XG |
99 | enum { |
100 | AUDIT_PRE_PAGE_FAULT, | |
101 | AUDIT_POST_PAGE_FAULT, | |
102 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
103 | AUDIT_POST_PTE_WRITE, |
104 | AUDIT_PRE_SYNC, | |
105 | AUDIT_POST_SYNC | |
8b1fe17c | 106 | }; |
37a7d8b0 | 107 | |
37a7d8b0 | 108 | #ifdef MMU_DEBUG |
5a9624af | 109 | bool dbg = 0; |
fa4a2c08 | 110 | module_param(dbg, bool, 0644); |
d6c69ee9 | 111 | #endif |
6aa8b732 | 112 | |
957ed9ef XG |
113 | #define PTE_PREFETCH_NUM 8 |
114 | ||
6aa8b732 AK |
115 | #define PT32_LEVEL_BITS 10 |
116 | ||
117 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 118 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 119 | |
e04da980 JR |
120 | #define PT32_LVL_OFFSET_MASK(level) \ |
121 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
122 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
123 | |
124 | #define PT32_INDEX(address, level)\ | |
125 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
126 | ||
127 | ||
6aa8b732 AK |
128 | #define PT32_BASE_ADDR_MASK PAGE_MASK |
129 | #define PT32_DIR_BASE_ADDR_MASK \ | |
130 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
131 | #define PT32_LVL_ADDR_MASK(level) \ |
132 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
133 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 134 | |
90bb6fc5 AK |
135 | #include <trace/events/kvm.h> |
136 | ||
220f773a TY |
137 | /* make pte_list_desc fit well in cache line */ |
138 | #define PTE_LIST_EXT 3 | |
139 | ||
53c07b18 XG |
140 | struct pte_list_desc { |
141 | u64 *sptes[PTE_LIST_EXT]; | |
142 | struct pte_list_desc *more; | |
cd4a4e53 AK |
143 | }; |
144 | ||
2d11123a AK |
145 | struct kvm_shadow_walk_iterator { |
146 | u64 addr; | |
147 | hpa_t shadow_addr; | |
2d11123a | 148 | u64 *sptep; |
dd3bfd59 | 149 | int level; |
2d11123a AK |
150 | unsigned index; |
151 | }; | |
152 | ||
7eb77e9f JS |
153 | #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \ |
154 | for (shadow_walk_init_using_root(&(_walker), (_vcpu), \ | |
155 | (_root), (_addr)); \ | |
156 | shadow_walk_okay(&(_walker)); \ | |
157 | shadow_walk_next(&(_walker))) | |
158 | ||
159 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
2d11123a AK |
160 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ |
161 | shadow_walk_okay(&(_walker)); \ | |
162 | shadow_walk_next(&(_walker))) | |
163 | ||
c2a2ac2b XG |
164 | #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ |
165 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
166 | shadow_walk_okay(&(_walker)) && \ | |
167 | ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \ | |
168 | __shadow_walk_next(&(_walker), spte)) | |
169 | ||
53c07b18 | 170 | static struct kmem_cache *pte_list_desc_cache; |
02c00b3a | 171 | struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 172 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 173 | |
ce88decf | 174 | static void mmu_spte_set(u64 *sptep, u64 spte); |
9fa72119 JS |
175 | static union kvm_mmu_page_role |
176 | kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu); | |
ce88decf | 177 | |
335e192a PB |
178 | #define CREATE_TRACE_POINTS |
179 | #include "mmutrace.h" | |
180 | ||
40ef75a7 LT |
181 | |
182 | static inline bool kvm_available_flush_tlb_with_range(void) | |
183 | { | |
afaf0b2f | 184 | return kvm_x86_ops.tlb_remote_flush_with_range; |
40ef75a7 LT |
185 | } |
186 | ||
187 | static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm, | |
188 | struct kvm_tlb_range *range) | |
189 | { | |
190 | int ret = -ENOTSUPP; | |
191 | ||
afaf0b2f | 192 | if (range && kvm_x86_ops.tlb_remote_flush_with_range) |
b3646477 | 193 | ret = static_call(kvm_x86_tlb_remote_flush_with_range)(kvm, range); |
40ef75a7 LT |
194 | |
195 | if (ret) | |
196 | kvm_flush_remote_tlbs(kvm); | |
197 | } | |
198 | ||
2f2fad08 | 199 | void kvm_flush_remote_tlbs_with_address(struct kvm *kvm, |
40ef75a7 LT |
200 | u64 start_gfn, u64 pages) |
201 | { | |
202 | struct kvm_tlb_range range; | |
203 | ||
204 | range.start_gfn = start_gfn; | |
205 | range.pages = pages; | |
206 | ||
207 | kvm_flush_remote_tlbs_with_range(kvm, &range); | |
208 | } | |
209 | ||
5a9624af | 210 | bool is_nx_huge_page_enabled(void) |
b8e8c830 PB |
211 | { |
212 | return READ_ONCE(nx_huge_pages); | |
213 | } | |
214 | ||
8f79b064 BG |
215 | static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn, |
216 | unsigned int access) | |
217 | { | |
218 | u64 mask = make_mmio_spte(vcpu, gfn, access); | |
8f79b064 | 219 | |
bb18842e | 220 | trace_mark_mmio_spte(sptep, gfn, mask); |
f2fd125d | 221 | mmu_spte_set(sptep, mask); |
ce88decf XG |
222 | } |
223 | ||
ce88decf XG |
224 | static gfn_t get_mmio_spte_gfn(u64 spte) |
225 | { | |
daa07cbc | 226 | u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask; |
28a1f3ac | 227 | |
8a967d65 | 228 | gpa |= (spte >> SHADOW_NONPRESENT_OR_RSVD_MASK_LEN) |
28a1f3ac JS |
229 | & shadow_nonpresent_or_rsvd_mask; |
230 | ||
231 | return gpa >> PAGE_SHIFT; | |
ce88decf XG |
232 | } |
233 | ||
234 | static unsigned get_mmio_spte_access(u64 spte) | |
235 | { | |
4af77151 | 236 | return spte & shadow_mmio_access_mask; |
ce88decf XG |
237 | } |
238 | ||
54bf36aa | 239 | static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
0a2b64c5 | 240 | kvm_pfn_t pfn, unsigned int access) |
ce88decf XG |
241 | { |
242 | if (unlikely(is_noslot_pfn(pfn))) { | |
54bf36aa | 243 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
244 | return true; |
245 | } | |
246 | ||
247 | return false; | |
248 | } | |
c7addb90 | 249 | |
54bf36aa | 250 | static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte) |
f8f55942 | 251 | { |
cae7ed3c | 252 | u64 kvm_gen, spte_gen, gen; |
089504c0 | 253 | |
cae7ed3c SC |
254 | gen = kvm_vcpu_memslots(vcpu)->generation; |
255 | if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS)) | |
256 | return false; | |
089504c0 | 257 | |
cae7ed3c | 258 | kvm_gen = gen & MMIO_SPTE_GEN_MASK; |
089504c0 XG |
259 | spte_gen = get_mmio_spte_generation(spte); |
260 | ||
261 | trace_check_mmio_spte(spte, kvm_gen, spte_gen); | |
262 | return likely(kvm_gen == spte_gen); | |
f8f55942 XG |
263 | } |
264 | ||
cd313569 MG |
265 | static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
266 | struct x86_exception *exception) | |
267 | { | |
ec7771ab | 268 | /* Check if guest physical address doesn't exceed guest maximum */ |
dc46515c | 269 | if (kvm_vcpu_is_illegal_gpa(vcpu, gpa)) { |
ec7771ab MG |
270 | exception->error_code |= PFERR_RSVD_MASK; |
271 | return UNMAPPED_GVA; | |
272 | } | |
273 | ||
cd313569 MG |
274 | return gpa; |
275 | } | |
276 | ||
6aa8b732 AK |
277 | static int is_cpuid_PSE36(void) |
278 | { | |
279 | return 1; | |
280 | } | |
281 | ||
73b1087e AK |
282 | static int is_nx(struct kvm_vcpu *vcpu) |
283 | { | |
f6801dff | 284 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
285 | } |
286 | ||
da928521 AK |
287 | static gfn_t pse36_gfn_delta(u32 gpte) |
288 | { | |
289 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
290 | ||
291 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
292 | } | |
293 | ||
603e0651 | 294 | #ifdef CONFIG_X86_64 |
d555c333 | 295 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 296 | { |
b19ee2ff | 297 | WRITE_ONCE(*sptep, spte); |
e663ee64 AK |
298 | } |
299 | ||
603e0651 | 300 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
a9221dd5 | 301 | { |
b19ee2ff | 302 | WRITE_ONCE(*sptep, spte); |
603e0651 XG |
303 | } |
304 | ||
305 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
306 | { | |
307 | return xchg(sptep, spte); | |
308 | } | |
c2a2ac2b XG |
309 | |
310 | static u64 __get_spte_lockless(u64 *sptep) | |
311 | { | |
6aa7de05 | 312 | return READ_ONCE(*sptep); |
c2a2ac2b | 313 | } |
a9221dd5 | 314 | #else |
603e0651 XG |
315 | union split_spte { |
316 | struct { | |
317 | u32 spte_low; | |
318 | u32 spte_high; | |
319 | }; | |
320 | u64 spte; | |
321 | }; | |
a9221dd5 | 322 | |
c2a2ac2b XG |
323 | static void count_spte_clear(u64 *sptep, u64 spte) |
324 | { | |
57354682 | 325 | struct kvm_mmu_page *sp = sptep_to_sp(sptep); |
c2a2ac2b XG |
326 | |
327 | if (is_shadow_present_pte(spte)) | |
328 | return; | |
329 | ||
330 | /* Ensure the spte is completely set before we increase the count */ | |
331 | smp_wmb(); | |
332 | sp->clear_spte_count++; | |
333 | } | |
334 | ||
603e0651 XG |
335 | static void __set_spte(u64 *sptep, u64 spte) |
336 | { | |
337 | union split_spte *ssptep, sspte; | |
a9221dd5 | 338 | |
603e0651 XG |
339 | ssptep = (union split_spte *)sptep; |
340 | sspte = (union split_spte)spte; | |
341 | ||
342 | ssptep->spte_high = sspte.spte_high; | |
343 | ||
344 | /* | |
345 | * If we map the spte from nonpresent to present, We should store | |
346 | * the high bits firstly, then set present bit, so cpu can not | |
347 | * fetch this spte while we are setting the spte. | |
348 | */ | |
349 | smp_wmb(); | |
350 | ||
b19ee2ff | 351 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
a9221dd5 AK |
352 | } |
353 | ||
603e0651 XG |
354 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
355 | { | |
356 | union split_spte *ssptep, sspte; | |
357 | ||
358 | ssptep = (union split_spte *)sptep; | |
359 | sspte = (union split_spte)spte; | |
360 | ||
b19ee2ff | 361 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
603e0651 XG |
362 | |
363 | /* | |
364 | * If we map the spte from present to nonpresent, we should clear | |
365 | * present bit firstly to avoid vcpu fetch the old high bits. | |
366 | */ | |
367 | smp_wmb(); | |
368 | ||
369 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 370 | count_spte_clear(sptep, spte); |
603e0651 XG |
371 | } |
372 | ||
373 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
374 | { | |
375 | union split_spte *ssptep, sspte, orig; | |
376 | ||
377 | ssptep = (union split_spte *)sptep; | |
378 | sspte = (union split_spte)spte; | |
379 | ||
380 | /* xchg acts as a barrier before the setting of the high bits */ | |
381 | orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); | |
41bc3186 ZJ |
382 | orig.spte_high = ssptep->spte_high; |
383 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 384 | count_spte_clear(sptep, spte); |
603e0651 XG |
385 | |
386 | return orig.spte; | |
387 | } | |
c2a2ac2b XG |
388 | |
389 | /* | |
390 | * The idea using the light way get the spte on x86_32 guest is from | |
39656e83 | 391 | * gup_get_pte (mm/gup.c). |
accaefe0 XG |
392 | * |
393 | * An spte tlb flush may be pending, because kvm_set_pte_rmapp | |
394 | * coalesces them and we are running out of the MMU lock. Therefore | |
395 | * we need to protect against in-progress updates of the spte. | |
396 | * | |
397 | * Reading the spte while an update is in progress may get the old value | |
398 | * for the high part of the spte. The race is fine for a present->non-present | |
399 | * change (because the high part of the spte is ignored for non-present spte), | |
400 | * but for a present->present change we must reread the spte. | |
401 | * | |
402 | * All such changes are done in two steps (present->non-present and | |
403 | * non-present->present), hence it is enough to count the number of | |
404 | * present->non-present updates: if it changed while reading the spte, | |
405 | * we might have hit the race. This is done using clear_spte_count. | |
c2a2ac2b XG |
406 | */ |
407 | static u64 __get_spte_lockless(u64 *sptep) | |
408 | { | |
57354682 | 409 | struct kvm_mmu_page *sp = sptep_to_sp(sptep); |
c2a2ac2b XG |
410 | union split_spte spte, *orig = (union split_spte *)sptep; |
411 | int count; | |
412 | ||
413 | retry: | |
414 | count = sp->clear_spte_count; | |
415 | smp_rmb(); | |
416 | ||
417 | spte.spte_low = orig->spte_low; | |
418 | smp_rmb(); | |
419 | ||
420 | spte.spte_high = orig->spte_high; | |
421 | smp_rmb(); | |
422 | ||
423 | if (unlikely(spte.spte_low != orig->spte_low || | |
424 | count != sp->clear_spte_count)) | |
425 | goto retry; | |
426 | ||
427 | return spte.spte; | |
428 | } | |
603e0651 XG |
429 | #endif |
430 | ||
8672b721 XG |
431 | static bool spte_has_volatile_bits(u64 spte) |
432 | { | |
f160c7b7 JS |
433 | if (!is_shadow_present_pte(spte)) |
434 | return false; | |
435 | ||
c7ba5b48 | 436 | /* |
6a6256f9 | 437 | * Always atomically update spte if it can be updated |
c7ba5b48 XG |
438 | * out of mmu-lock, it can ensure dirty bit is not lost, |
439 | * also, it can help us to get a stable is_writable_pte() | |
440 | * to ensure tlb flush is not missed. | |
441 | */ | |
f160c7b7 JS |
442 | if (spte_can_locklessly_be_made_writable(spte) || |
443 | is_access_track_spte(spte)) | |
c7ba5b48 XG |
444 | return true; |
445 | ||
ac8d57e5 | 446 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
447 | if ((spte & shadow_accessed_mask) == 0 || |
448 | (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0)) | |
449 | return true; | |
450 | } | |
8672b721 | 451 | |
f160c7b7 | 452 | return false; |
8672b721 XG |
453 | } |
454 | ||
1df9f2dc XG |
455 | /* Rules for using mmu_spte_set: |
456 | * Set the sptep from nonpresent to present. | |
457 | * Note: the sptep being assigned *must* be either not present | |
458 | * or in a state where the hardware will not attempt to update | |
459 | * the spte. | |
460 | */ | |
461 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
462 | { | |
463 | WARN_ON(is_shadow_present_pte(*sptep)); | |
464 | __set_spte(sptep, new_spte); | |
465 | } | |
466 | ||
f39a058d JS |
467 | /* |
468 | * Update the SPTE (excluding the PFN), but do not track changes in its | |
469 | * accessed/dirty status. | |
1df9f2dc | 470 | */ |
f39a058d | 471 | static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte) |
b79b93f9 | 472 | { |
c7ba5b48 | 473 | u64 old_spte = *sptep; |
4132779b | 474 | |
afd28fe1 | 475 | WARN_ON(!is_shadow_present_pte(new_spte)); |
b79b93f9 | 476 | |
6e7d0354 XG |
477 | if (!is_shadow_present_pte(old_spte)) { |
478 | mmu_spte_set(sptep, new_spte); | |
f39a058d | 479 | return old_spte; |
6e7d0354 | 480 | } |
4132779b | 481 | |
c7ba5b48 | 482 | if (!spte_has_volatile_bits(old_spte)) |
603e0651 | 483 | __update_clear_spte_fast(sptep, new_spte); |
4132779b | 484 | else |
603e0651 | 485 | old_spte = __update_clear_spte_slow(sptep, new_spte); |
4132779b | 486 | |
83ef6c81 JS |
487 | WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte)); |
488 | ||
f39a058d JS |
489 | return old_spte; |
490 | } | |
491 | ||
492 | /* Rules for using mmu_spte_update: | |
493 | * Update the state bits, it means the mapped pfn is not changed. | |
494 | * | |
495 | * Whenever we overwrite a writable spte with a read-only one we | |
496 | * should flush remote TLBs. Otherwise rmap_write_protect | |
497 | * will find a read-only spte, even though the writable spte | |
498 | * might be cached on a CPU's TLB, the return value indicates this | |
499 | * case. | |
500 | * | |
501 | * Returns true if the TLB needs to be flushed | |
502 | */ | |
503 | static bool mmu_spte_update(u64 *sptep, u64 new_spte) | |
504 | { | |
505 | bool flush = false; | |
506 | u64 old_spte = mmu_spte_update_no_track(sptep, new_spte); | |
507 | ||
508 | if (!is_shadow_present_pte(old_spte)) | |
509 | return false; | |
510 | ||
c7ba5b48 XG |
511 | /* |
512 | * For the spte updated out of mmu-lock is safe, since | |
6a6256f9 | 513 | * we always atomically update it, see the comments in |
c7ba5b48 XG |
514 | * spte_has_volatile_bits(). |
515 | */ | |
ea4114bc | 516 | if (spte_can_locklessly_be_made_writable(old_spte) && |
7f31c959 | 517 | !is_writable_pte(new_spte)) |
83ef6c81 | 518 | flush = true; |
4132779b | 519 | |
7e71a59b | 520 | /* |
83ef6c81 | 521 | * Flush TLB when accessed/dirty states are changed in the page tables, |
7e71a59b KH |
522 | * to guarantee consistency between TLB and page tables. |
523 | */ | |
7e71a59b | 524 | |
83ef6c81 JS |
525 | if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) { |
526 | flush = true; | |
4132779b | 527 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); |
83ef6c81 JS |
528 | } |
529 | ||
530 | if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) { | |
531 | flush = true; | |
4132779b | 532 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); |
83ef6c81 | 533 | } |
6e7d0354 | 534 | |
83ef6c81 | 535 | return flush; |
b79b93f9 AK |
536 | } |
537 | ||
1df9f2dc XG |
538 | /* |
539 | * Rules for using mmu_spte_clear_track_bits: | |
540 | * It sets the sptep from present to nonpresent, and track the | |
541 | * state bits, it is used to clear the last level sptep. | |
83ef6c81 | 542 | * Returns non-zero if the PTE was previously valid. |
1df9f2dc XG |
543 | */ |
544 | static int mmu_spte_clear_track_bits(u64 *sptep) | |
545 | { | |
ba049e93 | 546 | kvm_pfn_t pfn; |
1df9f2dc XG |
547 | u64 old_spte = *sptep; |
548 | ||
549 | if (!spte_has_volatile_bits(old_spte)) | |
603e0651 | 550 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc | 551 | else |
603e0651 | 552 | old_spte = __update_clear_spte_slow(sptep, 0ull); |
1df9f2dc | 553 | |
afd28fe1 | 554 | if (!is_shadow_present_pte(old_spte)) |
1df9f2dc XG |
555 | return 0; |
556 | ||
557 | pfn = spte_to_pfn(old_spte); | |
86fde74c XG |
558 | |
559 | /* | |
560 | * KVM does not hold the refcount of the page used by | |
561 | * kvm mmu, before reclaiming the page, we should | |
562 | * unmap it from mmu first. | |
563 | */ | |
bf4bea8e | 564 | WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn))); |
86fde74c | 565 | |
83ef6c81 | 566 | if (is_accessed_spte(old_spte)) |
1df9f2dc | 567 | kvm_set_pfn_accessed(pfn); |
83ef6c81 JS |
568 | |
569 | if (is_dirty_spte(old_spte)) | |
1df9f2dc | 570 | kvm_set_pfn_dirty(pfn); |
83ef6c81 | 571 | |
1df9f2dc XG |
572 | return 1; |
573 | } | |
574 | ||
575 | /* | |
576 | * Rules for using mmu_spte_clear_no_track: | |
577 | * Directly clear spte without caring the state bits of sptep, | |
578 | * it is used to set the upper level spte. | |
579 | */ | |
580 | static void mmu_spte_clear_no_track(u64 *sptep) | |
581 | { | |
603e0651 | 582 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc XG |
583 | } |
584 | ||
c2a2ac2b XG |
585 | static u64 mmu_spte_get_lockless(u64 *sptep) |
586 | { | |
587 | return __get_spte_lockless(sptep); | |
588 | } | |
589 | ||
d3e328f2 JS |
590 | /* Restore an acc-track PTE back to a regular PTE */ |
591 | static u64 restore_acc_track_spte(u64 spte) | |
592 | { | |
593 | u64 new_spte = spte; | |
8a967d65 PB |
594 | u64 saved_bits = (spte >> SHADOW_ACC_TRACK_SAVED_BITS_SHIFT) |
595 | & SHADOW_ACC_TRACK_SAVED_BITS_MASK; | |
d3e328f2 | 596 | |
ac8d57e5 | 597 | WARN_ON_ONCE(spte_ad_enabled(spte)); |
d3e328f2 JS |
598 | WARN_ON_ONCE(!is_access_track_spte(spte)); |
599 | ||
600 | new_spte &= ~shadow_acc_track_mask; | |
8a967d65 PB |
601 | new_spte &= ~(SHADOW_ACC_TRACK_SAVED_BITS_MASK << |
602 | SHADOW_ACC_TRACK_SAVED_BITS_SHIFT); | |
d3e328f2 JS |
603 | new_spte |= saved_bits; |
604 | ||
605 | return new_spte; | |
606 | } | |
607 | ||
f160c7b7 JS |
608 | /* Returns the Accessed status of the PTE and resets it at the same time. */ |
609 | static bool mmu_spte_age(u64 *sptep) | |
610 | { | |
611 | u64 spte = mmu_spte_get_lockless(sptep); | |
612 | ||
613 | if (!is_accessed_spte(spte)) | |
614 | return false; | |
615 | ||
ac8d57e5 | 616 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
617 | clear_bit((ffs(shadow_accessed_mask) - 1), |
618 | (unsigned long *)sptep); | |
619 | } else { | |
620 | /* | |
621 | * Capture the dirty status of the page, so that it doesn't get | |
622 | * lost when the SPTE is marked for access tracking. | |
623 | */ | |
624 | if (is_writable_pte(spte)) | |
625 | kvm_set_pfn_dirty(spte_to_pfn(spte)); | |
626 | ||
627 | spte = mark_spte_for_access_track(spte); | |
628 | mmu_spte_update_no_track(sptep, spte); | |
629 | } | |
630 | ||
631 | return true; | |
632 | } | |
633 | ||
c2a2ac2b XG |
634 | static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu) |
635 | { | |
c142786c AK |
636 | /* |
637 | * Prevent page table teardown by making any free-er wait during | |
638 | * kvm_flush_remote_tlbs() IPI to all active vcpus. | |
639 | */ | |
640 | local_irq_disable(); | |
36ca7e0a | 641 | |
c142786c AK |
642 | /* |
643 | * Make sure a following spte read is not reordered ahead of the write | |
644 | * to vcpu->mode. | |
645 | */ | |
36ca7e0a | 646 | smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES); |
c2a2ac2b XG |
647 | } |
648 | ||
649 | static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu) | |
650 | { | |
c142786c AK |
651 | /* |
652 | * Make sure the write to vcpu->mode is not reordered in front of | |
9a984586 | 653 | * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us |
c142786c AK |
654 | * OUTSIDE_GUEST_MODE and proceed to free the shadow page table. |
655 | */ | |
36ca7e0a | 656 | smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE); |
c142786c | 657 | local_irq_enable(); |
c2a2ac2b XG |
658 | } |
659 | ||
378f5cd6 | 660 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu, bool maybe_indirect) |
714b93da | 661 | { |
e2dec939 AK |
662 | int r; |
663 | ||
531281ad | 664 | /* 1 rmap, 1 parent PTE per level, and the prefetched rmaps. */ |
94ce87ef SC |
665 | r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
666 | 1 + PT64_ROOT_MAX_LEVEL + PTE_PREFETCH_NUM); | |
d3d25b04 | 667 | if (r) |
284aa868 | 668 | return r; |
94ce87ef SC |
669 | r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_shadow_page_cache, |
670 | PT64_ROOT_MAX_LEVEL); | |
d3d25b04 | 671 | if (r) |
171a90d7 | 672 | return r; |
378f5cd6 | 673 | if (maybe_indirect) { |
94ce87ef SC |
674 | r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_gfn_array_cache, |
675 | PT64_ROOT_MAX_LEVEL); | |
378f5cd6 SC |
676 | if (r) |
677 | return r; | |
678 | } | |
94ce87ef SC |
679 | return kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
680 | PT64_ROOT_MAX_LEVEL); | |
714b93da AK |
681 | } |
682 | ||
683 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
684 | { | |
94ce87ef SC |
685 | kvm_mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache); |
686 | kvm_mmu_free_memory_cache(&vcpu->arch.mmu_shadow_page_cache); | |
687 | kvm_mmu_free_memory_cache(&vcpu->arch.mmu_gfn_array_cache); | |
688 | kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache); | |
714b93da AK |
689 | } |
690 | ||
53c07b18 | 691 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 692 | { |
94ce87ef | 693 | return kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache); |
714b93da AK |
694 | } |
695 | ||
53c07b18 | 696 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 697 | { |
53c07b18 | 698 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
699 | } |
700 | ||
2032a93d LJ |
701 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
702 | { | |
703 | if (!sp->role.direct) | |
704 | return sp->gfns[index]; | |
705 | ||
706 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
707 | } | |
708 | ||
709 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
710 | { | |
e9f2a760 | 711 | if (!sp->role.direct) { |
2032a93d | 712 | sp->gfns[index] = gfn; |
e9f2a760 PB |
713 | return; |
714 | } | |
715 | ||
716 | if (WARN_ON(gfn != kvm_mmu_page_get_gfn(sp, index))) | |
717 | pr_err_ratelimited("gfn mismatch under direct page %llx " | |
718 | "(expected %llx, got %llx)\n", | |
719 | sp->gfn, | |
720 | kvm_mmu_page_get_gfn(sp, index), gfn); | |
2032a93d LJ |
721 | } |
722 | ||
05da4558 | 723 | /* |
d4dbf470 TY |
724 | * Return the pointer to the large page information for a given gfn, |
725 | * handling slots that are not large page aligned. | |
05da4558 | 726 | */ |
d4dbf470 TY |
727 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
728 | struct kvm_memory_slot *slot, | |
729 | int level) | |
05da4558 MT |
730 | { |
731 | unsigned long idx; | |
732 | ||
fb03cb6f | 733 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
db3fe4eb | 734 | return &slot->arch.lpage_info[level - 2][idx]; |
05da4558 MT |
735 | } |
736 | ||
547ffaed XG |
737 | static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot, |
738 | gfn_t gfn, int count) | |
739 | { | |
740 | struct kvm_lpage_info *linfo; | |
741 | int i; | |
742 | ||
3bae0459 | 743 | for (i = PG_LEVEL_2M; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) { |
547ffaed XG |
744 | linfo = lpage_info_slot(gfn, slot, i); |
745 | linfo->disallow_lpage += count; | |
746 | WARN_ON(linfo->disallow_lpage < 0); | |
747 | } | |
748 | } | |
749 | ||
750 | void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
751 | { | |
752 | update_gfn_disallow_lpage_count(slot, gfn, 1); | |
753 | } | |
754 | ||
755 | void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
756 | { | |
757 | update_gfn_disallow_lpage_count(slot, gfn, -1); | |
758 | } | |
759 | ||
3ed1a478 | 760 | static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 761 | { |
699023e2 | 762 | struct kvm_memslots *slots; |
d25797b2 | 763 | struct kvm_memory_slot *slot; |
3ed1a478 | 764 | gfn_t gfn; |
05da4558 | 765 | |
56ca57f9 | 766 | kvm->arch.indirect_shadow_pages++; |
3ed1a478 | 767 | gfn = sp->gfn; |
699023e2 PB |
768 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
769 | slot = __gfn_to_memslot(slots, gfn); | |
56ca57f9 XG |
770 | |
771 | /* the non-leaf shadow pages are keeping readonly. */ | |
3bae0459 | 772 | if (sp->role.level > PG_LEVEL_4K) |
56ca57f9 XG |
773 | return kvm_slot_page_track_add_page(kvm, slot, gfn, |
774 | KVM_PAGE_TRACK_WRITE); | |
775 | ||
547ffaed | 776 | kvm_mmu_gfn_disallow_lpage(slot, gfn); |
05da4558 MT |
777 | } |
778 | ||
29cf0f50 | 779 | void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
b8e8c830 PB |
780 | { |
781 | if (sp->lpage_disallowed) | |
782 | return; | |
783 | ||
784 | ++kvm->stat.nx_lpage_splits; | |
1aa9b957 JS |
785 | list_add_tail(&sp->lpage_disallowed_link, |
786 | &kvm->arch.lpage_disallowed_mmu_pages); | |
b8e8c830 PB |
787 | sp->lpage_disallowed = true; |
788 | } | |
789 | ||
3ed1a478 | 790 | static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 791 | { |
699023e2 | 792 | struct kvm_memslots *slots; |
d25797b2 | 793 | struct kvm_memory_slot *slot; |
3ed1a478 | 794 | gfn_t gfn; |
05da4558 | 795 | |
56ca57f9 | 796 | kvm->arch.indirect_shadow_pages--; |
3ed1a478 | 797 | gfn = sp->gfn; |
699023e2 PB |
798 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
799 | slot = __gfn_to_memslot(slots, gfn); | |
3bae0459 | 800 | if (sp->role.level > PG_LEVEL_4K) |
56ca57f9 XG |
801 | return kvm_slot_page_track_remove_page(kvm, slot, gfn, |
802 | KVM_PAGE_TRACK_WRITE); | |
803 | ||
547ffaed | 804 | kvm_mmu_gfn_allow_lpage(slot, gfn); |
05da4558 MT |
805 | } |
806 | ||
29cf0f50 | 807 | void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
b8e8c830 PB |
808 | { |
809 | --kvm->stat.nx_lpage_splits; | |
810 | sp->lpage_disallowed = false; | |
1aa9b957 | 811 | list_del(&sp->lpage_disallowed_link); |
b8e8c830 PB |
812 | } |
813 | ||
5d163b1c XG |
814 | static struct kvm_memory_slot * |
815 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
816 | bool no_dirty_log) | |
05da4558 MT |
817 | { |
818 | struct kvm_memory_slot *slot; | |
5d163b1c | 819 | |
54bf36aa | 820 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
91b0d268 PB |
821 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID) |
822 | return NULL; | |
044c59c4 | 823 | if (no_dirty_log && kvm_slot_dirty_track_enabled(slot)) |
91b0d268 | 824 | return NULL; |
5d163b1c XG |
825 | |
826 | return slot; | |
827 | } | |
828 | ||
290fc38d | 829 | /* |
018aabb5 | 830 | * About rmap_head encoding: |
cd4a4e53 | 831 | * |
018aabb5 TY |
832 | * If the bit zero of rmap_head->val is clear, then it points to the only spte |
833 | * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct | |
53c07b18 | 834 | * pte_list_desc containing more mappings. |
018aabb5 TY |
835 | */ |
836 | ||
837 | /* | |
838 | * Returns the number of pointers in the rmap chain, not counting the new one. | |
cd4a4e53 | 839 | */ |
53c07b18 | 840 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
018aabb5 | 841 | struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 842 | { |
53c07b18 | 843 | struct pte_list_desc *desc; |
53a27b39 | 844 | int i, count = 0; |
cd4a4e53 | 845 | |
018aabb5 | 846 | if (!rmap_head->val) { |
805a0f83 | 847 | rmap_printk("%p %llx 0->1\n", spte, *spte); |
018aabb5 TY |
848 | rmap_head->val = (unsigned long)spte; |
849 | } else if (!(rmap_head->val & 1)) { | |
805a0f83 | 850 | rmap_printk("%p %llx 1->many\n", spte, *spte); |
53c07b18 | 851 | desc = mmu_alloc_pte_list_desc(vcpu); |
018aabb5 | 852 | desc->sptes[0] = (u64 *)rmap_head->val; |
d555c333 | 853 | desc->sptes[1] = spte; |
018aabb5 | 854 | rmap_head->val = (unsigned long)desc | 1; |
cb16a7b3 | 855 | ++count; |
cd4a4e53 | 856 | } else { |
805a0f83 | 857 | rmap_printk("%p %llx many->many\n", spte, *spte); |
018aabb5 | 858 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
c6c4f961 | 859 | while (desc->sptes[PTE_LIST_EXT-1]) { |
53c07b18 | 860 | count += PTE_LIST_EXT; |
c6c4f961 LR |
861 | |
862 | if (!desc->more) { | |
863 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
864 | desc = desc->more; | |
865 | break; | |
866 | } | |
cd4a4e53 AK |
867 | desc = desc->more; |
868 | } | |
d555c333 | 869 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 870 | ++count; |
d555c333 | 871 | desc->sptes[i] = spte; |
cd4a4e53 | 872 | } |
53a27b39 | 873 | return count; |
cd4a4e53 AK |
874 | } |
875 | ||
53c07b18 | 876 | static void |
018aabb5 TY |
877 | pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head, |
878 | struct pte_list_desc *desc, int i, | |
879 | struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
880 | { |
881 | int j; | |
882 | ||
53c07b18 | 883 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 884 | ; |
d555c333 AK |
885 | desc->sptes[i] = desc->sptes[j]; |
886 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
887 | if (j != 0) |
888 | return; | |
889 | if (!prev_desc && !desc->more) | |
fe3c2b4c | 890 | rmap_head->val = 0; |
cd4a4e53 AK |
891 | else |
892 | if (prev_desc) | |
893 | prev_desc->more = desc->more; | |
894 | else | |
018aabb5 | 895 | rmap_head->val = (unsigned long)desc->more | 1; |
53c07b18 | 896 | mmu_free_pte_list_desc(desc); |
cd4a4e53 AK |
897 | } |
898 | ||
8daf3462 | 899 | static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 900 | { |
53c07b18 XG |
901 | struct pte_list_desc *desc; |
902 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
903 | int i; |
904 | ||
018aabb5 | 905 | if (!rmap_head->val) { |
8daf3462 | 906 | pr_err("%s: %p 0->BUG\n", __func__, spte); |
cd4a4e53 | 907 | BUG(); |
018aabb5 | 908 | } else if (!(rmap_head->val & 1)) { |
805a0f83 | 909 | rmap_printk("%p 1->0\n", spte); |
018aabb5 | 910 | if ((u64 *)rmap_head->val != spte) { |
8daf3462 | 911 | pr_err("%s: %p 1->BUG\n", __func__, spte); |
cd4a4e53 AK |
912 | BUG(); |
913 | } | |
018aabb5 | 914 | rmap_head->val = 0; |
cd4a4e53 | 915 | } else { |
805a0f83 | 916 | rmap_printk("%p many->many\n", spte); |
018aabb5 | 917 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
cd4a4e53 AK |
918 | prev_desc = NULL; |
919 | while (desc) { | |
018aabb5 | 920 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) { |
d555c333 | 921 | if (desc->sptes[i] == spte) { |
018aabb5 TY |
922 | pte_list_desc_remove_entry(rmap_head, |
923 | desc, i, prev_desc); | |
cd4a4e53 AK |
924 | return; |
925 | } | |
018aabb5 | 926 | } |
cd4a4e53 AK |
927 | prev_desc = desc; |
928 | desc = desc->more; | |
929 | } | |
8daf3462 | 930 | pr_err("%s: %p many->many\n", __func__, spte); |
cd4a4e53 AK |
931 | BUG(); |
932 | } | |
933 | } | |
934 | ||
e7912386 WY |
935 | static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep) |
936 | { | |
937 | mmu_spte_clear_track_bits(sptep); | |
938 | __pte_list_remove(sptep, rmap_head); | |
939 | } | |
940 | ||
018aabb5 TY |
941 | static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level, |
942 | struct kvm_memory_slot *slot) | |
53c07b18 | 943 | { |
77d11309 | 944 | unsigned long idx; |
53c07b18 | 945 | |
77d11309 | 946 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
3bae0459 | 947 | return &slot->arch.rmap[level - PG_LEVEL_4K][idx]; |
53c07b18 XG |
948 | } |
949 | ||
018aabb5 TY |
950 | static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, |
951 | struct kvm_mmu_page *sp) | |
9b9b1492 | 952 | { |
699023e2 | 953 | struct kvm_memslots *slots; |
9b9b1492 TY |
954 | struct kvm_memory_slot *slot; |
955 | ||
699023e2 PB |
956 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
957 | slot = __gfn_to_memslot(slots, gfn); | |
e4cd1da9 | 958 | return __gfn_to_rmap(gfn, sp->role.level, slot); |
9b9b1492 TY |
959 | } |
960 | ||
f759e2b4 XG |
961 | static bool rmap_can_add(struct kvm_vcpu *vcpu) |
962 | { | |
356ec69a | 963 | struct kvm_mmu_memory_cache *mc; |
f759e2b4 | 964 | |
356ec69a | 965 | mc = &vcpu->arch.mmu_pte_list_desc_cache; |
94ce87ef | 966 | return kvm_mmu_memory_cache_nr_free_objects(mc); |
f759e2b4 XG |
967 | } |
968 | ||
53c07b18 XG |
969 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
970 | { | |
971 | struct kvm_mmu_page *sp; | |
018aabb5 | 972 | struct kvm_rmap_head *rmap_head; |
53c07b18 | 973 | |
57354682 | 974 | sp = sptep_to_sp(spte); |
53c07b18 | 975 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); |
018aabb5 TY |
976 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
977 | return pte_list_add(vcpu, spte, rmap_head); | |
53c07b18 XG |
978 | } |
979 | ||
53c07b18 XG |
980 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
981 | { | |
982 | struct kvm_mmu_page *sp; | |
983 | gfn_t gfn; | |
018aabb5 | 984 | struct kvm_rmap_head *rmap_head; |
53c07b18 | 985 | |
57354682 | 986 | sp = sptep_to_sp(spte); |
53c07b18 | 987 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); |
018aabb5 | 988 | rmap_head = gfn_to_rmap(kvm, gfn, sp); |
8daf3462 | 989 | __pte_list_remove(spte, rmap_head); |
53c07b18 XG |
990 | } |
991 | ||
1e3f42f0 TY |
992 | /* |
993 | * Used by the following functions to iterate through the sptes linked by a | |
994 | * rmap. All fields are private and not assumed to be used outside. | |
995 | */ | |
996 | struct rmap_iterator { | |
997 | /* private fields */ | |
998 | struct pte_list_desc *desc; /* holds the sptep if not NULL */ | |
999 | int pos; /* index of the sptep */ | |
1000 | }; | |
1001 | ||
1002 | /* | |
1003 | * Iteration must be started by this function. This should also be used after | |
1004 | * removing/dropping sptes from the rmap link because in such cases the | |
0a03cbda | 1005 | * information in the iterator may not be valid. |
1e3f42f0 TY |
1006 | * |
1007 | * Returns sptep if found, NULL otherwise. | |
1008 | */ | |
018aabb5 TY |
1009 | static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head, |
1010 | struct rmap_iterator *iter) | |
1e3f42f0 | 1011 | { |
77fbbbd2 TY |
1012 | u64 *sptep; |
1013 | ||
018aabb5 | 1014 | if (!rmap_head->val) |
1e3f42f0 TY |
1015 | return NULL; |
1016 | ||
018aabb5 | 1017 | if (!(rmap_head->val & 1)) { |
1e3f42f0 | 1018 | iter->desc = NULL; |
77fbbbd2 TY |
1019 | sptep = (u64 *)rmap_head->val; |
1020 | goto out; | |
1e3f42f0 TY |
1021 | } |
1022 | ||
018aabb5 | 1023 | iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
1e3f42f0 | 1024 | iter->pos = 0; |
77fbbbd2 TY |
1025 | sptep = iter->desc->sptes[iter->pos]; |
1026 | out: | |
1027 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1028 | return sptep; | |
1e3f42f0 TY |
1029 | } |
1030 | ||
1031 | /* | |
1032 | * Must be used with a valid iterator: e.g. after rmap_get_first(). | |
1033 | * | |
1034 | * Returns sptep if found, NULL otherwise. | |
1035 | */ | |
1036 | static u64 *rmap_get_next(struct rmap_iterator *iter) | |
1037 | { | |
77fbbbd2 TY |
1038 | u64 *sptep; |
1039 | ||
1e3f42f0 TY |
1040 | if (iter->desc) { |
1041 | if (iter->pos < PTE_LIST_EXT - 1) { | |
1e3f42f0 TY |
1042 | ++iter->pos; |
1043 | sptep = iter->desc->sptes[iter->pos]; | |
1044 | if (sptep) | |
77fbbbd2 | 1045 | goto out; |
1e3f42f0 TY |
1046 | } |
1047 | ||
1048 | iter->desc = iter->desc->more; | |
1049 | ||
1050 | if (iter->desc) { | |
1051 | iter->pos = 0; | |
1052 | /* desc->sptes[0] cannot be NULL */ | |
77fbbbd2 TY |
1053 | sptep = iter->desc->sptes[iter->pos]; |
1054 | goto out; | |
1e3f42f0 TY |
1055 | } |
1056 | } | |
1057 | ||
1058 | return NULL; | |
77fbbbd2 TY |
1059 | out: |
1060 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1061 | return sptep; | |
1e3f42f0 TY |
1062 | } |
1063 | ||
018aabb5 TY |
1064 | #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \ |
1065 | for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \ | |
77fbbbd2 | 1066 | _spte_; _spte_ = rmap_get_next(_iter_)) |
0d536790 | 1067 | |
c3707958 | 1068 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 1069 | { |
1df9f2dc | 1070 | if (mmu_spte_clear_track_bits(sptep)) |
eb45fda4 | 1071 | rmap_remove(kvm, sptep); |
be38d276 AK |
1072 | } |
1073 | ||
8e22f955 XG |
1074 | |
1075 | static bool __drop_large_spte(struct kvm *kvm, u64 *sptep) | |
1076 | { | |
1077 | if (is_large_pte(*sptep)) { | |
57354682 | 1078 | WARN_ON(sptep_to_sp(sptep)->role.level == PG_LEVEL_4K); |
8e22f955 XG |
1079 | drop_spte(kvm, sptep); |
1080 | --kvm->stat.lpages; | |
1081 | return true; | |
1082 | } | |
1083 | ||
1084 | return false; | |
1085 | } | |
1086 | ||
1087 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) | |
1088 | { | |
c3134ce2 | 1089 | if (__drop_large_spte(vcpu->kvm, sptep)) { |
57354682 | 1090 | struct kvm_mmu_page *sp = sptep_to_sp(sptep); |
c3134ce2 LT |
1091 | |
1092 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn, | |
1093 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
1094 | } | |
8e22f955 XG |
1095 | } |
1096 | ||
1097 | /* | |
49fde340 | 1098 | * Write-protect on the specified @sptep, @pt_protect indicates whether |
c126d94f | 1099 | * spte write-protection is caused by protecting shadow page table. |
49fde340 | 1100 | * |
b4619660 | 1101 | * Note: write protection is difference between dirty logging and spte |
49fde340 XG |
1102 | * protection: |
1103 | * - for dirty logging, the spte can be set to writable at anytime if | |
1104 | * its dirty bitmap is properly set. | |
1105 | * - for spte protection, the spte can be writable only after unsync-ing | |
1106 | * shadow page. | |
8e22f955 | 1107 | * |
c126d94f | 1108 | * Return true if tlb need be flushed. |
8e22f955 | 1109 | */ |
c4f138b4 | 1110 | static bool spte_write_protect(u64 *sptep, bool pt_protect) |
d13bc5b5 XG |
1111 | { |
1112 | u64 spte = *sptep; | |
1113 | ||
49fde340 | 1114 | if (!is_writable_pte(spte) && |
ea4114bc | 1115 | !(pt_protect && spte_can_locklessly_be_made_writable(spte))) |
d13bc5b5 XG |
1116 | return false; |
1117 | ||
805a0f83 | 1118 | rmap_printk("spte %p %llx\n", sptep, *sptep); |
d13bc5b5 | 1119 | |
49fde340 XG |
1120 | if (pt_protect) |
1121 | spte &= ~SPTE_MMU_WRITEABLE; | |
d13bc5b5 | 1122 | spte = spte & ~PT_WRITABLE_MASK; |
49fde340 | 1123 | |
c126d94f | 1124 | return mmu_spte_update(sptep, spte); |
d13bc5b5 XG |
1125 | } |
1126 | ||
018aabb5 TY |
1127 | static bool __rmap_write_protect(struct kvm *kvm, |
1128 | struct kvm_rmap_head *rmap_head, | |
245c3912 | 1129 | bool pt_protect) |
98348e95 | 1130 | { |
1e3f42f0 TY |
1131 | u64 *sptep; |
1132 | struct rmap_iterator iter; | |
d13bc5b5 | 1133 | bool flush = false; |
374cbac0 | 1134 | |
018aabb5 | 1135 | for_each_rmap_spte(rmap_head, &iter, sptep) |
c4f138b4 | 1136 | flush |= spte_write_protect(sptep, pt_protect); |
855149aa | 1137 | |
d13bc5b5 | 1138 | return flush; |
a0ed4607 TY |
1139 | } |
1140 | ||
c4f138b4 | 1141 | static bool spte_clear_dirty(u64 *sptep) |
f4b4b180 KH |
1142 | { |
1143 | u64 spte = *sptep; | |
1144 | ||
805a0f83 | 1145 | rmap_printk("spte %p %llx\n", sptep, *sptep); |
f4b4b180 | 1146 | |
1f4e5fc8 | 1147 | MMU_WARN_ON(!spte_ad_enabled(spte)); |
f4b4b180 | 1148 | spte &= ~shadow_dirty_mask; |
f4b4b180 KH |
1149 | return mmu_spte_update(sptep, spte); |
1150 | } | |
1151 | ||
1f4e5fc8 | 1152 | static bool spte_wrprot_for_clear_dirty(u64 *sptep) |
ac8d57e5 PF |
1153 | { |
1154 | bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT, | |
1155 | (unsigned long *)sptep); | |
1f4e5fc8 | 1156 | if (was_writable && !spte_ad_enabled(*sptep)) |
ac8d57e5 PF |
1157 | kvm_set_pfn_dirty(spte_to_pfn(*sptep)); |
1158 | ||
1159 | return was_writable; | |
1160 | } | |
1161 | ||
1162 | /* | |
1163 | * Gets the GFN ready for another round of dirty logging by clearing the | |
1164 | * - D bit on ad-enabled SPTEs, and | |
1165 | * - W bit on ad-disabled SPTEs. | |
1166 | * Returns true iff any D or W bits were cleared. | |
1167 | */ | |
0a234f5d SC |
1168 | static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
1169 | struct kvm_memory_slot *slot) | |
f4b4b180 KH |
1170 | { |
1171 | u64 *sptep; | |
1172 | struct rmap_iterator iter; | |
1173 | bool flush = false; | |
1174 | ||
018aabb5 | 1175 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1f4e5fc8 PB |
1176 | if (spte_ad_need_write_protect(*sptep)) |
1177 | flush |= spte_wrprot_for_clear_dirty(sptep); | |
ac8d57e5 | 1178 | else |
1f4e5fc8 | 1179 | flush |= spte_clear_dirty(sptep); |
f4b4b180 KH |
1180 | |
1181 | return flush; | |
1182 | } | |
1183 | ||
5dc99b23 | 1184 | /** |
3b0f1d01 | 1185 | * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages |
5dc99b23 TY |
1186 | * @kvm: kvm instance |
1187 | * @slot: slot to protect | |
1188 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1189 | * @mask: indicates which pages we should protect | |
1190 | * | |
1191 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1192 | * logging we do not have any such mappings. | |
1193 | */ | |
3b0f1d01 | 1194 | static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, |
5dc99b23 TY |
1195 | struct kvm_memory_slot *slot, |
1196 | gfn_t gfn_offset, unsigned long mask) | |
a0ed4607 | 1197 | { |
018aabb5 | 1198 | struct kvm_rmap_head *rmap_head; |
a0ed4607 | 1199 | |
897218ff | 1200 | if (is_tdp_mmu_enabled(kvm)) |
a6a0b05d BG |
1201 | kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot, |
1202 | slot->base_gfn + gfn_offset, mask, true); | |
5dc99b23 | 1203 | while (mask) { |
018aabb5 | 1204 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
3bae0459 | 1205 | PG_LEVEL_4K, slot); |
018aabb5 | 1206 | __rmap_write_protect(kvm, rmap_head, false); |
05da4558 | 1207 | |
5dc99b23 TY |
1208 | /* clear the first set bit */ |
1209 | mask &= mask - 1; | |
1210 | } | |
374cbac0 AK |
1211 | } |
1212 | ||
f4b4b180 | 1213 | /** |
ac8d57e5 PF |
1214 | * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write |
1215 | * protect the page if the D-bit isn't supported. | |
f4b4b180 KH |
1216 | * @kvm: kvm instance |
1217 | * @slot: slot to clear D-bit | |
1218 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1219 | * @mask: indicates which pages we should clear D-bit | |
1220 | * | |
1221 | * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap. | |
1222 | */ | |
a018eba5 SC |
1223 | static void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, |
1224 | struct kvm_memory_slot *slot, | |
1225 | gfn_t gfn_offset, unsigned long mask) | |
f4b4b180 | 1226 | { |
018aabb5 | 1227 | struct kvm_rmap_head *rmap_head; |
f4b4b180 | 1228 | |
897218ff | 1229 | if (is_tdp_mmu_enabled(kvm)) |
a6a0b05d BG |
1230 | kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot, |
1231 | slot->base_gfn + gfn_offset, mask, false); | |
f4b4b180 | 1232 | while (mask) { |
018aabb5 | 1233 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
3bae0459 | 1234 | PG_LEVEL_4K, slot); |
0a234f5d | 1235 | __rmap_clear_dirty(kvm, rmap_head, slot); |
f4b4b180 KH |
1236 | |
1237 | /* clear the first set bit */ | |
1238 | mask &= mask - 1; | |
1239 | } | |
1240 | } | |
f4b4b180 | 1241 | |
3b0f1d01 KH |
1242 | /** |
1243 | * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected | |
1244 | * PT level pages. | |
1245 | * | |
1246 | * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to | |
1247 | * enable dirty logging for them. | |
1248 | * | |
1249 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1250 | * logging we do not have any such mappings. | |
1251 | */ | |
1252 | void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm, | |
1253 | struct kvm_memory_slot *slot, | |
1254 | gfn_t gfn_offset, unsigned long mask) | |
1255 | { | |
a018eba5 SC |
1256 | if (kvm_x86_ops.cpu_dirty_log_size) |
1257 | kvm_mmu_clear_dirty_pt_masked(kvm, slot, gfn_offset, mask); | |
88178fd4 KH |
1258 | else |
1259 | kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask); | |
3b0f1d01 KH |
1260 | } |
1261 | ||
fb04a1ed PX |
1262 | int kvm_cpu_dirty_log_size(void) |
1263 | { | |
6dd03800 | 1264 | return kvm_x86_ops.cpu_dirty_log_size; |
fb04a1ed PX |
1265 | } |
1266 | ||
aeecee2e XG |
1267 | bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm, |
1268 | struct kvm_memory_slot *slot, u64 gfn) | |
95d4c16c | 1269 | { |
018aabb5 | 1270 | struct kvm_rmap_head *rmap_head; |
5dc99b23 | 1271 | int i; |
2f84569f | 1272 | bool write_protected = false; |
95d4c16c | 1273 | |
3bae0459 | 1274 | for (i = PG_LEVEL_4K; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) { |
018aabb5 | 1275 | rmap_head = __gfn_to_rmap(gfn, i, slot); |
aeecee2e | 1276 | write_protected |= __rmap_write_protect(kvm, rmap_head, true); |
5dc99b23 TY |
1277 | } |
1278 | ||
897218ff | 1279 | if (is_tdp_mmu_enabled(kvm)) |
46044f72 BG |
1280 | write_protected |= |
1281 | kvm_tdp_mmu_write_protect_gfn(kvm, slot, gfn); | |
1282 | ||
5dc99b23 | 1283 | return write_protected; |
95d4c16c TY |
1284 | } |
1285 | ||
aeecee2e XG |
1286 | static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn) |
1287 | { | |
1288 | struct kvm_memory_slot *slot; | |
1289 | ||
1290 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); | |
1291 | return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn); | |
1292 | } | |
1293 | ||
0a234f5d SC |
1294 | static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
1295 | struct kvm_memory_slot *slot) | |
e930bffe | 1296 | { |
1e3f42f0 TY |
1297 | u64 *sptep; |
1298 | struct rmap_iterator iter; | |
6a49f85c | 1299 | bool flush = false; |
e930bffe | 1300 | |
018aabb5 | 1301 | while ((sptep = rmap_get_first(rmap_head, &iter))) { |
805a0f83 | 1302 | rmap_printk("spte %p %llx.\n", sptep, *sptep); |
1e3f42f0 | 1303 | |
e7912386 | 1304 | pte_list_remove(rmap_head, sptep); |
6a49f85c | 1305 | flush = true; |
e930bffe | 1306 | } |
1e3f42f0 | 1307 | |
6a49f85c XG |
1308 | return flush; |
1309 | } | |
1310 | ||
018aabb5 | 1311 | static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
6a49f85c XG |
1312 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1313 | unsigned long data) | |
1314 | { | |
0a234f5d | 1315 | return kvm_zap_rmapp(kvm, rmap_head, slot); |
e930bffe AA |
1316 | } |
1317 | ||
018aabb5 | 1318 | static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1319 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1320 | unsigned long data) | |
3da0dd43 | 1321 | { |
1e3f42f0 TY |
1322 | u64 *sptep; |
1323 | struct rmap_iterator iter; | |
3da0dd43 | 1324 | int need_flush = 0; |
1e3f42f0 | 1325 | u64 new_spte; |
3da0dd43 | 1326 | pte_t *ptep = (pte_t *)data; |
ba049e93 | 1327 | kvm_pfn_t new_pfn; |
3da0dd43 IE |
1328 | |
1329 | WARN_ON(pte_huge(*ptep)); | |
1330 | new_pfn = pte_pfn(*ptep); | |
1e3f42f0 | 1331 | |
0d536790 | 1332 | restart: |
018aabb5 | 1333 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
805a0f83 | 1334 | rmap_printk("spte %p %llx gfn %llx (%d)\n", |
f160c7b7 | 1335 | sptep, *sptep, gfn, level); |
1e3f42f0 | 1336 | |
3da0dd43 | 1337 | need_flush = 1; |
1e3f42f0 | 1338 | |
3da0dd43 | 1339 | if (pte_write(*ptep)) { |
e7912386 | 1340 | pte_list_remove(rmap_head, sptep); |
0d536790 | 1341 | goto restart; |
3da0dd43 | 1342 | } else { |
cb3eedab PB |
1343 | new_spte = kvm_mmu_changed_pte_notifier_make_spte( |
1344 | *sptep, new_pfn); | |
1e3f42f0 TY |
1345 | |
1346 | mmu_spte_clear_track_bits(sptep); | |
1347 | mmu_spte_set(sptep, new_spte); | |
3da0dd43 IE |
1348 | } |
1349 | } | |
1e3f42f0 | 1350 | |
3cc5ea94 LT |
1351 | if (need_flush && kvm_available_flush_tlb_with_range()) { |
1352 | kvm_flush_remote_tlbs_with_address(kvm, gfn, 1); | |
1353 | return 0; | |
1354 | } | |
1355 | ||
0cf853c5 | 1356 | return need_flush; |
3da0dd43 IE |
1357 | } |
1358 | ||
6ce1f4e2 XG |
1359 | struct slot_rmap_walk_iterator { |
1360 | /* input fields. */ | |
1361 | struct kvm_memory_slot *slot; | |
1362 | gfn_t start_gfn; | |
1363 | gfn_t end_gfn; | |
1364 | int start_level; | |
1365 | int end_level; | |
1366 | ||
1367 | /* output fields. */ | |
1368 | gfn_t gfn; | |
018aabb5 | 1369 | struct kvm_rmap_head *rmap; |
6ce1f4e2 XG |
1370 | int level; |
1371 | ||
1372 | /* private field. */ | |
018aabb5 | 1373 | struct kvm_rmap_head *end_rmap; |
6ce1f4e2 XG |
1374 | }; |
1375 | ||
1376 | static void | |
1377 | rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level) | |
1378 | { | |
1379 | iterator->level = level; | |
1380 | iterator->gfn = iterator->start_gfn; | |
1381 | iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot); | |
1382 | iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level, | |
1383 | iterator->slot); | |
1384 | } | |
1385 | ||
1386 | static void | |
1387 | slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator, | |
1388 | struct kvm_memory_slot *slot, int start_level, | |
1389 | int end_level, gfn_t start_gfn, gfn_t end_gfn) | |
1390 | { | |
1391 | iterator->slot = slot; | |
1392 | iterator->start_level = start_level; | |
1393 | iterator->end_level = end_level; | |
1394 | iterator->start_gfn = start_gfn; | |
1395 | iterator->end_gfn = end_gfn; | |
1396 | ||
1397 | rmap_walk_init_level(iterator, iterator->start_level); | |
1398 | } | |
1399 | ||
1400 | static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator) | |
1401 | { | |
1402 | return !!iterator->rmap; | |
1403 | } | |
1404 | ||
1405 | static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator) | |
1406 | { | |
1407 | if (++iterator->rmap <= iterator->end_rmap) { | |
1408 | iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level)); | |
1409 | return; | |
1410 | } | |
1411 | ||
1412 | if (++iterator->level > iterator->end_level) { | |
1413 | iterator->rmap = NULL; | |
1414 | return; | |
1415 | } | |
1416 | ||
1417 | rmap_walk_init_level(iterator, iterator->level); | |
1418 | } | |
1419 | ||
1420 | #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \ | |
1421 | _start_gfn, _end_gfn, _iter_) \ | |
1422 | for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \ | |
1423 | _end_level_, _start_gfn, _end_gfn); \ | |
1424 | slot_rmap_walk_okay(_iter_); \ | |
1425 | slot_rmap_walk_next(_iter_)) | |
1426 | ||
8f5c44f9 MS |
1427 | static __always_inline int |
1428 | kvm_handle_hva_range(struct kvm *kvm, | |
1429 | unsigned long start, | |
1430 | unsigned long end, | |
1431 | unsigned long data, | |
1432 | int (*handler)(struct kvm *kvm, | |
1433 | struct kvm_rmap_head *rmap_head, | |
1434 | struct kvm_memory_slot *slot, | |
1435 | gfn_t gfn, | |
1436 | int level, | |
1437 | unsigned long data)) | |
e930bffe | 1438 | { |
bc6678a3 | 1439 | struct kvm_memslots *slots; |
be6ba0f0 | 1440 | struct kvm_memory_slot *memslot; |
6ce1f4e2 XG |
1441 | struct slot_rmap_walk_iterator iterator; |
1442 | int ret = 0; | |
9da0e4d5 | 1443 | int i; |
bc6678a3 | 1444 | |
9da0e4d5 PB |
1445 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1446 | slots = __kvm_memslots(kvm, i); | |
1447 | kvm_for_each_memslot(memslot, slots) { | |
1448 | unsigned long hva_start, hva_end; | |
1449 | gfn_t gfn_start, gfn_end; | |
e930bffe | 1450 | |
9da0e4d5 PB |
1451 | hva_start = max(start, memslot->userspace_addr); |
1452 | hva_end = min(end, memslot->userspace_addr + | |
1453 | (memslot->npages << PAGE_SHIFT)); | |
1454 | if (hva_start >= hva_end) | |
1455 | continue; | |
1456 | /* | |
1457 | * {gfn(page) | page intersects with [hva_start, hva_end)} = | |
1458 | * {gfn_start, gfn_start+1, ..., gfn_end-1}. | |
1459 | */ | |
1460 | gfn_start = hva_to_gfn_memslot(hva_start, memslot); | |
1461 | gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot); | |
1462 | ||
3bae0459 | 1463 | for_each_slot_rmap_range(memslot, PG_LEVEL_4K, |
e662ec3e | 1464 | KVM_MAX_HUGEPAGE_LEVEL, |
9da0e4d5 PB |
1465 | gfn_start, gfn_end - 1, |
1466 | &iterator) | |
1467 | ret |= handler(kvm, iterator.rmap, memslot, | |
1468 | iterator.gfn, iterator.level, data); | |
1469 | } | |
e930bffe AA |
1470 | } |
1471 | ||
f395302e | 1472 | return ret; |
e930bffe AA |
1473 | } |
1474 | ||
84504ef3 TY |
1475 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
1476 | unsigned long data, | |
018aabb5 TY |
1477 | int (*handler)(struct kvm *kvm, |
1478 | struct kvm_rmap_head *rmap_head, | |
048212d0 | 1479 | struct kvm_memory_slot *slot, |
8a9522d2 | 1480 | gfn_t gfn, int level, |
84504ef3 TY |
1481 | unsigned long data)) |
1482 | { | |
1483 | return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler); | |
e930bffe AA |
1484 | } |
1485 | ||
fdfe7cbd WD |
1486 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end, |
1487 | unsigned flags) | |
b3ae2096 | 1488 | { |
063afacd BG |
1489 | int r; |
1490 | ||
1491 | r = kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp); | |
1492 | ||
897218ff | 1493 | if (is_tdp_mmu_enabled(kvm)) |
063afacd BG |
1494 | r |= kvm_tdp_mmu_zap_hva_range(kvm, start, end); |
1495 | ||
1496 | return r; | |
b3ae2096 TY |
1497 | } |
1498 | ||
748c0e31 | 1499 | int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) |
3da0dd43 | 1500 | { |
1d8dd6b3 BG |
1501 | int r; |
1502 | ||
1503 | r = kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); | |
1504 | ||
897218ff | 1505 | if (is_tdp_mmu_enabled(kvm)) |
1d8dd6b3 BG |
1506 | r |= kvm_tdp_mmu_set_spte_hva(kvm, hva, &pte); |
1507 | ||
1508 | return r; | |
e930bffe AA |
1509 | } |
1510 | ||
018aabb5 | 1511 | static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1512 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1513 | unsigned long data) | |
e930bffe | 1514 | { |
1e3f42f0 | 1515 | u64 *sptep; |
3f649ab7 | 1516 | struct rmap_iterator iter; |
e930bffe AA |
1517 | int young = 0; |
1518 | ||
f160c7b7 JS |
1519 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1520 | young |= mmu_spte_age(sptep); | |
0d536790 | 1521 | |
8a9522d2 | 1522 | trace_kvm_age_page(gfn, level, slot, young); |
e930bffe AA |
1523 | return young; |
1524 | } | |
1525 | ||
018aabb5 | 1526 | static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1527 | struct kvm_memory_slot *slot, gfn_t gfn, |
1528 | int level, unsigned long data) | |
8ee53820 | 1529 | { |
1e3f42f0 TY |
1530 | u64 *sptep; |
1531 | struct rmap_iterator iter; | |
8ee53820 | 1532 | |
83ef6c81 JS |
1533 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1534 | if (is_accessed_spte(*sptep)) | |
1535 | return 1; | |
83ef6c81 | 1536 | return 0; |
8ee53820 AA |
1537 | } |
1538 | ||
53a27b39 MT |
1539 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1540 | ||
852e3c19 | 1541 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 | 1542 | { |
018aabb5 | 1543 | struct kvm_rmap_head *rmap_head; |
852e3c19 JR |
1544 | struct kvm_mmu_page *sp; |
1545 | ||
57354682 | 1546 | sp = sptep_to_sp(spte); |
53a27b39 | 1547 | |
018aabb5 | 1548 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
53a27b39 | 1549 | |
018aabb5 | 1550 | kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0); |
c3134ce2 LT |
1551 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn, |
1552 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
53a27b39 MT |
1553 | } |
1554 | ||
57128468 | 1555 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end) |
e930bffe | 1556 | { |
f8e14497 BG |
1557 | int young = false; |
1558 | ||
1559 | young = kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp); | |
897218ff | 1560 | if (is_tdp_mmu_enabled(kvm)) |
f8e14497 BG |
1561 | young |= kvm_tdp_mmu_age_hva_range(kvm, start, end); |
1562 | ||
1563 | return young; | |
e930bffe AA |
1564 | } |
1565 | ||
8ee53820 AA |
1566 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) |
1567 | { | |
f8e14497 BG |
1568 | int young = false; |
1569 | ||
1570 | young = kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp); | |
897218ff | 1571 | if (is_tdp_mmu_enabled(kvm)) |
f8e14497 BG |
1572 | young |= kvm_tdp_mmu_test_age_hva(kvm, hva); |
1573 | ||
1574 | return young; | |
8ee53820 AA |
1575 | } |
1576 | ||
d6c69ee9 | 1577 | #ifdef MMU_DEBUG |
47ad8e68 | 1578 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1579 | { |
139bdb2d AK |
1580 | u64 *pos; |
1581 | u64 *end; | |
1582 | ||
47ad8e68 | 1583 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1584 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1585 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1586 | pos, *pos); |
6aa8b732 | 1587 | return 0; |
139bdb2d | 1588 | } |
6aa8b732 AK |
1589 | return 1; |
1590 | } | |
d6c69ee9 | 1591 | #endif |
6aa8b732 | 1592 | |
45221ab6 DH |
1593 | /* |
1594 | * This value is the sum of all of the kvm instances's | |
1595 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1596 | * aggregate version in order to make the slab shrinker | |
1597 | * faster | |
1598 | */ | |
bc8a3d89 | 1599 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, unsigned long nr) |
45221ab6 DH |
1600 | { |
1601 | kvm->arch.n_used_mmu_pages += nr; | |
1602 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
1603 | } | |
1604 | ||
834be0d8 | 1605 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) |
260746c0 | 1606 | { |
fa4a2c08 | 1607 | MMU_WARN_ON(!is_empty_shadow_page(sp->spt)); |
7775834a | 1608 | hlist_del(&sp->hash_link); |
bd4c86ea XG |
1609 | list_del(&sp->link); |
1610 | free_page((unsigned long)sp->spt); | |
834be0d8 GN |
1611 | if (!sp->role.direct) |
1612 | free_page((unsigned long)sp->gfns); | |
e8ad9a70 | 1613 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
1614 | } |
1615 | ||
cea0f0e7 AK |
1616 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1617 | { | |
114df303 | 1618 | return hash_64(gfn, KVM_MMU_HASH_SHIFT); |
cea0f0e7 AK |
1619 | } |
1620 | ||
714b93da | 1621 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1622 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1623 | { |
cea0f0e7 AK |
1624 | if (!parent_pte) |
1625 | return; | |
cea0f0e7 | 1626 | |
67052b35 | 1627 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1628 | } |
1629 | ||
4db35314 | 1630 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1631 | u64 *parent_pte) |
1632 | { | |
8daf3462 | 1633 | __pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1634 | } |
1635 | ||
bcdd9a93 XG |
1636 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
1637 | u64 *parent_pte) | |
1638 | { | |
1639 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 1640 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
1641 | } |
1642 | ||
47005792 | 1643 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct) |
ad8cfbe3 | 1644 | { |
67052b35 | 1645 | struct kvm_mmu_page *sp; |
7ddca7e4 | 1646 | |
94ce87ef SC |
1647 | sp = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache); |
1648 | sp->spt = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_shadow_page_cache); | |
67052b35 | 1649 | if (!direct) |
94ce87ef | 1650 | sp->gfns = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_gfn_array_cache); |
67052b35 | 1651 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
002c5f73 SC |
1652 | |
1653 | /* | |
1654 | * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages() | |
1655 | * depends on valid pages being added to the head of the list. See | |
1656 | * comments in kvm_zap_obsolete_pages(). | |
1657 | */ | |
ca333add | 1658 | sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen; |
67052b35 | 1659 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
67052b35 XG |
1660 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); |
1661 | return sp; | |
ad8cfbe3 MT |
1662 | } |
1663 | ||
67052b35 | 1664 | static void mark_unsync(u64 *spte); |
1047df1f | 1665 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 1666 | { |
74c4e63a TY |
1667 | u64 *sptep; |
1668 | struct rmap_iterator iter; | |
1669 | ||
1670 | for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) { | |
1671 | mark_unsync(sptep); | |
1672 | } | |
0074ff63 MT |
1673 | } |
1674 | ||
67052b35 | 1675 | static void mark_unsync(u64 *spte) |
0074ff63 | 1676 | { |
67052b35 | 1677 | struct kvm_mmu_page *sp; |
1047df1f | 1678 | unsigned int index; |
0074ff63 | 1679 | |
57354682 | 1680 | sp = sptep_to_sp(spte); |
1047df1f XG |
1681 | index = spte - sp->spt; |
1682 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1683 | return; |
1047df1f | 1684 | if (sp->unsync_children++) |
0074ff63 | 1685 | return; |
1047df1f | 1686 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1687 | } |
1688 | ||
e8bc217a | 1689 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1690 | struct kvm_mmu_page *sp) |
e8bc217a | 1691 | { |
1f50f1b3 | 1692 | return 0; |
e8bc217a MT |
1693 | } |
1694 | ||
60c8aec6 MT |
1695 | #define KVM_PAGE_ARRAY_NR 16 |
1696 | ||
1697 | struct kvm_mmu_pages { | |
1698 | struct mmu_page_and_offset { | |
1699 | struct kvm_mmu_page *sp; | |
1700 | unsigned int idx; | |
1701 | } page[KVM_PAGE_ARRAY_NR]; | |
1702 | unsigned int nr; | |
1703 | }; | |
1704 | ||
cded19f3 HE |
1705 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1706 | int idx) | |
4731d4c7 | 1707 | { |
60c8aec6 | 1708 | int i; |
4731d4c7 | 1709 | |
60c8aec6 MT |
1710 | if (sp->unsync) |
1711 | for (i=0; i < pvec->nr; i++) | |
1712 | if (pvec->page[i].sp == sp) | |
1713 | return 0; | |
1714 | ||
1715 | pvec->page[pvec->nr].sp = sp; | |
1716 | pvec->page[pvec->nr].idx = idx; | |
1717 | pvec->nr++; | |
1718 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1719 | } | |
1720 | ||
fd951457 TY |
1721 | static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx) |
1722 | { | |
1723 | --sp->unsync_children; | |
1724 | WARN_ON((int)sp->unsync_children < 0); | |
1725 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1726 | } | |
1727 | ||
60c8aec6 MT |
1728 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, |
1729 | struct kvm_mmu_pages *pvec) | |
1730 | { | |
1731 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1732 | |
37178b8b | 1733 | for_each_set_bit(i, sp->unsync_child_bitmap, 512) { |
7a8f1a74 | 1734 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1735 | u64 ent = sp->spt[i]; |
1736 | ||
fd951457 TY |
1737 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) { |
1738 | clear_unsync_child_bit(sp, i); | |
1739 | continue; | |
1740 | } | |
7a8f1a74 | 1741 | |
e47c4aee | 1742 | child = to_shadow_page(ent & PT64_BASE_ADDR_MASK); |
7a8f1a74 XG |
1743 | |
1744 | if (child->unsync_children) { | |
1745 | if (mmu_pages_add(pvec, child, i)) | |
1746 | return -ENOSPC; | |
1747 | ||
1748 | ret = __mmu_unsync_walk(child, pvec); | |
fd951457 TY |
1749 | if (!ret) { |
1750 | clear_unsync_child_bit(sp, i); | |
1751 | continue; | |
1752 | } else if (ret > 0) { | |
7a8f1a74 | 1753 | nr_unsync_leaf += ret; |
fd951457 | 1754 | } else |
7a8f1a74 XG |
1755 | return ret; |
1756 | } else if (child->unsync) { | |
1757 | nr_unsync_leaf++; | |
1758 | if (mmu_pages_add(pvec, child, i)) | |
1759 | return -ENOSPC; | |
1760 | } else | |
fd951457 | 1761 | clear_unsync_child_bit(sp, i); |
4731d4c7 MT |
1762 | } |
1763 | ||
60c8aec6 MT |
1764 | return nr_unsync_leaf; |
1765 | } | |
1766 | ||
e23d3fef XG |
1767 | #define INVALID_INDEX (-1) |
1768 | ||
60c8aec6 MT |
1769 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, |
1770 | struct kvm_mmu_pages *pvec) | |
1771 | { | |
0a47cd85 | 1772 | pvec->nr = 0; |
60c8aec6 MT |
1773 | if (!sp->unsync_children) |
1774 | return 0; | |
1775 | ||
e23d3fef | 1776 | mmu_pages_add(pvec, sp, INVALID_INDEX); |
60c8aec6 | 1777 | return __mmu_unsync_walk(sp, pvec); |
4731d4c7 MT |
1778 | } |
1779 | ||
4731d4c7 MT |
1780 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1781 | { | |
1782 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1783 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1784 | sp->unsync = 0; |
1785 | --kvm->stat.mmu_unsync; | |
1786 | } | |
1787 | ||
83cdb568 SC |
1788 | static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1789 | struct list_head *invalid_list); | |
7775834a XG |
1790 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
1791 | struct list_head *invalid_list); | |
4731d4c7 | 1792 | |
ac101b7c SC |
1793 | #define for_each_valid_sp(_kvm, _sp, _list) \ |
1794 | hlist_for_each_entry(_sp, _list, hash_link) \ | |
fac026da | 1795 | if (is_obsolete_sp((_kvm), (_sp))) { \ |
f3414bc7 | 1796 | } else |
1044b030 TY |
1797 | |
1798 | #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \ | |
ac101b7c SC |
1799 | for_each_valid_sp(_kvm, _sp, \ |
1800 | &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)]) \ | |
f3414bc7 | 1801 | if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else |
7ae680eb | 1802 | |
47c42e6b SC |
1803 | static inline bool is_ept_sp(struct kvm_mmu_page *sp) |
1804 | { | |
1805 | return sp->role.cr0_wp && sp->role.smap_andnot_wp; | |
1806 | } | |
1807 | ||
f918b443 | 1808 | /* @sp->gfn should be write-protected at the call site */ |
1f50f1b3 PB |
1809 | static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1810 | struct list_head *invalid_list) | |
4731d4c7 | 1811 | { |
47c42e6b SC |
1812 | if ((!is_ept_sp(sp) && sp->role.gpte_is_8_bytes != !!is_pae(vcpu)) || |
1813 | vcpu->arch.mmu->sync_page(vcpu, sp) == 0) { | |
d98ba053 | 1814 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
1f50f1b3 | 1815 | return false; |
4731d4c7 MT |
1816 | } |
1817 | ||
1f50f1b3 | 1818 | return true; |
4731d4c7 MT |
1819 | } |
1820 | ||
a2113634 SC |
1821 | static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm, |
1822 | struct list_head *invalid_list, | |
1823 | bool remote_flush) | |
1824 | { | |
cfd32acf | 1825 | if (!remote_flush && list_empty(invalid_list)) |
a2113634 SC |
1826 | return false; |
1827 | ||
1828 | if (!list_empty(invalid_list)) | |
1829 | kvm_mmu_commit_zap_page(kvm, invalid_list); | |
1830 | else | |
1831 | kvm_flush_remote_tlbs(kvm); | |
1832 | return true; | |
1833 | } | |
1834 | ||
35a70510 PB |
1835 | static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu, |
1836 | struct list_head *invalid_list, | |
1837 | bool remote_flush, bool local_flush) | |
1d9dc7e0 | 1838 | { |
a2113634 | 1839 | if (kvm_mmu_remote_flush_or_zap(vcpu->kvm, invalid_list, remote_flush)) |
35a70510 | 1840 | return; |
d98ba053 | 1841 | |
a2113634 | 1842 | if (local_flush) |
8c8560b8 | 1843 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
1d9dc7e0 XG |
1844 | } |
1845 | ||
e37fa785 XG |
1846 | #ifdef CONFIG_KVM_MMU_AUDIT |
1847 | #include "mmu_audit.c" | |
1848 | #else | |
1849 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { } | |
1850 | static void mmu_audit_disable(void) { } | |
1851 | #endif | |
1852 | ||
002c5f73 SC |
1853 | static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp) |
1854 | { | |
fac026da SC |
1855 | return sp->role.invalid || |
1856 | unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen); | |
002c5f73 SC |
1857 | } |
1858 | ||
1f50f1b3 | 1859 | static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 1860 | struct list_head *invalid_list) |
1d9dc7e0 | 1861 | { |
9a43c5d9 PB |
1862 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1863 | return __kvm_sync_page(vcpu, sp, invalid_list); | |
1d9dc7e0 XG |
1864 | } |
1865 | ||
9f1a122f | 1866 | /* @gfn should be write-protected at the call site */ |
2a74003a PB |
1867 | static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn, |
1868 | struct list_head *invalid_list) | |
9f1a122f | 1869 | { |
9f1a122f | 1870 | struct kvm_mmu_page *s; |
2a74003a | 1871 | bool ret = false; |
9f1a122f | 1872 | |
b67bfe0d | 1873 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
7ae680eb | 1874 | if (!s->unsync) |
9f1a122f XG |
1875 | continue; |
1876 | ||
3bae0459 | 1877 | WARN_ON(s->role.level != PG_LEVEL_4K); |
2a74003a | 1878 | ret |= kvm_sync_page(vcpu, s, invalid_list); |
9f1a122f XG |
1879 | } |
1880 | ||
2a74003a | 1881 | return ret; |
9f1a122f XG |
1882 | } |
1883 | ||
60c8aec6 | 1884 | struct mmu_page_path { |
2a7266a8 YZ |
1885 | struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL]; |
1886 | unsigned int idx[PT64_ROOT_MAX_LEVEL]; | |
4731d4c7 MT |
1887 | }; |
1888 | ||
60c8aec6 | 1889 | #define for_each_sp(pvec, sp, parents, i) \ |
0a47cd85 | 1890 | for (i = mmu_pages_first(&pvec, &parents); \ |
60c8aec6 MT |
1891 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ |
1892 | i = mmu_pages_next(&pvec, &parents, i)) | |
1893 | ||
cded19f3 HE |
1894 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1895 | struct mmu_page_path *parents, | |
1896 | int i) | |
60c8aec6 MT |
1897 | { |
1898 | int n; | |
1899 | ||
1900 | for (n = i+1; n < pvec->nr; n++) { | |
1901 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
0a47cd85 PB |
1902 | unsigned idx = pvec->page[n].idx; |
1903 | int level = sp->role.level; | |
60c8aec6 | 1904 | |
0a47cd85 | 1905 | parents->idx[level-1] = idx; |
3bae0459 | 1906 | if (level == PG_LEVEL_4K) |
0a47cd85 | 1907 | break; |
60c8aec6 | 1908 | |
0a47cd85 | 1909 | parents->parent[level-2] = sp; |
60c8aec6 MT |
1910 | } |
1911 | ||
1912 | return n; | |
1913 | } | |
1914 | ||
0a47cd85 PB |
1915 | static int mmu_pages_first(struct kvm_mmu_pages *pvec, |
1916 | struct mmu_page_path *parents) | |
1917 | { | |
1918 | struct kvm_mmu_page *sp; | |
1919 | int level; | |
1920 | ||
1921 | if (pvec->nr == 0) | |
1922 | return 0; | |
1923 | ||
e23d3fef XG |
1924 | WARN_ON(pvec->page[0].idx != INVALID_INDEX); |
1925 | ||
0a47cd85 PB |
1926 | sp = pvec->page[0].sp; |
1927 | level = sp->role.level; | |
3bae0459 | 1928 | WARN_ON(level == PG_LEVEL_4K); |
0a47cd85 PB |
1929 | |
1930 | parents->parent[level-2] = sp; | |
1931 | ||
1932 | /* Also set up a sentinel. Further entries in pvec are all | |
1933 | * children of sp, so this element is never overwritten. | |
1934 | */ | |
1935 | parents->parent[level-1] = NULL; | |
1936 | return mmu_pages_next(pvec, parents, 0); | |
1937 | } | |
1938 | ||
cded19f3 | 1939 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1940 | { |
60c8aec6 MT |
1941 | struct kvm_mmu_page *sp; |
1942 | unsigned int level = 0; | |
1943 | ||
1944 | do { | |
1945 | unsigned int idx = parents->idx[level]; | |
60c8aec6 MT |
1946 | sp = parents->parent[level]; |
1947 | if (!sp) | |
1948 | return; | |
1949 | ||
e23d3fef | 1950 | WARN_ON(idx == INVALID_INDEX); |
fd951457 | 1951 | clear_unsync_child_bit(sp, idx); |
60c8aec6 | 1952 | level++; |
0a47cd85 | 1953 | } while (!sp->unsync_children); |
60c8aec6 | 1954 | } |
4731d4c7 | 1955 | |
60c8aec6 MT |
1956 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1957 | struct kvm_mmu_page *parent) | |
1958 | { | |
1959 | int i; | |
1960 | struct kvm_mmu_page *sp; | |
1961 | struct mmu_page_path parents; | |
1962 | struct kvm_mmu_pages pages; | |
d98ba053 | 1963 | LIST_HEAD(invalid_list); |
50c9e6f3 | 1964 | bool flush = false; |
60c8aec6 | 1965 | |
60c8aec6 | 1966 | while (mmu_unsync_walk(parent, &pages)) { |
2f84569f | 1967 | bool protected = false; |
b1a36821 MT |
1968 | |
1969 | for_each_sp(pages, sp, parents, i) | |
54bf36aa | 1970 | protected |= rmap_write_protect(vcpu, sp->gfn); |
b1a36821 | 1971 | |
50c9e6f3 | 1972 | if (protected) { |
b1a36821 | 1973 | kvm_flush_remote_tlbs(vcpu->kvm); |
50c9e6f3 PB |
1974 | flush = false; |
1975 | } | |
b1a36821 | 1976 | |
60c8aec6 | 1977 | for_each_sp(pages, sp, parents, i) { |
1f50f1b3 | 1978 | flush |= kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
1979 | mmu_pages_clear_parents(&parents); |
1980 | } | |
531810ca | 1981 | if (need_resched() || rwlock_needbreak(&vcpu->kvm->mmu_lock)) { |
50c9e6f3 | 1982 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); |
531810ca | 1983 | cond_resched_rwlock_write(&vcpu->kvm->mmu_lock); |
50c9e6f3 PB |
1984 | flush = false; |
1985 | } | |
60c8aec6 | 1986 | } |
50c9e6f3 PB |
1987 | |
1988 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
4731d4c7 MT |
1989 | } |
1990 | ||
a30f47cb XG |
1991 | static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp) |
1992 | { | |
e5691a81 | 1993 | atomic_set(&sp->write_flooding_count, 0); |
a30f47cb XG |
1994 | } |
1995 | ||
1996 | static void clear_sp_write_flooding_count(u64 *spte) | |
1997 | { | |
57354682 | 1998 | __clear_sp_write_flooding_count(sptep_to_sp(spte)); |
a30f47cb XG |
1999 | } |
2000 | ||
cea0f0e7 AK |
2001 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
2002 | gfn_t gfn, | |
2003 | gva_t gaddr, | |
2004 | unsigned level, | |
f6e2c02b | 2005 | int direct, |
0a2b64c5 | 2006 | unsigned int access) |
cea0f0e7 | 2007 | { |
fb58a9c3 | 2008 | bool direct_mmu = vcpu->arch.mmu->direct_map; |
cea0f0e7 | 2009 | union kvm_mmu_page_role role; |
ac101b7c | 2010 | struct hlist_head *sp_list; |
cea0f0e7 | 2011 | unsigned quadrant; |
9f1a122f | 2012 | struct kvm_mmu_page *sp; |
9f1a122f | 2013 | bool need_sync = false; |
2a74003a | 2014 | bool flush = false; |
f3414bc7 | 2015 | int collisions = 0; |
2a74003a | 2016 | LIST_HEAD(invalid_list); |
cea0f0e7 | 2017 | |
36d9594d | 2018 | role = vcpu->arch.mmu->mmu_role.base; |
cea0f0e7 | 2019 | role.level = level; |
f6e2c02b | 2020 | role.direct = direct; |
84b0c8c6 | 2021 | if (role.direct) |
47c42e6b | 2022 | role.gpte_is_8_bytes = true; |
41074d07 | 2023 | role.access = access; |
fb58a9c3 | 2024 | if (!direct_mmu && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) { |
cea0f0e7 AK |
2025 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
2026 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
2027 | role.quadrant = quadrant; | |
2028 | } | |
ac101b7c SC |
2029 | |
2030 | sp_list = &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]; | |
2031 | for_each_valid_sp(vcpu->kvm, sp, sp_list) { | |
f3414bc7 DM |
2032 | if (sp->gfn != gfn) { |
2033 | collisions++; | |
2034 | continue; | |
2035 | } | |
2036 | ||
7ae680eb XG |
2037 | if (!need_sync && sp->unsync) |
2038 | need_sync = true; | |
4731d4c7 | 2039 | |
7ae680eb XG |
2040 | if (sp->role.word != role.word) |
2041 | continue; | |
4731d4c7 | 2042 | |
fb58a9c3 SC |
2043 | if (direct_mmu) |
2044 | goto trace_get_page; | |
2045 | ||
2a74003a PB |
2046 | if (sp->unsync) { |
2047 | /* The page is good, but __kvm_sync_page might still end | |
2048 | * up zapping it. If so, break in order to rebuild it. | |
2049 | */ | |
2050 | if (!__kvm_sync_page(vcpu, sp, &invalid_list)) | |
2051 | break; | |
2052 | ||
2053 | WARN_ON(!list_empty(&invalid_list)); | |
8c8560b8 | 2054 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
2a74003a | 2055 | } |
e02aa901 | 2056 | |
98bba238 | 2057 | if (sp->unsync_children) |
f6f6195b | 2058 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
e02aa901 | 2059 | |
a30f47cb | 2060 | __clear_sp_write_flooding_count(sp); |
fb58a9c3 SC |
2061 | |
2062 | trace_get_page: | |
7ae680eb | 2063 | trace_kvm_mmu_get_page(sp, false); |
f3414bc7 | 2064 | goto out; |
7ae680eb | 2065 | } |
47005792 | 2066 | |
dfc5aa00 | 2067 | ++vcpu->kvm->stat.mmu_cache_miss; |
47005792 TY |
2068 | |
2069 | sp = kvm_mmu_alloc_page(vcpu, direct); | |
2070 | ||
4db35314 AK |
2071 | sp->gfn = gfn; |
2072 | sp->role = role; | |
ac101b7c | 2073 | hlist_add_head(&sp->hash_link, sp_list); |
f6e2c02b | 2074 | if (!direct) { |
56ca57f9 XG |
2075 | /* |
2076 | * we should do write protection before syncing pages | |
2077 | * otherwise the content of the synced shadow page may | |
2078 | * be inconsistent with guest page table. | |
2079 | */ | |
2080 | account_shadowed(vcpu->kvm, sp); | |
3bae0459 | 2081 | if (level == PG_LEVEL_4K && rmap_write_protect(vcpu, gfn)) |
c3134ce2 | 2082 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1); |
9f1a122f | 2083 | |
3bae0459 | 2084 | if (level > PG_LEVEL_4K && need_sync) |
2a74003a | 2085 | flush |= kvm_sync_pages(vcpu, gfn, &invalid_list); |
4731d4c7 | 2086 | } |
f691fe1d | 2087 | trace_kvm_mmu_get_page(sp, true); |
2a74003a PB |
2088 | |
2089 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
f3414bc7 DM |
2090 | out: |
2091 | if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions) | |
2092 | vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions; | |
4db35314 | 2093 | return sp; |
cea0f0e7 AK |
2094 | } |
2095 | ||
7eb77e9f JS |
2096 | static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator, |
2097 | struct kvm_vcpu *vcpu, hpa_t root, | |
2098 | u64 addr) | |
2d11123a AK |
2099 | { |
2100 | iterator->addr = addr; | |
7eb77e9f | 2101 | iterator->shadow_addr = root; |
44dd3ffa | 2102 | iterator->level = vcpu->arch.mmu->shadow_root_level; |
81407ca5 | 2103 | |
2a7266a8 | 2104 | if (iterator->level == PT64_ROOT_4LEVEL && |
44dd3ffa VK |
2105 | vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL && |
2106 | !vcpu->arch.mmu->direct_map) | |
81407ca5 JR |
2107 | --iterator->level; |
2108 | ||
2d11123a | 2109 | if (iterator->level == PT32E_ROOT_LEVEL) { |
7eb77e9f JS |
2110 | /* |
2111 | * prev_root is currently only used for 64-bit hosts. So only | |
2112 | * the active root_hpa is valid here. | |
2113 | */ | |
44dd3ffa | 2114 | BUG_ON(root != vcpu->arch.mmu->root_hpa); |
7eb77e9f | 2115 | |
2d11123a | 2116 | iterator->shadow_addr |
44dd3ffa | 2117 | = vcpu->arch.mmu->pae_root[(addr >> 30) & 3]; |
2d11123a AK |
2118 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; |
2119 | --iterator->level; | |
2120 | if (!iterator->shadow_addr) | |
2121 | iterator->level = 0; | |
2122 | } | |
2123 | } | |
2124 | ||
7eb77e9f JS |
2125 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
2126 | struct kvm_vcpu *vcpu, u64 addr) | |
2127 | { | |
44dd3ffa | 2128 | shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa, |
7eb77e9f JS |
2129 | addr); |
2130 | } | |
2131 | ||
2d11123a AK |
2132 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) |
2133 | { | |
3bae0459 | 2134 | if (iterator->level < PG_LEVEL_4K) |
2d11123a | 2135 | return false; |
4d88954d | 2136 | |
2d11123a AK |
2137 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
2138 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
2139 | return true; | |
2140 | } | |
2141 | ||
c2a2ac2b XG |
2142 | static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator, |
2143 | u64 spte) | |
2d11123a | 2144 | { |
c2a2ac2b | 2145 | if (is_last_spte(spte, iterator->level)) { |
052331be XG |
2146 | iterator->level = 0; |
2147 | return; | |
2148 | } | |
2149 | ||
c2a2ac2b | 2150 | iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK; |
2d11123a AK |
2151 | --iterator->level; |
2152 | } | |
2153 | ||
c2a2ac2b XG |
2154 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) |
2155 | { | |
bb606a9b | 2156 | __shadow_walk_next(iterator, *iterator->sptep); |
c2a2ac2b XG |
2157 | } |
2158 | ||
cc4674d0 BG |
2159 | static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep, |
2160 | struct kvm_mmu_page *sp) | |
2161 | { | |
2162 | u64 spte; | |
2163 | ||
2164 | BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK); | |
2165 | ||
2166 | spte = make_nonleaf_spte(sp->spt, sp_ad_disabled(sp)); | |
2167 | ||
1df9f2dc | 2168 | mmu_spte_set(sptep, spte); |
98bba238 TY |
2169 | |
2170 | mmu_page_add_parent_pte(vcpu, sp, sptep); | |
2171 | ||
2172 | if (sp->unsync_children || sp->unsync) | |
2173 | mark_unsync(sptep); | |
32ef26a3 AK |
2174 | } |
2175 | ||
a357bd22 AK |
2176 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
2177 | unsigned direct_access) | |
2178 | { | |
2179 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
2180 | struct kvm_mmu_page *child; | |
2181 | ||
2182 | /* | |
2183 | * For the direct sp, if the guest pte's dirty bit | |
2184 | * changed form clean to dirty, it will corrupt the | |
2185 | * sp's access: allow writable in the read-only sp, | |
2186 | * so we should update the spte at this point to get | |
2187 | * a new sp with the correct access. | |
2188 | */ | |
e47c4aee | 2189 | child = to_shadow_page(*sptep & PT64_BASE_ADDR_MASK); |
a357bd22 AK |
2190 | if (child->role.access == direct_access) |
2191 | return; | |
2192 | ||
bcdd9a93 | 2193 | drop_parent_pte(child, sptep); |
c3134ce2 | 2194 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1); |
a357bd22 AK |
2195 | } |
2196 | } | |
2197 | ||
2de4085c BG |
2198 | /* Returns the number of zapped non-leaf child shadow pages. */ |
2199 | static int mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, | |
2200 | u64 *spte, struct list_head *invalid_list) | |
38e3b2b2 XG |
2201 | { |
2202 | u64 pte; | |
2203 | struct kvm_mmu_page *child; | |
2204 | ||
2205 | pte = *spte; | |
2206 | if (is_shadow_present_pte(pte)) { | |
505aef8f | 2207 | if (is_last_spte(pte, sp->role.level)) { |
c3707958 | 2208 | drop_spte(kvm, spte); |
505aef8f XG |
2209 | if (is_large_pte(pte)) |
2210 | --kvm->stat.lpages; | |
2211 | } else { | |
e47c4aee | 2212 | child = to_shadow_page(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2213 | drop_parent_pte(child, spte); |
2de4085c BG |
2214 | |
2215 | /* | |
2216 | * Recursively zap nested TDP SPs, parentless SPs are | |
2217 | * unlikely to be used again in the near future. This | |
2218 | * avoids retaining a large number of stale nested SPs. | |
2219 | */ | |
2220 | if (tdp_enabled && invalid_list && | |
2221 | child->role.guest_mode && !child->parent_ptes.val) | |
2222 | return kvm_mmu_prepare_zap_page(kvm, child, | |
2223 | invalid_list); | |
38e3b2b2 | 2224 | } |
ace569e0 | 2225 | } else if (is_mmio_spte(pte)) { |
ce88decf | 2226 | mmu_spte_clear_no_track(spte); |
ace569e0 | 2227 | } |
2de4085c | 2228 | return 0; |
38e3b2b2 XG |
2229 | } |
2230 | ||
2de4085c BG |
2231 | static int kvm_mmu_page_unlink_children(struct kvm *kvm, |
2232 | struct kvm_mmu_page *sp, | |
2233 | struct list_head *invalid_list) | |
a436036b | 2234 | { |
2de4085c | 2235 | int zapped = 0; |
697fe2e2 | 2236 | unsigned i; |
697fe2e2 | 2237 | |
38e3b2b2 | 2238 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
2de4085c BG |
2239 | zapped += mmu_page_zap_pte(kvm, sp, sp->spt + i, invalid_list); |
2240 | ||
2241 | return zapped; | |
a436036b AK |
2242 | } |
2243 | ||
31aa2b44 | 2244 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b | 2245 | { |
1e3f42f0 TY |
2246 | u64 *sptep; |
2247 | struct rmap_iterator iter; | |
a436036b | 2248 | |
018aabb5 | 2249 | while ((sptep = rmap_get_first(&sp->parent_ptes, &iter))) |
1e3f42f0 | 2250 | drop_parent_pte(sp, sptep); |
31aa2b44 AK |
2251 | } |
2252 | ||
60c8aec6 | 2253 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
2254 | struct kvm_mmu_page *parent, |
2255 | struct list_head *invalid_list) | |
4731d4c7 | 2256 | { |
60c8aec6 MT |
2257 | int i, zapped = 0; |
2258 | struct mmu_page_path parents; | |
2259 | struct kvm_mmu_pages pages; | |
4731d4c7 | 2260 | |
3bae0459 | 2261 | if (parent->role.level == PG_LEVEL_4K) |
4731d4c7 | 2262 | return 0; |
60c8aec6 | 2263 | |
60c8aec6 MT |
2264 | while (mmu_unsync_walk(parent, &pages)) { |
2265 | struct kvm_mmu_page *sp; | |
2266 | ||
2267 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 2268 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 2269 | mmu_pages_clear_parents(&parents); |
77662e00 | 2270 | zapped++; |
60c8aec6 | 2271 | } |
60c8aec6 MT |
2272 | } |
2273 | ||
2274 | return zapped; | |
4731d4c7 MT |
2275 | } |
2276 | ||
83cdb568 SC |
2277 | static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm, |
2278 | struct kvm_mmu_page *sp, | |
2279 | struct list_head *invalid_list, | |
2280 | int *nr_zapped) | |
31aa2b44 | 2281 | { |
83cdb568 | 2282 | bool list_unstable; |
f691fe1d | 2283 | |
7775834a | 2284 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 2285 | ++kvm->stat.mmu_shadow_zapped; |
83cdb568 | 2286 | *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list); |
2de4085c | 2287 | *nr_zapped += kvm_mmu_page_unlink_children(kvm, sp, invalid_list); |
31aa2b44 | 2288 | kvm_mmu_unlink_parents(kvm, sp); |
5304b8d3 | 2289 | |
83cdb568 SC |
2290 | /* Zapping children means active_mmu_pages has become unstable. */ |
2291 | list_unstable = *nr_zapped; | |
2292 | ||
f6e2c02b | 2293 | if (!sp->role.invalid && !sp->role.direct) |
3ed1a478 | 2294 | unaccount_shadowed(kvm, sp); |
5304b8d3 | 2295 | |
4731d4c7 MT |
2296 | if (sp->unsync) |
2297 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 2298 | if (!sp->root_count) { |
54a4f023 | 2299 | /* Count self */ |
83cdb568 | 2300 | (*nr_zapped)++; |
f95eec9b SC |
2301 | |
2302 | /* | |
2303 | * Already invalid pages (previously active roots) are not on | |
2304 | * the active page list. See list_del() in the "else" case of | |
2305 | * !sp->root_count. | |
2306 | */ | |
2307 | if (sp->role.invalid) | |
2308 | list_add(&sp->link, invalid_list); | |
2309 | else | |
2310 | list_move(&sp->link, invalid_list); | |
aa6bd187 | 2311 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 2312 | } else { |
f95eec9b SC |
2313 | /* |
2314 | * Remove the active root from the active page list, the root | |
2315 | * will be explicitly freed when the root_count hits zero. | |
2316 | */ | |
2317 | list_del(&sp->link); | |
05988d72 | 2318 | |
10605204 SC |
2319 | /* |
2320 | * Obsolete pages cannot be used on any vCPUs, see the comment | |
2321 | * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also | |
2322 | * treats invalid shadow pages as being obsolete. | |
2323 | */ | |
2324 | if (!is_obsolete_sp(kvm, sp)) | |
05988d72 | 2325 | kvm_reload_remote_mmus(kvm); |
2e53d63a | 2326 | } |
7775834a | 2327 | |
b8e8c830 PB |
2328 | if (sp->lpage_disallowed) |
2329 | unaccount_huge_nx_page(kvm, sp); | |
2330 | ||
7775834a | 2331 | sp->role.invalid = 1; |
83cdb568 SC |
2332 | return list_unstable; |
2333 | } | |
2334 | ||
2335 | static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, | |
2336 | struct list_head *invalid_list) | |
2337 | { | |
2338 | int nr_zapped; | |
2339 | ||
2340 | __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped); | |
2341 | return nr_zapped; | |
a436036b AK |
2342 | } |
2343 | ||
7775834a XG |
2344 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
2345 | struct list_head *invalid_list) | |
2346 | { | |
945315b9 | 2347 | struct kvm_mmu_page *sp, *nsp; |
7775834a XG |
2348 | |
2349 | if (list_empty(invalid_list)) | |
2350 | return; | |
2351 | ||
c142786c | 2352 | /* |
9753f529 LT |
2353 | * We need to make sure everyone sees our modifications to |
2354 | * the page tables and see changes to vcpu->mode here. The barrier | |
2355 | * in the kvm_flush_remote_tlbs() achieves this. This pairs | |
2356 | * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end. | |
2357 | * | |
2358 | * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit | |
2359 | * guest mode and/or lockless shadow page table walks. | |
c142786c AK |
2360 | */ |
2361 | kvm_flush_remote_tlbs(kvm); | |
c2a2ac2b | 2362 | |
945315b9 | 2363 | list_for_each_entry_safe(sp, nsp, invalid_list, link) { |
7775834a | 2364 | WARN_ON(!sp->role.invalid || sp->root_count); |
aa6bd187 | 2365 | kvm_mmu_free_page(sp); |
945315b9 | 2366 | } |
7775834a XG |
2367 | } |
2368 | ||
6b82ef2c SC |
2369 | static unsigned long kvm_mmu_zap_oldest_mmu_pages(struct kvm *kvm, |
2370 | unsigned long nr_to_zap) | |
5da59607 | 2371 | { |
6b82ef2c SC |
2372 | unsigned long total_zapped = 0; |
2373 | struct kvm_mmu_page *sp, *tmp; | |
ba7888dd | 2374 | LIST_HEAD(invalid_list); |
6b82ef2c SC |
2375 | bool unstable; |
2376 | int nr_zapped; | |
5da59607 TY |
2377 | |
2378 | if (list_empty(&kvm->arch.active_mmu_pages)) | |
ba7888dd SC |
2379 | return 0; |
2380 | ||
6b82ef2c | 2381 | restart: |
8fc51726 | 2382 | list_for_each_entry_safe_reverse(sp, tmp, &kvm->arch.active_mmu_pages, link) { |
6b82ef2c SC |
2383 | /* |
2384 | * Don't zap active root pages, the page itself can't be freed | |
2385 | * and zapping it will just force vCPUs to realloc and reload. | |
2386 | */ | |
2387 | if (sp->root_count) | |
2388 | continue; | |
2389 | ||
2390 | unstable = __kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, | |
2391 | &nr_zapped); | |
2392 | total_zapped += nr_zapped; | |
2393 | if (total_zapped >= nr_to_zap) | |
ba7888dd SC |
2394 | break; |
2395 | ||
6b82ef2c SC |
2396 | if (unstable) |
2397 | goto restart; | |
ba7888dd | 2398 | } |
5da59607 | 2399 | |
6b82ef2c SC |
2400 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
2401 | ||
2402 | kvm->stat.mmu_recycled += total_zapped; | |
2403 | return total_zapped; | |
2404 | } | |
2405 | ||
afe8d7e6 SC |
2406 | static inline unsigned long kvm_mmu_available_pages(struct kvm *kvm) |
2407 | { | |
2408 | if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages) | |
2409 | return kvm->arch.n_max_mmu_pages - | |
2410 | kvm->arch.n_used_mmu_pages; | |
2411 | ||
2412 | return 0; | |
5da59607 TY |
2413 | } |
2414 | ||
ba7888dd SC |
2415 | static int make_mmu_pages_available(struct kvm_vcpu *vcpu) |
2416 | { | |
6b82ef2c | 2417 | unsigned long avail = kvm_mmu_available_pages(vcpu->kvm); |
ba7888dd | 2418 | |
6b82ef2c | 2419 | if (likely(avail >= KVM_MIN_FREE_MMU_PAGES)) |
ba7888dd SC |
2420 | return 0; |
2421 | ||
6b82ef2c | 2422 | kvm_mmu_zap_oldest_mmu_pages(vcpu->kvm, KVM_REFILL_PAGES - avail); |
ba7888dd | 2423 | |
6e6ec584 SC |
2424 | /* |
2425 | * Note, this check is intentionally soft, it only guarantees that one | |
2426 | * page is available, while the caller may end up allocating as many as | |
2427 | * four pages, e.g. for PAE roots or for 5-level paging. Temporarily | |
2428 | * exceeding the (arbitrary by default) limit will not harm the host, | |
2429 | * being too agressive may unnecessarily kill the guest, and getting an | |
2430 | * exact count is far more trouble than it's worth, especially in the | |
2431 | * page fault paths. | |
2432 | */ | |
ba7888dd SC |
2433 | if (!kvm_mmu_available_pages(vcpu->kvm)) |
2434 | return -ENOSPC; | |
2435 | return 0; | |
2436 | } | |
2437 | ||
82ce2c96 IE |
2438 | /* |
2439 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 2440 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 2441 | */ |
bc8a3d89 | 2442 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages) |
82ce2c96 | 2443 | { |
531810ca | 2444 | write_lock(&kvm->mmu_lock); |
b34cb590 | 2445 | |
49d5ca26 | 2446 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
6b82ef2c SC |
2447 | kvm_mmu_zap_oldest_mmu_pages(kvm, kvm->arch.n_used_mmu_pages - |
2448 | goal_nr_mmu_pages); | |
82ce2c96 | 2449 | |
49d5ca26 | 2450 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 2451 | } |
82ce2c96 | 2452 | |
49d5ca26 | 2453 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
b34cb590 | 2454 | |
531810ca | 2455 | write_unlock(&kvm->mmu_lock); |
82ce2c96 IE |
2456 | } |
2457 | ||
1cb3f3ae | 2458 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 2459 | { |
4db35314 | 2460 | struct kvm_mmu_page *sp; |
d98ba053 | 2461 | LIST_HEAD(invalid_list); |
a436036b AK |
2462 | int r; |
2463 | ||
9ad17b10 | 2464 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 2465 | r = 0; |
531810ca | 2466 | write_lock(&kvm->mmu_lock); |
b67bfe0d | 2467 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn) { |
9ad17b10 | 2468 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
2469 | sp->role.word); |
2470 | r = 1; | |
f41d335a | 2471 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 2472 | } |
d98ba053 | 2473 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
531810ca | 2474 | write_unlock(&kvm->mmu_lock); |
1cb3f3ae | 2475 | |
a436036b | 2476 | return r; |
cea0f0e7 | 2477 | } |
96ad91ae SC |
2478 | |
2479 | static int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) | |
2480 | { | |
2481 | gpa_t gpa; | |
2482 | int r; | |
2483 | ||
2484 | if (vcpu->arch.mmu->direct_map) | |
2485 | return 0; | |
2486 | ||
2487 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); | |
2488 | ||
2489 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); | |
2490 | ||
2491 | return r; | |
2492 | } | |
cea0f0e7 | 2493 | |
5c520e90 | 2494 | static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
9cf5cf5a XG |
2495 | { |
2496 | trace_kvm_mmu_unsync_page(sp); | |
2497 | ++vcpu->kvm->stat.mmu_unsync; | |
2498 | sp->unsync = 1; | |
2499 | ||
2500 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
2501 | } |
2502 | ||
5a9624af PB |
2503 | bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, |
2504 | bool can_unsync) | |
4731d4c7 | 2505 | { |
5c520e90 | 2506 | struct kvm_mmu_page *sp; |
4731d4c7 | 2507 | |
3d0c27ad XG |
2508 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) |
2509 | return true; | |
9cf5cf5a | 2510 | |
5c520e90 | 2511 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
36a2e677 | 2512 | if (!can_unsync) |
3d0c27ad | 2513 | return true; |
36a2e677 | 2514 | |
5c520e90 XG |
2515 | if (sp->unsync) |
2516 | continue; | |
9cf5cf5a | 2517 | |
3bae0459 | 2518 | WARN_ON(sp->role.level != PG_LEVEL_4K); |
5c520e90 | 2519 | kvm_unsync_page(vcpu, sp); |
4731d4c7 | 2520 | } |
3d0c27ad | 2521 | |
578e1c4d JS |
2522 | /* |
2523 | * We need to ensure that the marking of unsync pages is visible | |
2524 | * before the SPTE is updated to allow writes because | |
2525 | * kvm_mmu_sync_roots() checks the unsync flags without holding | |
2526 | * the MMU lock and so can race with this. If the SPTE was updated | |
2527 | * before the page had been marked as unsync-ed, something like the | |
2528 | * following could happen: | |
2529 | * | |
2530 | * CPU 1 CPU 2 | |
2531 | * --------------------------------------------------------------------- | |
2532 | * 1.2 Host updates SPTE | |
2533 | * to be writable | |
2534 | * 2.1 Guest writes a GPTE for GVA X. | |
2535 | * (GPTE being in the guest page table shadowed | |
2536 | * by the SP from CPU 1.) | |
2537 | * This reads SPTE during the page table walk. | |
2538 | * Since SPTE.W is read as 1, there is no | |
2539 | * fault. | |
2540 | * | |
2541 | * 2.2 Guest issues TLB flush. | |
2542 | * That causes a VM Exit. | |
2543 | * | |
2544 | * 2.3 kvm_mmu_sync_pages() reads sp->unsync. | |
2545 | * Since it is false, so it just returns. | |
2546 | * | |
2547 | * 2.4 Guest accesses GVA X. | |
2548 | * Since the mapping in the SP was not updated, | |
2549 | * so the old mapping for GVA X incorrectly | |
2550 | * gets used. | |
2551 | * 1.1 Host marks SP | |
2552 | * as unsync | |
2553 | * (sp->unsync = true) | |
2554 | * | |
2555 | * The write barrier below ensures that 1.1 happens before 1.2 and thus | |
2556 | * the situation in 2.4 does not arise. The implicit barrier in 2.2 | |
2557 | * pairs with this write barrier. | |
2558 | */ | |
2559 | smp_wmb(); | |
2560 | ||
3d0c27ad | 2561 | return false; |
4731d4c7 MT |
2562 | } |
2563 | ||
799a4190 BG |
2564 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
2565 | unsigned int pte_access, int level, | |
2566 | gfn_t gfn, kvm_pfn_t pfn, bool speculative, | |
2567 | bool can_unsync, bool host_writable) | |
2568 | { | |
2569 | u64 spte; | |
2570 | struct kvm_mmu_page *sp; | |
2571 | int ret; | |
2572 | ||
2573 | if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access)) | |
2574 | return 0; | |
2575 | ||
2576 | sp = sptep_to_sp(sptep); | |
2577 | ||
2578 | ret = make_spte(vcpu, pte_access, level, gfn, pfn, *sptep, speculative, | |
2579 | can_unsync, host_writable, sp_ad_disabled(sp), &spte); | |
2580 | ||
2581 | if (spte & PT_WRITABLE_MASK) | |
2582 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
2583 | ||
12703759 SC |
2584 | if (*sptep == spte) |
2585 | ret |= SET_SPTE_SPURIOUS; | |
2586 | else if (mmu_spte_update(sptep, spte)) | |
5ce4786f | 2587 | ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH; |
1e73f9dd MT |
2588 | return ret; |
2589 | } | |
2590 | ||
0a2b64c5 | 2591 | static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
e88b8093 | 2592 | unsigned int pte_access, bool write_fault, int level, |
0a2b64c5 BG |
2593 | gfn_t gfn, kvm_pfn_t pfn, bool speculative, |
2594 | bool host_writable) | |
1e73f9dd MT |
2595 | { |
2596 | int was_rmapped = 0; | |
53a27b39 | 2597 | int rmap_count; |
5ce4786f | 2598 | int set_spte_ret; |
c4371c2a | 2599 | int ret = RET_PF_FIXED; |
c2a4eadf | 2600 | bool flush = false; |
1e73f9dd | 2601 | |
f7616203 XG |
2602 | pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__, |
2603 | *sptep, write_fault, gfn); | |
1e73f9dd | 2604 | |
afd28fe1 | 2605 | if (is_shadow_present_pte(*sptep)) { |
1e73f9dd MT |
2606 | /* |
2607 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2608 | * the parent of the now unreachable PTE. | |
2609 | */ | |
3bae0459 | 2610 | if (level > PG_LEVEL_4K && !is_large_pte(*sptep)) { |
1e73f9dd | 2611 | struct kvm_mmu_page *child; |
d555c333 | 2612 | u64 pte = *sptep; |
1e73f9dd | 2613 | |
e47c4aee | 2614 | child = to_shadow_page(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2615 | drop_parent_pte(child, sptep); |
c2a4eadf | 2616 | flush = true; |
d555c333 | 2617 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2618 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2619 | spte_to_pfn(*sptep), pfn); |
c3707958 | 2620 | drop_spte(vcpu->kvm, sptep); |
c2a4eadf | 2621 | flush = true; |
6bed6b9e JR |
2622 | } else |
2623 | was_rmapped = 1; | |
1e73f9dd | 2624 | } |
852e3c19 | 2625 | |
5ce4786f JS |
2626 | set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn, |
2627 | speculative, true, host_writable); | |
2628 | if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) { | |
1e73f9dd | 2629 | if (write_fault) |
9b8ebbdb | 2630 | ret = RET_PF_EMULATE; |
8c8560b8 | 2631 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
a378b4e6 | 2632 | } |
c3134ce2 | 2633 | |
c2a4eadf | 2634 | if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush) |
c3134ce2 LT |
2635 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, |
2636 | KVM_PAGES_PER_HPAGE(level)); | |
1e73f9dd | 2637 | |
029499b4 | 2638 | if (unlikely(is_mmio_spte(*sptep))) |
9b8ebbdb | 2639 | ret = RET_PF_EMULATE; |
ce88decf | 2640 | |
12703759 SC |
2641 | /* |
2642 | * The fault is fully spurious if and only if the new SPTE and old SPTE | |
2643 | * are identical, and emulation is not required. | |
2644 | */ | |
2645 | if ((set_spte_ret & SET_SPTE_SPURIOUS) && ret == RET_PF_FIXED) { | |
2646 | WARN_ON_ONCE(!was_rmapped); | |
2647 | return RET_PF_SPURIOUS; | |
2648 | } | |
2649 | ||
d555c333 | 2650 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
335e192a | 2651 | trace_kvm_mmu_set_spte(level, gfn, sptep); |
d555c333 | 2652 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2653 | ++vcpu->kvm->stat.lpages; |
2654 | ||
ffb61bb3 | 2655 | if (is_shadow_present_pte(*sptep)) { |
ffb61bb3 XG |
2656 | if (!was_rmapped) { |
2657 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
2658 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
2659 | rmap_recycle(vcpu, sptep, gfn); | |
2660 | } | |
1c4f1fd6 | 2661 | } |
cb9aaa30 | 2662 | |
9b8ebbdb | 2663 | return ret; |
1c4f1fd6 AK |
2664 | } |
2665 | ||
ba049e93 | 2666 | static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
957ed9ef XG |
2667 | bool no_dirty_log) |
2668 | { | |
2669 | struct kvm_memory_slot *slot; | |
957ed9ef | 2670 | |
5d163b1c | 2671 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
903816fa | 2672 | if (!slot) |
6c8ee57b | 2673 | return KVM_PFN_ERR_FAULT; |
957ed9ef | 2674 | |
037d92dc | 2675 | return gfn_to_pfn_memslot_atomic(slot, gfn); |
957ed9ef XG |
2676 | } |
2677 | ||
2678 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
2679 | struct kvm_mmu_page *sp, | |
2680 | u64 *start, u64 *end) | |
2681 | { | |
2682 | struct page *pages[PTE_PREFETCH_NUM]; | |
d9ef13c2 | 2683 | struct kvm_memory_slot *slot; |
0a2b64c5 | 2684 | unsigned int access = sp->role.access; |
957ed9ef XG |
2685 | int i, ret; |
2686 | gfn_t gfn; | |
2687 | ||
2688 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
d9ef13c2 PB |
2689 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK); |
2690 | if (!slot) | |
957ed9ef XG |
2691 | return -1; |
2692 | ||
d9ef13c2 | 2693 | ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start); |
957ed9ef XG |
2694 | if (ret <= 0) |
2695 | return -1; | |
2696 | ||
43fdcda9 | 2697 | for (i = 0; i < ret; i++, gfn++, start++) { |
e88b8093 | 2698 | mmu_set_spte(vcpu, start, access, false, sp->role.level, gfn, |
029499b4 | 2699 | page_to_pfn(pages[i]), true, true); |
43fdcda9 JS |
2700 | put_page(pages[i]); |
2701 | } | |
957ed9ef XG |
2702 | |
2703 | return 0; | |
2704 | } | |
2705 | ||
2706 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2707 | struct kvm_mmu_page *sp, u64 *sptep) | |
2708 | { | |
2709 | u64 *spte, *start = NULL; | |
2710 | int i; | |
2711 | ||
2712 | WARN_ON(!sp->role.direct); | |
2713 | ||
2714 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2715 | spte = sp->spt + i; | |
2716 | ||
2717 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 2718 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
2719 | if (!start) |
2720 | continue; | |
2721 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2722 | break; | |
2723 | start = NULL; | |
2724 | } else if (!start) | |
2725 | start = spte; | |
2726 | } | |
2727 | } | |
2728 | ||
2729 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2730 | { | |
2731 | struct kvm_mmu_page *sp; | |
2732 | ||
57354682 | 2733 | sp = sptep_to_sp(sptep); |
ac8d57e5 | 2734 | |
957ed9ef | 2735 | /* |
ac8d57e5 PF |
2736 | * Without accessed bits, there's no way to distinguish between |
2737 | * actually accessed translations and prefetched, so disable pte | |
2738 | * prefetch if accessed bits aren't available. | |
957ed9ef | 2739 | */ |
ac8d57e5 | 2740 | if (sp_ad_disabled(sp)) |
957ed9ef XG |
2741 | return; |
2742 | ||
3bae0459 | 2743 | if (sp->role.level > PG_LEVEL_4K) |
957ed9ef XG |
2744 | return; |
2745 | ||
4a42d848 DS |
2746 | /* |
2747 | * If addresses are being invalidated, skip prefetching to avoid | |
2748 | * accidentally prefetching those addresses. | |
2749 | */ | |
2750 | if (unlikely(vcpu->kvm->mmu_notifier_count)) | |
2751 | return; | |
2752 | ||
957ed9ef XG |
2753 | __direct_pte_prefetch(vcpu, sp, sptep); |
2754 | } | |
2755 | ||
1b6d9d9e SC |
2756 | static int host_pfn_mapping_level(struct kvm *kvm, gfn_t gfn, kvm_pfn_t pfn, |
2757 | struct kvm_memory_slot *slot) | |
db543216 | 2758 | { |
db543216 SC |
2759 | unsigned long hva; |
2760 | pte_t *pte; | |
2761 | int level; | |
2762 | ||
e851265a | 2763 | if (!PageCompound(pfn_to_page(pfn)) && !kvm_is_zone_device_pfn(pfn)) |
3bae0459 | 2764 | return PG_LEVEL_4K; |
db543216 | 2765 | |
293e306e SC |
2766 | /* |
2767 | * Note, using the already-retrieved memslot and __gfn_to_hva_memslot() | |
2768 | * is not solely for performance, it's also necessary to avoid the | |
2769 | * "writable" check in __gfn_to_hva_many(), which will always fail on | |
2770 | * read-only memslots due to gfn_to_hva() assuming writes. Earlier | |
2771 | * page fault steps have already verified the guest isn't writing a | |
2772 | * read-only memslot. | |
2773 | */ | |
db543216 SC |
2774 | hva = __gfn_to_hva_memslot(slot, gfn); |
2775 | ||
1b6d9d9e | 2776 | pte = lookup_address_in_mm(kvm->mm, hva, &level); |
db543216 | 2777 | if (unlikely(!pte)) |
3bae0459 | 2778 | return PG_LEVEL_4K; |
db543216 SC |
2779 | |
2780 | return level; | |
2781 | } | |
2782 | ||
1b6d9d9e SC |
2783 | int kvm_mmu_max_mapping_level(struct kvm *kvm, struct kvm_memory_slot *slot, |
2784 | gfn_t gfn, kvm_pfn_t pfn, int max_level) | |
2785 | { | |
2786 | struct kvm_lpage_info *linfo; | |
2787 | ||
2788 | max_level = min(max_level, max_huge_page_level); | |
2789 | for ( ; max_level > PG_LEVEL_4K; max_level--) { | |
2790 | linfo = lpage_info_slot(gfn, slot, max_level); | |
2791 | if (!linfo->disallow_lpage) | |
2792 | break; | |
2793 | } | |
2794 | ||
2795 | if (max_level == PG_LEVEL_4K) | |
2796 | return PG_LEVEL_4K; | |
2797 | ||
2798 | return host_pfn_mapping_level(kvm, gfn, pfn, slot); | |
2799 | } | |
2800 | ||
bb18842e BG |
2801 | int kvm_mmu_hugepage_adjust(struct kvm_vcpu *vcpu, gfn_t gfn, |
2802 | int max_level, kvm_pfn_t *pfnp, | |
2803 | bool huge_page_disallowed, int *req_level) | |
0885904d | 2804 | { |
293e306e | 2805 | struct kvm_memory_slot *slot; |
0885904d | 2806 | kvm_pfn_t pfn = *pfnp; |
17eff019 | 2807 | kvm_pfn_t mask; |
83f06fa7 | 2808 | int level; |
17eff019 | 2809 | |
3cf06612 SC |
2810 | *req_level = PG_LEVEL_4K; |
2811 | ||
3bae0459 SC |
2812 | if (unlikely(max_level == PG_LEVEL_4K)) |
2813 | return PG_LEVEL_4K; | |
17eff019 | 2814 | |
e851265a | 2815 | if (is_error_noslot_pfn(pfn) || kvm_is_reserved_pfn(pfn)) |
3bae0459 | 2816 | return PG_LEVEL_4K; |
17eff019 | 2817 | |
293e306e SC |
2818 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, true); |
2819 | if (!slot) | |
3bae0459 | 2820 | return PG_LEVEL_4K; |
293e306e | 2821 | |
1b6d9d9e | 2822 | level = kvm_mmu_max_mapping_level(vcpu->kvm, slot, gfn, pfn, max_level); |
3bae0459 | 2823 | if (level == PG_LEVEL_4K) |
83f06fa7 | 2824 | return level; |
17eff019 | 2825 | |
3cf06612 SC |
2826 | *req_level = level = min(level, max_level); |
2827 | ||
2828 | /* | |
2829 | * Enforce the iTLB multihit workaround after capturing the requested | |
2830 | * level, which will be used to do precise, accurate accounting. | |
2831 | */ | |
2832 | if (huge_page_disallowed) | |
2833 | return PG_LEVEL_4K; | |
0885904d SC |
2834 | |
2835 | /* | |
17eff019 SC |
2836 | * mmu_notifier_retry() was successful and mmu_lock is held, so |
2837 | * the pmd can't be split from under us. | |
0885904d | 2838 | */ |
17eff019 SC |
2839 | mask = KVM_PAGES_PER_HPAGE(level) - 1; |
2840 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
2841 | *pfnp = pfn & ~mask; | |
83f06fa7 SC |
2842 | |
2843 | return level; | |
0885904d SC |
2844 | } |
2845 | ||
bb18842e BG |
2846 | void disallowed_hugepage_adjust(u64 spte, gfn_t gfn, int cur_level, |
2847 | kvm_pfn_t *pfnp, int *goal_levelp) | |
b8e8c830 | 2848 | { |
bb18842e | 2849 | int level = *goal_levelp; |
b8e8c830 | 2850 | |
7d945312 | 2851 | if (cur_level == level && level > PG_LEVEL_4K && |
b8e8c830 PB |
2852 | is_shadow_present_pte(spte) && |
2853 | !is_large_pte(spte)) { | |
2854 | /* | |
2855 | * A small SPTE exists for this pfn, but FNAME(fetch) | |
2856 | * and __direct_map would like to create a large PTE | |
2857 | * instead: just force them to go down another level, | |
2858 | * patching back for them into pfn the next 9 bits of | |
2859 | * the address. | |
2860 | */ | |
7d945312 BG |
2861 | u64 page_mask = KVM_PAGES_PER_HPAGE(level) - |
2862 | KVM_PAGES_PER_HPAGE(level - 1); | |
b8e8c830 | 2863 | *pfnp |= gfn & page_mask; |
bb18842e | 2864 | (*goal_levelp)--; |
b8e8c830 PB |
2865 | } |
2866 | } | |
2867 | ||
6c2fd34f | 2868 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, |
83f06fa7 | 2869 | int map_writable, int max_level, kvm_pfn_t pfn, |
6c2fd34f | 2870 | bool prefault, bool is_tdp) |
140754bc | 2871 | { |
6c2fd34f SC |
2872 | bool nx_huge_page_workaround_enabled = is_nx_huge_page_enabled(); |
2873 | bool write = error_code & PFERR_WRITE_MASK; | |
2874 | bool exec = error_code & PFERR_FETCH_MASK; | |
2875 | bool huge_page_disallowed = exec && nx_huge_page_workaround_enabled; | |
3fcf2d1b | 2876 | struct kvm_shadow_walk_iterator it; |
140754bc | 2877 | struct kvm_mmu_page *sp; |
3cf06612 | 2878 | int level, req_level, ret; |
3fcf2d1b PB |
2879 | gfn_t gfn = gpa >> PAGE_SHIFT; |
2880 | gfn_t base_gfn = gfn; | |
6aa8b732 | 2881 | |
0c7a98e3 | 2882 | if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa))) |
3fcf2d1b | 2883 | return RET_PF_RETRY; |
989c6b34 | 2884 | |
3cf06612 SC |
2885 | level = kvm_mmu_hugepage_adjust(vcpu, gfn, max_level, &pfn, |
2886 | huge_page_disallowed, &req_level); | |
4cd071d1 | 2887 | |
335e192a | 2888 | trace_kvm_mmu_spte_requested(gpa, level, pfn); |
3fcf2d1b | 2889 | for_each_shadow_entry(vcpu, gpa, it) { |
b8e8c830 PB |
2890 | /* |
2891 | * We cannot overwrite existing page tables with an NX | |
2892 | * large page, as the leaf could be executable. | |
2893 | */ | |
dcc70651 | 2894 | if (nx_huge_page_workaround_enabled) |
7d945312 BG |
2895 | disallowed_hugepage_adjust(*it.sptep, gfn, it.level, |
2896 | &pfn, &level); | |
b8e8c830 | 2897 | |
3fcf2d1b PB |
2898 | base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
2899 | if (it.level == level) | |
9f652d21 | 2900 | break; |
6aa8b732 | 2901 | |
3fcf2d1b PB |
2902 | drop_large_spte(vcpu, it.sptep); |
2903 | if (!is_shadow_present_pte(*it.sptep)) { | |
2904 | sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr, | |
2905 | it.level - 1, true, ACC_ALL); | |
c9fa0b3b | 2906 | |
3fcf2d1b | 2907 | link_shadow_page(vcpu, it.sptep, sp); |
5bcaf3e1 SC |
2908 | if (is_tdp && huge_page_disallowed && |
2909 | req_level >= it.level) | |
b8e8c830 | 2910 | account_huge_nx_page(vcpu->kvm, sp); |
9f652d21 AK |
2911 | } |
2912 | } | |
3fcf2d1b PB |
2913 | |
2914 | ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL, | |
2915 | write, level, base_gfn, pfn, prefault, | |
2916 | map_writable); | |
12703759 SC |
2917 | if (ret == RET_PF_SPURIOUS) |
2918 | return ret; | |
2919 | ||
3fcf2d1b PB |
2920 | direct_pte_prefetch(vcpu, it.sptep); |
2921 | ++vcpu->stat.pf_fixed; | |
2922 | return ret; | |
6aa8b732 AK |
2923 | } |
2924 | ||
77db5cbd | 2925 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 2926 | { |
585a8b9b | 2927 | send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk); |
bf998156 HY |
2928 | } |
2929 | ||
ba049e93 | 2930 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn) |
bf998156 | 2931 | { |
4d8b81ab XG |
2932 | /* |
2933 | * Do not cache the mmio info caused by writing the readonly gfn | |
2934 | * into the spte otherwise read access on readonly gfn also can | |
2935 | * caused mmio page fault and treat it as mmio access. | |
4d8b81ab XG |
2936 | */ |
2937 | if (pfn == KVM_PFN_ERR_RO_FAULT) | |
9b8ebbdb | 2938 | return RET_PF_EMULATE; |
4d8b81ab | 2939 | |
e6c1502b | 2940 | if (pfn == KVM_PFN_ERR_HWPOISON) { |
54bf36aa | 2941 | kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current); |
9b8ebbdb | 2942 | return RET_PF_RETRY; |
d7c55201 | 2943 | } |
edba23e5 | 2944 | |
2c151b25 | 2945 | return -EFAULT; |
bf998156 HY |
2946 | } |
2947 | ||
d7c55201 | 2948 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, |
0a2b64c5 BG |
2949 | kvm_pfn_t pfn, unsigned int access, |
2950 | int *ret_val) | |
d7c55201 | 2951 | { |
d7c55201 | 2952 | /* The pfn is invalid, report the error! */ |
81c52c56 | 2953 | if (unlikely(is_error_pfn(pfn))) { |
d7c55201 | 2954 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); |
798e88b3 | 2955 | return true; |
d7c55201 XG |
2956 | } |
2957 | ||
ce88decf | 2958 | if (unlikely(is_noslot_pfn(pfn))) |
4af77151 SC |
2959 | vcpu_cache_mmio_info(vcpu, gva, gfn, |
2960 | access & shadow_mmio_access_mask); | |
d7c55201 | 2961 | |
798e88b3 | 2962 | return false; |
d7c55201 XG |
2963 | } |
2964 | ||
e5552fd2 | 2965 | static bool page_fault_can_be_fast(u32 error_code) |
c7ba5b48 | 2966 | { |
1c118b82 XG |
2967 | /* |
2968 | * Do not fix the mmio spte with invalid generation number which | |
2969 | * need to be updated by slow page fault path. | |
2970 | */ | |
2971 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
2972 | return false; | |
2973 | ||
f160c7b7 JS |
2974 | /* See if the page fault is due to an NX violation */ |
2975 | if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)) | |
2976 | == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)))) | |
2977 | return false; | |
2978 | ||
c7ba5b48 | 2979 | /* |
f160c7b7 JS |
2980 | * #PF can be fast if: |
2981 | * 1. The shadow page table entry is not present, which could mean that | |
2982 | * the fault is potentially caused by access tracking (if enabled). | |
2983 | * 2. The shadow page table entry is present and the fault | |
2984 | * is caused by write-protect, that means we just need change the W | |
2985 | * bit of the spte which can be done out of mmu-lock. | |
2986 | * | |
2987 | * However, if access tracking is disabled we know that a non-present | |
2988 | * page must be a genuine page fault where we have to create a new SPTE. | |
2989 | * So, if access tracking is disabled, we return true only for write | |
2990 | * accesses to a present page. | |
c7ba5b48 | 2991 | */ |
c7ba5b48 | 2992 | |
f160c7b7 JS |
2993 | return shadow_acc_track_mask != 0 || |
2994 | ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)) | |
2995 | == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)); | |
c7ba5b48 XG |
2996 | } |
2997 | ||
97dceba2 JS |
2998 | /* |
2999 | * Returns true if the SPTE was fixed successfully. Otherwise, | |
3000 | * someone else modified the SPTE from its original value. | |
3001 | */ | |
c7ba5b48 | 3002 | static bool |
92a476cb | 3003 | fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d3e328f2 | 3004 | u64 *sptep, u64 old_spte, u64 new_spte) |
c7ba5b48 | 3005 | { |
c7ba5b48 XG |
3006 | gfn_t gfn; |
3007 | ||
3008 | WARN_ON(!sp->role.direct); | |
3009 | ||
9b51a630 KH |
3010 | /* |
3011 | * Theoretically we could also set dirty bit (and flush TLB) here in | |
3012 | * order to eliminate unnecessary PML logging. See comments in | |
3013 | * set_spte. But fast_page_fault is very unlikely to happen with PML | |
3014 | * enabled, so we do not do this. This might result in the same GPA | |
3015 | * to be logged in PML buffer again when the write really happens, and | |
3016 | * eventually to be called by mark_page_dirty twice. But it's also no | |
3017 | * harm. This also avoids the TLB flush needed after setting dirty bit | |
3018 | * so non-PML cases won't be impacted. | |
3019 | * | |
3020 | * Compare with set_spte where instead shadow_dirty_mask is set. | |
3021 | */ | |
f160c7b7 | 3022 | if (cmpxchg64(sptep, old_spte, new_spte) != old_spte) |
97dceba2 JS |
3023 | return false; |
3024 | ||
d3e328f2 | 3025 | if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) { |
f160c7b7 JS |
3026 | /* |
3027 | * The gfn of direct spte is stable since it is | |
3028 | * calculated by sp->gfn. | |
3029 | */ | |
3030 | gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt); | |
3031 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
3032 | } | |
c7ba5b48 XG |
3033 | |
3034 | return true; | |
3035 | } | |
3036 | ||
d3e328f2 JS |
3037 | static bool is_access_allowed(u32 fault_err_code, u64 spte) |
3038 | { | |
3039 | if (fault_err_code & PFERR_FETCH_MASK) | |
3040 | return is_executable_pte(spte); | |
3041 | ||
3042 | if (fault_err_code & PFERR_WRITE_MASK) | |
3043 | return is_writable_pte(spte); | |
3044 | ||
3045 | /* Fault was on Read access */ | |
3046 | return spte & PT_PRESENT_MASK; | |
3047 | } | |
3048 | ||
c7ba5b48 | 3049 | /* |
c4371c2a | 3050 | * Returns one of RET_PF_INVALID, RET_PF_FIXED or RET_PF_SPURIOUS. |
c7ba5b48 | 3051 | */ |
c4371c2a SC |
3052 | static int fast_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
3053 | u32 error_code) | |
c7ba5b48 XG |
3054 | { |
3055 | struct kvm_shadow_walk_iterator iterator; | |
92a476cb | 3056 | struct kvm_mmu_page *sp; |
c4371c2a | 3057 | int ret = RET_PF_INVALID; |
c7ba5b48 | 3058 | u64 spte = 0ull; |
97dceba2 | 3059 | uint retry_count = 0; |
c7ba5b48 | 3060 | |
e5552fd2 | 3061 | if (!page_fault_can_be_fast(error_code)) |
c4371c2a | 3062 | return ret; |
c7ba5b48 XG |
3063 | |
3064 | walk_shadow_page_lockless_begin(vcpu); | |
c7ba5b48 | 3065 | |
97dceba2 | 3066 | do { |
d3e328f2 | 3067 | u64 new_spte; |
c7ba5b48 | 3068 | |
736c291c | 3069 | for_each_shadow_entry_lockless(vcpu, cr2_or_gpa, iterator, spte) |
f9fa2509 | 3070 | if (!is_shadow_present_pte(spte)) |
d162f30a JS |
3071 | break; |
3072 | ||
57354682 | 3073 | sp = sptep_to_sp(iterator.sptep); |
97dceba2 JS |
3074 | if (!is_last_spte(spte, sp->role.level)) |
3075 | break; | |
c7ba5b48 | 3076 | |
97dceba2 | 3077 | /* |
f160c7b7 JS |
3078 | * Check whether the memory access that caused the fault would |
3079 | * still cause it if it were to be performed right now. If not, | |
3080 | * then this is a spurious fault caused by TLB lazily flushed, | |
3081 | * or some other CPU has already fixed the PTE after the | |
3082 | * current CPU took the fault. | |
97dceba2 JS |
3083 | * |
3084 | * Need not check the access of upper level table entries since | |
3085 | * they are always ACC_ALL. | |
3086 | */ | |
d3e328f2 | 3087 | if (is_access_allowed(error_code, spte)) { |
c4371c2a | 3088 | ret = RET_PF_SPURIOUS; |
d3e328f2 JS |
3089 | break; |
3090 | } | |
f160c7b7 | 3091 | |
d3e328f2 JS |
3092 | new_spte = spte; |
3093 | ||
3094 | if (is_access_track_spte(spte)) | |
3095 | new_spte = restore_acc_track_spte(new_spte); | |
3096 | ||
3097 | /* | |
3098 | * Currently, to simplify the code, write-protection can | |
3099 | * be removed in the fast path only if the SPTE was | |
3100 | * write-protected for dirty-logging or access tracking. | |
3101 | */ | |
3102 | if ((error_code & PFERR_WRITE_MASK) && | |
e6302698 | 3103 | spte_can_locklessly_be_made_writable(spte)) { |
d3e328f2 | 3104 | new_spte |= PT_WRITABLE_MASK; |
f160c7b7 JS |
3105 | |
3106 | /* | |
d3e328f2 JS |
3107 | * Do not fix write-permission on the large spte. Since |
3108 | * we only dirty the first page into the dirty-bitmap in | |
3109 | * fast_pf_fix_direct_spte(), other pages are missed | |
3110 | * if its slot has dirty logging enabled. | |
3111 | * | |
3112 | * Instead, we let the slow page fault path create a | |
3113 | * normal spte to fix the access. | |
3114 | * | |
3115 | * See the comments in kvm_arch_commit_memory_region(). | |
f160c7b7 | 3116 | */ |
3bae0459 | 3117 | if (sp->role.level > PG_LEVEL_4K) |
f160c7b7 | 3118 | break; |
97dceba2 | 3119 | } |
c7ba5b48 | 3120 | |
f160c7b7 | 3121 | /* Verify that the fault can be handled in the fast path */ |
d3e328f2 JS |
3122 | if (new_spte == spte || |
3123 | !is_access_allowed(error_code, new_spte)) | |
97dceba2 JS |
3124 | break; |
3125 | ||
3126 | /* | |
3127 | * Currently, fast page fault only works for direct mapping | |
3128 | * since the gfn is not stable for indirect shadow page. See | |
3ecad8c2 | 3129 | * Documentation/virt/kvm/locking.rst to get more detail. |
97dceba2 | 3130 | */ |
c4371c2a SC |
3131 | if (fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte, |
3132 | new_spte)) { | |
3133 | ret = RET_PF_FIXED; | |
97dceba2 | 3134 | break; |
c4371c2a | 3135 | } |
97dceba2 JS |
3136 | |
3137 | if (++retry_count > 4) { | |
3138 | printk_once(KERN_WARNING | |
3139 | "kvm: Fast #PF retrying more than 4 times.\n"); | |
3140 | break; | |
3141 | } | |
3142 | ||
97dceba2 | 3143 | } while (true); |
c126d94f | 3144 | |
736c291c | 3145 | trace_fast_page_fault(vcpu, cr2_or_gpa, error_code, iterator.sptep, |
c4371c2a | 3146 | spte, ret); |
c7ba5b48 XG |
3147 | walk_shadow_page_lockless_end(vcpu); |
3148 | ||
c4371c2a | 3149 | return ret; |
c7ba5b48 XG |
3150 | } |
3151 | ||
74b566e6 JS |
3152 | static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa, |
3153 | struct list_head *invalid_list) | |
17ac10ad | 3154 | { |
4db35314 | 3155 | struct kvm_mmu_page *sp; |
17ac10ad | 3156 | |
74b566e6 | 3157 | if (!VALID_PAGE(*root_hpa)) |
7b53aa56 | 3158 | return; |
35af577a | 3159 | |
e47c4aee | 3160 | sp = to_shadow_page(*root_hpa & PT64_BASE_ADDR_MASK); |
02c00b3a BG |
3161 | |
3162 | if (kvm_mmu_put_root(kvm, sp)) { | |
897218ff | 3163 | if (is_tdp_mmu_page(sp)) |
02c00b3a BG |
3164 | kvm_tdp_mmu_free_root(kvm, sp); |
3165 | else if (sp->role.invalid) | |
3166 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); | |
3167 | } | |
17ac10ad | 3168 | |
74b566e6 JS |
3169 | *root_hpa = INVALID_PAGE; |
3170 | } | |
3171 | ||
08fb59d8 | 3172 | /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */ |
6a82cd1c VK |
3173 | void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
3174 | ulong roots_to_free) | |
74b566e6 | 3175 | { |
4d710de9 | 3176 | struct kvm *kvm = vcpu->kvm; |
74b566e6 JS |
3177 | int i; |
3178 | LIST_HEAD(invalid_list); | |
08fb59d8 | 3179 | bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT; |
74b566e6 | 3180 | |
b94742c9 | 3181 | BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG); |
74b566e6 | 3182 | |
08fb59d8 | 3183 | /* Before acquiring the MMU lock, see if we need to do any real work. */ |
b94742c9 JS |
3184 | if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) { |
3185 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
3186 | if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) && | |
3187 | VALID_PAGE(mmu->prev_roots[i].hpa)) | |
3188 | break; | |
3189 | ||
3190 | if (i == KVM_MMU_NUM_PREV_ROOTS) | |
3191 | return; | |
3192 | } | |
35af577a | 3193 | |
531810ca | 3194 | write_lock(&kvm->mmu_lock); |
17ac10ad | 3195 | |
b94742c9 JS |
3196 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) |
3197 | if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) | |
4d710de9 | 3198 | mmu_free_root_page(kvm, &mmu->prev_roots[i].hpa, |
b94742c9 | 3199 | &invalid_list); |
7c390d35 | 3200 | |
08fb59d8 JS |
3201 | if (free_active_root) { |
3202 | if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL && | |
3203 | (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) { | |
4d710de9 | 3204 | mmu_free_root_page(kvm, &mmu->root_hpa, &invalid_list); |
04d45551 | 3205 | } else if (mmu->pae_root) { |
08fb59d8 JS |
3206 | for (i = 0; i < 4; ++i) |
3207 | if (mmu->pae_root[i] != 0) | |
4d710de9 | 3208 | mmu_free_root_page(kvm, |
08fb59d8 JS |
3209 | &mmu->pae_root[i], |
3210 | &invalid_list); | |
08fb59d8 | 3211 | } |
04d45551 | 3212 | mmu->root_hpa = INVALID_PAGE; |
be01e8e2 | 3213 | mmu->root_pgd = 0; |
17ac10ad | 3214 | } |
74b566e6 | 3215 | |
4d710de9 | 3216 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
531810ca | 3217 | write_unlock(&kvm->mmu_lock); |
17ac10ad | 3218 | } |
74b566e6 | 3219 | EXPORT_SYMBOL_GPL(kvm_mmu_free_roots); |
17ac10ad | 3220 | |
8986ecc0 MT |
3221 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
3222 | { | |
3223 | int ret = 0; | |
3224 | ||
995decb6 | 3225 | if (!kvm_vcpu_is_visible_gfn(vcpu, root_gfn)) { |
a8eeb04a | 3226 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
3227 | ret = 1; |
3228 | } | |
3229 | ||
3230 | return ret; | |
3231 | } | |
3232 | ||
8123f265 SC |
3233 | static hpa_t mmu_alloc_root(struct kvm_vcpu *vcpu, gfn_t gfn, gva_t gva, |
3234 | u8 level, bool direct) | |
651dd37a JR |
3235 | { |
3236 | struct kvm_mmu_page *sp; | |
8123f265 | 3237 | |
8123f265 SC |
3238 | sp = kvm_mmu_get_page(vcpu, gfn, gva, level, direct, ACC_ALL); |
3239 | ++sp->root_count; | |
3240 | ||
8123f265 SC |
3241 | return __pa(sp->spt); |
3242 | } | |
3243 | ||
3244 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) | |
3245 | { | |
b37233c9 SC |
3246 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
3247 | u8 shadow_root_level = mmu->shadow_root_level; | |
8123f265 | 3248 | hpa_t root; |
7ebaf15e | 3249 | unsigned i; |
651dd37a | 3250 | |
897218ff | 3251 | if (is_tdp_mmu_enabled(vcpu->kvm)) { |
02c00b3a | 3252 | root = kvm_tdp_mmu_get_vcpu_root_hpa(vcpu); |
b37233c9 | 3253 | mmu->root_hpa = root; |
02c00b3a | 3254 | } else if (shadow_root_level >= PT64_ROOT_4LEVEL) { |
6e6ec584 | 3255 | root = mmu_alloc_root(vcpu, 0, 0, shadow_root_level, true); |
b37233c9 | 3256 | mmu->root_hpa = root; |
8123f265 | 3257 | } else if (shadow_root_level == PT32E_ROOT_LEVEL) { |
73ad1606 SC |
3258 | if (WARN_ON_ONCE(!mmu->pae_root)) |
3259 | return -EIO; | |
3260 | ||
651dd37a | 3261 | for (i = 0; i < 4; ++i) { |
e49e0b7b SC |
3262 | WARN_ON_ONCE(mmu->pae_root[i] && |
3263 | VALID_PAGE(mmu->pae_root[i])); | |
651dd37a | 3264 | |
8123f265 SC |
3265 | root = mmu_alloc_root(vcpu, i << (30 - PAGE_SHIFT), |
3266 | i << 30, PT32_ROOT_LEVEL, true); | |
17e368d9 SC |
3267 | mmu->pae_root[i] = root | PT_PRESENT_MASK | |
3268 | shadow_me_mask; | |
651dd37a | 3269 | } |
b37233c9 | 3270 | mmu->root_hpa = __pa(mmu->pae_root); |
73ad1606 SC |
3271 | } else { |
3272 | WARN_ONCE(1, "Bad TDP root level = %d\n", shadow_root_level); | |
3273 | return -EIO; | |
3274 | } | |
3651c7fc | 3275 | |
be01e8e2 | 3276 | /* root_pgd is ignored for direct MMUs. */ |
b37233c9 | 3277 | mmu->root_pgd = 0; |
651dd37a JR |
3278 | |
3279 | return 0; | |
3280 | } | |
3281 | ||
3282 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 3283 | { |
b37233c9 | 3284 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
6e0918ae | 3285 | u64 pdptrs[4], pm_mask; |
be01e8e2 | 3286 | gfn_t root_gfn, root_pgd; |
8123f265 | 3287 | hpa_t root; |
81407ca5 | 3288 | int i; |
3bb65a22 | 3289 | |
b37233c9 | 3290 | root_pgd = mmu->get_guest_pgd(vcpu); |
be01e8e2 | 3291 | root_gfn = root_pgd >> PAGE_SHIFT; |
17ac10ad | 3292 | |
651dd37a JR |
3293 | if (mmu_check_root(vcpu, root_gfn)) |
3294 | return 1; | |
3295 | ||
6e0918ae SC |
3296 | if (mmu->root_level == PT32E_ROOT_LEVEL) { |
3297 | for (i = 0; i < 4; ++i) { | |
3298 | pdptrs[i] = mmu->get_pdptr(vcpu, i); | |
3299 | if (!(pdptrs[i] & PT_PRESENT_MASK)) | |
3300 | continue; | |
3301 | ||
3302 | if (mmu_check_root(vcpu, pdptrs[i] >> PAGE_SHIFT)) | |
3303 | return 1; | |
3304 | } | |
3305 | } | |
3306 | ||
651dd37a JR |
3307 | /* |
3308 | * Do we shadow a long mode page table? If so we need to | |
3309 | * write-protect the guests page table root. | |
3310 | */ | |
b37233c9 | 3311 | if (mmu->root_level >= PT64_ROOT_4LEVEL) { |
8123f265 | 3312 | root = mmu_alloc_root(vcpu, root_gfn, 0, |
b37233c9 | 3313 | mmu->shadow_root_level, false); |
b37233c9 | 3314 | mmu->root_hpa = root; |
be01e8e2 | 3315 | goto set_root_pgd; |
17ac10ad | 3316 | } |
f87f9288 | 3317 | |
73ad1606 SC |
3318 | if (WARN_ON_ONCE(!mmu->pae_root)) |
3319 | return -EIO; | |
3320 | ||
651dd37a JR |
3321 | /* |
3322 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
3323 | * or a PAE 3-level page table. In either case we need to be aware that |
3324 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 3325 | */ |
17e368d9 | 3326 | pm_mask = PT_PRESENT_MASK | shadow_me_mask; |
748e52b9 | 3327 | if (mmu->shadow_root_level == PT64_ROOT_4LEVEL) { |
81407ca5 JR |
3328 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; |
3329 | ||
73ad1606 SC |
3330 | if (WARN_ON_ONCE(!mmu->lm_root)) |
3331 | return -EIO; | |
3332 | ||
748e52b9 | 3333 | mmu->lm_root[0] = __pa(mmu->pae_root) | pm_mask; |
04d45551 SC |
3334 | } |
3335 | ||
17ac10ad | 3336 | for (i = 0; i < 4; ++i) { |
e49e0b7b | 3337 | WARN_ON_ONCE(mmu->pae_root[i] && VALID_PAGE(mmu->pae_root[i])); |
6e6ec584 | 3338 | |
b37233c9 | 3339 | if (mmu->root_level == PT32E_ROOT_LEVEL) { |
6e0918ae | 3340 | if (!(pdptrs[i] & PT_PRESENT_MASK)) { |
b37233c9 | 3341 | mmu->pae_root[i] = 0; |
417726a3 AK |
3342 | continue; |
3343 | } | |
6e0918ae | 3344 | root_gfn = pdptrs[i] >> PAGE_SHIFT; |
5a7388c2 | 3345 | } |
8facbbff | 3346 | |
8123f265 SC |
3347 | root = mmu_alloc_root(vcpu, root_gfn, i << 30, |
3348 | PT32_ROOT_LEVEL, false); | |
b37233c9 | 3349 | mmu->pae_root[i] = root | pm_mask; |
17ac10ad | 3350 | } |
81407ca5 | 3351 | |
ba0a194f | 3352 | if (mmu->shadow_root_level == PT64_ROOT_4LEVEL) |
b37233c9 | 3353 | mmu->root_hpa = __pa(mmu->lm_root); |
ba0a194f SC |
3354 | else |
3355 | mmu->root_hpa = __pa(mmu->pae_root); | |
81407ca5 | 3356 | |
be01e8e2 | 3357 | set_root_pgd: |
b37233c9 | 3358 | mmu->root_pgd = root_pgd; |
ad7dc69a | 3359 | |
8986ecc0 | 3360 | return 0; |
17ac10ad AK |
3361 | } |
3362 | ||
748e52b9 SC |
3363 | static int mmu_alloc_special_roots(struct kvm_vcpu *vcpu) |
3364 | { | |
3365 | struct kvm_mmu *mmu = vcpu->arch.mmu; | |
3366 | u64 *lm_root, *pae_root; | |
3367 | ||
3368 | /* | |
3369 | * When shadowing 32-bit or PAE NPT with 64-bit NPT, the PML4 and PDP | |
3370 | * tables are allocated and initialized at root creation as there is no | |
3371 | * equivalent level in the guest's NPT to shadow. Allocate the tables | |
3372 | * on demand, as running a 32-bit L1 VMM on 64-bit KVM is very rare. | |
3373 | */ | |
3374 | if (mmu->direct_map || mmu->root_level >= PT64_ROOT_4LEVEL || | |
3375 | mmu->shadow_root_level < PT64_ROOT_4LEVEL) | |
3376 | return 0; | |
3377 | ||
3378 | /* | |
3379 | * This mess only works with 4-level paging and needs to be updated to | |
3380 | * work with 5-level paging. | |
3381 | */ | |
3382 | if (WARN_ON_ONCE(mmu->shadow_root_level != PT64_ROOT_4LEVEL)) | |
3383 | return -EIO; | |
3384 | ||
3385 | if (mmu->pae_root && mmu->lm_root) | |
3386 | return 0; | |
3387 | ||
3388 | /* | |
3389 | * The special roots should always be allocated in concert. Yell and | |
3390 | * bail if KVM ends up in a state where only one of the roots is valid. | |
3391 | */ | |
3392 | if (WARN_ON_ONCE(!tdp_enabled || mmu->pae_root || mmu->lm_root)) | |
3393 | return -EIO; | |
3394 | ||
3395 | /* Unlike 32-bit NPT, the PDP table doesn't need to be in low mem. */ | |
3396 | pae_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); | |
3397 | if (!pae_root) | |
3398 | return -ENOMEM; | |
3399 | ||
3400 | lm_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); | |
3401 | if (!lm_root) { | |
3402 | free_page((unsigned long)pae_root); | |
3403 | return -ENOMEM; | |
3404 | } | |
3405 | ||
3406 | mmu->pae_root = pae_root; | |
3407 | mmu->lm_root = lm_root; | |
3408 | ||
3409 | return 0; | |
3410 | } | |
3411 | ||
578e1c4d | 3412 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) |
0ba73cda MT |
3413 | { |
3414 | int i; | |
3415 | struct kvm_mmu_page *sp; | |
3416 | ||
44dd3ffa | 3417 | if (vcpu->arch.mmu->direct_map) |
81407ca5 JR |
3418 | return; |
3419 | ||
44dd3ffa | 3420 | if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) |
0ba73cda | 3421 | return; |
6903074c | 3422 | |
56f17dd3 | 3423 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); |
578e1c4d | 3424 | |
44dd3ffa VK |
3425 | if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) { |
3426 | hpa_t root = vcpu->arch.mmu->root_hpa; | |
e47c4aee | 3427 | sp = to_shadow_page(root); |
578e1c4d JS |
3428 | |
3429 | /* | |
3430 | * Even if another CPU was marking the SP as unsync-ed | |
3431 | * simultaneously, any guest page table changes are not | |
3432 | * guaranteed to be visible anyway until this VCPU issues a TLB | |
3433 | * flush strictly after those changes are made. We only need to | |
3434 | * ensure that the other CPU sets these flags before any actual | |
3435 | * changes to the page tables are made. The comments in | |
3436 | * mmu_need_write_protect() describe what could go wrong if this | |
3437 | * requirement isn't satisfied. | |
3438 | */ | |
3439 | if (!smp_load_acquire(&sp->unsync) && | |
3440 | !smp_load_acquire(&sp->unsync_children)) | |
3441 | return; | |
3442 | ||
531810ca | 3443 | write_lock(&vcpu->kvm->mmu_lock); |
578e1c4d JS |
3444 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); |
3445 | ||
0ba73cda | 3446 | mmu_sync_children(vcpu, sp); |
578e1c4d | 3447 | |
0375f7fa | 3448 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
531810ca | 3449 | write_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
3450 | return; |
3451 | } | |
578e1c4d | 3452 | |
531810ca | 3453 | write_lock(&vcpu->kvm->mmu_lock); |
578e1c4d JS |
3454 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); |
3455 | ||
0ba73cda | 3456 | for (i = 0; i < 4; ++i) { |
44dd3ffa | 3457 | hpa_t root = vcpu->arch.mmu->pae_root[i]; |
0ba73cda | 3458 | |
8986ecc0 | 3459 | if (root && VALID_PAGE(root)) { |
0ba73cda | 3460 | root &= PT64_BASE_ADDR_MASK; |
e47c4aee | 3461 | sp = to_shadow_page(root); |
0ba73cda MT |
3462 | mmu_sync_children(vcpu, sp); |
3463 | } | |
3464 | } | |
0ba73cda | 3465 | |
578e1c4d | 3466 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
531810ca | 3467 | write_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
3468 | } |
3469 | ||
736c291c | 3470 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gpa_t vaddr, |
ab9ae313 | 3471 | u32 access, struct x86_exception *exception) |
6aa8b732 | 3472 | { |
ab9ae313 AK |
3473 | if (exception) |
3474 | exception->error_code = 0; | |
6aa8b732 AK |
3475 | return vaddr; |
3476 | } | |
3477 | ||
736c291c | 3478 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gpa_t vaddr, |
ab9ae313 AK |
3479 | u32 access, |
3480 | struct x86_exception *exception) | |
6539e738 | 3481 | { |
ab9ae313 AK |
3482 | if (exception) |
3483 | exception->error_code = 0; | |
54987b7a | 3484 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception); |
6539e738 JR |
3485 | } |
3486 | ||
d625b155 XG |
3487 | static bool |
3488 | __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level) | |
3489 | { | |
b5c3c1b3 | 3490 | int bit7 = (pte >> 7) & 1; |
d625b155 | 3491 | |
b5c3c1b3 | 3492 | return pte & rsvd_check->rsvd_bits_mask[bit7][level-1]; |
d625b155 XG |
3493 | } |
3494 | ||
b5c3c1b3 | 3495 | static bool __is_bad_mt_xwr(struct rsvd_bits_validate *rsvd_check, u64 pte) |
d625b155 | 3496 | { |
b5c3c1b3 | 3497 | return rsvd_check->bad_mt_xwr & BIT_ULL(pte & 0x3f); |
d625b155 XG |
3498 | } |
3499 | ||
ded58749 | 3500 | static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf | 3501 | { |
9034e6e8 PB |
3502 | /* |
3503 | * A nested guest cannot use the MMIO cache if it is using nested | |
3504 | * page tables, because cr2 is a nGPA while the cache stores GPAs. | |
3505 | */ | |
3506 | if (mmu_is_nested(vcpu)) | |
3507 | return false; | |
3508 | ||
ce88decf XG |
3509 | if (direct) |
3510 | return vcpu_match_mmio_gpa(vcpu, addr); | |
3511 | ||
3512 | return vcpu_match_mmio_gva(vcpu, addr); | |
3513 | } | |
3514 | ||
95fb5b02 BG |
3515 | /* |
3516 | * Return the level of the lowest level SPTE added to sptes. | |
3517 | * That SPTE may be non-present. | |
3518 | */ | |
39b4d43e | 3519 | static int get_walk(struct kvm_vcpu *vcpu, u64 addr, u64 *sptes, int *root_level) |
ce88decf XG |
3520 | { |
3521 | struct kvm_shadow_walk_iterator iterator; | |
2aa07893 | 3522 | int leaf = -1; |
95fb5b02 | 3523 | u64 spte; |
ce88decf XG |
3524 | |
3525 | walk_shadow_page_lockless_begin(vcpu); | |
47ab8751 | 3526 | |
39b4d43e SC |
3527 | for (shadow_walk_init(&iterator, vcpu, addr), |
3528 | *root_level = iterator.level; | |
47ab8751 XG |
3529 | shadow_walk_okay(&iterator); |
3530 | __shadow_walk_next(&iterator, spte)) { | |
95fb5b02 | 3531 | leaf = iterator.level; |
47ab8751 XG |
3532 | spte = mmu_spte_get_lockless(iterator.sptep); |
3533 | ||
dde81f94 | 3534 | sptes[leaf] = spte; |
47ab8751 | 3535 | |
ce88decf XG |
3536 | if (!is_shadow_present_pte(spte)) |
3537 | break; | |
95fb5b02 BG |
3538 | } |
3539 | ||
3540 | walk_shadow_page_lockless_end(vcpu); | |
3541 | ||
3542 | return leaf; | |
3543 | } | |
3544 | ||
9aa41879 | 3545 | /* return true if reserved bit(s) are detected on a valid, non-MMIO SPTE. */ |
95fb5b02 BG |
3546 | static bool get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep) |
3547 | { | |
dde81f94 | 3548 | u64 sptes[PT64_ROOT_MAX_LEVEL + 1]; |
95fb5b02 | 3549 | struct rsvd_bits_validate *rsvd_check; |
39b4d43e | 3550 | int root, leaf, level; |
95fb5b02 BG |
3551 | bool reserved = false; |
3552 | ||
3553 | if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) { | |
3554 | *sptep = 0ull; | |
3555 | return reserved; | |
3556 | } | |
3557 | ||
3558 | if (is_tdp_mmu_root(vcpu->kvm, vcpu->arch.mmu->root_hpa)) | |
39b4d43e | 3559 | leaf = kvm_tdp_mmu_get_walk(vcpu, addr, sptes, &root); |
95fb5b02 | 3560 | else |
39b4d43e | 3561 | leaf = get_walk(vcpu, addr, sptes, &root); |
95fb5b02 | 3562 | |
2aa07893 SC |
3563 | if (unlikely(leaf < 0)) { |
3564 | *sptep = 0ull; | |
3565 | return reserved; | |
3566 | } | |
3567 | ||
9aa41879 SC |
3568 | *sptep = sptes[leaf]; |
3569 | ||
3570 | /* | |
3571 | * Skip reserved bits checks on the terminal leaf if it's not a valid | |
3572 | * SPTE. Note, this also (intentionally) skips MMIO SPTEs, which, by | |
3573 | * design, always have reserved bits set. The purpose of the checks is | |
3574 | * to detect reserved bits on non-MMIO SPTEs. i.e. buggy SPTEs. | |
3575 | */ | |
3576 | if (!is_shadow_present_pte(sptes[leaf])) | |
3577 | leaf++; | |
95fb5b02 BG |
3578 | |
3579 | rsvd_check = &vcpu->arch.mmu->shadow_zero_check; | |
3580 | ||
9aa41879 | 3581 | for (level = root; level >= leaf; level--) |
b5c3c1b3 SC |
3582 | /* |
3583 | * Use a bitwise-OR instead of a logical-OR to aggregate the | |
3584 | * reserved bit and EPT's invalid memtype/XWR checks to avoid | |
3585 | * adding a Jcc in the loop. | |
3586 | */ | |
dde81f94 SC |
3587 | reserved |= __is_bad_mt_xwr(rsvd_check, sptes[level]) | |
3588 | __is_rsvd_bits_set(rsvd_check, sptes[level], level); | |
47ab8751 | 3589 | |
47ab8751 XG |
3590 | if (reserved) { |
3591 | pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n", | |
3592 | __func__, addr); | |
95fb5b02 | 3593 | for (level = root; level >= leaf; level--) |
47ab8751 | 3594 | pr_err("------ spte 0x%llx level %d.\n", |
dde81f94 | 3595 | sptes[level], level); |
47ab8751 | 3596 | } |
ddce6208 | 3597 | |
47ab8751 | 3598 | return reserved; |
ce88decf XG |
3599 | } |
3600 | ||
e08d26f0 | 3601 | static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf XG |
3602 | { |
3603 | u64 spte; | |
47ab8751 | 3604 | bool reserved; |
ce88decf | 3605 | |
ded58749 | 3606 | if (mmio_info_in_cache(vcpu, addr, direct)) |
9b8ebbdb | 3607 | return RET_PF_EMULATE; |
ce88decf | 3608 | |
95fb5b02 | 3609 | reserved = get_mmio_spte(vcpu, addr, &spte); |
450869d6 | 3610 | if (WARN_ON(reserved)) |
9b8ebbdb | 3611 | return -EINVAL; |
ce88decf XG |
3612 | |
3613 | if (is_mmio_spte(spte)) { | |
3614 | gfn_t gfn = get_mmio_spte_gfn(spte); | |
0a2b64c5 | 3615 | unsigned int access = get_mmio_spte_access(spte); |
ce88decf | 3616 | |
54bf36aa | 3617 | if (!check_mmio_spte(vcpu, spte)) |
9b8ebbdb | 3618 | return RET_PF_INVALID; |
f8f55942 | 3619 | |
ce88decf XG |
3620 | if (direct) |
3621 | addr = 0; | |
4f022648 XG |
3622 | |
3623 | trace_handle_mmio_page_fault(addr, gfn, access); | |
ce88decf | 3624 | vcpu_cache_mmio_info(vcpu, addr, gfn, access); |
9b8ebbdb | 3625 | return RET_PF_EMULATE; |
ce88decf XG |
3626 | } |
3627 | ||
ce88decf XG |
3628 | /* |
3629 | * If the page table is zapped by other cpus, let CPU fault again on | |
3630 | * the address. | |
3631 | */ | |
9b8ebbdb | 3632 | return RET_PF_RETRY; |
ce88decf | 3633 | } |
ce88decf | 3634 | |
3d0c27ad XG |
3635 | static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu, |
3636 | u32 error_code, gfn_t gfn) | |
3637 | { | |
3638 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3639 | return false; | |
3640 | ||
3641 | if (!(error_code & PFERR_PRESENT_MASK) || | |
3642 | !(error_code & PFERR_WRITE_MASK)) | |
3643 | return false; | |
3644 | ||
3645 | /* | |
3646 | * guest is writing the page which is write tracked which can | |
3647 | * not be fixed by page fault handler. | |
3648 | */ | |
3649 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) | |
3650 | return true; | |
3651 | ||
3652 | return false; | |
3653 | } | |
3654 | ||
e5691a81 XG |
3655 | static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr) |
3656 | { | |
3657 | struct kvm_shadow_walk_iterator iterator; | |
3658 | u64 spte; | |
3659 | ||
e5691a81 XG |
3660 | walk_shadow_page_lockless_begin(vcpu); |
3661 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { | |
3662 | clear_sp_write_flooding_count(iterator.sptep); | |
3663 | if (!is_shadow_present_pte(spte)) | |
3664 | break; | |
3665 | } | |
3666 | walk_shadow_page_lockless_end(vcpu); | |
3667 | } | |
3668 | ||
e8c22266 VK |
3669 | static bool kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
3670 | gfn_t gfn) | |
af585b92 GN |
3671 | { |
3672 | struct kvm_arch_async_pf arch; | |
fb67e14f | 3673 | |
7c90705b | 3674 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 3675 | arch.gfn = gfn; |
44dd3ffa | 3676 | arch.direct_map = vcpu->arch.mmu->direct_map; |
d8dd54e0 | 3677 | arch.cr3 = vcpu->arch.mmu->get_guest_pgd(vcpu); |
af585b92 | 3678 | |
9f1a8526 SC |
3679 | return kvm_setup_async_pf(vcpu, cr2_or_gpa, |
3680 | kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch); | |
af585b92 GN |
3681 | } |
3682 | ||
78b2c54a | 3683 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
4a42d848 DS |
3684 | gpa_t cr2_or_gpa, kvm_pfn_t *pfn, hva_t *hva, |
3685 | bool write, bool *writable) | |
af585b92 | 3686 | { |
c36b7150 | 3687 | struct kvm_memory_slot *slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
af585b92 GN |
3688 | bool async; |
3689 | ||
c36b7150 PB |
3690 | /* Don't expose private memslots to L2. */ |
3691 | if (is_guest_mode(vcpu) && !kvm_is_visible_memslot(slot)) { | |
3a2936de | 3692 | *pfn = KVM_PFN_NOSLOT; |
c583eed6 | 3693 | *writable = false; |
3a2936de JM |
3694 | return false; |
3695 | } | |
3696 | ||
3520469d | 3697 | async = false; |
4a42d848 DS |
3698 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, |
3699 | write, writable, hva); | |
af585b92 GN |
3700 | if (!async) |
3701 | return false; /* *pfn has correct page already */ | |
3702 | ||
9bc1f09f | 3703 | if (!prefault && kvm_can_do_async_pf(vcpu)) { |
9f1a8526 | 3704 | trace_kvm_try_async_get_page(cr2_or_gpa, gfn); |
af585b92 | 3705 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
9f1a8526 | 3706 | trace_kvm_async_pf_doublefault(cr2_or_gpa, gfn); |
af585b92 GN |
3707 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); |
3708 | return true; | |
9f1a8526 | 3709 | } else if (kvm_arch_setup_async_pf(vcpu, cr2_or_gpa, gfn)) |
af585b92 GN |
3710 | return true; |
3711 | } | |
3712 | ||
4a42d848 DS |
3713 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, |
3714 | write, writable, hva); | |
af585b92 GN |
3715 | return false; |
3716 | } | |
3717 | ||
0f90e1c1 SC |
3718 | static int direct_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, |
3719 | bool prefault, int max_level, bool is_tdp) | |
6aa8b732 | 3720 | { |
367fd790 | 3721 | bool write = error_code & PFERR_WRITE_MASK; |
0f90e1c1 | 3722 | bool map_writable; |
6aa8b732 | 3723 | |
0f90e1c1 SC |
3724 | gfn_t gfn = gpa >> PAGE_SHIFT; |
3725 | unsigned long mmu_seq; | |
3726 | kvm_pfn_t pfn; | |
4a42d848 | 3727 | hva_t hva; |
83f06fa7 | 3728 | int r; |
ce88decf | 3729 | |
3d0c27ad | 3730 | if (page_fault_handle_page_track(vcpu, error_code, gfn)) |
9b8ebbdb | 3731 | return RET_PF_EMULATE; |
ce88decf | 3732 | |
bb18842e BG |
3733 | if (!is_tdp_mmu_root(vcpu->kvm, vcpu->arch.mmu->root_hpa)) { |
3734 | r = fast_page_fault(vcpu, gpa, error_code); | |
3735 | if (r != RET_PF_INVALID) | |
3736 | return r; | |
3737 | } | |
83291445 | 3738 | |
378f5cd6 | 3739 | r = mmu_topup_memory_caches(vcpu, false); |
e2dec939 AK |
3740 | if (r) |
3741 | return r; | |
714b93da | 3742 | |
367fd790 SC |
3743 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
3744 | smp_rmb(); | |
3745 | ||
4a42d848 DS |
3746 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, &hva, |
3747 | write, &map_writable)) | |
367fd790 SC |
3748 | return RET_PF_RETRY; |
3749 | ||
0f90e1c1 | 3750 | if (handle_abnormal_pfn(vcpu, is_tdp ? 0 : gpa, gfn, pfn, ACC_ALL, &r)) |
367fd790 | 3751 | return r; |
6aa8b732 | 3752 | |
367fd790 | 3753 | r = RET_PF_RETRY; |
a2855afc BG |
3754 | |
3755 | if (is_tdp_mmu_root(vcpu->kvm, vcpu->arch.mmu->root_hpa)) | |
3756 | read_lock(&vcpu->kvm->mmu_lock); | |
3757 | else | |
3758 | write_lock(&vcpu->kvm->mmu_lock); | |
3759 | ||
4a42d848 | 3760 | if (!is_noslot_pfn(pfn) && mmu_notifier_retry_hva(vcpu->kvm, mmu_seq, hva)) |
367fd790 | 3761 | goto out_unlock; |
7bd7ded6 SC |
3762 | r = make_mmu_pages_available(vcpu); |
3763 | if (r) | |
367fd790 | 3764 | goto out_unlock; |
bb18842e BG |
3765 | |
3766 | if (is_tdp_mmu_root(vcpu->kvm, vcpu->arch.mmu->root_hpa)) | |
3767 | r = kvm_tdp_mmu_map(vcpu, gpa, error_code, map_writable, max_level, | |
3768 | pfn, prefault); | |
3769 | else | |
3770 | r = __direct_map(vcpu, gpa, error_code, map_writable, max_level, pfn, | |
3771 | prefault, is_tdp); | |
0f90e1c1 | 3772 | |
367fd790 | 3773 | out_unlock: |
a2855afc BG |
3774 | if (is_tdp_mmu_root(vcpu->kvm, vcpu->arch.mmu->root_hpa)) |
3775 | read_unlock(&vcpu->kvm->mmu_lock); | |
3776 | else | |
3777 | write_unlock(&vcpu->kvm->mmu_lock); | |
367fd790 SC |
3778 | kvm_release_pfn_clean(pfn); |
3779 | return r; | |
6aa8b732 AK |
3780 | } |
3781 | ||
0f90e1c1 SC |
3782 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, |
3783 | u32 error_code, bool prefault) | |
3784 | { | |
3785 | pgprintk("%s: gva %lx error %x\n", __func__, gpa, error_code); | |
3786 | ||
3787 | /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */ | |
3788 | return direct_page_fault(vcpu, gpa & PAGE_MASK, error_code, prefault, | |
3bae0459 | 3789 | PG_LEVEL_2M, false); |
0f90e1c1 SC |
3790 | } |
3791 | ||
1261bfa3 | 3792 | int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code, |
d0006530 | 3793 | u64 fault_address, char *insn, int insn_len) |
1261bfa3 WL |
3794 | { |
3795 | int r = 1; | |
9ce372b3 | 3796 | u32 flags = vcpu->arch.apf.host_apf_flags; |
1261bfa3 | 3797 | |
736c291c SC |
3798 | #ifndef CONFIG_X86_64 |
3799 | /* A 64-bit CR2 should be impossible on 32-bit KVM. */ | |
3800 | if (WARN_ON_ONCE(fault_address >> 32)) | |
3801 | return -EFAULT; | |
3802 | #endif | |
3803 | ||
c595ceee | 3804 | vcpu->arch.l1tf_flush_l1d = true; |
9ce372b3 | 3805 | if (!flags) { |
1261bfa3 WL |
3806 | trace_kvm_page_fault(fault_address, error_code); |
3807 | ||
d0006530 | 3808 | if (kvm_event_needs_reinjection(vcpu)) |
1261bfa3 WL |
3809 | kvm_mmu_unprotect_page_virt(vcpu, fault_address); |
3810 | r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn, | |
3811 | insn_len); | |
9ce372b3 | 3812 | } else if (flags & KVM_PV_REASON_PAGE_NOT_PRESENT) { |
68fd66f1 | 3813 | vcpu->arch.apf.host_apf_flags = 0; |
1261bfa3 | 3814 | local_irq_disable(); |
6bca69ad | 3815 | kvm_async_pf_task_wait_schedule(fault_address); |
1261bfa3 | 3816 | local_irq_enable(); |
9ce372b3 VK |
3817 | } else { |
3818 | WARN_ONCE(1, "Unexpected host async PF flags: %x\n", flags); | |
1261bfa3 | 3819 | } |
9ce372b3 | 3820 | |
1261bfa3 WL |
3821 | return r; |
3822 | } | |
3823 | EXPORT_SYMBOL_GPL(kvm_handle_page_fault); | |
3824 | ||
7a02674d SC |
3825 | int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, |
3826 | bool prefault) | |
fb72d167 | 3827 | { |
cb9b88c6 | 3828 | int max_level; |
fb72d167 | 3829 | |
e662ec3e | 3830 | for (max_level = KVM_MAX_HUGEPAGE_LEVEL; |
3bae0459 | 3831 | max_level > PG_LEVEL_4K; |
cb9b88c6 SC |
3832 | max_level--) { |
3833 | int page_num = KVM_PAGES_PER_HPAGE(max_level); | |
0f90e1c1 | 3834 | gfn_t base = (gpa >> PAGE_SHIFT) & ~(page_num - 1); |
ce88decf | 3835 | |
cb9b88c6 SC |
3836 | if (kvm_mtrr_check_gfn_range_consistency(vcpu, base, page_num)) |
3837 | break; | |
fd136902 | 3838 | } |
852e3c19 | 3839 | |
0f90e1c1 SC |
3840 | return direct_page_fault(vcpu, gpa, error_code, prefault, |
3841 | max_level, true); | |
fb72d167 JR |
3842 | } |
3843 | ||
8a3c1a33 PB |
3844 | static void nonpaging_init_context(struct kvm_vcpu *vcpu, |
3845 | struct kvm_mmu *context) | |
6aa8b732 | 3846 | { |
6aa8b732 | 3847 | context->page_fault = nonpaging_page_fault; |
6aa8b732 | 3848 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
e8bc217a | 3849 | context->sync_page = nonpaging_sync_page; |
5efac074 | 3850 | context->invlpg = NULL; |
cea0f0e7 | 3851 | context->root_level = 0; |
6aa8b732 | 3852 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
c5a78f2b | 3853 | context->direct_map = true; |
2d48a985 | 3854 | context->nx = false; |
6aa8b732 AK |
3855 | } |
3856 | ||
be01e8e2 | 3857 | static inline bool is_root_usable(struct kvm_mmu_root_info *root, gpa_t pgd, |
0be44352 SC |
3858 | union kvm_mmu_page_role role) |
3859 | { | |
be01e8e2 | 3860 | return (role.direct || pgd == root->pgd) && |
e47c4aee SC |
3861 | VALID_PAGE(root->hpa) && to_shadow_page(root->hpa) && |
3862 | role.word == to_shadow_page(root->hpa)->role.word; | |
0be44352 SC |
3863 | } |
3864 | ||
b94742c9 | 3865 | /* |
be01e8e2 | 3866 | * Find out if a previously cached root matching the new pgd/role is available. |
b94742c9 JS |
3867 | * The current root is also inserted into the cache. |
3868 | * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is | |
3869 | * returned. | |
3870 | * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and | |
3871 | * false is returned. This root should now be freed by the caller. | |
3872 | */ | |
be01e8e2 | 3873 | static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_pgd, |
b94742c9 JS |
3874 | union kvm_mmu_page_role new_role) |
3875 | { | |
3876 | uint i; | |
3877 | struct kvm_mmu_root_info root; | |
44dd3ffa | 3878 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
b94742c9 | 3879 | |
be01e8e2 | 3880 | root.pgd = mmu->root_pgd; |
b94742c9 JS |
3881 | root.hpa = mmu->root_hpa; |
3882 | ||
be01e8e2 | 3883 | if (is_root_usable(&root, new_pgd, new_role)) |
0be44352 SC |
3884 | return true; |
3885 | ||
b94742c9 JS |
3886 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { |
3887 | swap(root, mmu->prev_roots[i]); | |
3888 | ||
be01e8e2 | 3889 | if (is_root_usable(&root, new_pgd, new_role)) |
b94742c9 JS |
3890 | break; |
3891 | } | |
3892 | ||
3893 | mmu->root_hpa = root.hpa; | |
be01e8e2 | 3894 | mmu->root_pgd = root.pgd; |
b94742c9 JS |
3895 | |
3896 | return i < KVM_MMU_NUM_PREV_ROOTS; | |
3897 | } | |
3898 | ||
be01e8e2 | 3899 | static bool fast_pgd_switch(struct kvm_vcpu *vcpu, gpa_t new_pgd, |
b869855b | 3900 | union kvm_mmu_page_role new_role) |
6aa8b732 | 3901 | { |
44dd3ffa | 3902 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
7c390d35 JS |
3903 | |
3904 | /* | |
3905 | * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid | |
3906 | * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs | |
3907 | * later if necessary. | |
3908 | */ | |
3909 | if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL && | |
b869855b | 3910 | mmu->root_level >= PT64_ROOT_4LEVEL) |
fe9304d3 | 3911 | return cached_root_available(vcpu, new_pgd, new_role); |
7c390d35 JS |
3912 | |
3913 | return false; | |
6aa8b732 AK |
3914 | } |
3915 | ||
be01e8e2 | 3916 | static void __kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd, |
ade61e28 | 3917 | union kvm_mmu_page_role new_role, |
4a632ac6 | 3918 | bool skip_tlb_flush, bool skip_mmu_sync) |
6aa8b732 | 3919 | { |
be01e8e2 | 3920 | if (!fast_pgd_switch(vcpu, new_pgd, new_role)) { |
b869855b SC |
3921 | kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, KVM_MMU_ROOT_CURRENT); |
3922 | return; | |
3923 | } | |
3924 | ||
3925 | /* | |
3926 | * It's possible that the cached previous root page is obsolete because | |
3927 | * of a change in the MMU generation number. However, changing the | |
3928 | * generation number is accompanied by KVM_REQ_MMU_RELOAD, which will | |
3929 | * free the root set here and allocate a new one. | |
3930 | */ | |
3931 | kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu); | |
3932 | ||
71fe7013 | 3933 | if (!skip_mmu_sync || force_flush_and_sync_on_reuse) |
b869855b | 3934 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
71fe7013 | 3935 | if (!skip_tlb_flush || force_flush_and_sync_on_reuse) |
b869855b | 3936 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
b869855b SC |
3937 | |
3938 | /* | |
3939 | * The last MMIO access's GVA and GPA are cached in the VCPU. When | |
3940 | * switching to a new CR3, that GVA->GPA mapping may no longer be | |
3941 | * valid. So clear any cached MMIO info even when we don't need to sync | |
3942 | * the shadow page tables. | |
3943 | */ | |
3944 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); | |
3945 | ||
daa5b6c1 BG |
3946 | /* |
3947 | * If this is a direct root page, it doesn't have a write flooding | |
3948 | * count. Otherwise, clear the write flooding count. | |
3949 | */ | |
3950 | if (!new_role.direct) | |
3951 | __clear_sp_write_flooding_count( | |
3952 | to_shadow_page(vcpu->arch.mmu->root_hpa)); | |
6aa8b732 AK |
3953 | } |
3954 | ||
be01e8e2 | 3955 | void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd, bool skip_tlb_flush, |
4a632ac6 | 3956 | bool skip_mmu_sync) |
0aab33e4 | 3957 | { |
be01e8e2 | 3958 | __kvm_mmu_new_pgd(vcpu, new_pgd, kvm_mmu_calc_root_page_role(vcpu), |
4a632ac6 | 3959 | skip_tlb_flush, skip_mmu_sync); |
0aab33e4 | 3960 | } |
be01e8e2 | 3961 | EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd); |
0aab33e4 | 3962 | |
5777ed34 JR |
3963 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
3964 | { | |
9f8fe504 | 3965 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
3966 | } |
3967 | ||
54bf36aa | 3968 | static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
0a2b64c5 | 3969 | unsigned int access, int *nr_present) |
ce88decf XG |
3970 | { |
3971 | if (unlikely(is_mmio_spte(*sptep))) { | |
3972 | if (gfn != get_mmio_spte_gfn(*sptep)) { | |
3973 | mmu_spte_clear_no_track(sptep); | |
3974 | return true; | |
3975 | } | |
3976 | ||
3977 | (*nr_present)++; | |
54bf36aa | 3978 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
3979 | return true; |
3980 | } | |
3981 | ||
3982 | return false; | |
3983 | } | |
3984 | ||
6bb69c9b PB |
3985 | static inline bool is_last_gpte(struct kvm_mmu *mmu, |
3986 | unsigned level, unsigned gpte) | |
6fd01b71 | 3987 | { |
6bb69c9b PB |
3988 | /* |
3989 | * The RHS has bit 7 set iff level < mmu->last_nonleaf_level. | |
3990 | * If it is clear, there are no large pages at this level, so clear | |
3991 | * PT_PAGE_SIZE_MASK in gpte if that is the case. | |
3992 | */ | |
3993 | gpte &= level - mmu->last_nonleaf_level; | |
3994 | ||
829ee279 | 3995 | /* |
3bae0459 SC |
3996 | * PG_LEVEL_4K always terminates. The RHS has bit 7 set |
3997 | * iff level <= PG_LEVEL_4K, which for our purpose means | |
3998 | * level == PG_LEVEL_4K; set PT_PAGE_SIZE_MASK in gpte then. | |
829ee279 | 3999 | */ |
3bae0459 | 4000 | gpte |= level - PG_LEVEL_4K - 1; |
829ee279 | 4001 | |
6bb69c9b | 4002 | return gpte & PT_PAGE_SIZE_MASK; |
6fd01b71 AK |
4003 | } |
4004 | ||
37406aaa NHE |
4005 | #define PTTYPE_EPT 18 /* arbitrary */ |
4006 | #define PTTYPE PTTYPE_EPT | |
4007 | #include "paging_tmpl.h" | |
4008 | #undef PTTYPE | |
4009 | ||
6aa8b732 AK |
4010 | #define PTTYPE 64 |
4011 | #include "paging_tmpl.h" | |
4012 | #undef PTTYPE | |
4013 | ||
4014 | #define PTTYPE 32 | |
4015 | #include "paging_tmpl.h" | |
4016 | #undef PTTYPE | |
4017 | ||
6dc98b86 XG |
4018 | static void |
4019 | __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, | |
4020 | struct rsvd_bits_validate *rsvd_check, | |
5b7f575c | 4021 | u64 pa_bits_rsvd, int level, bool nx, bool gbpages, |
6fec2144 | 4022 | bool pse, bool amd) |
82725b20 | 4023 | { |
5f7dde7b | 4024 | u64 gbpages_bit_rsvd = 0; |
a0c0feb5 | 4025 | u64 nonleaf_bit8_rsvd = 0; |
5b7f575c | 4026 | u64 high_bits_rsvd; |
82725b20 | 4027 | |
a0a64f50 | 4028 | rsvd_check->bad_mt_xwr = 0; |
25d92081 | 4029 | |
6dc98b86 | 4030 | if (!gbpages) |
5f7dde7b | 4031 | gbpages_bit_rsvd = rsvd_bits(7, 7); |
a0c0feb5 | 4032 | |
5b7f575c SC |
4033 | if (level == PT32E_ROOT_LEVEL) |
4034 | high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 62); | |
4035 | else | |
4036 | high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51); | |
4037 | ||
4038 | /* Note, NX doesn't exist in PDPTEs, this is handled below. */ | |
4039 | if (!nx) | |
4040 | high_bits_rsvd |= rsvd_bits(63, 63); | |
4041 | ||
a0c0feb5 PB |
4042 | /* |
4043 | * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for | |
4044 | * leaf entries) on AMD CPUs only. | |
4045 | */ | |
6fec2144 | 4046 | if (amd) |
a0c0feb5 PB |
4047 | nonleaf_bit8_rsvd = rsvd_bits(8, 8); |
4048 | ||
6dc98b86 | 4049 | switch (level) { |
82725b20 DE |
4050 | case PT32_ROOT_LEVEL: |
4051 | /* no rsvd bits for 2 level 4K page table entries */ | |
a0a64f50 XG |
4052 | rsvd_check->rsvd_bits_mask[0][1] = 0; |
4053 | rsvd_check->rsvd_bits_mask[0][0] = 0; | |
4054 | rsvd_check->rsvd_bits_mask[1][0] = | |
4055 | rsvd_check->rsvd_bits_mask[0][0]; | |
f815bce8 | 4056 | |
6dc98b86 | 4057 | if (!pse) { |
a0a64f50 | 4058 | rsvd_check->rsvd_bits_mask[1][1] = 0; |
f815bce8 XG |
4059 | break; |
4060 | } | |
4061 | ||
82725b20 DE |
4062 | if (is_cpuid_PSE36()) |
4063 | /* 36bits PSE 4MB page */ | |
a0a64f50 | 4064 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); |
82725b20 DE |
4065 | else |
4066 | /* 32 bits PSE 4MB page */ | |
a0a64f50 | 4067 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); |
82725b20 DE |
4068 | break; |
4069 | case PT32E_ROOT_LEVEL: | |
5b7f575c SC |
4070 | rsvd_check->rsvd_bits_mask[0][2] = rsvd_bits(63, 63) | |
4071 | high_bits_rsvd | | |
4072 | rsvd_bits(5, 8) | | |
4073 | rsvd_bits(1, 2); /* PDPTE */ | |
4074 | rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd; /* PDE */ | |
4075 | rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd; /* PTE */ | |
4076 | rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd | | |
4077 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
4078 | rsvd_check->rsvd_bits_mask[1][0] = |
4079 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 | 4080 | break; |
855feb67 | 4081 | case PT64_ROOT_5LEVEL: |
5b7f575c SC |
4082 | rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd | |
4083 | nonleaf_bit8_rsvd | | |
4084 | rsvd_bits(7, 7); | |
855feb67 YZ |
4085 | rsvd_check->rsvd_bits_mask[1][4] = |
4086 | rsvd_check->rsvd_bits_mask[0][4]; | |
df561f66 | 4087 | fallthrough; |
2a7266a8 | 4088 | case PT64_ROOT_4LEVEL: |
5b7f575c SC |
4089 | rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd | |
4090 | nonleaf_bit8_rsvd | | |
4091 | rsvd_bits(7, 7); | |
4092 | rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd | | |
4093 | gbpages_bit_rsvd; | |
4094 | rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd; | |
4095 | rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd; | |
a0a64f50 XG |
4096 | rsvd_check->rsvd_bits_mask[1][3] = |
4097 | rsvd_check->rsvd_bits_mask[0][3]; | |
5b7f575c SC |
4098 | rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd | |
4099 | gbpages_bit_rsvd | | |
4100 | rsvd_bits(13, 29); | |
4101 | rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd | | |
4102 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
4103 | rsvd_check->rsvd_bits_mask[1][0] = |
4104 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 DE |
4105 | break; |
4106 | } | |
4107 | } | |
4108 | ||
6dc98b86 XG |
4109 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
4110 | struct kvm_mmu *context) | |
4111 | { | |
4112 | __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check, | |
5b7f575c SC |
4113 | vcpu->arch.reserved_gpa_bits, |
4114 | context->root_level, context->nx, | |
d6321d49 | 4115 | guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES), |
23493d0a SC |
4116 | is_pse(vcpu), |
4117 | guest_cpuid_is_amd_or_hygon(vcpu)); | |
6dc98b86 XG |
4118 | } |
4119 | ||
81b8eebb XG |
4120 | static void |
4121 | __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check, | |
5b7f575c | 4122 | u64 pa_bits_rsvd, bool execonly) |
25d92081 | 4123 | { |
5b7f575c | 4124 | u64 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51); |
951f9fd7 | 4125 | u64 bad_mt_xwr; |
25d92081 | 4126 | |
5b7f575c SC |
4127 | rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd | rsvd_bits(3, 7); |
4128 | rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd | rsvd_bits(3, 7); | |
4129 | rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd | rsvd_bits(3, 6); | |
4130 | rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd | rsvd_bits(3, 6); | |
4131 | rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd; | |
25d92081 YZ |
4132 | |
4133 | /* large page */ | |
855feb67 | 4134 | rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4]; |
a0a64f50 | 4135 | rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3]; |
5b7f575c SC |
4136 | rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd | rsvd_bits(12, 29); |
4137 | rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd | rsvd_bits(12, 20); | |
a0a64f50 | 4138 | rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0]; |
25d92081 | 4139 | |
951f9fd7 PB |
4140 | bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */ |
4141 | bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */ | |
4142 | bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */ | |
4143 | bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */ | |
4144 | bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */ | |
4145 | if (!execonly) { | |
4146 | /* bits 0..2 must not be 100 unless VMX capabilities allow it */ | |
4147 | bad_mt_xwr |= REPEAT_BYTE(1ull << 4); | |
25d92081 | 4148 | } |
951f9fd7 | 4149 | rsvd_check->bad_mt_xwr = bad_mt_xwr; |
25d92081 YZ |
4150 | } |
4151 | ||
81b8eebb XG |
4152 | static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu, |
4153 | struct kvm_mmu *context, bool execonly) | |
4154 | { | |
4155 | __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check, | |
5b7f575c | 4156 | vcpu->arch.reserved_gpa_bits, execonly); |
81b8eebb XG |
4157 | } |
4158 | ||
6f8e65a6 SC |
4159 | static inline u64 reserved_hpa_bits(void) |
4160 | { | |
4161 | return rsvd_bits(shadow_phys_bits, 63); | |
4162 | } | |
4163 | ||
c258b62b XG |
4164 | /* |
4165 | * the page table on host is the shadow page table for the page | |
4166 | * table in guest or amd nested guest, its mmu features completely | |
4167 | * follow the features in guest. | |
4168 | */ | |
4169 | void | |
4170 | reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context) | |
4171 | { | |
36d9594d VK |
4172 | bool uses_nx = context->nx || |
4173 | context->mmu_role.base.smep_andnot_wp; | |
ea2800dd BS |
4174 | struct rsvd_bits_validate *shadow_zero_check; |
4175 | int i; | |
5f0b8199 | 4176 | |
6fec2144 PB |
4177 | /* |
4178 | * Passing "true" to the last argument is okay; it adds a check | |
4179 | * on bit 8 of the SPTEs which KVM doesn't use anyway. | |
4180 | */ | |
ea2800dd BS |
4181 | shadow_zero_check = &context->shadow_zero_check; |
4182 | __reset_rsvds_bits_mask(vcpu, shadow_zero_check, | |
6f8e65a6 | 4183 | reserved_hpa_bits(), |
5f0b8199 | 4184 | context->shadow_root_level, uses_nx, |
d6321d49 RK |
4185 | guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES), |
4186 | is_pse(vcpu), true); | |
ea2800dd BS |
4187 | |
4188 | if (!shadow_me_mask) | |
4189 | return; | |
4190 | ||
4191 | for (i = context->shadow_root_level; --i >= 0;) { | |
4192 | shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask; | |
4193 | shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask; | |
4194 | } | |
4195 | ||
c258b62b XG |
4196 | } |
4197 | EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask); | |
4198 | ||
6fec2144 PB |
4199 | static inline bool boot_cpu_is_amd(void) |
4200 | { | |
4201 | WARN_ON_ONCE(!tdp_enabled); | |
4202 | return shadow_x_mask == 0; | |
4203 | } | |
4204 | ||
c258b62b XG |
4205 | /* |
4206 | * the direct page table on host, use as much mmu features as | |
4207 | * possible, however, kvm currently does not do execution-protection. | |
4208 | */ | |
4209 | static void | |
4210 | reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4211 | struct kvm_mmu *context) | |
4212 | { | |
ea2800dd BS |
4213 | struct rsvd_bits_validate *shadow_zero_check; |
4214 | int i; | |
4215 | ||
4216 | shadow_zero_check = &context->shadow_zero_check; | |
4217 | ||
6fec2144 | 4218 | if (boot_cpu_is_amd()) |
ea2800dd | 4219 | __reset_rsvds_bits_mask(vcpu, shadow_zero_check, |
6f8e65a6 | 4220 | reserved_hpa_bits(), |
c258b62b | 4221 | context->shadow_root_level, false, |
b8291adc BP |
4222 | boot_cpu_has(X86_FEATURE_GBPAGES), |
4223 | true, true); | |
c258b62b | 4224 | else |
ea2800dd | 4225 | __reset_rsvds_bits_mask_ept(shadow_zero_check, |
6f8e65a6 | 4226 | reserved_hpa_bits(), false); |
c258b62b | 4227 | |
ea2800dd BS |
4228 | if (!shadow_me_mask) |
4229 | return; | |
4230 | ||
4231 | for (i = context->shadow_root_level; --i >= 0;) { | |
4232 | shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask; | |
4233 | shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask; | |
4234 | } | |
c258b62b XG |
4235 | } |
4236 | ||
4237 | /* | |
4238 | * as the comments in reset_shadow_zero_bits_mask() except it | |
4239 | * is the shadow page table for intel nested guest. | |
4240 | */ | |
4241 | static void | |
4242 | reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4243 | struct kvm_mmu *context, bool execonly) | |
4244 | { | |
4245 | __reset_rsvds_bits_mask_ept(&context->shadow_zero_check, | |
6f8e65a6 | 4246 | reserved_hpa_bits(), execonly); |
c258b62b XG |
4247 | } |
4248 | ||
09f037aa PB |
4249 | #define BYTE_MASK(access) \ |
4250 | ((1 & (access) ? 2 : 0) | \ | |
4251 | (2 & (access) ? 4 : 0) | \ | |
4252 | (3 & (access) ? 8 : 0) | \ | |
4253 | (4 & (access) ? 16 : 0) | \ | |
4254 | (5 & (access) ? 32 : 0) | \ | |
4255 | (6 & (access) ? 64 : 0) | \ | |
4256 | (7 & (access) ? 128 : 0)) | |
4257 | ||
4258 | ||
edc90b7d XG |
4259 | static void update_permission_bitmask(struct kvm_vcpu *vcpu, |
4260 | struct kvm_mmu *mmu, bool ept) | |
97d64b78 | 4261 | { |
09f037aa PB |
4262 | unsigned byte; |
4263 | ||
4264 | const u8 x = BYTE_MASK(ACC_EXEC_MASK); | |
4265 | const u8 w = BYTE_MASK(ACC_WRITE_MASK); | |
4266 | const u8 u = BYTE_MASK(ACC_USER_MASK); | |
4267 | ||
4268 | bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0; | |
4269 | bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0; | |
4270 | bool cr0_wp = is_write_protection(vcpu); | |
97d64b78 | 4271 | |
97d64b78 | 4272 | for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) { |
09f037aa PB |
4273 | unsigned pfec = byte << 1; |
4274 | ||
97ec8c06 | 4275 | /* |
09f037aa PB |
4276 | * Each "*f" variable has a 1 bit for each UWX value |
4277 | * that causes a fault with the given PFEC. | |
97ec8c06 | 4278 | */ |
97d64b78 | 4279 | |
09f037aa | 4280 | /* Faults from writes to non-writable pages */ |
a6a6d3b1 | 4281 | u8 wf = (pfec & PFERR_WRITE_MASK) ? (u8)~w : 0; |
09f037aa | 4282 | /* Faults from user mode accesses to supervisor pages */ |
a6a6d3b1 | 4283 | u8 uf = (pfec & PFERR_USER_MASK) ? (u8)~u : 0; |
09f037aa | 4284 | /* Faults from fetches of non-executable pages*/ |
a6a6d3b1 | 4285 | u8 ff = (pfec & PFERR_FETCH_MASK) ? (u8)~x : 0; |
09f037aa PB |
4286 | /* Faults from kernel mode fetches of user pages */ |
4287 | u8 smepf = 0; | |
4288 | /* Faults from kernel mode accesses of user pages */ | |
4289 | u8 smapf = 0; | |
4290 | ||
4291 | if (!ept) { | |
4292 | /* Faults from kernel mode accesses to user pages */ | |
4293 | u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u; | |
4294 | ||
4295 | /* Not really needed: !nx will cause pte.nx to fault */ | |
4296 | if (!mmu->nx) | |
4297 | ff = 0; | |
4298 | ||
4299 | /* Allow supervisor writes if !cr0.wp */ | |
4300 | if (!cr0_wp) | |
4301 | wf = (pfec & PFERR_USER_MASK) ? wf : 0; | |
4302 | ||
4303 | /* Disallow supervisor fetches of user code if cr4.smep */ | |
4304 | if (cr4_smep) | |
4305 | smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0; | |
4306 | ||
4307 | /* | |
4308 | * SMAP:kernel-mode data accesses from user-mode | |
4309 | * mappings should fault. A fault is considered | |
4310 | * as a SMAP violation if all of the following | |
39337ad1 | 4311 | * conditions are true: |
09f037aa PB |
4312 | * - X86_CR4_SMAP is set in CR4 |
4313 | * - A user page is accessed | |
4314 | * - The access is not a fetch | |
4315 | * - Page fault in kernel mode | |
4316 | * - if CPL = 3 or X86_EFLAGS_AC is clear | |
4317 | * | |
4318 | * Here, we cover the first three conditions. | |
4319 | * The fourth is computed dynamically in permission_fault(); | |
4320 | * PFERR_RSVD_MASK bit will be set in PFEC if the access is | |
4321 | * *not* subject to SMAP restrictions. | |
4322 | */ | |
4323 | if (cr4_smap) | |
4324 | smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf; | |
97d64b78 | 4325 | } |
09f037aa PB |
4326 | |
4327 | mmu->permissions[byte] = ff | uf | wf | smepf | smapf; | |
97d64b78 AK |
4328 | } |
4329 | } | |
4330 | ||
2d344105 HH |
4331 | /* |
4332 | * PKU is an additional mechanism by which the paging controls access to | |
4333 | * user-mode addresses based on the value in the PKRU register. Protection | |
4334 | * key violations are reported through a bit in the page fault error code. | |
4335 | * Unlike other bits of the error code, the PK bit is not known at the | |
4336 | * call site of e.g. gva_to_gpa; it must be computed directly in | |
4337 | * permission_fault based on two bits of PKRU, on some machine state (CR4, | |
4338 | * CR0, EFER, CPL), and on other bits of the error code and the page tables. | |
4339 | * | |
4340 | * In particular the following conditions come from the error code, the | |
4341 | * page tables and the machine state: | |
4342 | * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1 | |
4343 | * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch) | |
4344 | * - PK is always zero if U=0 in the page tables | |
4345 | * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access. | |
4346 | * | |
4347 | * The PKRU bitmask caches the result of these four conditions. The error | |
4348 | * code (minus the P bit) and the page table's U bit form an index into the | |
4349 | * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed | |
4350 | * with the two bits of the PKRU register corresponding to the protection key. | |
4351 | * For the first three conditions above the bits will be 00, thus masking | |
4352 | * away both AD and WD. For all reads or if the last condition holds, WD | |
4353 | * only will be masked away. | |
4354 | */ | |
4355 | static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
4356 | bool ept) | |
4357 | { | |
4358 | unsigned bit; | |
4359 | bool wp; | |
4360 | ||
4361 | if (ept) { | |
4362 | mmu->pkru_mask = 0; | |
4363 | return; | |
4364 | } | |
4365 | ||
4366 | /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */ | |
4367 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) { | |
4368 | mmu->pkru_mask = 0; | |
4369 | return; | |
4370 | } | |
4371 | ||
4372 | wp = is_write_protection(vcpu); | |
4373 | ||
4374 | for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) { | |
4375 | unsigned pfec, pkey_bits; | |
4376 | bool check_pkey, check_write, ff, uf, wf, pte_user; | |
4377 | ||
4378 | pfec = bit << 1; | |
4379 | ff = pfec & PFERR_FETCH_MASK; | |
4380 | uf = pfec & PFERR_USER_MASK; | |
4381 | wf = pfec & PFERR_WRITE_MASK; | |
4382 | ||
4383 | /* PFEC.RSVD is replaced by ACC_USER_MASK. */ | |
4384 | pte_user = pfec & PFERR_RSVD_MASK; | |
4385 | ||
4386 | /* | |
4387 | * Only need to check the access which is not an | |
4388 | * instruction fetch and is to a user page. | |
4389 | */ | |
4390 | check_pkey = (!ff && pte_user); | |
4391 | /* | |
4392 | * write access is controlled by PKRU if it is a | |
4393 | * user access or CR0.WP = 1. | |
4394 | */ | |
4395 | check_write = check_pkey && wf && (uf || wp); | |
4396 | ||
4397 | /* PKRU.AD stops both read and write access. */ | |
4398 | pkey_bits = !!check_pkey; | |
4399 | /* PKRU.WD stops write access. */ | |
4400 | pkey_bits |= (!!check_write) << 1; | |
4401 | ||
4402 | mmu->pkru_mask |= (pkey_bits & 3) << pfec; | |
4403 | } | |
4404 | } | |
4405 | ||
6bb69c9b | 4406 | static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
6fd01b71 | 4407 | { |
6bb69c9b PB |
4408 | unsigned root_level = mmu->root_level; |
4409 | ||
4410 | mmu->last_nonleaf_level = root_level; | |
4411 | if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu)) | |
4412 | mmu->last_nonleaf_level++; | |
6fd01b71 AK |
4413 | } |
4414 | ||
8a3c1a33 PB |
4415 | static void paging64_init_context_common(struct kvm_vcpu *vcpu, |
4416 | struct kvm_mmu *context, | |
4417 | int level) | |
6aa8b732 | 4418 | { |
2d48a985 | 4419 | context->nx = is_nx(vcpu); |
4d6931c3 | 4420 | context->root_level = level; |
2d48a985 | 4421 | |
4d6931c3 | 4422 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 4423 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4424 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4425 | update_last_nonleaf_level(vcpu, context); |
6aa8b732 | 4426 | |
fa4a2c08 | 4427 | MMU_WARN_ON(!is_pae(vcpu)); |
6aa8b732 | 4428 | context->page_fault = paging64_page_fault; |
6aa8b732 | 4429 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 4430 | context->sync_page = paging64_sync_page; |
a7052897 | 4431 | context->invlpg = paging64_invlpg; |
17ac10ad | 4432 | context->shadow_root_level = level; |
c5a78f2b | 4433 | context->direct_map = false; |
6aa8b732 AK |
4434 | } |
4435 | ||
8a3c1a33 PB |
4436 | static void paging64_init_context(struct kvm_vcpu *vcpu, |
4437 | struct kvm_mmu *context) | |
17ac10ad | 4438 | { |
855feb67 YZ |
4439 | int root_level = is_la57_mode(vcpu) ? |
4440 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4441 | ||
4442 | paging64_init_context_common(vcpu, context, root_level); | |
17ac10ad AK |
4443 | } |
4444 | ||
8a3c1a33 PB |
4445 | static void paging32_init_context(struct kvm_vcpu *vcpu, |
4446 | struct kvm_mmu *context) | |
6aa8b732 | 4447 | { |
2d48a985 | 4448 | context->nx = false; |
4d6931c3 | 4449 | context->root_level = PT32_ROOT_LEVEL; |
2d48a985 | 4450 | |
4d6931c3 | 4451 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 4452 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4453 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4454 | update_last_nonleaf_level(vcpu, context); |
6aa8b732 | 4455 | |
6aa8b732 | 4456 | context->page_fault = paging32_page_fault; |
6aa8b732 | 4457 | context->gva_to_gpa = paging32_gva_to_gpa; |
e8bc217a | 4458 | context->sync_page = paging32_sync_page; |
a7052897 | 4459 | context->invlpg = paging32_invlpg; |
6aa8b732 | 4460 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
c5a78f2b | 4461 | context->direct_map = false; |
6aa8b732 AK |
4462 | } |
4463 | ||
8a3c1a33 PB |
4464 | static void paging32E_init_context(struct kvm_vcpu *vcpu, |
4465 | struct kvm_mmu *context) | |
6aa8b732 | 4466 | { |
8a3c1a33 | 4467 | paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
4468 | } |
4469 | ||
a336282d VK |
4470 | static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu) |
4471 | { | |
4472 | union kvm_mmu_extended_role ext = {0}; | |
4473 | ||
7dcd5755 | 4474 | ext.cr0_pg = !!is_paging(vcpu); |
0699c64a | 4475 | ext.cr4_pae = !!is_pae(vcpu); |
a336282d VK |
4476 | ext.cr4_smep = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
4477 | ext.cr4_smap = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMAP); | |
4478 | ext.cr4_pse = !!is_pse(vcpu); | |
4479 | ext.cr4_pke = !!kvm_read_cr4_bits(vcpu, X86_CR4_PKE); | |
de3ccd26 | 4480 | ext.maxphyaddr = cpuid_maxphyaddr(vcpu); |
a336282d VK |
4481 | |
4482 | ext.valid = 1; | |
4483 | ||
4484 | return ext; | |
4485 | } | |
4486 | ||
7dcd5755 VK |
4487 | static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu, |
4488 | bool base_only) | |
4489 | { | |
4490 | union kvm_mmu_role role = {0}; | |
4491 | ||
4492 | role.base.access = ACC_ALL; | |
4493 | role.base.nxe = !!is_nx(vcpu); | |
7dcd5755 VK |
4494 | role.base.cr0_wp = is_write_protection(vcpu); |
4495 | role.base.smm = is_smm(vcpu); | |
4496 | role.base.guest_mode = is_guest_mode(vcpu); | |
4497 | ||
4498 | if (base_only) | |
4499 | return role; | |
4500 | ||
4501 | role.ext = kvm_calc_mmu_role_ext(vcpu); | |
4502 | ||
4503 | return role; | |
4504 | } | |
4505 | ||
d468d94b SC |
4506 | static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu *vcpu) |
4507 | { | |
4508 | /* Use 5-level TDP if and only if it's useful/necessary. */ | |
83013059 | 4509 | if (max_tdp_level == 5 && cpuid_maxphyaddr(vcpu) <= 48) |
d468d94b SC |
4510 | return 4; |
4511 | ||
83013059 | 4512 | return max_tdp_level; |
d468d94b SC |
4513 | } |
4514 | ||
7dcd5755 VK |
4515 | static union kvm_mmu_role |
4516 | kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only) | |
9fa72119 | 4517 | { |
7dcd5755 | 4518 | union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only); |
9fa72119 | 4519 | |
7dcd5755 | 4520 | role.base.ad_disabled = (shadow_accessed_mask == 0); |
d468d94b | 4521 | role.base.level = kvm_mmu_get_tdp_level(vcpu); |
7dcd5755 | 4522 | role.base.direct = true; |
47c42e6b | 4523 | role.base.gpte_is_8_bytes = true; |
9fa72119 JS |
4524 | |
4525 | return role; | |
4526 | } | |
4527 | ||
8a3c1a33 | 4528 | static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 4529 | { |
8c008659 | 4530 | struct kvm_mmu *context = &vcpu->arch.root_mmu; |
7dcd5755 VK |
4531 | union kvm_mmu_role new_role = |
4532 | kvm_calc_tdp_mmu_root_page_role(vcpu, false); | |
fb72d167 | 4533 | |
7dcd5755 VK |
4534 | if (new_role.as_u64 == context->mmu_role.as_u64) |
4535 | return; | |
4536 | ||
4537 | context->mmu_role.as_u64 = new_role.as_u64; | |
7a02674d | 4538 | context->page_fault = kvm_tdp_page_fault; |
e8bc217a | 4539 | context->sync_page = nonpaging_sync_page; |
5efac074 | 4540 | context->invlpg = NULL; |
d468d94b | 4541 | context->shadow_root_level = kvm_mmu_get_tdp_level(vcpu); |
c5a78f2b | 4542 | context->direct_map = true; |
d8dd54e0 | 4543 | context->get_guest_pgd = get_cr3; |
e4e517b4 | 4544 | context->get_pdptr = kvm_pdptr_read; |
cb659db8 | 4545 | context->inject_page_fault = kvm_inject_page_fault; |
fb72d167 JR |
4546 | |
4547 | if (!is_paging(vcpu)) { | |
2d48a985 | 4548 | context->nx = false; |
fb72d167 JR |
4549 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
4550 | context->root_level = 0; | |
4551 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 4552 | context->nx = is_nx(vcpu); |
855feb67 YZ |
4553 | context->root_level = is_la57_mode(vcpu) ? |
4554 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4d6931c3 DB |
4555 | reset_rsvds_bits_mask(vcpu, context); |
4556 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4557 | } else if (is_pae(vcpu)) { |
2d48a985 | 4558 | context->nx = is_nx(vcpu); |
fb72d167 | 4559 | context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 DB |
4560 | reset_rsvds_bits_mask(vcpu, context); |
4561 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4562 | } else { |
2d48a985 | 4563 | context->nx = false; |
fb72d167 | 4564 | context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 DB |
4565 | reset_rsvds_bits_mask(vcpu, context); |
4566 | context->gva_to_gpa = paging32_gva_to_gpa; | |
fb72d167 JR |
4567 | } |
4568 | ||
25d92081 | 4569 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4570 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4571 | update_last_nonleaf_level(vcpu, context); |
c258b62b | 4572 | reset_tdp_shadow_zero_bits_mask(vcpu, context); |
fb72d167 JR |
4573 | } |
4574 | ||
7dcd5755 | 4575 | static union kvm_mmu_role |
59505b55 | 4576 | kvm_calc_shadow_root_page_role_common(struct kvm_vcpu *vcpu, bool base_only) |
7dcd5755 VK |
4577 | { |
4578 | union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only); | |
4579 | ||
4580 | role.base.smep_andnot_wp = role.ext.cr4_smep && | |
4581 | !is_write_protection(vcpu); | |
4582 | role.base.smap_andnot_wp = role.ext.cr4_smap && | |
4583 | !is_write_protection(vcpu); | |
47c42e6b | 4584 | role.base.gpte_is_8_bytes = !!is_pae(vcpu); |
9fa72119 | 4585 | |
59505b55 SC |
4586 | return role; |
4587 | } | |
4588 | ||
4589 | static union kvm_mmu_role | |
4590 | kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only) | |
4591 | { | |
4592 | union kvm_mmu_role role = | |
4593 | kvm_calc_shadow_root_page_role_common(vcpu, base_only); | |
4594 | ||
4595 | role.base.direct = !is_paging(vcpu); | |
4596 | ||
9fa72119 | 4597 | if (!is_long_mode(vcpu)) |
7dcd5755 | 4598 | role.base.level = PT32E_ROOT_LEVEL; |
9fa72119 | 4599 | else if (is_la57_mode(vcpu)) |
7dcd5755 | 4600 | role.base.level = PT64_ROOT_5LEVEL; |
9fa72119 | 4601 | else |
7dcd5755 | 4602 | role.base.level = PT64_ROOT_4LEVEL; |
9fa72119 JS |
4603 | |
4604 | return role; | |
4605 | } | |
4606 | ||
8c008659 PB |
4607 | static void shadow_mmu_init_context(struct kvm_vcpu *vcpu, struct kvm_mmu *context, |
4608 | u32 cr0, u32 cr4, u32 efer, | |
4609 | union kvm_mmu_role new_role) | |
9fa72119 | 4610 | { |
929d1cfa | 4611 | if (!(cr0 & X86_CR0_PG)) |
8a3c1a33 | 4612 | nonpaging_init_context(vcpu, context); |
929d1cfa | 4613 | else if (efer & EFER_LMA) |
8a3c1a33 | 4614 | paging64_init_context(vcpu, context); |
929d1cfa | 4615 | else if (cr4 & X86_CR4_PAE) |
8a3c1a33 | 4616 | paging32E_init_context(vcpu, context); |
6aa8b732 | 4617 | else |
8a3c1a33 | 4618 | paging32_init_context(vcpu, context); |
a770f6f2 | 4619 | |
7dcd5755 | 4620 | context->mmu_role.as_u64 = new_role.as_u64; |
c258b62b | 4621 | reset_shadow_zero_bits_mask(vcpu, context); |
52fde8df | 4622 | } |
0f04a2ac VK |
4623 | |
4624 | static void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, u32 cr0, u32 cr4, u32 efer) | |
4625 | { | |
8c008659 | 4626 | struct kvm_mmu *context = &vcpu->arch.root_mmu; |
0f04a2ac VK |
4627 | union kvm_mmu_role new_role = |
4628 | kvm_calc_shadow_mmu_root_page_role(vcpu, false); | |
4629 | ||
4630 | if (new_role.as_u64 != context->mmu_role.as_u64) | |
8c008659 | 4631 | shadow_mmu_init_context(vcpu, context, cr0, cr4, efer, new_role); |
0f04a2ac VK |
4632 | } |
4633 | ||
59505b55 SC |
4634 | static union kvm_mmu_role |
4635 | kvm_calc_shadow_npt_root_page_role(struct kvm_vcpu *vcpu) | |
4636 | { | |
4637 | union kvm_mmu_role role = | |
4638 | kvm_calc_shadow_root_page_role_common(vcpu, false); | |
4639 | ||
4640 | role.base.direct = false; | |
d468d94b | 4641 | role.base.level = kvm_mmu_get_tdp_level(vcpu); |
59505b55 SC |
4642 | |
4643 | return role; | |
4644 | } | |
4645 | ||
0f04a2ac VK |
4646 | void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, u32 cr0, u32 cr4, u32 efer, |
4647 | gpa_t nested_cr3) | |
4648 | { | |
8c008659 | 4649 | struct kvm_mmu *context = &vcpu->arch.guest_mmu; |
59505b55 | 4650 | union kvm_mmu_role new_role = kvm_calc_shadow_npt_root_page_role(vcpu); |
0f04a2ac | 4651 | |
096586fd SC |
4652 | context->shadow_root_level = new_role.base.level; |
4653 | ||
a506fdd2 VK |
4654 | __kvm_mmu_new_pgd(vcpu, nested_cr3, new_role.base, false, false); |
4655 | ||
0f04a2ac | 4656 | if (new_role.as_u64 != context->mmu_role.as_u64) |
8c008659 | 4657 | shadow_mmu_init_context(vcpu, context, cr0, cr4, efer, new_role); |
0f04a2ac VK |
4658 | } |
4659 | EXPORT_SYMBOL_GPL(kvm_init_shadow_npt_mmu); | |
52fde8df | 4660 | |
a336282d VK |
4661 | static union kvm_mmu_role |
4662 | kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty, | |
bb1fcc70 | 4663 | bool execonly, u8 level) |
9fa72119 | 4664 | { |
552c69b1 | 4665 | union kvm_mmu_role role = {0}; |
14c07ad8 | 4666 | |
47c42e6b SC |
4667 | /* SMM flag is inherited from root_mmu */ |
4668 | role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm; | |
9fa72119 | 4669 | |
bb1fcc70 | 4670 | role.base.level = level; |
47c42e6b | 4671 | role.base.gpte_is_8_bytes = true; |
a336282d VK |
4672 | role.base.direct = false; |
4673 | role.base.ad_disabled = !accessed_dirty; | |
4674 | role.base.guest_mode = true; | |
4675 | role.base.access = ACC_ALL; | |
9fa72119 | 4676 | |
47c42e6b SC |
4677 | /* |
4678 | * WP=1 and NOT_WP=1 is an impossible combination, use WP and the | |
4679 | * SMAP variation to denote shadow EPT entries. | |
4680 | */ | |
4681 | role.base.cr0_wp = true; | |
4682 | role.base.smap_andnot_wp = true; | |
4683 | ||
552c69b1 | 4684 | role.ext = kvm_calc_mmu_role_ext(vcpu); |
a336282d | 4685 | role.ext.execonly = execonly; |
9fa72119 JS |
4686 | |
4687 | return role; | |
4688 | } | |
4689 | ||
ae1e2d10 | 4690 | void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly, |
50c28f21 | 4691 | bool accessed_dirty, gpa_t new_eptp) |
155a97a3 | 4692 | { |
8c008659 | 4693 | struct kvm_mmu *context = &vcpu->arch.guest_mmu; |
bb1fcc70 | 4694 | u8 level = vmx_eptp_page_walk_level(new_eptp); |
a336282d VK |
4695 | union kvm_mmu_role new_role = |
4696 | kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty, | |
bb1fcc70 | 4697 | execonly, level); |
a336282d | 4698 | |
be01e8e2 | 4699 | __kvm_mmu_new_pgd(vcpu, new_eptp, new_role.base, true, true); |
a336282d | 4700 | |
a336282d VK |
4701 | if (new_role.as_u64 == context->mmu_role.as_u64) |
4702 | return; | |
ad896af0 | 4703 | |
bb1fcc70 | 4704 | context->shadow_root_level = level; |
155a97a3 NHE |
4705 | |
4706 | context->nx = true; | |
ae1e2d10 | 4707 | context->ept_ad = accessed_dirty; |
155a97a3 NHE |
4708 | context->page_fault = ept_page_fault; |
4709 | context->gva_to_gpa = ept_gva_to_gpa; | |
4710 | context->sync_page = ept_sync_page; | |
4711 | context->invlpg = ept_invlpg; | |
bb1fcc70 | 4712 | context->root_level = level; |
155a97a3 | 4713 | context->direct_map = false; |
a336282d | 4714 | context->mmu_role.as_u64 = new_role.as_u64; |
3dc773e7 | 4715 | |
155a97a3 | 4716 | update_permission_bitmask(vcpu, context, true); |
2d344105 | 4717 | update_pkru_bitmask(vcpu, context, true); |
fd19d3b4 | 4718 | update_last_nonleaf_level(vcpu, context); |
155a97a3 | 4719 | reset_rsvds_bits_mask_ept(vcpu, context, execonly); |
c258b62b | 4720 | reset_ept_shadow_zero_bits_mask(vcpu, context, execonly); |
155a97a3 NHE |
4721 | } |
4722 | EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu); | |
4723 | ||
8a3c1a33 | 4724 | static void init_kvm_softmmu(struct kvm_vcpu *vcpu) |
52fde8df | 4725 | { |
8c008659 | 4726 | struct kvm_mmu *context = &vcpu->arch.root_mmu; |
ad896af0 | 4727 | |
929d1cfa PB |
4728 | kvm_init_shadow_mmu(vcpu, |
4729 | kvm_read_cr0_bits(vcpu, X86_CR0_PG), | |
4730 | kvm_read_cr4_bits(vcpu, X86_CR4_PAE), | |
4731 | vcpu->arch.efer); | |
4732 | ||
d8dd54e0 | 4733 | context->get_guest_pgd = get_cr3; |
ad896af0 PB |
4734 | context->get_pdptr = kvm_pdptr_read; |
4735 | context->inject_page_fault = kvm_inject_page_fault; | |
6aa8b732 AK |
4736 | } |
4737 | ||
8a3c1a33 | 4738 | static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
02f59dc9 | 4739 | { |
bf627a92 | 4740 | union kvm_mmu_role new_role = kvm_calc_mmu_role_common(vcpu, false); |
02f59dc9 JR |
4741 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; |
4742 | ||
bf627a92 VK |
4743 | if (new_role.as_u64 == g_context->mmu_role.as_u64) |
4744 | return; | |
4745 | ||
4746 | g_context->mmu_role.as_u64 = new_role.as_u64; | |
d8dd54e0 | 4747 | g_context->get_guest_pgd = get_cr3; |
e4e517b4 | 4748 | g_context->get_pdptr = kvm_pdptr_read; |
02f59dc9 JR |
4749 | g_context->inject_page_fault = kvm_inject_page_fault; |
4750 | ||
5efac074 PB |
4751 | /* |
4752 | * L2 page tables are never shadowed, so there is no need to sync | |
4753 | * SPTEs. | |
4754 | */ | |
4755 | g_context->invlpg = NULL; | |
4756 | ||
02f59dc9 | 4757 | /* |
44dd3ffa | 4758 | * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using |
0af2593b DM |
4759 | * L1's nested page tables (e.g. EPT12). The nested translation |
4760 | * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using | |
4761 | * L2's page tables as the first level of translation and L1's | |
4762 | * nested page tables as the second level of translation. Basically | |
4763 | * the gva_to_gpa functions between mmu and nested_mmu are swapped. | |
02f59dc9 JR |
4764 | */ |
4765 | if (!is_paging(vcpu)) { | |
2d48a985 | 4766 | g_context->nx = false; |
02f59dc9 JR |
4767 | g_context->root_level = 0; |
4768 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
4769 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 4770 | g_context->nx = is_nx(vcpu); |
855feb67 YZ |
4771 | g_context->root_level = is_la57_mode(vcpu) ? |
4772 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4d6931c3 | 4773 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4774 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
4775 | } else if (is_pae(vcpu)) { | |
2d48a985 | 4776 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 4777 | g_context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 | 4778 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4779 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
4780 | } else { | |
2d48a985 | 4781 | g_context->nx = false; |
02f59dc9 | 4782 | g_context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 | 4783 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4784 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; |
4785 | } | |
4786 | ||
25d92081 | 4787 | update_permission_bitmask(vcpu, g_context, false); |
2d344105 | 4788 | update_pkru_bitmask(vcpu, g_context, false); |
6bb69c9b | 4789 | update_last_nonleaf_level(vcpu, g_context); |
02f59dc9 JR |
4790 | } |
4791 | ||
1c53da3f | 4792 | void kvm_init_mmu(struct kvm_vcpu *vcpu, bool reset_roots) |
fb72d167 | 4793 | { |
1c53da3f | 4794 | if (reset_roots) { |
b94742c9 JS |
4795 | uint i; |
4796 | ||
44dd3ffa | 4797 | vcpu->arch.mmu->root_hpa = INVALID_PAGE; |
b94742c9 JS |
4798 | |
4799 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
44dd3ffa | 4800 | vcpu->arch.mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID; |
1c53da3f JS |
4801 | } |
4802 | ||
02f59dc9 | 4803 | if (mmu_is_nested(vcpu)) |
e0c6db3e | 4804 | init_kvm_nested_mmu(vcpu); |
02f59dc9 | 4805 | else if (tdp_enabled) |
e0c6db3e | 4806 | init_kvm_tdp_mmu(vcpu); |
fb72d167 | 4807 | else |
e0c6db3e | 4808 | init_kvm_softmmu(vcpu); |
fb72d167 | 4809 | } |
1c53da3f | 4810 | EXPORT_SYMBOL_GPL(kvm_init_mmu); |
fb72d167 | 4811 | |
9fa72119 JS |
4812 | static union kvm_mmu_page_role |
4813 | kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu) | |
4814 | { | |
7dcd5755 VK |
4815 | union kvm_mmu_role role; |
4816 | ||
9fa72119 | 4817 | if (tdp_enabled) |
7dcd5755 | 4818 | role = kvm_calc_tdp_mmu_root_page_role(vcpu, true); |
9fa72119 | 4819 | else |
7dcd5755 VK |
4820 | role = kvm_calc_shadow_mmu_root_page_role(vcpu, true); |
4821 | ||
4822 | return role.base; | |
9fa72119 | 4823 | } |
fb72d167 | 4824 | |
8a3c1a33 | 4825 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu) |
6aa8b732 | 4826 | { |
95f93af4 | 4827 | kvm_mmu_unload(vcpu); |
1c53da3f | 4828 | kvm_init_mmu(vcpu, true); |
17c3ba9d | 4829 | } |
8668a3c4 | 4830 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
4831 | |
4832 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 4833 | { |
714b93da AK |
4834 | int r; |
4835 | ||
378f5cd6 | 4836 | r = mmu_topup_memory_caches(vcpu, !vcpu->arch.mmu->direct_map); |
748e52b9 SC |
4837 | if (r) |
4838 | goto out; | |
4839 | r = mmu_alloc_special_roots(vcpu); | |
17c3ba9d AK |
4840 | if (r) |
4841 | goto out; | |
6e6ec584 SC |
4842 | write_lock(&vcpu->kvm->mmu_lock); |
4843 | if (make_mmu_pages_available(vcpu)) | |
4844 | r = -ENOSPC; | |
4845 | else if (vcpu->arch.mmu->direct_map) | |
4846 | r = mmu_alloc_direct_roots(vcpu); | |
4847 | else | |
4848 | r = mmu_alloc_shadow_roots(vcpu); | |
4849 | write_unlock(&vcpu->kvm->mmu_lock); | |
8986ecc0 MT |
4850 | if (r) |
4851 | goto out; | |
a91f387b SC |
4852 | |
4853 | kvm_mmu_sync_roots(vcpu); | |
4854 | ||
727a7e27 | 4855 | kvm_mmu_load_pgd(vcpu); |
b3646477 | 4856 | static_call(kvm_x86_tlb_flush_current)(vcpu); |
714b93da AK |
4857 | out: |
4858 | return r; | |
6aa8b732 | 4859 | } |
17c3ba9d AK |
4860 | |
4861 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
4862 | { | |
14c07ad8 VK |
4863 | kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL); |
4864 | WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa)); | |
4865 | kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL); | |
4866 | WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa)); | |
17c3ba9d | 4867 | } |
6aa8b732 | 4868 | |
79539cec AK |
4869 | static bool need_remote_flush(u64 old, u64 new) |
4870 | { | |
4871 | if (!is_shadow_present_pte(old)) | |
4872 | return false; | |
4873 | if (!is_shadow_present_pte(new)) | |
4874 | return true; | |
4875 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
4876 | return true; | |
53166229 GN |
4877 | old ^= shadow_nx_mask; |
4878 | new ^= shadow_nx_mask; | |
79539cec AK |
4879 | return (old & ~new & PT64_PERM_MASK) != 0; |
4880 | } | |
4881 | ||
889e5cbc | 4882 | static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, |
0e0fee5c | 4883 | int *bytes) |
da4a00f0 | 4884 | { |
0e0fee5c | 4885 | u64 gentry = 0; |
889e5cbc | 4886 | int r; |
72016f3a | 4887 | |
72016f3a AK |
4888 | /* |
4889 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
4890 | * as the current vcpu paging mode since we update the sptes only |
4891 | * when they have the same mode. | |
72016f3a | 4892 | */ |
889e5cbc | 4893 | if (is_pae(vcpu) && *bytes == 4) { |
72016f3a | 4894 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
889e5cbc XG |
4895 | *gpa &= ~(gpa_t)7; |
4896 | *bytes = 8; | |
08e850c6 AK |
4897 | } |
4898 | ||
0e0fee5c JS |
4899 | if (*bytes == 4 || *bytes == 8) { |
4900 | r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes); | |
4901 | if (r) | |
4902 | gentry = 0; | |
72016f3a AK |
4903 | } |
4904 | ||
889e5cbc XG |
4905 | return gentry; |
4906 | } | |
4907 | ||
4908 | /* | |
4909 | * If we're seeing too many writes to a page, it may no longer be a page table, | |
4910 | * or we may be forking, in which case it is better to unmap the page. | |
4911 | */ | |
a138fe75 | 4912 | static bool detect_write_flooding(struct kvm_mmu_page *sp) |
889e5cbc | 4913 | { |
a30f47cb XG |
4914 | /* |
4915 | * Skip write-flooding detected for the sp whose level is 1, because | |
4916 | * it can become unsync, then the guest page is not write-protected. | |
4917 | */ | |
3bae0459 | 4918 | if (sp->role.level == PG_LEVEL_4K) |
a30f47cb | 4919 | return false; |
3246af0e | 4920 | |
e5691a81 XG |
4921 | atomic_inc(&sp->write_flooding_count); |
4922 | return atomic_read(&sp->write_flooding_count) >= 3; | |
889e5cbc XG |
4923 | } |
4924 | ||
4925 | /* | |
4926 | * Misaligned accesses are too much trouble to fix up; also, they usually | |
4927 | * indicate a page is not used as a page table. | |
4928 | */ | |
4929 | static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa, | |
4930 | int bytes) | |
4931 | { | |
4932 | unsigned offset, pte_size, misaligned; | |
4933 | ||
4934 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
4935 | gpa, bytes, sp->role.word); | |
4936 | ||
4937 | offset = offset_in_page(gpa); | |
47c42e6b | 4938 | pte_size = sp->role.gpte_is_8_bytes ? 8 : 4; |
5d9ca30e XG |
4939 | |
4940 | /* | |
4941 | * Sometimes, the OS only writes the last one bytes to update status | |
4942 | * bits, for example, in linux, andb instruction is used in clear_bit(). | |
4943 | */ | |
4944 | if (!(offset & (pte_size - 1)) && bytes == 1) | |
4945 | return false; | |
4946 | ||
889e5cbc XG |
4947 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
4948 | misaligned |= bytes < 4; | |
4949 | ||
4950 | return misaligned; | |
4951 | } | |
4952 | ||
4953 | static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte) | |
4954 | { | |
4955 | unsigned page_offset, quadrant; | |
4956 | u64 *spte; | |
4957 | int level; | |
4958 | ||
4959 | page_offset = offset_in_page(gpa); | |
4960 | level = sp->role.level; | |
4961 | *nspte = 1; | |
47c42e6b | 4962 | if (!sp->role.gpte_is_8_bytes) { |
889e5cbc XG |
4963 | page_offset <<= 1; /* 32->64 */ |
4964 | /* | |
4965 | * A 32-bit pde maps 4MB while the shadow pdes map | |
4966 | * only 2MB. So we need to double the offset again | |
4967 | * and zap two pdes instead of one. | |
4968 | */ | |
4969 | if (level == PT32_ROOT_LEVEL) { | |
4970 | page_offset &= ~7; /* kill rounding error */ | |
4971 | page_offset <<= 1; | |
4972 | *nspte = 2; | |
4973 | } | |
4974 | quadrant = page_offset >> PAGE_SHIFT; | |
4975 | page_offset &= ~PAGE_MASK; | |
4976 | if (quadrant != sp->role.quadrant) | |
4977 | return NULL; | |
4978 | } | |
4979 | ||
4980 | spte = &sp->spt[page_offset / sizeof(*spte)]; | |
4981 | return spte; | |
4982 | } | |
4983 | ||
13d268ca | 4984 | static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
d126363d JS |
4985 | const u8 *new, int bytes, |
4986 | struct kvm_page_track_notifier_node *node) | |
889e5cbc XG |
4987 | { |
4988 | gfn_t gfn = gpa >> PAGE_SHIFT; | |
889e5cbc | 4989 | struct kvm_mmu_page *sp; |
889e5cbc XG |
4990 | LIST_HEAD(invalid_list); |
4991 | u64 entry, gentry, *spte; | |
4992 | int npte; | |
b8c67b7a | 4993 | bool remote_flush, local_flush; |
889e5cbc XG |
4994 | |
4995 | /* | |
4996 | * If we don't have indirect shadow pages, it means no page is | |
4997 | * write-protected, so we can exit simply. | |
4998 | */ | |
6aa7de05 | 4999 | if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) |
889e5cbc XG |
5000 | return; |
5001 | ||
b8c67b7a | 5002 | remote_flush = local_flush = false; |
889e5cbc XG |
5003 | |
5004 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); | |
5005 | ||
889e5cbc XG |
5006 | /* |
5007 | * No need to care whether allocation memory is successful | |
5008 | * or not since pte prefetch is skiped if it does not have | |
5009 | * enough objects in the cache. | |
5010 | */ | |
378f5cd6 | 5011 | mmu_topup_memory_caches(vcpu, true); |
889e5cbc | 5012 | |
531810ca | 5013 | write_lock(&vcpu->kvm->mmu_lock); |
0e0fee5c JS |
5014 | |
5015 | gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes); | |
5016 | ||
889e5cbc | 5017 | ++vcpu->kvm->stat.mmu_pte_write; |
0375f7fa | 5018 | kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
889e5cbc | 5019 | |
b67bfe0d | 5020 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
a30f47cb | 5021 | if (detect_write_misaligned(sp, gpa, bytes) || |
a138fe75 | 5022 | detect_write_flooding(sp)) { |
b8c67b7a | 5023 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
4cee5764 | 5024 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
5025 | continue; |
5026 | } | |
889e5cbc XG |
5027 | |
5028 | spte = get_written_sptes(sp, gpa, &npte); | |
5029 | if (!spte) | |
5030 | continue; | |
5031 | ||
0671a8e7 | 5032 | local_flush = true; |
ac1b714e | 5033 | while (npte--) { |
79539cec | 5034 | entry = *spte; |
2de4085c | 5035 | mmu_page_zap_pte(vcpu->kvm, sp, spte, NULL); |
c5e2184d SC |
5036 | if (gentry && sp->role.level != PG_LEVEL_4K) |
5037 | ++vcpu->kvm->stat.mmu_pde_zapped; | |
9bb4f6b1 | 5038 | if (need_remote_flush(entry, *spte)) |
0671a8e7 | 5039 | remote_flush = true; |
ac1b714e | 5040 | ++spte; |
9b7a0325 | 5041 | } |
9b7a0325 | 5042 | } |
b8c67b7a | 5043 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush); |
0375f7fa | 5044 | kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
531810ca | 5045 | write_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
5046 | } |
5047 | ||
736c291c | 5048 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code, |
dc25e89e | 5049 | void *insn, int insn_len) |
3067714c | 5050 | { |
92daa48b | 5051 | int r, emulation_type = EMULTYPE_PF; |
44dd3ffa | 5052 | bool direct = vcpu->arch.mmu->direct_map; |
3067714c | 5053 | |
6948199a | 5054 | if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa))) |
ddce6208 SC |
5055 | return RET_PF_RETRY; |
5056 | ||
9b8ebbdb | 5057 | r = RET_PF_INVALID; |
e9ee956e | 5058 | if (unlikely(error_code & PFERR_RSVD_MASK)) { |
736c291c | 5059 | r = handle_mmio_page_fault(vcpu, cr2_or_gpa, direct); |
472faffa | 5060 | if (r == RET_PF_EMULATE) |
e9ee956e | 5061 | goto emulate; |
e9ee956e | 5062 | } |
3067714c | 5063 | |
9b8ebbdb | 5064 | if (r == RET_PF_INVALID) { |
7a02674d SC |
5065 | r = kvm_mmu_do_page_fault(vcpu, cr2_or_gpa, |
5066 | lower_32_bits(error_code), false); | |
7b367bc9 SC |
5067 | if (WARN_ON_ONCE(r == RET_PF_INVALID)) |
5068 | return -EIO; | |
9b8ebbdb PB |
5069 | } |
5070 | ||
3067714c | 5071 | if (r < 0) |
e9ee956e | 5072 | return r; |
83a2ba4c SC |
5073 | if (r != RET_PF_EMULATE) |
5074 | return 1; | |
3067714c | 5075 | |
14727754 TL |
5076 | /* |
5077 | * Before emulating the instruction, check if the error code | |
5078 | * was due to a RO violation while translating the guest page. | |
5079 | * This can occur when using nested virtualization with nested | |
5080 | * paging in both guests. If true, we simply unprotect the page | |
5081 | * and resume the guest. | |
14727754 | 5082 | */ |
44dd3ffa | 5083 | if (vcpu->arch.mmu->direct_map && |
eebed243 | 5084 | (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) { |
736c291c | 5085 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2_or_gpa)); |
14727754 TL |
5086 | return 1; |
5087 | } | |
5088 | ||
472faffa SC |
5089 | /* |
5090 | * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still | |
5091 | * optimistically try to just unprotect the page and let the processor | |
5092 | * re-execute the instruction that caused the page fault. Do not allow | |
5093 | * retrying MMIO emulation, as it's not only pointless but could also | |
5094 | * cause us to enter an infinite loop because the processor will keep | |
6c3dfeb6 SC |
5095 | * faulting on the non-existent MMIO address. Retrying an instruction |
5096 | * from a nested guest is also pointless and dangerous as we are only | |
5097 | * explicitly shadowing L1's page tables, i.e. unprotecting something | |
5098 | * for L1 isn't going to magically fix whatever issue cause L2 to fail. | |
472faffa | 5099 | */ |
736c291c | 5100 | if (!mmio_info_in_cache(vcpu, cr2_or_gpa, direct) && !is_guest_mode(vcpu)) |
92daa48b | 5101 | emulation_type |= EMULTYPE_ALLOW_RETRY_PF; |
e9ee956e | 5102 | emulate: |
736c291c | 5103 | return x86_emulate_instruction(vcpu, cr2_or_gpa, emulation_type, insn, |
60fc3d02 | 5104 | insn_len); |
3067714c AK |
5105 | } |
5106 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
5107 | ||
5efac074 PB |
5108 | void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
5109 | gva_t gva, hpa_t root_hpa) | |
a7052897 | 5110 | { |
b94742c9 | 5111 | int i; |
7eb77e9f | 5112 | |
5efac074 PB |
5113 | /* It's actually a GPA for vcpu->arch.guest_mmu. */ |
5114 | if (mmu != &vcpu->arch.guest_mmu) { | |
5115 | /* INVLPG on a non-canonical address is a NOP according to the SDM. */ | |
5116 | if (is_noncanonical_address(gva, vcpu)) | |
5117 | return; | |
5118 | ||
b3646477 | 5119 | static_call(kvm_x86_tlb_flush_gva)(vcpu, gva); |
5efac074 PB |
5120 | } |
5121 | ||
5122 | if (!mmu->invlpg) | |
faff8758 JS |
5123 | return; |
5124 | ||
5efac074 PB |
5125 | if (root_hpa == INVALID_PAGE) { |
5126 | mmu->invlpg(vcpu, gva, mmu->root_hpa); | |
956bf353 | 5127 | |
5efac074 PB |
5128 | /* |
5129 | * INVLPG is required to invalidate any global mappings for the VA, | |
5130 | * irrespective of PCID. Since it would take us roughly similar amount | |
5131 | * of work to determine whether any of the prev_root mappings of the VA | |
5132 | * is marked global, or to just sync it blindly, so we might as well | |
5133 | * just always sync it. | |
5134 | * | |
5135 | * Mappings not reachable via the current cr3 or the prev_roots will be | |
5136 | * synced when switching to that cr3, so nothing needs to be done here | |
5137 | * for them. | |
5138 | */ | |
5139 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
5140 | if (VALID_PAGE(mmu->prev_roots[i].hpa)) | |
5141 | mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa); | |
5142 | } else { | |
5143 | mmu->invlpg(vcpu, gva, root_hpa); | |
5144 | } | |
5145 | } | |
956bf353 | 5146 | |
5efac074 PB |
5147 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
5148 | { | |
5149 | kvm_mmu_invalidate_gva(vcpu, vcpu->arch.mmu, gva, INVALID_PAGE); | |
a7052897 MT |
5150 | ++vcpu->stat.invlpg; |
5151 | } | |
5152 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
5153 | ||
5efac074 | 5154 | |
eb4b248e JS |
5155 | void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid) |
5156 | { | |
44dd3ffa | 5157 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
faff8758 | 5158 | bool tlb_flush = false; |
b94742c9 | 5159 | uint i; |
eb4b248e JS |
5160 | |
5161 | if (pcid == kvm_get_active_pcid(vcpu)) { | |
7eb77e9f | 5162 | mmu->invlpg(vcpu, gva, mmu->root_hpa); |
faff8758 | 5163 | tlb_flush = true; |
eb4b248e JS |
5164 | } |
5165 | ||
b94742c9 JS |
5166 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { |
5167 | if (VALID_PAGE(mmu->prev_roots[i].hpa) && | |
be01e8e2 | 5168 | pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd)) { |
b94742c9 JS |
5169 | mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa); |
5170 | tlb_flush = true; | |
5171 | } | |
956bf353 | 5172 | } |
ade61e28 | 5173 | |
faff8758 | 5174 | if (tlb_flush) |
b3646477 | 5175 | static_call(kvm_x86_tlb_flush_gva)(vcpu, gva); |
faff8758 | 5176 | |
eb4b248e JS |
5177 | ++vcpu->stat.invlpg; |
5178 | ||
5179 | /* | |
b94742c9 JS |
5180 | * Mappings not reachable via the current cr3 or the prev_roots will be |
5181 | * synced when switching to that cr3, so nothing needs to be done here | |
5182 | * for them. | |
eb4b248e JS |
5183 | */ |
5184 | } | |
eb4b248e | 5185 | |
83013059 SC |
5186 | void kvm_configure_mmu(bool enable_tdp, int tdp_max_root_level, |
5187 | int tdp_huge_page_level) | |
18552672 | 5188 | { |
bde77235 | 5189 | tdp_enabled = enable_tdp; |
83013059 | 5190 | max_tdp_level = tdp_max_root_level; |
703c335d SC |
5191 | |
5192 | /* | |
1d92d2e8 | 5193 | * max_huge_page_level reflects KVM's MMU capabilities irrespective |
703c335d SC |
5194 | * of kernel support, e.g. KVM may be capable of using 1GB pages when |
5195 | * the kernel is not. But, KVM never creates a page size greater than | |
5196 | * what is used by the kernel for any given HVA, i.e. the kernel's | |
5197 | * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust(). | |
5198 | */ | |
5199 | if (tdp_enabled) | |
1d92d2e8 | 5200 | max_huge_page_level = tdp_huge_page_level; |
703c335d | 5201 | else if (boot_cpu_has(X86_FEATURE_GBPAGES)) |
1d92d2e8 | 5202 | max_huge_page_level = PG_LEVEL_1G; |
703c335d | 5203 | else |
1d92d2e8 | 5204 | max_huge_page_level = PG_LEVEL_2M; |
18552672 | 5205 | } |
bde77235 | 5206 | EXPORT_SYMBOL_GPL(kvm_configure_mmu); |
85875a13 SC |
5207 | |
5208 | /* The return value indicates if tlb flush on all vcpus is needed. */ | |
0a234f5d SC |
5209 | typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
5210 | struct kvm_memory_slot *slot); | |
85875a13 SC |
5211 | |
5212 | /* The caller should hold mmu-lock before calling this function. */ | |
5213 | static __always_inline bool | |
5214 | slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5215 | slot_level_handler fn, int start_level, int end_level, | |
5216 | gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb) | |
5217 | { | |
5218 | struct slot_rmap_walk_iterator iterator; | |
5219 | bool flush = false; | |
5220 | ||
5221 | for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn, | |
5222 | end_gfn, &iterator) { | |
5223 | if (iterator.rmap) | |
0a234f5d | 5224 | flush |= fn(kvm, iterator.rmap, memslot); |
85875a13 | 5225 | |
531810ca | 5226 | if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) { |
85875a13 | 5227 | if (flush && lock_flush_tlb) { |
f285c633 BG |
5228 | kvm_flush_remote_tlbs_with_address(kvm, |
5229 | start_gfn, | |
5230 | iterator.gfn - start_gfn + 1); | |
85875a13 SC |
5231 | flush = false; |
5232 | } | |
531810ca | 5233 | cond_resched_rwlock_write(&kvm->mmu_lock); |
85875a13 SC |
5234 | } |
5235 | } | |
5236 | ||
5237 | if (flush && lock_flush_tlb) { | |
f285c633 BG |
5238 | kvm_flush_remote_tlbs_with_address(kvm, start_gfn, |
5239 | end_gfn - start_gfn + 1); | |
85875a13 SC |
5240 | flush = false; |
5241 | } | |
5242 | ||
5243 | return flush; | |
5244 | } | |
5245 | ||
5246 | static __always_inline bool | |
5247 | slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5248 | slot_level_handler fn, int start_level, int end_level, | |
5249 | bool lock_flush_tlb) | |
5250 | { | |
5251 | return slot_handle_level_range(kvm, memslot, fn, start_level, | |
5252 | end_level, memslot->base_gfn, | |
5253 | memslot->base_gfn + memslot->npages - 1, | |
5254 | lock_flush_tlb); | |
5255 | } | |
5256 | ||
85875a13 SC |
5257 | static __always_inline bool |
5258 | slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5259 | slot_level_handler fn, bool lock_flush_tlb) | |
5260 | { | |
3bae0459 SC |
5261 | return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K, |
5262 | PG_LEVEL_4K, lock_flush_tlb); | |
85875a13 SC |
5263 | } |
5264 | ||
1cfff4d9 | 5265 | static void free_mmu_pages(struct kvm_mmu *mmu) |
6aa8b732 | 5266 | { |
1cfff4d9 JP |
5267 | free_page((unsigned long)mmu->pae_root); |
5268 | free_page((unsigned long)mmu->lm_root); | |
6aa8b732 AK |
5269 | } |
5270 | ||
04d28e37 | 5271 | static int __kvm_mmu_create(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
6aa8b732 | 5272 | { |
17ac10ad | 5273 | struct page *page; |
6aa8b732 AK |
5274 | int i; |
5275 | ||
04d28e37 SC |
5276 | mmu->root_hpa = INVALID_PAGE; |
5277 | mmu->root_pgd = 0; | |
5278 | mmu->translate_gpa = translate_gpa; | |
5279 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
5280 | mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID; | |
5281 | ||
17ac10ad | 5282 | /* |
b6b80c78 SC |
5283 | * When using PAE paging, the four PDPTEs are treated as 'root' pages, |
5284 | * while the PDP table is a per-vCPU construct that's allocated at MMU | |
5285 | * creation. When emulating 32-bit mode, cr3 is only 32 bits even on | |
5286 | * x86_64. Therefore we need to allocate the PDP table in the first | |
04d45551 SC |
5287 | * 4GB of memory, which happens to fit the DMA32 zone. TDP paging |
5288 | * generally doesn't use PAE paging and can skip allocating the PDP | |
5289 | * table. The main exception, handled here, is SVM's 32-bit NPT. The | |
5290 | * other exception is for shadowing L1's 32-bit or PAE NPT on 64-bit | |
5291 | * KVM; that horror is handled on-demand by mmu_alloc_shadow_roots(). | |
17ac10ad | 5292 | */ |
d468d94b | 5293 | if (tdp_enabled && kvm_mmu_get_tdp_level(vcpu) > PT32E_ROOT_LEVEL) |
b6b80c78 SC |
5294 | return 0; |
5295 | ||
254272ce | 5296 | page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32); |
17ac10ad | 5297 | if (!page) |
d7fa6ab2 WY |
5298 | return -ENOMEM; |
5299 | ||
1cfff4d9 | 5300 | mmu->pae_root = page_address(page); |
17ac10ad | 5301 | for (i = 0; i < 4; ++i) |
1cfff4d9 | 5302 | mmu->pae_root[i] = INVALID_PAGE; |
17ac10ad | 5303 | |
6aa8b732 | 5304 | return 0; |
6aa8b732 AK |
5305 | } |
5306 | ||
8018c27b | 5307 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 5308 | { |
1cfff4d9 | 5309 | int ret; |
b94742c9 | 5310 | |
5962bfb7 | 5311 | vcpu->arch.mmu_pte_list_desc_cache.kmem_cache = pte_list_desc_cache; |
5f6078f9 SC |
5312 | vcpu->arch.mmu_pte_list_desc_cache.gfp_zero = __GFP_ZERO; |
5313 | ||
5962bfb7 | 5314 | vcpu->arch.mmu_page_header_cache.kmem_cache = mmu_page_header_cache; |
5f6078f9 | 5315 | vcpu->arch.mmu_page_header_cache.gfp_zero = __GFP_ZERO; |
5962bfb7 | 5316 | |
96880883 SC |
5317 | vcpu->arch.mmu_shadow_page_cache.gfp_zero = __GFP_ZERO; |
5318 | ||
44dd3ffa VK |
5319 | vcpu->arch.mmu = &vcpu->arch.root_mmu; |
5320 | vcpu->arch.walk_mmu = &vcpu->arch.root_mmu; | |
6aa8b732 | 5321 | |
14c07ad8 | 5322 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; |
1cfff4d9 | 5323 | |
04d28e37 | 5324 | ret = __kvm_mmu_create(vcpu, &vcpu->arch.guest_mmu); |
1cfff4d9 JP |
5325 | if (ret) |
5326 | return ret; | |
5327 | ||
04d28e37 | 5328 | ret = __kvm_mmu_create(vcpu, &vcpu->arch.root_mmu); |
1cfff4d9 JP |
5329 | if (ret) |
5330 | goto fail_allocate_root; | |
5331 | ||
5332 | return ret; | |
5333 | fail_allocate_root: | |
5334 | free_mmu_pages(&vcpu->arch.guest_mmu); | |
5335 | return ret; | |
6aa8b732 AK |
5336 | } |
5337 | ||
fbb158cb | 5338 | #define BATCH_ZAP_PAGES 10 |
002c5f73 SC |
5339 | static void kvm_zap_obsolete_pages(struct kvm *kvm) |
5340 | { | |
5341 | struct kvm_mmu_page *sp, *node; | |
fbb158cb | 5342 | int nr_zapped, batch = 0; |
002c5f73 SC |
5343 | |
5344 | restart: | |
5345 | list_for_each_entry_safe_reverse(sp, node, | |
5346 | &kvm->arch.active_mmu_pages, link) { | |
5347 | /* | |
5348 | * No obsolete valid page exists before a newly created page | |
5349 | * since active_mmu_pages is a FIFO list. | |
5350 | */ | |
5351 | if (!is_obsolete_sp(kvm, sp)) | |
5352 | break; | |
5353 | ||
5354 | /* | |
f95eec9b SC |
5355 | * Invalid pages should never land back on the list of active |
5356 | * pages. Skip the bogus page, otherwise we'll get stuck in an | |
5357 | * infinite loop if the page gets put back on the list (again). | |
002c5f73 | 5358 | */ |
f95eec9b | 5359 | if (WARN_ON(sp->role.invalid)) |
002c5f73 SC |
5360 | continue; |
5361 | ||
4506ecf4 SC |
5362 | /* |
5363 | * No need to flush the TLB since we're only zapping shadow | |
5364 | * pages with an obsolete generation number and all vCPUS have | |
5365 | * loaded a new root, i.e. the shadow pages being zapped cannot | |
5366 | * be in active use by the guest. | |
5367 | */ | |
fbb158cb | 5368 | if (batch >= BATCH_ZAP_PAGES && |
531810ca | 5369 | cond_resched_rwlock_write(&kvm->mmu_lock)) { |
fbb158cb | 5370 | batch = 0; |
002c5f73 SC |
5371 | goto restart; |
5372 | } | |
5373 | ||
10605204 SC |
5374 | if (__kvm_mmu_prepare_zap_page(kvm, sp, |
5375 | &kvm->arch.zapped_obsolete_pages, &nr_zapped)) { | |
fbb158cb | 5376 | batch += nr_zapped; |
002c5f73 | 5377 | goto restart; |
fbb158cb | 5378 | } |
002c5f73 SC |
5379 | } |
5380 | ||
4506ecf4 SC |
5381 | /* |
5382 | * Trigger a remote TLB flush before freeing the page tables to ensure | |
5383 | * KVM is not in the middle of a lockless shadow page table walk, which | |
5384 | * may reference the pages. | |
5385 | */ | |
10605204 | 5386 | kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages); |
002c5f73 SC |
5387 | } |
5388 | ||
5389 | /* | |
5390 | * Fast invalidate all shadow pages and use lock-break technique | |
5391 | * to zap obsolete pages. | |
5392 | * | |
5393 | * It's required when memslot is being deleted or VM is being | |
5394 | * destroyed, in these cases, we should ensure that KVM MMU does | |
5395 | * not use any resource of the being-deleted slot or all slots | |
5396 | * after calling the function. | |
5397 | */ | |
5398 | static void kvm_mmu_zap_all_fast(struct kvm *kvm) | |
5399 | { | |
ca333add SC |
5400 | lockdep_assert_held(&kvm->slots_lock); |
5401 | ||
531810ca | 5402 | write_lock(&kvm->mmu_lock); |
14a3c4f4 | 5403 | trace_kvm_mmu_zap_all_fast(kvm); |
ca333add SC |
5404 | |
5405 | /* | |
5406 | * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is | |
5407 | * held for the entire duration of zapping obsolete pages, it's | |
5408 | * impossible for there to be multiple invalid generations associated | |
5409 | * with *valid* shadow pages at any given time, i.e. there is exactly | |
5410 | * one valid generation and (at most) one invalid generation. | |
5411 | */ | |
5412 | kvm->arch.mmu_valid_gen = kvm->arch.mmu_valid_gen ? 0 : 1; | |
002c5f73 | 5413 | |
4506ecf4 SC |
5414 | /* |
5415 | * Notify all vcpus to reload its shadow page table and flush TLB. | |
5416 | * Then all vcpus will switch to new shadow page table with the new | |
5417 | * mmu_valid_gen. | |
5418 | * | |
5419 | * Note: we need to do this under the protection of mmu_lock, | |
5420 | * otherwise, vcpu would purge shadow page but miss tlb flush. | |
5421 | */ | |
5422 | kvm_reload_remote_mmus(kvm); | |
5423 | ||
002c5f73 | 5424 | kvm_zap_obsolete_pages(kvm); |
faaf05b0 | 5425 | |
897218ff | 5426 | if (is_tdp_mmu_enabled(kvm)) |
faaf05b0 BG |
5427 | kvm_tdp_mmu_zap_all(kvm); |
5428 | ||
531810ca | 5429 | write_unlock(&kvm->mmu_lock); |
002c5f73 SC |
5430 | } |
5431 | ||
10605204 SC |
5432 | static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm) |
5433 | { | |
5434 | return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages)); | |
5435 | } | |
5436 | ||
b5f5fdca | 5437 | static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm, |
d126363d JS |
5438 | struct kvm_memory_slot *slot, |
5439 | struct kvm_page_track_notifier_node *node) | |
b5f5fdca | 5440 | { |
002c5f73 | 5441 | kvm_mmu_zap_all_fast(kvm); |
1bad2b2a XG |
5442 | } |
5443 | ||
13d268ca | 5444 | void kvm_mmu_init_vm(struct kvm *kvm) |
1bad2b2a | 5445 | { |
13d268ca | 5446 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; |
1bad2b2a | 5447 | |
fe5db27d BG |
5448 | kvm_mmu_init_tdp_mmu(kvm); |
5449 | ||
13d268ca | 5450 | node->track_write = kvm_mmu_pte_write; |
b5f5fdca | 5451 | node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot; |
13d268ca | 5452 | kvm_page_track_register_notifier(kvm, node); |
1bad2b2a XG |
5453 | } |
5454 | ||
13d268ca | 5455 | void kvm_mmu_uninit_vm(struct kvm *kvm) |
1bad2b2a | 5456 | { |
13d268ca | 5457 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; |
1bad2b2a | 5458 | |
13d268ca | 5459 | kvm_page_track_unregister_notifier(kvm, node); |
fe5db27d BG |
5460 | |
5461 | kvm_mmu_uninit_tdp_mmu(kvm); | |
1bad2b2a XG |
5462 | } |
5463 | ||
efdfe536 XG |
5464 | void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end) |
5465 | { | |
5466 | struct kvm_memslots *slots; | |
5467 | struct kvm_memory_slot *memslot; | |
9da0e4d5 | 5468 | int i; |
faaf05b0 | 5469 | bool flush; |
efdfe536 | 5470 | |
531810ca | 5471 | write_lock(&kvm->mmu_lock); |
9da0e4d5 PB |
5472 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
5473 | slots = __kvm_memslots(kvm, i); | |
5474 | kvm_for_each_memslot(memslot, slots) { | |
5475 | gfn_t start, end; | |
5476 | ||
5477 | start = max(gfn_start, memslot->base_gfn); | |
5478 | end = min(gfn_end, memslot->base_gfn + memslot->npages); | |
5479 | if (start >= end) | |
5480 | continue; | |
efdfe536 | 5481 | |
92da008f | 5482 | slot_handle_level_range(kvm, memslot, kvm_zap_rmapp, |
3bae0459 | 5483 | PG_LEVEL_4K, |
e662ec3e | 5484 | KVM_MAX_HUGEPAGE_LEVEL, |
92da008f | 5485 | start, end - 1, true); |
9da0e4d5 | 5486 | } |
efdfe536 XG |
5487 | } |
5488 | ||
897218ff | 5489 | if (is_tdp_mmu_enabled(kvm)) { |
faaf05b0 BG |
5490 | flush = kvm_tdp_mmu_zap_gfn_range(kvm, gfn_start, gfn_end); |
5491 | if (flush) | |
5492 | kvm_flush_remote_tlbs(kvm); | |
5493 | } | |
5494 | ||
531810ca | 5495 | write_unlock(&kvm->mmu_lock); |
efdfe536 XG |
5496 | } |
5497 | ||
018aabb5 | 5498 | static bool slot_rmap_write_protect(struct kvm *kvm, |
0a234f5d SC |
5499 | struct kvm_rmap_head *rmap_head, |
5500 | struct kvm_memory_slot *slot) | |
d77aa73c | 5501 | { |
018aabb5 | 5502 | return __rmap_write_protect(kvm, rmap_head, false); |
d77aa73c XG |
5503 | } |
5504 | ||
1c91cad4 | 5505 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, |
3c9bd400 JZ |
5506 | struct kvm_memory_slot *memslot, |
5507 | int start_level) | |
6aa8b732 | 5508 | { |
d77aa73c | 5509 | bool flush; |
6aa8b732 | 5510 | |
531810ca | 5511 | write_lock(&kvm->mmu_lock); |
3c9bd400 | 5512 | flush = slot_handle_level(kvm, memslot, slot_rmap_write_protect, |
e662ec3e | 5513 | start_level, KVM_MAX_HUGEPAGE_LEVEL, false); |
897218ff | 5514 | if (is_tdp_mmu_enabled(kvm)) |
a6a0b05d | 5515 | flush |= kvm_tdp_mmu_wrprot_slot(kvm, memslot, PG_LEVEL_4K); |
531810ca | 5516 | write_unlock(&kvm->mmu_lock); |
198c74f4 | 5517 | |
198c74f4 XG |
5518 | /* |
5519 | * We can flush all the TLBs out of the mmu lock without TLB | |
5520 | * corruption since we just change the spte from writable to | |
5521 | * readonly so that we only need to care the case of changing | |
5522 | * spte from present to present (changing the spte from present | |
5523 | * to nonpresent will flush all the TLBs immediately), in other | |
5524 | * words, the only case we care is mmu_spte_update() where we | |
bdd303cb | 5525 | * have checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE |
198c74f4 XG |
5526 | * instead of PT_WRITABLE_MASK, that means it does not depend |
5527 | * on PT_WRITABLE_MASK anymore. | |
5528 | */ | |
d91ffee9 | 5529 | if (flush) |
7f42aa76 | 5530 | kvm_arch_flush_remote_tlbs_memslot(kvm, memslot); |
6aa8b732 | 5531 | } |
37a7d8b0 | 5532 | |
3ea3b7fa | 5533 | static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm, |
0a234f5d SC |
5534 | struct kvm_rmap_head *rmap_head, |
5535 | struct kvm_memory_slot *slot) | |
3ea3b7fa WL |
5536 | { |
5537 | u64 *sptep; | |
5538 | struct rmap_iterator iter; | |
5539 | int need_tlb_flush = 0; | |
ba049e93 | 5540 | kvm_pfn_t pfn; |
3ea3b7fa WL |
5541 | struct kvm_mmu_page *sp; |
5542 | ||
0d536790 | 5543 | restart: |
018aabb5 | 5544 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
57354682 | 5545 | sp = sptep_to_sp(sptep); |
3ea3b7fa WL |
5546 | pfn = spte_to_pfn(*sptep); |
5547 | ||
5548 | /* | |
decf6333 XG |
5549 | * We cannot do huge page mapping for indirect shadow pages, |
5550 | * which are found on the last rmap (level = 1) when not using | |
5551 | * tdp; such shadow pages are synced with the page table in | |
5552 | * the guest, and the guest page table is using 4K page size | |
5553 | * mapping if the indirect sp has level = 1. | |
3ea3b7fa | 5554 | */ |
a78986aa | 5555 | if (sp->role.direct && !kvm_is_reserved_pfn(pfn) && |
9eba50f8 SC |
5556 | sp->role.level < kvm_mmu_max_mapping_level(kvm, slot, sp->gfn, |
5557 | pfn, PG_LEVEL_NUM)) { | |
e7912386 | 5558 | pte_list_remove(rmap_head, sptep); |
40ef75a7 LT |
5559 | |
5560 | if (kvm_available_flush_tlb_with_range()) | |
5561 | kvm_flush_remote_tlbs_with_address(kvm, sp->gfn, | |
5562 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
5563 | else | |
5564 | need_tlb_flush = 1; | |
5565 | ||
0d536790 XG |
5566 | goto restart; |
5567 | } | |
3ea3b7fa WL |
5568 | } |
5569 | ||
5570 | return need_tlb_flush; | |
5571 | } | |
5572 | ||
5573 | void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, | |
f36f3f28 | 5574 | const struct kvm_memory_slot *memslot) |
3ea3b7fa | 5575 | { |
f36f3f28 | 5576 | /* FIXME: const-ify all uses of struct kvm_memory_slot. */ |
9eba50f8 SC |
5577 | struct kvm_memory_slot *slot = (struct kvm_memory_slot *)memslot; |
5578 | ||
531810ca | 5579 | write_lock(&kvm->mmu_lock); |
9eba50f8 | 5580 | slot_handle_leaf(kvm, slot, kvm_mmu_zap_collapsible_spte, true); |
14881998 | 5581 | |
897218ff | 5582 | if (is_tdp_mmu_enabled(kvm)) |
9eba50f8 | 5583 | kvm_tdp_mmu_zap_collapsible_sptes(kvm, slot); |
531810ca | 5584 | write_unlock(&kvm->mmu_lock); |
3ea3b7fa WL |
5585 | } |
5586 | ||
b3594ffb SC |
5587 | void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm, |
5588 | struct kvm_memory_slot *memslot) | |
5589 | { | |
5590 | /* | |
7f42aa76 SC |
5591 | * All current use cases for flushing the TLBs for a specific memslot |
5592 | * are related to dirty logging, and do the TLB flush out of mmu_lock. | |
5593 | * The interaction between the various operations on memslot must be | |
5594 | * serialized by slots_locks to ensure the TLB flush from one operation | |
5595 | * is observed by any other operation on the same memslot. | |
b3594ffb SC |
5596 | */ |
5597 | lockdep_assert_held(&kvm->slots_lock); | |
cec37648 SC |
5598 | kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn, |
5599 | memslot->npages); | |
b3594ffb SC |
5600 | } |
5601 | ||
f4b4b180 KH |
5602 | void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, |
5603 | struct kvm_memory_slot *memslot) | |
5604 | { | |
d77aa73c | 5605 | bool flush; |
f4b4b180 | 5606 | |
531810ca | 5607 | write_lock(&kvm->mmu_lock); |
d77aa73c | 5608 | flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false); |
897218ff | 5609 | if (is_tdp_mmu_enabled(kvm)) |
a6a0b05d | 5610 | flush |= kvm_tdp_mmu_clear_dirty_slot(kvm, memslot); |
531810ca | 5611 | write_unlock(&kvm->mmu_lock); |
f4b4b180 | 5612 | |
f4b4b180 KH |
5613 | /* |
5614 | * It's also safe to flush TLBs out of mmu lock here as currently this | |
5615 | * function is only used for dirty logging, in which case flushing TLB | |
5616 | * out of mmu lock also guarantees no dirty pages will be lost in | |
5617 | * dirty_bitmap. | |
5618 | */ | |
5619 | if (flush) | |
7f42aa76 | 5620 | kvm_arch_flush_remote_tlbs_memslot(kvm, memslot); |
f4b4b180 | 5621 | } |
f4b4b180 | 5622 | |
92f58b5c | 5623 | void kvm_mmu_zap_all(struct kvm *kvm) |
5304b8d3 XG |
5624 | { |
5625 | struct kvm_mmu_page *sp, *node; | |
7390de1e | 5626 | LIST_HEAD(invalid_list); |
83cdb568 | 5627 | int ign; |
5304b8d3 | 5628 | |
531810ca | 5629 | write_lock(&kvm->mmu_lock); |
5304b8d3 | 5630 | restart: |
8a674adc | 5631 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) { |
f95eec9b | 5632 | if (WARN_ON(sp->role.invalid)) |
4771450c | 5633 | continue; |
92f58b5c | 5634 | if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign)) |
5304b8d3 | 5635 | goto restart; |
531810ca | 5636 | if (cond_resched_rwlock_write(&kvm->mmu_lock)) |
5304b8d3 XG |
5637 | goto restart; |
5638 | } | |
5639 | ||
4771450c | 5640 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
faaf05b0 | 5641 | |
897218ff | 5642 | if (is_tdp_mmu_enabled(kvm)) |
faaf05b0 BG |
5643 | kvm_tdp_mmu_zap_all(kvm); |
5644 | ||
531810ca | 5645 | write_unlock(&kvm->mmu_lock); |
5304b8d3 XG |
5646 | } |
5647 | ||
15248258 | 5648 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen) |
f8f55942 | 5649 | { |
164bf7e5 | 5650 | WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS); |
e1359e2b | 5651 | |
164bf7e5 | 5652 | gen &= MMIO_SPTE_GEN_MASK; |
e1359e2b | 5653 | |
f8f55942 | 5654 | /* |
e1359e2b SC |
5655 | * Generation numbers are incremented in multiples of the number of |
5656 | * address spaces in order to provide unique generations across all | |
5657 | * address spaces. Strip what is effectively the address space | |
5658 | * modifier prior to checking for a wrap of the MMIO generation so | |
5659 | * that a wrap in any address space is detected. | |
5660 | */ | |
5661 | gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1); | |
5662 | ||
f8f55942 | 5663 | /* |
e1359e2b | 5664 | * The very rare case: if the MMIO generation number has wrapped, |
f8f55942 | 5665 | * zap all shadow pages. |
f8f55942 | 5666 | */ |
e1359e2b | 5667 | if (unlikely(gen == 0)) { |
ae0f5499 | 5668 | kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n"); |
92f58b5c | 5669 | kvm_mmu_zap_all_fast(kvm); |
7a2e8aaf | 5670 | } |
f8f55942 XG |
5671 | } |
5672 | ||
70534a73 DC |
5673 | static unsigned long |
5674 | mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) | |
3ee16c81 IE |
5675 | { |
5676 | struct kvm *kvm; | |
1495f230 | 5677 | int nr_to_scan = sc->nr_to_scan; |
70534a73 | 5678 | unsigned long freed = 0; |
3ee16c81 | 5679 | |
0d9ce162 | 5680 | mutex_lock(&kvm_lock); |
3ee16c81 IE |
5681 | |
5682 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
3d56cbdf | 5683 | int idx; |
d98ba053 | 5684 | LIST_HEAD(invalid_list); |
3ee16c81 | 5685 | |
35f2d16b TY |
5686 | /* |
5687 | * Never scan more than sc->nr_to_scan VM instances. | |
5688 | * Will not hit this condition practically since we do not try | |
5689 | * to shrink more than one VM and it is very unlikely to see | |
5690 | * !n_used_mmu_pages so many times. | |
5691 | */ | |
5692 | if (!nr_to_scan--) | |
5693 | break; | |
19526396 GN |
5694 | /* |
5695 | * n_used_mmu_pages is accessed without holding kvm->mmu_lock | |
5696 | * here. We may skip a VM instance errorneosly, but we do not | |
5697 | * want to shrink a VM that only started to populate its MMU | |
5698 | * anyway. | |
5699 | */ | |
10605204 SC |
5700 | if (!kvm->arch.n_used_mmu_pages && |
5701 | !kvm_has_zapped_obsolete_pages(kvm)) | |
19526396 | 5702 | continue; |
19526396 | 5703 | |
f656ce01 | 5704 | idx = srcu_read_lock(&kvm->srcu); |
531810ca | 5705 | write_lock(&kvm->mmu_lock); |
3ee16c81 | 5706 | |
10605204 SC |
5707 | if (kvm_has_zapped_obsolete_pages(kvm)) { |
5708 | kvm_mmu_commit_zap_page(kvm, | |
5709 | &kvm->arch.zapped_obsolete_pages); | |
5710 | goto unlock; | |
5711 | } | |
5712 | ||
ebdb292d | 5713 | freed = kvm_mmu_zap_oldest_mmu_pages(kvm, sc->nr_to_scan); |
19526396 | 5714 | |
10605204 | 5715 | unlock: |
531810ca | 5716 | write_unlock(&kvm->mmu_lock); |
f656ce01 | 5717 | srcu_read_unlock(&kvm->srcu, idx); |
19526396 | 5718 | |
70534a73 DC |
5719 | /* |
5720 | * unfair on small ones | |
5721 | * per-vm shrinkers cry out | |
5722 | * sadness comes quickly | |
5723 | */ | |
19526396 GN |
5724 | list_move_tail(&kvm->vm_list, &vm_list); |
5725 | break; | |
3ee16c81 | 5726 | } |
3ee16c81 | 5727 | |
0d9ce162 | 5728 | mutex_unlock(&kvm_lock); |
70534a73 | 5729 | return freed; |
70534a73 DC |
5730 | } |
5731 | ||
5732 | static unsigned long | |
5733 | mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc) | |
5734 | { | |
45221ab6 | 5735 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); |
3ee16c81 IE |
5736 | } |
5737 | ||
5738 | static struct shrinker mmu_shrinker = { | |
70534a73 DC |
5739 | .count_objects = mmu_shrink_count, |
5740 | .scan_objects = mmu_shrink_scan, | |
3ee16c81 IE |
5741 | .seeks = DEFAULT_SEEKS * 10, |
5742 | }; | |
5743 | ||
2ddfd20e | 5744 | static void mmu_destroy_caches(void) |
b5a33a75 | 5745 | { |
c1bd743e TH |
5746 | kmem_cache_destroy(pte_list_desc_cache); |
5747 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
5748 | } |
5749 | ||
7b6f8a06 KH |
5750 | static void kvm_set_mmio_spte_mask(void) |
5751 | { | |
5752 | u64 mask; | |
7b6f8a06 KH |
5753 | |
5754 | /* | |
6129ed87 SC |
5755 | * Set a reserved PA bit in MMIO SPTEs to generate page faults with |
5756 | * PFEC.RSVD=1 on MMIO accesses. 64-bit PTEs (PAE, x86-64, and EPT | |
5757 | * paging) support a maximum of 52 bits of PA, i.e. if the CPU supports | |
5758 | * 52-bit physical addresses then there are no reserved PA bits in the | |
5759 | * PTEs and so the reserved PA approach must be disabled. | |
7b6f8a06 | 5760 | */ |
6129ed87 SC |
5761 | if (shadow_phys_bits < 52) |
5762 | mask = BIT_ULL(51) | PT_PRESENT_MASK; | |
5763 | else | |
5764 | mask = 0; | |
7b6f8a06 | 5765 | |
e7581cac | 5766 | kvm_mmu_set_mmio_spte_mask(mask, ACC_WRITE_MASK | ACC_USER_MASK); |
7b6f8a06 KH |
5767 | } |
5768 | ||
b8e8c830 PB |
5769 | static bool get_nx_auto_mode(void) |
5770 | { | |
5771 | /* Return true when CPU has the bug, and mitigations are ON */ | |
5772 | return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT) && !cpu_mitigations_off(); | |
5773 | } | |
5774 | ||
5775 | static void __set_nx_huge_pages(bool val) | |
5776 | { | |
5777 | nx_huge_pages = itlb_multihit_kvm_mitigation = val; | |
5778 | } | |
5779 | ||
5780 | static int set_nx_huge_pages(const char *val, const struct kernel_param *kp) | |
5781 | { | |
5782 | bool old_val = nx_huge_pages; | |
5783 | bool new_val; | |
5784 | ||
5785 | /* In "auto" mode deploy workaround only if CPU has the bug. */ | |
5786 | if (sysfs_streq(val, "off")) | |
5787 | new_val = 0; | |
5788 | else if (sysfs_streq(val, "force")) | |
5789 | new_val = 1; | |
5790 | else if (sysfs_streq(val, "auto")) | |
5791 | new_val = get_nx_auto_mode(); | |
5792 | else if (strtobool(val, &new_val) < 0) | |
5793 | return -EINVAL; | |
5794 | ||
5795 | __set_nx_huge_pages(new_val); | |
5796 | ||
5797 | if (new_val != old_val) { | |
5798 | struct kvm *kvm; | |
b8e8c830 PB |
5799 | |
5800 | mutex_lock(&kvm_lock); | |
5801 | ||
5802 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
ed69a6cb | 5803 | mutex_lock(&kvm->slots_lock); |
b8e8c830 | 5804 | kvm_mmu_zap_all_fast(kvm); |
ed69a6cb | 5805 | mutex_unlock(&kvm->slots_lock); |
1aa9b957 JS |
5806 | |
5807 | wake_up_process(kvm->arch.nx_lpage_recovery_thread); | |
b8e8c830 PB |
5808 | } |
5809 | mutex_unlock(&kvm_lock); | |
5810 | } | |
5811 | ||
5812 | return 0; | |
5813 | } | |
5814 | ||
b5a33a75 AK |
5815 | int kvm_mmu_module_init(void) |
5816 | { | |
ab271bd4 AB |
5817 | int ret = -ENOMEM; |
5818 | ||
b8e8c830 PB |
5819 | if (nx_huge_pages == -1) |
5820 | __set_nx_huge_pages(get_nx_auto_mode()); | |
5821 | ||
36d9594d VK |
5822 | /* |
5823 | * MMU roles use union aliasing which is, generally speaking, an | |
5824 | * undefined behavior. However, we supposedly know how compilers behave | |
5825 | * and the current status quo is unlikely to change. Guardians below are | |
5826 | * supposed to let us know if the assumption becomes false. | |
5827 | */ | |
5828 | BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32)); | |
5829 | BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32)); | |
5830 | BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64)); | |
5831 | ||
28a1f3ac | 5832 | kvm_mmu_reset_all_pte_masks(); |
f160c7b7 | 5833 | |
7b6f8a06 KH |
5834 | kvm_set_mmio_spte_mask(); |
5835 | ||
53c07b18 XG |
5836 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
5837 | sizeof(struct pte_list_desc), | |
46bea48a | 5838 | 0, SLAB_ACCOUNT, NULL); |
53c07b18 | 5839 | if (!pte_list_desc_cache) |
ab271bd4 | 5840 | goto out; |
b5a33a75 | 5841 | |
d3d25b04 AK |
5842 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
5843 | sizeof(struct kvm_mmu_page), | |
46bea48a | 5844 | 0, SLAB_ACCOUNT, NULL); |
d3d25b04 | 5845 | if (!mmu_page_header_cache) |
ab271bd4 | 5846 | goto out; |
d3d25b04 | 5847 | |
908c7f19 | 5848 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL)) |
ab271bd4 | 5849 | goto out; |
45bf21a8 | 5850 | |
ab271bd4 AB |
5851 | ret = register_shrinker(&mmu_shrinker); |
5852 | if (ret) | |
5853 | goto out; | |
3ee16c81 | 5854 | |
b5a33a75 AK |
5855 | return 0; |
5856 | ||
ab271bd4 | 5857 | out: |
3ee16c81 | 5858 | mmu_destroy_caches(); |
ab271bd4 | 5859 | return ret; |
b5a33a75 AK |
5860 | } |
5861 | ||
3ad82a7e | 5862 | /* |
39337ad1 | 5863 | * Calculate mmu pages needed for kvm. |
3ad82a7e | 5864 | */ |
bc8a3d89 | 5865 | unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm) |
3ad82a7e | 5866 | { |
bc8a3d89 BG |
5867 | unsigned long nr_mmu_pages; |
5868 | unsigned long nr_pages = 0; | |
bc6678a3 | 5869 | struct kvm_memslots *slots; |
be6ba0f0 | 5870 | struct kvm_memory_slot *memslot; |
9da0e4d5 | 5871 | int i; |
3ad82a7e | 5872 | |
9da0e4d5 PB |
5873 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
5874 | slots = __kvm_memslots(kvm, i); | |
90d83dc3 | 5875 | |
9da0e4d5 PB |
5876 | kvm_for_each_memslot(memslot, slots) |
5877 | nr_pages += memslot->npages; | |
5878 | } | |
3ad82a7e ZX |
5879 | |
5880 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
bc8a3d89 | 5881 | nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES); |
3ad82a7e ZX |
5882 | |
5883 | return nr_mmu_pages; | |
5884 | } | |
5885 | ||
c42fffe3 XG |
5886 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
5887 | { | |
95f93af4 | 5888 | kvm_mmu_unload(vcpu); |
1cfff4d9 JP |
5889 | free_mmu_pages(&vcpu->arch.root_mmu); |
5890 | free_mmu_pages(&vcpu->arch.guest_mmu); | |
c42fffe3 | 5891 | mmu_free_memory_caches(vcpu); |
b034cf01 XG |
5892 | } |
5893 | ||
b034cf01 XG |
5894 | void kvm_mmu_module_exit(void) |
5895 | { | |
5896 | mmu_destroy_caches(); | |
5897 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
5898 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
5899 | mmu_audit_disable(); |
5900 | } | |
1aa9b957 JS |
5901 | |
5902 | static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp) | |
5903 | { | |
5904 | unsigned int old_val; | |
5905 | int err; | |
5906 | ||
5907 | old_val = nx_huge_pages_recovery_ratio; | |
5908 | err = param_set_uint(val, kp); | |
5909 | if (err) | |
5910 | return err; | |
5911 | ||
5912 | if (READ_ONCE(nx_huge_pages) && | |
5913 | !old_val && nx_huge_pages_recovery_ratio) { | |
5914 | struct kvm *kvm; | |
5915 | ||
5916 | mutex_lock(&kvm_lock); | |
5917 | ||
5918 | list_for_each_entry(kvm, &vm_list, vm_list) | |
5919 | wake_up_process(kvm->arch.nx_lpage_recovery_thread); | |
5920 | ||
5921 | mutex_unlock(&kvm_lock); | |
5922 | } | |
5923 | ||
5924 | return err; | |
5925 | } | |
5926 | ||
5927 | static void kvm_recover_nx_lpages(struct kvm *kvm) | |
5928 | { | |
5929 | int rcu_idx; | |
5930 | struct kvm_mmu_page *sp; | |
5931 | unsigned int ratio; | |
5932 | LIST_HEAD(invalid_list); | |
5933 | ulong to_zap; | |
5934 | ||
5935 | rcu_idx = srcu_read_lock(&kvm->srcu); | |
531810ca | 5936 | write_lock(&kvm->mmu_lock); |
1aa9b957 JS |
5937 | |
5938 | ratio = READ_ONCE(nx_huge_pages_recovery_ratio); | |
5939 | to_zap = ratio ? DIV_ROUND_UP(kvm->stat.nx_lpage_splits, ratio) : 0; | |
7d919c7a SC |
5940 | for ( ; to_zap; --to_zap) { |
5941 | if (list_empty(&kvm->arch.lpage_disallowed_mmu_pages)) | |
5942 | break; | |
5943 | ||
1aa9b957 JS |
5944 | /* |
5945 | * We use a separate list instead of just using active_mmu_pages | |
5946 | * because the number of lpage_disallowed pages is expected to | |
5947 | * be relatively small compared to the total. | |
5948 | */ | |
5949 | sp = list_first_entry(&kvm->arch.lpage_disallowed_mmu_pages, | |
5950 | struct kvm_mmu_page, | |
5951 | lpage_disallowed_link); | |
5952 | WARN_ON_ONCE(!sp->lpage_disallowed); | |
897218ff | 5953 | if (is_tdp_mmu_page(sp)) { |
29cf0f50 BG |
5954 | kvm_tdp_mmu_zap_gfn_range(kvm, sp->gfn, |
5955 | sp->gfn + KVM_PAGES_PER_HPAGE(sp->role.level)); | |
8d1a182e | 5956 | } else { |
29cf0f50 BG |
5957 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
5958 | WARN_ON_ONCE(sp->lpage_disallowed); | |
5959 | } | |
1aa9b957 | 5960 | |
531810ca | 5961 | if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) { |
1aa9b957 | 5962 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
531810ca | 5963 | cond_resched_rwlock_write(&kvm->mmu_lock); |
1aa9b957 JS |
5964 | } |
5965 | } | |
e8950569 | 5966 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
1aa9b957 | 5967 | |
531810ca | 5968 | write_unlock(&kvm->mmu_lock); |
1aa9b957 JS |
5969 | srcu_read_unlock(&kvm->srcu, rcu_idx); |
5970 | } | |
5971 | ||
5972 | static long get_nx_lpage_recovery_timeout(u64 start_time) | |
5973 | { | |
5974 | return READ_ONCE(nx_huge_pages) && READ_ONCE(nx_huge_pages_recovery_ratio) | |
5975 | ? start_time + 60 * HZ - get_jiffies_64() | |
5976 | : MAX_SCHEDULE_TIMEOUT; | |
5977 | } | |
5978 | ||
5979 | static int kvm_nx_lpage_recovery_worker(struct kvm *kvm, uintptr_t data) | |
5980 | { | |
5981 | u64 start_time; | |
5982 | long remaining_time; | |
5983 | ||
5984 | while (true) { | |
5985 | start_time = get_jiffies_64(); | |
5986 | remaining_time = get_nx_lpage_recovery_timeout(start_time); | |
5987 | ||
5988 | set_current_state(TASK_INTERRUPTIBLE); | |
5989 | while (!kthread_should_stop() && remaining_time > 0) { | |
5990 | schedule_timeout(remaining_time); | |
5991 | remaining_time = get_nx_lpage_recovery_timeout(start_time); | |
5992 | set_current_state(TASK_INTERRUPTIBLE); | |
5993 | } | |
5994 | ||
5995 | set_current_state(TASK_RUNNING); | |
5996 | ||
5997 | if (kthread_should_stop()) | |
5998 | return 0; | |
5999 | ||
6000 | kvm_recover_nx_lpages(kvm); | |
6001 | } | |
6002 | } | |
6003 | ||
6004 | int kvm_mmu_post_init_vm(struct kvm *kvm) | |
6005 | { | |
6006 | int err; | |
6007 | ||
6008 | err = kvm_vm_create_worker_thread(kvm, kvm_nx_lpage_recovery_worker, 0, | |
6009 | "kvm-nx-lpage-recovery", | |
6010 | &kvm->arch.nx_lpage_recovery_thread); | |
6011 | if (!err) | |
6012 | kthread_unpark(kvm->arch.nx_lpage_recovery_thread); | |
6013 | ||
6014 | return err; | |
6015 | } | |
6016 | ||
6017 | void kvm_mmu_pre_destroy_vm(struct kvm *kvm) | |
6018 | { | |
6019 | if (kvm->arch.nx_lpage_recovery_thread) | |
6020 | kthread_stop(kvm->arch.nx_lpage_recovery_thread); | |
6021 | } |