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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
6aa8b732 AK |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * This module enables machines with Intel VT-x extensions to run virtual | |
6 | * machines without emulation or binary translation. | |
7 | * | |
8 | * MMU support | |
9 | * | |
10 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 11 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
12 | * |
13 | * Authors: | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
15 | * Avi Kivity <avi@qumranet.com> | |
6aa8b732 | 16 | */ |
e495606d | 17 | |
af585b92 | 18 | #include "irq.h" |
88197e6a | 19 | #include "ioapic.h" |
1d737c8a | 20 | #include "mmu.h" |
6ca9a6f3 | 21 | #include "mmu_internal.h" |
fe5db27d | 22 | #include "tdp_mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
2f728d66 | 25 | #include "kvm_emulate.h" |
5f7dde7b | 26 | #include "cpuid.h" |
5a9624af | 27 | #include "spte.h" |
e495606d | 28 | |
edf88417 | 29 | #include <linux/kvm_host.h> |
6aa8b732 AK |
30 | #include <linux/types.h> |
31 | #include <linux/string.h> | |
6aa8b732 AK |
32 | #include <linux/mm.h> |
33 | #include <linux/highmem.h> | |
1767e931 PG |
34 | #include <linux/moduleparam.h> |
35 | #include <linux/export.h> | |
448353ca | 36 | #include <linux/swap.h> |
05da4558 | 37 | #include <linux/hugetlb.h> |
2f333bcb | 38 | #include <linux/compiler.h> |
bc6678a3 | 39 | #include <linux/srcu.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
3f07c014 | 41 | #include <linux/sched/signal.h> |
bf998156 | 42 | #include <linux/uaccess.h> |
114df303 | 43 | #include <linux/hash.h> |
f160c7b7 | 44 | #include <linux/kern_levels.h> |
1aa9b957 | 45 | #include <linux/kthread.h> |
6aa8b732 | 46 | |
e495606d | 47 | #include <asm/page.h> |
eb243d1d | 48 | #include <asm/memtype.h> |
e495606d | 49 | #include <asm/cmpxchg.h> |
4e542370 | 50 | #include <asm/io.h> |
13673a90 | 51 | #include <asm/vmx.h> |
3d0c27ad | 52 | #include <asm/kvm_page_track.h> |
1261bfa3 | 53 | #include "trace.h" |
6aa8b732 | 54 | |
b8e8c830 PB |
55 | extern bool itlb_multihit_kvm_mitigation; |
56 | ||
57 | static int __read_mostly nx_huge_pages = -1; | |
13fb5927 PB |
58 | #ifdef CONFIG_PREEMPT_RT |
59 | /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */ | |
60 | static uint __read_mostly nx_huge_pages_recovery_ratio = 0; | |
61 | #else | |
1aa9b957 | 62 | static uint __read_mostly nx_huge_pages_recovery_ratio = 60; |
13fb5927 | 63 | #endif |
b8e8c830 PB |
64 | |
65 | static int set_nx_huge_pages(const char *val, const struct kernel_param *kp); | |
1aa9b957 | 66 | static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp); |
b8e8c830 | 67 | |
d5d6c18d | 68 | static const struct kernel_param_ops nx_huge_pages_ops = { |
b8e8c830 PB |
69 | .set = set_nx_huge_pages, |
70 | .get = param_get_bool, | |
71 | }; | |
72 | ||
d5d6c18d | 73 | static const struct kernel_param_ops nx_huge_pages_recovery_ratio_ops = { |
1aa9b957 JS |
74 | .set = set_nx_huge_pages_recovery_ratio, |
75 | .get = param_get_uint, | |
76 | }; | |
77 | ||
b8e8c830 PB |
78 | module_param_cb(nx_huge_pages, &nx_huge_pages_ops, &nx_huge_pages, 0644); |
79 | __MODULE_PARM_TYPE(nx_huge_pages, "bool"); | |
1aa9b957 JS |
80 | module_param_cb(nx_huge_pages_recovery_ratio, &nx_huge_pages_recovery_ratio_ops, |
81 | &nx_huge_pages_recovery_ratio, 0644); | |
82 | __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio, "uint"); | |
b8e8c830 | 83 | |
71fe7013 SC |
84 | static bool __read_mostly force_flush_and_sync_on_reuse; |
85 | module_param_named(flush_on_reuse, force_flush_and_sync_on_reuse, bool, 0644); | |
86 | ||
18552672 JR |
87 | /* |
88 | * When setting this variable to true it enables Two-Dimensional-Paging | |
89 | * where the hardware walks 2 page tables: | |
90 | * 1. the guest-virtual to guest-physical | |
91 | * 2. while doing 1. it walks guest-physical to host-physical | |
92 | * If the hardware supports that we don't need to do shadow paging. | |
93 | */ | |
2f333bcb | 94 | bool tdp_enabled = false; |
18552672 | 95 | |
1d92d2e8 | 96 | static int max_huge_page_level __read_mostly; |
83013059 | 97 | static int max_tdp_level __read_mostly; |
703c335d | 98 | |
8b1fe17c XG |
99 | enum { |
100 | AUDIT_PRE_PAGE_FAULT, | |
101 | AUDIT_POST_PAGE_FAULT, | |
102 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
103 | AUDIT_POST_PTE_WRITE, |
104 | AUDIT_PRE_SYNC, | |
105 | AUDIT_POST_SYNC | |
8b1fe17c | 106 | }; |
37a7d8b0 | 107 | |
37a7d8b0 | 108 | #ifdef MMU_DEBUG |
5a9624af | 109 | bool dbg = 0; |
fa4a2c08 | 110 | module_param(dbg, bool, 0644); |
d6c69ee9 | 111 | #endif |
6aa8b732 | 112 | |
957ed9ef XG |
113 | #define PTE_PREFETCH_NUM 8 |
114 | ||
6aa8b732 AK |
115 | #define PT32_LEVEL_BITS 10 |
116 | ||
117 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 118 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 119 | |
e04da980 JR |
120 | #define PT32_LVL_OFFSET_MASK(level) \ |
121 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
122 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
123 | |
124 | #define PT32_INDEX(address, level)\ | |
125 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
126 | ||
127 | ||
6aa8b732 AK |
128 | #define PT32_BASE_ADDR_MASK PAGE_MASK |
129 | #define PT32_DIR_BASE_ADDR_MASK \ | |
130 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
131 | #define PT32_LVL_ADDR_MASK(level) \ |
132 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
133 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 134 | |
90bb6fc5 AK |
135 | #include <trace/events/kvm.h> |
136 | ||
220f773a TY |
137 | /* make pte_list_desc fit well in cache line */ |
138 | #define PTE_LIST_EXT 3 | |
139 | ||
53c07b18 XG |
140 | struct pte_list_desc { |
141 | u64 *sptes[PTE_LIST_EXT]; | |
142 | struct pte_list_desc *more; | |
cd4a4e53 AK |
143 | }; |
144 | ||
2d11123a AK |
145 | struct kvm_shadow_walk_iterator { |
146 | u64 addr; | |
147 | hpa_t shadow_addr; | |
2d11123a | 148 | u64 *sptep; |
dd3bfd59 | 149 | int level; |
2d11123a AK |
150 | unsigned index; |
151 | }; | |
152 | ||
7eb77e9f JS |
153 | #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \ |
154 | for (shadow_walk_init_using_root(&(_walker), (_vcpu), \ | |
155 | (_root), (_addr)); \ | |
156 | shadow_walk_okay(&(_walker)); \ | |
157 | shadow_walk_next(&(_walker))) | |
158 | ||
159 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
2d11123a AK |
160 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ |
161 | shadow_walk_okay(&(_walker)); \ | |
162 | shadow_walk_next(&(_walker))) | |
163 | ||
c2a2ac2b XG |
164 | #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ |
165 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
166 | shadow_walk_okay(&(_walker)) && \ | |
167 | ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \ | |
168 | __shadow_walk_next(&(_walker), spte)) | |
169 | ||
53c07b18 | 170 | static struct kmem_cache *pte_list_desc_cache; |
02c00b3a | 171 | struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 172 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 173 | |
ce88decf | 174 | static void mmu_spte_set(u64 *sptep, u64 spte); |
9fa72119 JS |
175 | static union kvm_mmu_page_role |
176 | kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu); | |
ce88decf | 177 | |
335e192a PB |
178 | #define CREATE_TRACE_POINTS |
179 | #include "mmutrace.h" | |
180 | ||
40ef75a7 LT |
181 | |
182 | static inline bool kvm_available_flush_tlb_with_range(void) | |
183 | { | |
afaf0b2f | 184 | return kvm_x86_ops.tlb_remote_flush_with_range; |
40ef75a7 LT |
185 | } |
186 | ||
187 | static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm, | |
188 | struct kvm_tlb_range *range) | |
189 | { | |
190 | int ret = -ENOTSUPP; | |
191 | ||
afaf0b2f SC |
192 | if (range && kvm_x86_ops.tlb_remote_flush_with_range) |
193 | ret = kvm_x86_ops.tlb_remote_flush_with_range(kvm, range); | |
40ef75a7 LT |
194 | |
195 | if (ret) | |
196 | kvm_flush_remote_tlbs(kvm); | |
197 | } | |
198 | ||
2f2fad08 | 199 | void kvm_flush_remote_tlbs_with_address(struct kvm *kvm, |
40ef75a7 LT |
200 | u64 start_gfn, u64 pages) |
201 | { | |
202 | struct kvm_tlb_range range; | |
203 | ||
204 | range.start_gfn = start_gfn; | |
205 | range.pages = pages; | |
206 | ||
207 | kvm_flush_remote_tlbs_with_range(kvm, &range); | |
208 | } | |
209 | ||
5a9624af | 210 | bool is_nx_huge_page_enabled(void) |
b8e8c830 PB |
211 | { |
212 | return READ_ONCE(nx_huge_pages); | |
213 | } | |
214 | ||
8f79b064 BG |
215 | static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn, |
216 | unsigned int access) | |
217 | { | |
218 | u64 mask = make_mmio_spte(vcpu, gfn, access); | |
8f79b064 | 219 | |
bb18842e | 220 | trace_mark_mmio_spte(sptep, gfn, mask); |
f2fd125d | 221 | mmu_spte_set(sptep, mask); |
ce88decf XG |
222 | } |
223 | ||
ce88decf XG |
224 | static gfn_t get_mmio_spte_gfn(u64 spte) |
225 | { | |
daa07cbc | 226 | u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask; |
28a1f3ac | 227 | |
8a967d65 | 228 | gpa |= (spte >> SHADOW_NONPRESENT_OR_RSVD_MASK_LEN) |
28a1f3ac JS |
229 | & shadow_nonpresent_or_rsvd_mask; |
230 | ||
231 | return gpa >> PAGE_SHIFT; | |
ce88decf XG |
232 | } |
233 | ||
234 | static unsigned get_mmio_spte_access(u64 spte) | |
235 | { | |
4af77151 | 236 | return spte & shadow_mmio_access_mask; |
ce88decf XG |
237 | } |
238 | ||
54bf36aa | 239 | static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
0a2b64c5 | 240 | kvm_pfn_t pfn, unsigned int access) |
ce88decf XG |
241 | { |
242 | if (unlikely(is_noslot_pfn(pfn))) { | |
54bf36aa | 243 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
244 | return true; |
245 | } | |
246 | ||
247 | return false; | |
248 | } | |
c7addb90 | 249 | |
54bf36aa | 250 | static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte) |
f8f55942 | 251 | { |
cae7ed3c | 252 | u64 kvm_gen, spte_gen, gen; |
089504c0 | 253 | |
cae7ed3c SC |
254 | gen = kvm_vcpu_memslots(vcpu)->generation; |
255 | if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS)) | |
256 | return false; | |
089504c0 | 257 | |
cae7ed3c | 258 | kvm_gen = gen & MMIO_SPTE_GEN_MASK; |
089504c0 XG |
259 | spte_gen = get_mmio_spte_generation(spte); |
260 | ||
261 | trace_check_mmio_spte(spte, kvm_gen, spte_gen); | |
262 | return likely(kvm_gen == spte_gen); | |
f8f55942 XG |
263 | } |
264 | ||
cd313569 MG |
265 | static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
266 | struct x86_exception *exception) | |
267 | { | |
ec7771ab | 268 | /* Check if guest physical address doesn't exceed guest maximum */ |
dc46515c | 269 | if (kvm_vcpu_is_illegal_gpa(vcpu, gpa)) { |
ec7771ab MG |
270 | exception->error_code |= PFERR_RSVD_MASK; |
271 | return UNMAPPED_GVA; | |
272 | } | |
273 | ||
cd313569 MG |
274 | return gpa; |
275 | } | |
276 | ||
6aa8b732 AK |
277 | static int is_cpuid_PSE36(void) |
278 | { | |
279 | return 1; | |
280 | } | |
281 | ||
73b1087e AK |
282 | static int is_nx(struct kvm_vcpu *vcpu) |
283 | { | |
f6801dff | 284 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
285 | } |
286 | ||
da928521 AK |
287 | static gfn_t pse36_gfn_delta(u32 gpte) |
288 | { | |
289 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
290 | ||
291 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
292 | } | |
293 | ||
603e0651 | 294 | #ifdef CONFIG_X86_64 |
d555c333 | 295 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 296 | { |
b19ee2ff | 297 | WRITE_ONCE(*sptep, spte); |
e663ee64 AK |
298 | } |
299 | ||
603e0651 | 300 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
a9221dd5 | 301 | { |
b19ee2ff | 302 | WRITE_ONCE(*sptep, spte); |
603e0651 XG |
303 | } |
304 | ||
305 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
306 | { | |
307 | return xchg(sptep, spte); | |
308 | } | |
c2a2ac2b XG |
309 | |
310 | static u64 __get_spte_lockless(u64 *sptep) | |
311 | { | |
6aa7de05 | 312 | return READ_ONCE(*sptep); |
c2a2ac2b | 313 | } |
a9221dd5 | 314 | #else |
603e0651 XG |
315 | union split_spte { |
316 | struct { | |
317 | u32 spte_low; | |
318 | u32 spte_high; | |
319 | }; | |
320 | u64 spte; | |
321 | }; | |
a9221dd5 | 322 | |
c2a2ac2b XG |
323 | static void count_spte_clear(u64 *sptep, u64 spte) |
324 | { | |
57354682 | 325 | struct kvm_mmu_page *sp = sptep_to_sp(sptep); |
c2a2ac2b XG |
326 | |
327 | if (is_shadow_present_pte(spte)) | |
328 | return; | |
329 | ||
330 | /* Ensure the spte is completely set before we increase the count */ | |
331 | smp_wmb(); | |
332 | sp->clear_spte_count++; | |
333 | } | |
334 | ||
603e0651 XG |
335 | static void __set_spte(u64 *sptep, u64 spte) |
336 | { | |
337 | union split_spte *ssptep, sspte; | |
a9221dd5 | 338 | |
603e0651 XG |
339 | ssptep = (union split_spte *)sptep; |
340 | sspte = (union split_spte)spte; | |
341 | ||
342 | ssptep->spte_high = sspte.spte_high; | |
343 | ||
344 | /* | |
345 | * If we map the spte from nonpresent to present, We should store | |
346 | * the high bits firstly, then set present bit, so cpu can not | |
347 | * fetch this spte while we are setting the spte. | |
348 | */ | |
349 | smp_wmb(); | |
350 | ||
b19ee2ff | 351 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
a9221dd5 AK |
352 | } |
353 | ||
603e0651 XG |
354 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
355 | { | |
356 | union split_spte *ssptep, sspte; | |
357 | ||
358 | ssptep = (union split_spte *)sptep; | |
359 | sspte = (union split_spte)spte; | |
360 | ||
b19ee2ff | 361 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
603e0651 XG |
362 | |
363 | /* | |
364 | * If we map the spte from present to nonpresent, we should clear | |
365 | * present bit firstly to avoid vcpu fetch the old high bits. | |
366 | */ | |
367 | smp_wmb(); | |
368 | ||
369 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 370 | count_spte_clear(sptep, spte); |
603e0651 XG |
371 | } |
372 | ||
373 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
374 | { | |
375 | union split_spte *ssptep, sspte, orig; | |
376 | ||
377 | ssptep = (union split_spte *)sptep; | |
378 | sspte = (union split_spte)spte; | |
379 | ||
380 | /* xchg acts as a barrier before the setting of the high bits */ | |
381 | orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); | |
41bc3186 ZJ |
382 | orig.spte_high = ssptep->spte_high; |
383 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 384 | count_spte_clear(sptep, spte); |
603e0651 XG |
385 | |
386 | return orig.spte; | |
387 | } | |
c2a2ac2b XG |
388 | |
389 | /* | |
390 | * The idea using the light way get the spte on x86_32 guest is from | |
39656e83 | 391 | * gup_get_pte (mm/gup.c). |
accaefe0 XG |
392 | * |
393 | * An spte tlb flush may be pending, because kvm_set_pte_rmapp | |
394 | * coalesces them and we are running out of the MMU lock. Therefore | |
395 | * we need to protect against in-progress updates of the spte. | |
396 | * | |
397 | * Reading the spte while an update is in progress may get the old value | |
398 | * for the high part of the spte. The race is fine for a present->non-present | |
399 | * change (because the high part of the spte is ignored for non-present spte), | |
400 | * but for a present->present change we must reread the spte. | |
401 | * | |
402 | * All such changes are done in two steps (present->non-present and | |
403 | * non-present->present), hence it is enough to count the number of | |
404 | * present->non-present updates: if it changed while reading the spte, | |
405 | * we might have hit the race. This is done using clear_spte_count. | |
c2a2ac2b XG |
406 | */ |
407 | static u64 __get_spte_lockless(u64 *sptep) | |
408 | { | |
57354682 | 409 | struct kvm_mmu_page *sp = sptep_to_sp(sptep); |
c2a2ac2b XG |
410 | union split_spte spte, *orig = (union split_spte *)sptep; |
411 | int count; | |
412 | ||
413 | retry: | |
414 | count = sp->clear_spte_count; | |
415 | smp_rmb(); | |
416 | ||
417 | spte.spte_low = orig->spte_low; | |
418 | smp_rmb(); | |
419 | ||
420 | spte.spte_high = orig->spte_high; | |
421 | smp_rmb(); | |
422 | ||
423 | if (unlikely(spte.spte_low != orig->spte_low || | |
424 | count != sp->clear_spte_count)) | |
425 | goto retry; | |
426 | ||
427 | return spte.spte; | |
428 | } | |
603e0651 XG |
429 | #endif |
430 | ||
8672b721 XG |
431 | static bool spte_has_volatile_bits(u64 spte) |
432 | { | |
f160c7b7 JS |
433 | if (!is_shadow_present_pte(spte)) |
434 | return false; | |
435 | ||
c7ba5b48 | 436 | /* |
6a6256f9 | 437 | * Always atomically update spte if it can be updated |
c7ba5b48 XG |
438 | * out of mmu-lock, it can ensure dirty bit is not lost, |
439 | * also, it can help us to get a stable is_writable_pte() | |
440 | * to ensure tlb flush is not missed. | |
441 | */ | |
f160c7b7 JS |
442 | if (spte_can_locklessly_be_made_writable(spte) || |
443 | is_access_track_spte(spte)) | |
c7ba5b48 XG |
444 | return true; |
445 | ||
ac8d57e5 | 446 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
447 | if ((spte & shadow_accessed_mask) == 0 || |
448 | (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0)) | |
449 | return true; | |
450 | } | |
8672b721 | 451 | |
f160c7b7 | 452 | return false; |
8672b721 XG |
453 | } |
454 | ||
1df9f2dc XG |
455 | /* Rules for using mmu_spte_set: |
456 | * Set the sptep from nonpresent to present. | |
457 | * Note: the sptep being assigned *must* be either not present | |
458 | * or in a state where the hardware will not attempt to update | |
459 | * the spte. | |
460 | */ | |
461 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
462 | { | |
463 | WARN_ON(is_shadow_present_pte(*sptep)); | |
464 | __set_spte(sptep, new_spte); | |
465 | } | |
466 | ||
f39a058d JS |
467 | /* |
468 | * Update the SPTE (excluding the PFN), but do not track changes in its | |
469 | * accessed/dirty status. | |
1df9f2dc | 470 | */ |
f39a058d | 471 | static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte) |
b79b93f9 | 472 | { |
c7ba5b48 | 473 | u64 old_spte = *sptep; |
4132779b | 474 | |
afd28fe1 | 475 | WARN_ON(!is_shadow_present_pte(new_spte)); |
b79b93f9 | 476 | |
6e7d0354 XG |
477 | if (!is_shadow_present_pte(old_spte)) { |
478 | mmu_spte_set(sptep, new_spte); | |
f39a058d | 479 | return old_spte; |
6e7d0354 | 480 | } |
4132779b | 481 | |
c7ba5b48 | 482 | if (!spte_has_volatile_bits(old_spte)) |
603e0651 | 483 | __update_clear_spte_fast(sptep, new_spte); |
4132779b | 484 | else |
603e0651 | 485 | old_spte = __update_clear_spte_slow(sptep, new_spte); |
4132779b | 486 | |
83ef6c81 JS |
487 | WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte)); |
488 | ||
f39a058d JS |
489 | return old_spte; |
490 | } | |
491 | ||
492 | /* Rules for using mmu_spte_update: | |
493 | * Update the state bits, it means the mapped pfn is not changed. | |
494 | * | |
495 | * Whenever we overwrite a writable spte with a read-only one we | |
496 | * should flush remote TLBs. Otherwise rmap_write_protect | |
497 | * will find a read-only spte, even though the writable spte | |
498 | * might be cached on a CPU's TLB, the return value indicates this | |
499 | * case. | |
500 | * | |
501 | * Returns true if the TLB needs to be flushed | |
502 | */ | |
503 | static bool mmu_spte_update(u64 *sptep, u64 new_spte) | |
504 | { | |
505 | bool flush = false; | |
506 | u64 old_spte = mmu_spte_update_no_track(sptep, new_spte); | |
507 | ||
508 | if (!is_shadow_present_pte(old_spte)) | |
509 | return false; | |
510 | ||
c7ba5b48 XG |
511 | /* |
512 | * For the spte updated out of mmu-lock is safe, since | |
6a6256f9 | 513 | * we always atomically update it, see the comments in |
c7ba5b48 XG |
514 | * spte_has_volatile_bits(). |
515 | */ | |
ea4114bc | 516 | if (spte_can_locklessly_be_made_writable(old_spte) && |
7f31c959 | 517 | !is_writable_pte(new_spte)) |
83ef6c81 | 518 | flush = true; |
4132779b | 519 | |
7e71a59b | 520 | /* |
83ef6c81 | 521 | * Flush TLB when accessed/dirty states are changed in the page tables, |
7e71a59b KH |
522 | * to guarantee consistency between TLB and page tables. |
523 | */ | |
7e71a59b | 524 | |
83ef6c81 JS |
525 | if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) { |
526 | flush = true; | |
4132779b | 527 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); |
83ef6c81 JS |
528 | } |
529 | ||
530 | if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) { | |
531 | flush = true; | |
4132779b | 532 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); |
83ef6c81 | 533 | } |
6e7d0354 | 534 | |
83ef6c81 | 535 | return flush; |
b79b93f9 AK |
536 | } |
537 | ||
1df9f2dc XG |
538 | /* |
539 | * Rules for using mmu_spte_clear_track_bits: | |
540 | * It sets the sptep from present to nonpresent, and track the | |
541 | * state bits, it is used to clear the last level sptep. | |
83ef6c81 | 542 | * Returns non-zero if the PTE was previously valid. |
1df9f2dc XG |
543 | */ |
544 | static int mmu_spte_clear_track_bits(u64 *sptep) | |
545 | { | |
ba049e93 | 546 | kvm_pfn_t pfn; |
1df9f2dc XG |
547 | u64 old_spte = *sptep; |
548 | ||
549 | if (!spte_has_volatile_bits(old_spte)) | |
603e0651 | 550 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc | 551 | else |
603e0651 | 552 | old_spte = __update_clear_spte_slow(sptep, 0ull); |
1df9f2dc | 553 | |
afd28fe1 | 554 | if (!is_shadow_present_pte(old_spte)) |
1df9f2dc XG |
555 | return 0; |
556 | ||
557 | pfn = spte_to_pfn(old_spte); | |
86fde74c XG |
558 | |
559 | /* | |
560 | * KVM does not hold the refcount of the page used by | |
561 | * kvm mmu, before reclaiming the page, we should | |
562 | * unmap it from mmu first. | |
563 | */ | |
bf4bea8e | 564 | WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn))); |
86fde74c | 565 | |
83ef6c81 | 566 | if (is_accessed_spte(old_spte)) |
1df9f2dc | 567 | kvm_set_pfn_accessed(pfn); |
83ef6c81 JS |
568 | |
569 | if (is_dirty_spte(old_spte)) | |
1df9f2dc | 570 | kvm_set_pfn_dirty(pfn); |
83ef6c81 | 571 | |
1df9f2dc XG |
572 | return 1; |
573 | } | |
574 | ||
575 | /* | |
576 | * Rules for using mmu_spte_clear_no_track: | |
577 | * Directly clear spte without caring the state bits of sptep, | |
578 | * it is used to set the upper level spte. | |
579 | */ | |
580 | static void mmu_spte_clear_no_track(u64 *sptep) | |
581 | { | |
603e0651 | 582 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc XG |
583 | } |
584 | ||
c2a2ac2b XG |
585 | static u64 mmu_spte_get_lockless(u64 *sptep) |
586 | { | |
587 | return __get_spte_lockless(sptep); | |
588 | } | |
589 | ||
d3e328f2 JS |
590 | /* Restore an acc-track PTE back to a regular PTE */ |
591 | static u64 restore_acc_track_spte(u64 spte) | |
592 | { | |
593 | u64 new_spte = spte; | |
8a967d65 PB |
594 | u64 saved_bits = (spte >> SHADOW_ACC_TRACK_SAVED_BITS_SHIFT) |
595 | & SHADOW_ACC_TRACK_SAVED_BITS_MASK; | |
d3e328f2 | 596 | |
ac8d57e5 | 597 | WARN_ON_ONCE(spte_ad_enabled(spte)); |
d3e328f2 JS |
598 | WARN_ON_ONCE(!is_access_track_spte(spte)); |
599 | ||
600 | new_spte &= ~shadow_acc_track_mask; | |
8a967d65 PB |
601 | new_spte &= ~(SHADOW_ACC_TRACK_SAVED_BITS_MASK << |
602 | SHADOW_ACC_TRACK_SAVED_BITS_SHIFT); | |
d3e328f2 JS |
603 | new_spte |= saved_bits; |
604 | ||
605 | return new_spte; | |
606 | } | |
607 | ||
f160c7b7 JS |
608 | /* Returns the Accessed status of the PTE and resets it at the same time. */ |
609 | static bool mmu_spte_age(u64 *sptep) | |
610 | { | |
611 | u64 spte = mmu_spte_get_lockless(sptep); | |
612 | ||
613 | if (!is_accessed_spte(spte)) | |
614 | return false; | |
615 | ||
ac8d57e5 | 616 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
617 | clear_bit((ffs(shadow_accessed_mask) - 1), |
618 | (unsigned long *)sptep); | |
619 | } else { | |
620 | /* | |
621 | * Capture the dirty status of the page, so that it doesn't get | |
622 | * lost when the SPTE is marked for access tracking. | |
623 | */ | |
624 | if (is_writable_pte(spte)) | |
625 | kvm_set_pfn_dirty(spte_to_pfn(spte)); | |
626 | ||
627 | spte = mark_spte_for_access_track(spte); | |
628 | mmu_spte_update_no_track(sptep, spte); | |
629 | } | |
630 | ||
631 | return true; | |
632 | } | |
633 | ||
c2a2ac2b XG |
634 | static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu) |
635 | { | |
c142786c AK |
636 | /* |
637 | * Prevent page table teardown by making any free-er wait during | |
638 | * kvm_flush_remote_tlbs() IPI to all active vcpus. | |
639 | */ | |
640 | local_irq_disable(); | |
36ca7e0a | 641 | |
c142786c AK |
642 | /* |
643 | * Make sure a following spte read is not reordered ahead of the write | |
644 | * to vcpu->mode. | |
645 | */ | |
36ca7e0a | 646 | smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES); |
c2a2ac2b XG |
647 | } |
648 | ||
649 | static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu) | |
650 | { | |
c142786c AK |
651 | /* |
652 | * Make sure the write to vcpu->mode is not reordered in front of | |
9a984586 | 653 | * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us |
c142786c AK |
654 | * OUTSIDE_GUEST_MODE and proceed to free the shadow page table. |
655 | */ | |
36ca7e0a | 656 | smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE); |
c142786c | 657 | local_irq_enable(); |
c2a2ac2b XG |
658 | } |
659 | ||
378f5cd6 | 660 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu, bool maybe_indirect) |
714b93da | 661 | { |
e2dec939 AK |
662 | int r; |
663 | ||
531281ad | 664 | /* 1 rmap, 1 parent PTE per level, and the prefetched rmaps. */ |
94ce87ef SC |
665 | r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
666 | 1 + PT64_ROOT_MAX_LEVEL + PTE_PREFETCH_NUM); | |
d3d25b04 | 667 | if (r) |
284aa868 | 668 | return r; |
94ce87ef SC |
669 | r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_shadow_page_cache, |
670 | PT64_ROOT_MAX_LEVEL); | |
d3d25b04 | 671 | if (r) |
171a90d7 | 672 | return r; |
378f5cd6 | 673 | if (maybe_indirect) { |
94ce87ef SC |
674 | r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_gfn_array_cache, |
675 | PT64_ROOT_MAX_LEVEL); | |
378f5cd6 SC |
676 | if (r) |
677 | return r; | |
678 | } | |
94ce87ef SC |
679 | return kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
680 | PT64_ROOT_MAX_LEVEL); | |
714b93da AK |
681 | } |
682 | ||
683 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
684 | { | |
94ce87ef SC |
685 | kvm_mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache); |
686 | kvm_mmu_free_memory_cache(&vcpu->arch.mmu_shadow_page_cache); | |
687 | kvm_mmu_free_memory_cache(&vcpu->arch.mmu_gfn_array_cache); | |
688 | kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache); | |
714b93da AK |
689 | } |
690 | ||
53c07b18 | 691 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 692 | { |
94ce87ef | 693 | return kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache); |
714b93da AK |
694 | } |
695 | ||
53c07b18 | 696 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 697 | { |
53c07b18 | 698 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
699 | } |
700 | ||
2032a93d LJ |
701 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
702 | { | |
703 | if (!sp->role.direct) | |
704 | return sp->gfns[index]; | |
705 | ||
706 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
707 | } | |
708 | ||
709 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
710 | { | |
e9f2a760 | 711 | if (!sp->role.direct) { |
2032a93d | 712 | sp->gfns[index] = gfn; |
e9f2a760 PB |
713 | return; |
714 | } | |
715 | ||
716 | if (WARN_ON(gfn != kvm_mmu_page_get_gfn(sp, index))) | |
717 | pr_err_ratelimited("gfn mismatch under direct page %llx " | |
718 | "(expected %llx, got %llx)\n", | |
719 | sp->gfn, | |
720 | kvm_mmu_page_get_gfn(sp, index), gfn); | |
2032a93d LJ |
721 | } |
722 | ||
05da4558 | 723 | /* |
d4dbf470 TY |
724 | * Return the pointer to the large page information for a given gfn, |
725 | * handling slots that are not large page aligned. | |
05da4558 | 726 | */ |
d4dbf470 TY |
727 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
728 | struct kvm_memory_slot *slot, | |
729 | int level) | |
05da4558 MT |
730 | { |
731 | unsigned long idx; | |
732 | ||
fb03cb6f | 733 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
db3fe4eb | 734 | return &slot->arch.lpage_info[level - 2][idx]; |
05da4558 MT |
735 | } |
736 | ||
547ffaed XG |
737 | static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot, |
738 | gfn_t gfn, int count) | |
739 | { | |
740 | struct kvm_lpage_info *linfo; | |
741 | int i; | |
742 | ||
3bae0459 | 743 | for (i = PG_LEVEL_2M; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) { |
547ffaed XG |
744 | linfo = lpage_info_slot(gfn, slot, i); |
745 | linfo->disallow_lpage += count; | |
746 | WARN_ON(linfo->disallow_lpage < 0); | |
747 | } | |
748 | } | |
749 | ||
750 | void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
751 | { | |
752 | update_gfn_disallow_lpage_count(slot, gfn, 1); | |
753 | } | |
754 | ||
755 | void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
756 | { | |
757 | update_gfn_disallow_lpage_count(slot, gfn, -1); | |
758 | } | |
759 | ||
3ed1a478 | 760 | static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 761 | { |
699023e2 | 762 | struct kvm_memslots *slots; |
d25797b2 | 763 | struct kvm_memory_slot *slot; |
3ed1a478 | 764 | gfn_t gfn; |
05da4558 | 765 | |
56ca57f9 | 766 | kvm->arch.indirect_shadow_pages++; |
3ed1a478 | 767 | gfn = sp->gfn; |
699023e2 PB |
768 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
769 | slot = __gfn_to_memslot(slots, gfn); | |
56ca57f9 XG |
770 | |
771 | /* the non-leaf shadow pages are keeping readonly. */ | |
3bae0459 | 772 | if (sp->role.level > PG_LEVEL_4K) |
56ca57f9 XG |
773 | return kvm_slot_page_track_add_page(kvm, slot, gfn, |
774 | KVM_PAGE_TRACK_WRITE); | |
775 | ||
547ffaed | 776 | kvm_mmu_gfn_disallow_lpage(slot, gfn); |
05da4558 MT |
777 | } |
778 | ||
29cf0f50 | 779 | void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
b8e8c830 PB |
780 | { |
781 | if (sp->lpage_disallowed) | |
782 | return; | |
783 | ||
784 | ++kvm->stat.nx_lpage_splits; | |
1aa9b957 JS |
785 | list_add_tail(&sp->lpage_disallowed_link, |
786 | &kvm->arch.lpage_disallowed_mmu_pages); | |
b8e8c830 PB |
787 | sp->lpage_disallowed = true; |
788 | } | |
789 | ||
3ed1a478 | 790 | static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 791 | { |
699023e2 | 792 | struct kvm_memslots *slots; |
d25797b2 | 793 | struct kvm_memory_slot *slot; |
3ed1a478 | 794 | gfn_t gfn; |
05da4558 | 795 | |
56ca57f9 | 796 | kvm->arch.indirect_shadow_pages--; |
3ed1a478 | 797 | gfn = sp->gfn; |
699023e2 PB |
798 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
799 | slot = __gfn_to_memslot(slots, gfn); | |
3bae0459 | 800 | if (sp->role.level > PG_LEVEL_4K) |
56ca57f9 XG |
801 | return kvm_slot_page_track_remove_page(kvm, slot, gfn, |
802 | KVM_PAGE_TRACK_WRITE); | |
803 | ||
547ffaed | 804 | kvm_mmu_gfn_allow_lpage(slot, gfn); |
05da4558 MT |
805 | } |
806 | ||
29cf0f50 | 807 | void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
b8e8c830 PB |
808 | { |
809 | --kvm->stat.nx_lpage_splits; | |
810 | sp->lpage_disallowed = false; | |
1aa9b957 | 811 | list_del(&sp->lpage_disallowed_link); |
b8e8c830 PB |
812 | } |
813 | ||
5d163b1c XG |
814 | static struct kvm_memory_slot * |
815 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
816 | bool no_dirty_log) | |
05da4558 MT |
817 | { |
818 | struct kvm_memory_slot *slot; | |
5d163b1c | 819 | |
54bf36aa | 820 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
91b0d268 PB |
821 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID) |
822 | return NULL; | |
823 | if (no_dirty_log && slot->dirty_bitmap) | |
824 | return NULL; | |
5d163b1c XG |
825 | |
826 | return slot; | |
827 | } | |
828 | ||
290fc38d | 829 | /* |
018aabb5 | 830 | * About rmap_head encoding: |
cd4a4e53 | 831 | * |
018aabb5 TY |
832 | * If the bit zero of rmap_head->val is clear, then it points to the only spte |
833 | * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct | |
53c07b18 | 834 | * pte_list_desc containing more mappings. |
018aabb5 TY |
835 | */ |
836 | ||
837 | /* | |
838 | * Returns the number of pointers in the rmap chain, not counting the new one. | |
cd4a4e53 | 839 | */ |
53c07b18 | 840 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
018aabb5 | 841 | struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 842 | { |
53c07b18 | 843 | struct pte_list_desc *desc; |
53a27b39 | 844 | int i, count = 0; |
cd4a4e53 | 845 | |
018aabb5 | 846 | if (!rmap_head->val) { |
53c07b18 | 847 | rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte); |
018aabb5 TY |
848 | rmap_head->val = (unsigned long)spte; |
849 | } else if (!(rmap_head->val & 1)) { | |
53c07b18 XG |
850 | rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte); |
851 | desc = mmu_alloc_pte_list_desc(vcpu); | |
018aabb5 | 852 | desc->sptes[0] = (u64 *)rmap_head->val; |
d555c333 | 853 | desc->sptes[1] = spte; |
018aabb5 | 854 | rmap_head->val = (unsigned long)desc | 1; |
cb16a7b3 | 855 | ++count; |
cd4a4e53 | 856 | } else { |
53c07b18 | 857 | rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte); |
018aabb5 | 858 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
53c07b18 | 859 | while (desc->sptes[PTE_LIST_EXT-1] && desc->more) { |
cd4a4e53 | 860 | desc = desc->more; |
53c07b18 | 861 | count += PTE_LIST_EXT; |
53a27b39 | 862 | } |
53c07b18 XG |
863 | if (desc->sptes[PTE_LIST_EXT-1]) { |
864 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
cd4a4e53 AK |
865 | desc = desc->more; |
866 | } | |
d555c333 | 867 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 868 | ++count; |
d555c333 | 869 | desc->sptes[i] = spte; |
cd4a4e53 | 870 | } |
53a27b39 | 871 | return count; |
cd4a4e53 AK |
872 | } |
873 | ||
53c07b18 | 874 | static void |
018aabb5 TY |
875 | pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head, |
876 | struct pte_list_desc *desc, int i, | |
877 | struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
878 | { |
879 | int j; | |
880 | ||
53c07b18 | 881 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 882 | ; |
d555c333 AK |
883 | desc->sptes[i] = desc->sptes[j]; |
884 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
885 | if (j != 0) |
886 | return; | |
887 | if (!prev_desc && !desc->more) | |
fe3c2b4c | 888 | rmap_head->val = 0; |
cd4a4e53 AK |
889 | else |
890 | if (prev_desc) | |
891 | prev_desc->more = desc->more; | |
892 | else | |
018aabb5 | 893 | rmap_head->val = (unsigned long)desc->more | 1; |
53c07b18 | 894 | mmu_free_pte_list_desc(desc); |
cd4a4e53 AK |
895 | } |
896 | ||
8daf3462 | 897 | static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 898 | { |
53c07b18 XG |
899 | struct pte_list_desc *desc; |
900 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
901 | int i; |
902 | ||
018aabb5 | 903 | if (!rmap_head->val) { |
8daf3462 | 904 | pr_err("%s: %p 0->BUG\n", __func__, spte); |
cd4a4e53 | 905 | BUG(); |
018aabb5 | 906 | } else if (!(rmap_head->val & 1)) { |
8daf3462 | 907 | rmap_printk("%s: %p 1->0\n", __func__, spte); |
018aabb5 | 908 | if ((u64 *)rmap_head->val != spte) { |
8daf3462 | 909 | pr_err("%s: %p 1->BUG\n", __func__, spte); |
cd4a4e53 AK |
910 | BUG(); |
911 | } | |
018aabb5 | 912 | rmap_head->val = 0; |
cd4a4e53 | 913 | } else { |
8daf3462 | 914 | rmap_printk("%s: %p many->many\n", __func__, spte); |
018aabb5 | 915 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
cd4a4e53 AK |
916 | prev_desc = NULL; |
917 | while (desc) { | |
018aabb5 | 918 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) { |
d555c333 | 919 | if (desc->sptes[i] == spte) { |
018aabb5 TY |
920 | pte_list_desc_remove_entry(rmap_head, |
921 | desc, i, prev_desc); | |
cd4a4e53 AK |
922 | return; |
923 | } | |
018aabb5 | 924 | } |
cd4a4e53 AK |
925 | prev_desc = desc; |
926 | desc = desc->more; | |
927 | } | |
8daf3462 | 928 | pr_err("%s: %p many->many\n", __func__, spte); |
cd4a4e53 AK |
929 | BUG(); |
930 | } | |
931 | } | |
932 | ||
e7912386 WY |
933 | static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep) |
934 | { | |
935 | mmu_spte_clear_track_bits(sptep); | |
936 | __pte_list_remove(sptep, rmap_head); | |
937 | } | |
938 | ||
018aabb5 TY |
939 | static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level, |
940 | struct kvm_memory_slot *slot) | |
53c07b18 | 941 | { |
77d11309 | 942 | unsigned long idx; |
53c07b18 | 943 | |
77d11309 | 944 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
3bae0459 | 945 | return &slot->arch.rmap[level - PG_LEVEL_4K][idx]; |
53c07b18 XG |
946 | } |
947 | ||
018aabb5 TY |
948 | static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, |
949 | struct kvm_mmu_page *sp) | |
9b9b1492 | 950 | { |
699023e2 | 951 | struct kvm_memslots *slots; |
9b9b1492 TY |
952 | struct kvm_memory_slot *slot; |
953 | ||
699023e2 PB |
954 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
955 | slot = __gfn_to_memslot(slots, gfn); | |
e4cd1da9 | 956 | return __gfn_to_rmap(gfn, sp->role.level, slot); |
9b9b1492 TY |
957 | } |
958 | ||
f759e2b4 XG |
959 | static bool rmap_can_add(struct kvm_vcpu *vcpu) |
960 | { | |
356ec69a | 961 | struct kvm_mmu_memory_cache *mc; |
f759e2b4 | 962 | |
356ec69a | 963 | mc = &vcpu->arch.mmu_pte_list_desc_cache; |
94ce87ef | 964 | return kvm_mmu_memory_cache_nr_free_objects(mc); |
f759e2b4 XG |
965 | } |
966 | ||
53c07b18 XG |
967 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
968 | { | |
969 | struct kvm_mmu_page *sp; | |
018aabb5 | 970 | struct kvm_rmap_head *rmap_head; |
53c07b18 | 971 | |
57354682 | 972 | sp = sptep_to_sp(spte); |
53c07b18 | 973 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); |
018aabb5 TY |
974 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
975 | return pte_list_add(vcpu, spte, rmap_head); | |
53c07b18 XG |
976 | } |
977 | ||
53c07b18 XG |
978 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
979 | { | |
980 | struct kvm_mmu_page *sp; | |
981 | gfn_t gfn; | |
018aabb5 | 982 | struct kvm_rmap_head *rmap_head; |
53c07b18 | 983 | |
57354682 | 984 | sp = sptep_to_sp(spte); |
53c07b18 | 985 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); |
018aabb5 | 986 | rmap_head = gfn_to_rmap(kvm, gfn, sp); |
8daf3462 | 987 | __pte_list_remove(spte, rmap_head); |
53c07b18 XG |
988 | } |
989 | ||
1e3f42f0 TY |
990 | /* |
991 | * Used by the following functions to iterate through the sptes linked by a | |
992 | * rmap. All fields are private and not assumed to be used outside. | |
993 | */ | |
994 | struct rmap_iterator { | |
995 | /* private fields */ | |
996 | struct pte_list_desc *desc; /* holds the sptep if not NULL */ | |
997 | int pos; /* index of the sptep */ | |
998 | }; | |
999 | ||
1000 | /* | |
1001 | * Iteration must be started by this function. This should also be used after | |
1002 | * removing/dropping sptes from the rmap link because in such cases the | |
0a03cbda | 1003 | * information in the iterator may not be valid. |
1e3f42f0 TY |
1004 | * |
1005 | * Returns sptep if found, NULL otherwise. | |
1006 | */ | |
018aabb5 TY |
1007 | static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head, |
1008 | struct rmap_iterator *iter) | |
1e3f42f0 | 1009 | { |
77fbbbd2 TY |
1010 | u64 *sptep; |
1011 | ||
018aabb5 | 1012 | if (!rmap_head->val) |
1e3f42f0 TY |
1013 | return NULL; |
1014 | ||
018aabb5 | 1015 | if (!(rmap_head->val & 1)) { |
1e3f42f0 | 1016 | iter->desc = NULL; |
77fbbbd2 TY |
1017 | sptep = (u64 *)rmap_head->val; |
1018 | goto out; | |
1e3f42f0 TY |
1019 | } |
1020 | ||
018aabb5 | 1021 | iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
1e3f42f0 | 1022 | iter->pos = 0; |
77fbbbd2 TY |
1023 | sptep = iter->desc->sptes[iter->pos]; |
1024 | out: | |
1025 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1026 | return sptep; | |
1e3f42f0 TY |
1027 | } |
1028 | ||
1029 | /* | |
1030 | * Must be used with a valid iterator: e.g. after rmap_get_first(). | |
1031 | * | |
1032 | * Returns sptep if found, NULL otherwise. | |
1033 | */ | |
1034 | static u64 *rmap_get_next(struct rmap_iterator *iter) | |
1035 | { | |
77fbbbd2 TY |
1036 | u64 *sptep; |
1037 | ||
1e3f42f0 TY |
1038 | if (iter->desc) { |
1039 | if (iter->pos < PTE_LIST_EXT - 1) { | |
1e3f42f0 TY |
1040 | ++iter->pos; |
1041 | sptep = iter->desc->sptes[iter->pos]; | |
1042 | if (sptep) | |
77fbbbd2 | 1043 | goto out; |
1e3f42f0 TY |
1044 | } |
1045 | ||
1046 | iter->desc = iter->desc->more; | |
1047 | ||
1048 | if (iter->desc) { | |
1049 | iter->pos = 0; | |
1050 | /* desc->sptes[0] cannot be NULL */ | |
77fbbbd2 TY |
1051 | sptep = iter->desc->sptes[iter->pos]; |
1052 | goto out; | |
1e3f42f0 TY |
1053 | } |
1054 | } | |
1055 | ||
1056 | return NULL; | |
77fbbbd2 TY |
1057 | out: |
1058 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1059 | return sptep; | |
1e3f42f0 TY |
1060 | } |
1061 | ||
018aabb5 TY |
1062 | #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \ |
1063 | for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \ | |
77fbbbd2 | 1064 | _spte_; _spte_ = rmap_get_next(_iter_)) |
0d536790 | 1065 | |
c3707958 | 1066 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 1067 | { |
1df9f2dc | 1068 | if (mmu_spte_clear_track_bits(sptep)) |
eb45fda4 | 1069 | rmap_remove(kvm, sptep); |
be38d276 AK |
1070 | } |
1071 | ||
8e22f955 XG |
1072 | |
1073 | static bool __drop_large_spte(struct kvm *kvm, u64 *sptep) | |
1074 | { | |
1075 | if (is_large_pte(*sptep)) { | |
57354682 | 1076 | WARN_ON(sptep_to_sp(sptep)->role.level == PG_LEVEL_4K); |
8e22f955 XG |
1077 | drop_spte(kvm, sptep); |
1078 | --kvm->stat.lpages; | |
1079 | return true; | |
1080 | } | |
1081 | ||
1082 | return false; | |
1083 | } | |
1084 | ||
1085 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) | |
1086 | { | |
c3134ce2 | 1087 | if (__drop_large_spte(vcpu->kvm, sptep)) { |
57354682 | 1088 | struct kvm_mmu_page *sp = sptep_to_sp(sptep); |
c3134ce2 LT |
1089 | |
1090 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn, | |
1091 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
1092 | } | |
8e22f955 XG |
1093 | } |
1094 | ||
1095 | /* | |
49fde340 | 1096 | * Write-protect on the specified @sptep, @pt_protect indicates whether |
c126d94f | 1097 | * spte write-protection is caused by protecting shadow page table. |
49fde340 | 1098 | * |
b4619660 | 1099 | * Note: write protection is difference between dirty logging and spte |
49fde340 XG |
1100 | * protection: |
1101 | * - for dirty logging, the spte can be set to writable at anytime if | |
1102 | * its dirty bitmap is properly set. | |
1103 | * - for spte protection, the spte can be writable only after unsync-ing | |
1104 | * shadow page. | |
8e22f955 | 1105 | * |
c126d94f | 1106 | * Return true if tlb need be flushed. |
8e22f955 | 1107 | */ |
c4f138b4 | 1108 | static bool spte_write_protect(u64 *sptep, bool pt_protect) |
d13bc5b5 XG |
1109 | { |
1110 | u64 spte = *sptep; | |
1111 | ||
49fde340 | 1112 | if (!is_writable_pte(spte) && |
ea4114bc | 1113 | !(pt_protect && spte_can_locklessly_be_made_writable(spte))) |
d13bc5b5 XG |
1114 | return false; |
1115 | ||
1116 | rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep); | |
1117 | ||
49fde340 XG |
1118 | if (pt_protect) |
1119 | spte &= ~SPTE_MMU_WRITEABLE; | |
d13bc5b5 | 1120 | spte = spte & ~PT_WRITABLE_MASK; |
49fde340 | 1121 | |
c126d94f | 1122 | return mmu_spte_update(sptep, spte); |
d13bc5b5 XG |
1123 | } |
1124 | ||
018aabb5 TY |
1125 | static bool __rmap_write_protect(struct kvm *kvm, |
1126 | struct kvm_rmap_head *rmap_head, | |
245c3912 | 1127 | bool pt_protect) |
98348e95 | 1128 | { |
1e3f42f0 TY |
1129 | u64 *sptep; |
1130 | struct rmap_iterator iter; | |
d13bc5b5 | 1131 | bool flush = false; |
374cbac0 | 1132 | |
018aabb5 | 1133 | for_each_rmap_spte(rmap_head, &iter, sptep) |
c4f138b4 | 1134 | flush |= spte_write_protect(sptep, pt_protect); |
855149aa | 1135 | |
d13bc5b5 | 1136 | return flush; |
a0ed4607 TY |
1137 | } |
1138 | ||
c4f138b4 | 1139 | static bool spte_clear_dirty(u64 *sptep) |
f4b4b180 KH |
1140 | { |
1141 | u64 spte = *sptep; | |
1142 | ||
1143 | rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep); | |
1144 | ||
1f4e5fc8 | 1145 | MMU_WARN_ON(!spte_ad_enabled(spte)); |
f4b4b180 | 1146 | spte &= ~shadow_dirty_mask; |
f4b4b180 KH |
1147 | return mmu_spte_update(sptep, spte); |
1148 | } | |
1149 | ||
1f4e5fc8 | 1150 | static bool spte_wrprot_for_clear_dirty(u64 *sptep) |
ac8d57e5 PF |
1151 | { |
1152 | bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT, | |
1153 | (unsigned long *)sptep); | |
1f4e5fc8 | 1154 | if (was_writable && !spte_ad_enabled(*sptep)) |
ac8d57e5 PF |
1155 | kvm_set_pfn_dirty(spte_to_pfn(*sptep)); |
1156 | ||
1157 | return was_writable; | |
1158 | } | |
1159 | ||
1160 | /* | |
1161 | * Gets the GFN ready for another round of dirty logging by clearing the | |
1162 | * - D bit on ad-enabled SPTEs, and | |
1163 | * - W bit on ad-disabled SPTEs. | |
1164 | * Returns true iff any D or W bits were cleared. | |
1165 | */ | |
018aabb5 | 1166 | static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
f4b4b180 KH |
1167 | { |
1168 | u64 *sptep; | |
1169 | struct rmap_iterator iter; | |
1170 | bool flush = false; | |
1171 | ||
018aabb5 | 1172 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1f4e5fc8 PB |
1173 | if (spte_ad_need_write_protect(*sptep)) |
1174 | flush |= spte_wrprot_for_clear_dirty(sptep); | |
ac8d57e5 | 1175 | else |
1f4e5fc8 | 1176 | flush |= spte_clear_dirty(sptep); |
f4b4b180 KH |
1177 | |
1178 | return flush; | |
1179 | } | |
1180 | ||
c4f138b4 | 1181 | static bool spte_set_dirty(u64 *sptep) |
f4b4b180 KH |
1182 | { |
1183 | u64 spte = *sptep; | |
1184 | ||
1185 | rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep); | |
1186 | ||
1f4e5fc8 | 1187 | /* |
afaf0b2f | 1188 | * Similar to the !kvm_x86_ops.slot_disable_log_dirty case, |
1f4e5fc8 PB |
1189 | * do not bother adding back write access to pages marked |
1190 | * SPTE_AD_WRPROT_ONLY_MASK. | |
1191 | */ | |
f4b4b180 KH |
1192 | spte |= shadow_dirty_mask; |
1193 | ||
1194 | return mmu_spte_update(sptep, spte); | |
1195 | } | |
1196 | ||
018aabb5 | 1197 | static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
f4b4b180 KH |
1198 | { |
1199 | u64 *sptep; | |
1200 | struct rmap_iterator iter; | |
1201 | bool flush = false; | |
1202 | ||
018aabb5 | 1203 | for_each_rmap_spte(rmap_head, &iter, sptep) |
ac8d57e5 PF |
1204 | if (spte_ad_enabled(*sptep)) |
1205 | flush |= spte_set_dirty(sptep); | |
f4b4b180 KH |
1206 | |
1207 | return flush; | |
1208 | } | |
1209 | ||
5dc99b23 | 1210 | /** |
3b0f1d01 | 1211 | * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages |
5dc99b23 TY |
1212 | * @kvm: kvm instance |
1213 | * @slot: slot to protect | |
1214 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1215 | * @mask: indicates which pages we should protect | |
1216 | * | |
1217 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1218 | * logging we do not have any such mappings. | |
1219 | */ | |
3b0f1d01 | 1220 | static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, |
5dc99b23 TY |
1221 | struct kvm_memory_slot *slot, |
1222 | gfn_t gfn_offset, unsigned long mask) | |
a0ed4607 | 1223 | { |
018aabb5 | 1224 | struct kvm_rmap_head *rmap_head; |
a0ed4607 | 1225 | |
a6a0b05d BG |
1226 | if (kvm->arch.tdp_mmu_enabled) |
1227 | kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot, | |
1228 | slot->base_gfn + gfn_offset, mask, true); | |
5dc99b23 | 1229 | while (mask) { |
018aabb5 | 1230 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
3bae0459 | 1231 | PG_LEVEL_4K, slot); |
018aabb5 | 1232 | __rmap_write_protect(kvm, rmap_head, false); |
05da4558 | 1233 | |
5dc99b23 TY |
1234 | /* clear the first set bit */ |
1235 | mask &= mask - 1; | |
1236 | } | |
374cbac0 AK |
1237 | } |
1238 | ||
f4b4b180 | 1239 | /** |
ac8d57e5 PF |
1240 | * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write |
1241 | * protect the page if the D-bit isn't supported. | |
f4b4b180 KH |
1242 | * @kvm: kvm instance |
1243 | * @slot: slot to clear D-bit | |
1244 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1245 | * @mask: indicates which pages we should clear D-bit | |
1246 | * | |
1247 | * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap. | |
1248 | */ | |
1249 | void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, | |
1250 | struct kvm_memory_slot *slot, | |
1251 | gfn_t gfn_offset, unsigned long mask) | |
1252 | { | |
018aabb5 | 1253 | struct kvm_rmap_head *rmap_head; |
f4b4b180 | 1254 | |
a6a0b05d BG |
1255 | if (kvm->arch.tdp_mmu_enabled) |
1256 | kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot, | |
1257 | slot->base_gfn + gfn_offset, mask, false); | |
f4b4b180 | 1258 | while (mask) { |
018aabb5 | 1259 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
3bae0459 | 1260 | PG_LEVEL_4K, slot); |
018aabb5 | 1261 | __rmap_clear_dirty(kvm, rmap_head); |
f4b4b180 KH |
1262 | |
1263 | /* clear the first set bit */ | |
1264 | mask &= mask - 1; | |
1265 | } | |
1266 | } | |
1267 | EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked); | |
1268 | ||
3b0f1d01 KH |
1269 | /** |
1270 | * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected | |
1271 | * PT level pages. | |
1272 | * | |
1273 | * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to | |
1274 | * enable dirty logging for them. | |
1275 | * | |
1276 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1277 | * logging we do not have any such mappings. | |
1278 | */ | |
1279 | void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm, | |
1280 | struct kvm_memory_slot *slot, | |
1281 | gfn_t gfn_offset, unsigned long mask) | |
1282 | { | |
afaf0b2f SC |
1283 | if (kvm_x86_ops.enable_log_dirty_pt_masked) |
1284 | kvm_x86_ops.enable_log_dirty_pt_masked(kvm, slot, gfn_offset, | |
88178fd4 KH |
1285 | mask); |
1286 | else | |
1287 | kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask); | |
3b0f1d01 KH |
1288 | } |
1289 | ||
aeecee2e XG |
1290 | bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm, |
1291 | struct kvm_memory_slot *slot, u64 gfn) | |
95d4c16c | 1292 | { |
018aabb5 | 1293 | struct kvm_rmap_head *rmap_head; |
5dc99b23 | 1294 | int i; |
2f84569f | 1295 | bool write_protected = false; |
95d4c16c | 1296 | |
3bae0459 | 1297 | for (i = PG_LEVEL_4K; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) { |
018aabb5 | 1298 | rmap_head = __gfn_to_rmap(gfn, i, slot); |
aeecee2e | 1299 | write_protected |= __rmap_write_protect(kvm, rmap_head, true); |
5dc99b23 TY |
1300 | } |
1301 | ||
46044f72 BG |
1302 | if (kvm->arch.tdp_mmu_enabled) |
1303 | write_protected |= | |
1304 | kvm_tdp_mmu_write_protect_gfn(kvm, slot, gfn); | |
1305 | ||
5dc99b23 | 1306 | return write_protected; |
95d4c16c TY |
1307 | } |
1308 | ||
aeecee2e XG |
1309 | static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn) |
1310 | { | |
1311 | struct kvm_memory_slot *slot; | |
1312 | ||
1313 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); | |
1314 | return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn); | |
1315 | } | |
1316 | ||
018aabb5 | 1317 | static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
e930bffe | 1318 | { |
1e3f42f0 TY |
1319 | u64 *sptep; |
1320 | struct rmap_iterator iter; | |
6a49f85c | 1321 | bool flush = false; |
e930bffe | 1322 | |
018aabb5 | 1323 | while ((sptep = rmap_get_first(rmap_head, &iter))) { |
6a49f85c | 1324 | rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep); |
1e3f42f0 | 1325 | |
e7912386 | 1326 | pte_list_remove(rmap_head, sptep); |
6a49f85c | 1327 | flush = true; |
e930bffe | 1328 | } |
1e3f42f0 | 1329 | |
6a49f85c XG |
1330 | return flush; |
1331 | } | |
1332 | ||
018aabb5 | 1333 | static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
6a49f85c XG |
1334 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1335 | unsigned long data) | |
1336 | { | |
018aabb5 | 1337 | return kvm_zap_rmapp(kvm, rmap_head); |
e930bffe AA |
1338 | } |
1339 | ||
018aabb5 | 1340 | static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1341 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1342 | unsigned long data) | |
3da0dd43 | 1343 | { |
1e3f42f0 TY |
1344 | u64 *sptep; |
1345 | struct rmap_iterator iter; | |
3da0dd43 | 1346 | int need_flush = 0; |
1e3f42f0 | 1347 | u64 new_spte; |
3da0dd43 | 1348 | pte_t *ptep = (pte_t *)data; |
ba049e93 | 1349 | kvm_pfn_t new_pfn; |
3da0dd43 IE |
1350 | |
1351 | WARN_ON(pte_huge(*ptep)); | |
1352 | new_pfn = pte_pfn(*ptep); | |
1e3f42f0 | 1353 | |
0d536790 | 1354 | restart: |
018aabb5 | 1355 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
8a9522d2 | 1356 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n", |
f160c7b7 | 1357 | sptep, *sptep, gfn, level); |
1e3f42f0 | 1358 | |
3da0dd43 | 1359 | need_flush = 1; |
1e3f42f0 | 1360 | |
3da0dd43 | 1361 | if (pte_write(*ptep)) { |
e7912386 | 1362 | pte_list_remove(rmap_head, sptep); |
0d536790 | 1363 | goto restart; |
3da0dd43 | 1364 | } else { |
cb3eedab PB |
1365 | new_spte = kvm_mmu_changed_pte_notifier_make_spte( |
1366 | *sptep, new_pfn); | |
1e3f42f0 TY |
1367 | |
1368 | mmu_spte_clear_track_bits(sptep); | |
1369 | mmu_spte_set(sptep, new_spte); | |
3da0dd43 IE |
1370 | } |
1371 | } | |
1e3f42f0 | 1372 | |
3cc5ea94 LT |
1373 | if (need_flush && kvm_available_flush_tlb_with_range()) { |
1374 | kvm_flush_remote_tlbs_with_address(kvm, gfn, 1); | |
1375 | return 0; | |
1376 | } | |
1377 | ||
0cf853c5 | 1378 | return need_flush; |
3da0dd43 IE |
1379 | } |
1380 | ||
6ce1f4e2 XG |
1381 | struct slot_rmap_walk_iterator { |
1382 | /* input fields. */ | |
1383 | struct kvm_memory_slot *slot; | |
1384 | gfn_t start_gfn; | |
1385 | gfn_t end_gfn; | |
1386 | int start_level; | |
1387 | int end_level; | |
1388 | ||
1389 | /* output fields. */ | |
1390 | gfn_t gfn; | |
018aabb5 | 1391 | struct kvm_rmap_head *rmap; |
6ce1f4e2 XG |
1392 | int level; |
1393 | ||
1394 | /* private field. */ | |
018aabb5 | 1395 | struct kvm_rmap_head *end_rmap; |
6ce1f4e2 XG |
1396 | }; |
1397 | ||
1398 | static void | |
1399 | rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level) | |
1400 | { | |
1401 | iterator->level = level; | |
1402 | iterator->gfn = iterator->start_gfn; | |
1403 | iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot); | |
1404 | iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level, | |
1405 | iterator->slot); | |
1406 | } | |
1407 | ||
1408 | static void | |
1409 | slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator, | |
1410 | struct kvm_memory_slot *slot, int start_level, | |
1411 | int end_level, gfn_t start_gfn, gfn_t end_gfn) | |
1412 | { | |
1413 | iterator->slot = slot; | |
1414 | iterator->start_level = start_level; | |
1415 | iterator->end_level = end_level; | |
1416 | iterator->start_gfn = start_gfn; | |
1417 | iterator->end_gfn = end_gfn; | |
1418 | ||
1419 | rmap_walk_init_level(iterator, iterator->start_level); | |
1420 | } | |
1421 | ||
1422 | static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator) | |
1423 | { | |
1424 | return !!iterator->rmap; | |
1425 | } | |
1426 | ||
1427 | static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator) | |
1428 | { | |
1429 | if (++iterator->rmap <= iterator->end_rmap) { | |
1430 | iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level)); | |
1431 | return; | |
1432 | } | |
1433 | ||
1434 | if (++iterator->level > iterator->end_level) { | |
1435 | iterator->rmap = NULL; | |
1436 | return; | |
1437 | } | |
1438 | ||
1439 | rmap_walk_init_level(iterator, iterator->level); | |
1440 | } | |
1441 | ||
1442 | #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \ | |
1443 | _start_gfn, _end_gfn, _iter_) \ | |
1444 | for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \ | |
1445 | _end_level_, _start_gfn, _end_gfn); \ | |
1446 | slot_rmap_walk_okay(_iter_); \ | |
1447 | slot_rmap_walk_next(_iter_)) | |
1448 | ||
84504ef3 TY |
1449 | static int kvm_handle_hva_range(struct kvm *kvm, |
1450 | unsigned long start, | |
1451 | unsigned long end, | |
1452 | unsigned long data, | |
1453 | int (*handler)(struct kvm *kvm, | |
018aabb5 | 1454 | struct kvm_rmap_head *rmap_head, |
048212d0 | 1455 | struct kvm_memory_slot *slot, |
8a9522d2 ALC |
1456 | gfn_t gfn, |
1457 | int level, | |
84504ef3 | 1458 | unsigned long data)) |
e930bffe | 1459 | { |
bc6678a3 | 1460 | struct kvm_memslots *slots; |
be6ba0f0 | 1461 | struct kvm_memory_slot *memslot; |
6ce1f4e2 XG |
1462 | struct slot_rmap_walk_iterator iterator; |
1463 | int ret = 0; | |
9da0e4d5 | 1464 | int i; |
bc6678a3 | 1465 | |
9da0e4d5 PB |
1466 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1467 | slots = __kvm_memslots(kvm, i); | |
1468 | kvm_for_each_memslot(memslot, slots) { | |
1469 | unsigned long hva_start, hva_end; | |
1470 | gfn_t gfn_start, gfn_end; | |
e930bffe | 1471 | |
9da0e4d5 PB |
1472 | hva_start = max(start, memslot->userspace_addr); |
1473 | hva_end = min(end, memslot->userspace_addr + | |
1474 | (memslot->npages << PAGE_SHIFT)); | |
1475 | if (hva_start >= hva_end) | |
1476 | continue; | |
1477 | /* | |
1478 | * {gfn(page) | page intersects with [hva_start, hva_end)} = | |
1479 | * {gfn_start, gfn_start+1, ..., gfn_end-1}. | |
1480 | */ | |
1481 | gfn_start = hva_to_gfn_memslot(hva_start, memslot); | |
1482 | gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot); | |
1483 | ||
3bae0459 | 1484 | for_each_slot_rmap_range(memslot, PG_LEVEL_4K, |
e662ec3e | 1485 | KVM_MAX_HUGEPAGE_LEVEL, |
9da0e4d5 PB |
1486 | gfn_start, gfn_end - 1, |
1487 | &iterator) | |
1488 | ret |= handler(kvm, iterator.rmap, memslot, | |
1489 | iterator.gfn, iterator.level, data); | |
1490 | } | |
e930bffe AA |
1491 | } |
1492 | ||
f395302e | 1493 | return ret; |
e930bffe AA |
1494 | } |
1495 | ||
84504ef3 TY |
1496 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
1497 | unsigned long data, | |
018aabb5 TY |
1498 | int (*handler)(struct kvm *kvm, |
1499 | struct kvm_rmap_head *rmap_head, | |
048212d0 | 1500 | struct kvm_memory_slot *slot, |
8a9522d2 | 1501 | gfn_t gfn, int level, |
84504ef3 TY |
1502 | unsigned long data)) |
1503 | { | |
1504 | return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler); | |
e930bffe AA |
1505 | } |
1506 | ||
fdfe7cbd WD |
1507 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end, |
1508 | unsigned flags) | |
b3ae2096 | 1509 | { |
063afacd BG |
1510 | int r; |
1511 | ||
1512 | r = kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp); | |
1513 | ||
1514 | if (kvm->arch.tdp_mmu_enabled) | |
1515 | r |= kvm_tdp_mmu_zap_hva_range(kvm, start, end); | |
1516 | ||
1517 | return r; | |
b3ae2096 TY |
1518 | } |
1519 | ||
748c0e31 | 1520 | int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) |
3da0dd43 | 1521 | { |
1d8dd6b3 BG |
1522 | int r; |
1523 | ||
1524 | r = kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); | |
1525 | ||
1526 | if (kvm->arch.tdp_mmu_enabled) | |
1527 | r |= kvm_tdp_mmu_set_spte_hva(kvm, hva, &pte); | |
1528 | ||
1529 | return r; | |
e930bffe AA |
1530 | } |
1531 | ||
018aabb5 | 1532 | static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1533 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1534 | unsigned long data) | |
e930bffe | 1535 | { |
1e3f42f0 | 1536 | u64 *sptep; |
3f649ab7 | 1537 | struct rmap_iterator iter; |
e930bffe AA |
1538 | int young = 0; |
1539 | ||
f160c7b7 JS |
1540 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1541 | young |= mmu_spte_age(sptep); | |
0d536790 | 1542 | |
8a9522d2 | 1543 | trace_kvm_age_page(gfn, level, slot, young); |
e930bffe AA |
1544 | return young; |
1545 | } | |
1546 | ||
018aabb5 | 1547 | static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1548 | struct kvm_memory_slot *slot, gfn_t gfn, |
1549 | int level, unsigned long data) | |
8ee53820 | 1550 | { |
1e3f42f0 TY |
1551 | u64 *sptep; |
1552 | struct rmap_iterator iter; | |
8ee53820 | 1553 | |
83ef6c81 JS |
1554 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1555 | if (is_accessed_spte(*sptep)) | |
1556 | return 1; | |
83ef6c81 | 1557 | return 0; |
8ee53820 AA |
1558 | } |
1559 | ||
53a27b39 MT |
1560 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1561 | ||
852e3c19 | 1562 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 | 1563 | { |
018aabb5 | 1564 | struct kvm_rmap_head *rmap_head; |
852e3c19 JR |
1565 | struct kvm_mmu_page *sp; |
1566 | ||
57354682 | 1567 | sp = sptep_to_sp(spte); |
53a27b39 | 1568 | |
018aabb5 | 1569 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
53a27b39 | 1570 | |
018aabb5 | 1571 | kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0); |
c3134ce2 LT |
1572 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn, |
1573 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
53a27b39 MT |
1574 | } |
1575 | ||
57128468 | 1576 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end) |
e930bffe | 1577 | { |
f8e14497 BG |
1578 | int young = false; |
1579 | ||
1580 | young = kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp); | |
1581 | if (kvm->arch.tdp_mmu_enabled) | |
1582 | young |= kvm_tdp_mmu_age_hva_range(kvm, start, end); | |
1583 | ||
1584 | return young; | |
e930bffe AA |
1585 | } |
1586 | ||
8ee53820 AA |
1587 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) |
1588 | { | |
f8e14497 BG |
1589 | int young = false; |
1590 | ||
1591 | young = kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp); | |
1592 | if (kvm->arch.tdp_mmu_enabled) | |
1593 | young |= kvm_tdp_mmu_test_age_hva(kvm, hva); | |
1594 | ||
1595 | return young; | |
8ee53820 AA |
1596 | } |
1597 | ||
d6c69ee9 | 1598 | #ifdef MMU_DEBUG |
47ad8e68 | 1599 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1600 | { |
139bdb2d AK |
1601 | u64 *pos; |
1602 | u64 *end; | |
1603 | ||
47ad8e68 | 1604 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1605 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1606 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1607 | pos, *pos); |
6aa8b732 | 1608 | return 0; |
139bdb2d | 1609 | } |
6aa8b732 AK |
1610 | return 1; |
1611 | } | |
d6c69ee9 | 1612 | #endif |
6aa8b732 | 1613 | |
45221ab6 DH |
1614 | /* |
1615 | * This value is the sum of all of the kvm instances's | |
1616 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1617 | * aggregate version in order to make the slab shrinker | |
1618 | * faster | |
1619 | */ | |
bc8a3d89 | 1620 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, unsigned long nr) |
45221ab6 DH |
1621 | { |
1622 | kvm->arch.n_used_mmu_pages += nr; | |
1623 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
1624 | } | |
1625 | ||
834be0d8 | 1626 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) |
260746c0 | 1627 | { |
fa4a2c08 | 1628 | MMU_WARN_ON(!is_empty_shadow_page(sp->spt)); |
7775834a | 1629 | hlist_del(&sp->hash_link); |
bd4c86ea XG |
1630 | list_del(&sp->link); |
1631 | free_page((unsigned long)sp->spt); | |
834be0d8 GN |
1632 | if (!sp->role.direct) |
1633 | free_page((unsigned long)sp->gfns); | |
e8ad9a70 | 1634 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
1635 | } |
1636 | ||
cea0f0e7 AK |
1637 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1638 | { | |
114df303 | 1639 | return hash_64(gfn, KVM_MMU_HASH_SHIFT); |
cea0f0e7 AK |
1640 | } |
1641 | ||
714b93da | 1642 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1643 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1644 | { |
cea0f0e7 AK |
1645 | if (!parent_pte) |
1646 | return; | |
cea0f0e7 | 1647 | |
67052b35 | 1648 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1649 | } |
1650 | ||
4db35314 | 1651 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1652 | u64 *parent_pte) |
1653 | { | |
8daf3462 | 1654 | __pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1655 | } |
1656 | ||
bcdd9a93 XG |
1657 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
1658 | u64 *parent_pte) | |
1659 | { | |
1660 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 1661 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
1662 | } |
1663 | ||
47005792 | 1664 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct) |
ad8cfbe3 | 1665 | { |
67052b35 | 1666 | struct kvm_mmu_page *sp; |
7ddca7e4 | 1667 | |
94ce87ef SC |
1668 | sp = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache); |
1669 | sp->spt = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_shadow_page_cache); | |
67052b35 | 1670 | if (!direct) |
94ce87ef | 1671 | sp->gfns = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_gfn_array_cache); |
67052b35 | 1672 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
002c5f73 SC |
1673 | |
1674 | /* | |
1675 | * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages() | |
1676 | * depends on valid pages being added to the head of the list. See | |
1677 | * comments in kvm_zap_obsolete_pages(). | |
1678 | */ | |
ca333add | 1679 | sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen; |
67052b35 | 1680 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
67052b35 XG |
1681 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); |
1682 | return sp; | |
ad8cfbe3 MT |
1683 | } |
1684 | ||
67052b35 | 1685 | static void mark_unsync(u64 *spte); |
1047df1f | 1686 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 1687 | { |
74c4e63a TY |
1688 | u64 *sptep; |
1689 | struct rmap_iterator iter; | |
1690 | ||
1691 | for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) { | |
1692 | mark_unsync(sptep); | |
1693 | } | |
0074ff63 MT |
1694 | } |
1695 | ||
67052b35 | 1696 | static void mark_unsync(u64 *spte) |
0074ff63 | 1697 | { |
67052b35 | 1698 | struct kvm_mmu_page *sp; |
1047df1f | 1699 | unsigned int index; |
0074ff63 | 1700 | |
57354682 | 1701 | sp = sptep_to_sp(spte); |
1047df1f XG |
1702 | index = spte - sp->spt; |
1703 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1704 | return; |
1047df1f | 1705 | if (sp->unsync_children++) |
0074ff63 | 1706 | return; |
1047df1f | 1707 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1708 | } |
1709 | ||
e8bc217a | 1710 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1711 | struct kvm_mmu_page *sp) |
e8bc217a | 1712 | { |
1f50f1b3 | 1713 | return 0; |
e8bc217a MT |
1714 | } |
1715 | ||
0f53b5b1 XG |
1716 | static void nonpaging_update_pte(struct kvm_vcpu *vcpu, |
1717 | struct kvm_mmu_page *sp, u64 *spte, | |
7c562522 | 1718 | const void *pte) |
0f53b5b1 XG |
1719 | { |
1720 | WARN_ON(1); | |
1721 | } | |
1722 | ||
60c8aec6 MT |
1723 | #define KVM_PAGE_ARRAY_NR 16 |
1724 | ||
1725 | struct kvm_mmu_pages { | |
1726 | struct mmu_page_and_offset { | |
1727 | struct kvm_mmu_page *sp; | |
1728 | unsigned int idx; | |
1729 | } page[KVM_PAGE_ARRAY_NR]; | |
1730 | unsigned int nr; | |
1731 | }; | |
1732 | ||
cded19f3 HE |
1733 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1734 | int idx) | |
4731d4c7 | 1735 | { |
60c8aec6 | 1736 | int i; |
4731d4c7 | 1737 | |
60c8aec6 MT |
1738 | if (sp->unsync) |
1739 | for (i=0; i < pvec->nr; i++) | |
1740 | if (pvec->page[i].sp == sp) | |
1741 | return 0; | |
1742 | ||
1743 | pvec->page[pvec->nr].sp = sp; | |
1744 | pvec->page[pvec->nr].idx = idx; | |
1745 | pvec->nr++; | |
1746 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1747 | } | |
1748 | ||
fd951457 TY |
1749 | static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx) |
1750 | { | |
1751 | --sp->unsync_children; | |
1752 | WARN_ON((int)sp->unsync_children < 0); | |
1753 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1754 | } | |
1755 | ||
60c8aec6 MT |
1756 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, |
1757 | struct kvm_mmu_pages *pvec) | |
1758 | { | |
1759 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1760 | |
37178b8b | 1761 | for_each_set_bit(i, sp->unsync_child_bitmap, 512) { |
7a8f1a74 | 1762 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1763 | u64 ent = sp->spt[i]; |
1764 | ||
fd951457 TY |
1765 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) { |
1766 | clear_unsync_child_bit(sp, i); | |
1767 | continue; | |
1768 | } | |
7a8f1a74 | 1769 | |
e47c4aee | 1770 | child = to_shadow_page(ent & PT64_BASE_ADDR_MASK); |
7a8f1a74 XG |
1771 | |
1772 | if (child->unsync_children) { | |
1773 | if (mmu_pages_add(pvec, child, i)) | |
1774 | return -ENOSPC; | |
1775 | ||
1776 | ret = __mmu_unsync_walk(child, pvec); | |
fd951457 TY |
1777 | if (!ret) { |
1778 | clear_unsync_child_bit(sp, i); | |
1779 | continue; | |
1780 | } else if (ret > 0) { | |
7a8f1a74 | 1781 | nr_unsync_leaf += ret; |
fd951457 | 1782 | } else |
7a8f1a74 XG |
1783 | return ret; |
1784 | } else if (child->unsync) { | |
1785 | nr_unsync_leaf++; | |
1786 | if (mmu_pages_add(pvec, child, i)) | |
1787 | return -ENOSPC; | |
1788 | } else | |
fd951457 | 1789 | clear_unsync_child_bit(sp, i); |
4731d4c7 MT |
1790 | } |
1791 | ||
60c8aec6 MT |
1792 | return nr_unsync_leaf; |
1793 | } | |
1794 | ||
e23d3fef XG |
1795 | #define INVALID_INDEX (-1) |
1796 | ||
60c8aec6 MT |
1797 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, |
1798 | struct kvm_mmu_pages *pvec) | |
1799 | { | |
0a47cd85 | 1800 | pvec->nr = 0; |
60c8aec6 MT |
1801 | if (!sp->unsync_children) |
1802 | return 0; | |
1803 | ||
e23d3fef | 1804 | mmu_pages_add(pvec, sp, INVALID_INDEX); |
60c8aec6 | 1805 | return __mmu_unsync_walk(sp, pvec); |
4731d4c7 MT |
1806 | } |
1807 | ||
4731d4c7 MT |
1808 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1809 | { | |
1810 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1811 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1812 | sp->unsync = 0; |
1813 | --kvm->stat.mmu_unsync; | |
1814 | } | |
1815 | ||
83cdb568 SC |
1816 | static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1817 | struct list_head *invalid_list); | |
7775834a XG |
1818 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
1819 | struct list_head *invalid_list); | |
4731d4c7 | 1820 | |
ac101b7c SC |
1821 | #define for_each_valid_sp(_kvm, _sp, _list) \ |
1822 | hlist_for_each_entry(_sp, _list, hash_link) \ | |
fac026da | 1823 | if (is_obsolete_sp((_kvm), (_sp))) { \ |
f3414bc7 | 1824 | } else |
1044b030 TY |
1825 | |
1826 | #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \ | |
ac101b7c SC |
1827 | for_each_valid_sp(_kvm, _sp, \ |
1828 | &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)]) \ | |
f3414bc7 | 1829 | if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else |
7ae680eb | 1830 | |
47c42e6b SC |
1831 | static inline bool is_ept_sp(struct kvm_mmu_page *sp) |
1832 | { | |
1833 | return sp->role.cr0_wp && sp->role.smap_andnot_wp; | |
1834 | } | |
1835 | ||
f918b443 | 1836 | /* @sp->gfn should be write-protected at the call site */ |
1f50f1b3 PB |
1837 | static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1838 | struct list_head *invalid_list) | |
4731d4c7 | 1839 | { |
47c42e6b SC |
1840 | if ((!is_ept_sp(sp) && sp->role.gpte_is_8_bytes != !!is_pae(vcpu)) || |
1841 | vcpu->arch.mmu->sync_page(vcpu, sp) == 0) { | |
d98ba053 | 1842 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
1f50f1b3 | 1843 | return false; |
4731d4c7 MT |
1844 | } |
1845 | ||
1f50f1b3 | 1846 | return true; |
4731d4c7 MT |
1847 | } |
1848 | ||
a2113634 SC |
1849 | static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm, |
1850 | struct list_head *invalid_list, | |
1851 | bool remote_flush) | |
1852 | { | |
cfd32acf | 1853 | if (!remote_flush && list_empty(invalid_list)) |
a2113634 SC |
1854 | return false; |
1855 | ||
1856 | if (!list_empty(invalid_list)) | |
1857 | kvm_mmu_commit_zap_page(kvm, invalid_list); | |
1858 | else | |
1859 | kvm_flush_remote_tlbs(kvm); | |
1860 | return true; | |
1861 | } | |
1862 | ||
35a70510 PB |
1863 | static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu, |
1864 | struct list_head *invalid_list, | |
1865 | bool remote_flush, bool local_flush) | |
1d9dc7e0 | 1866 | { |
a2113634 | 1867 | if (kvm_mmu_remote_flush_or_zap(vcpu->kvm, invalid_list, remote_flush)) |
35a70510 | 1868 | return; |
d98ba053 | 1869 | |
a2113634 | 1870 | if (local_flush) |
8c8560b8 | 1871 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
1d9dc7e0 XG |
1872 | } |
1873 | ||
e37fa785 XG |
1874 | #ifdef CONFIG_KVM_MMU_AUDIT |
1875 | #include "mmu_audit.c" | |
1876 | #else | |
1877 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { } | |
1878 | static void mmu_audit_disable(void) { } | |
1879 | #endif | |
1880 | ||
002c5f73 SC |
1881 | static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp) |
1882 | { | |
fac026da SC |
1883 | return sp->role.invalid || |
1884 | unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen); | |
002c5f73 SC |
1885 | } |
1886 | ||
1f50f1b3 | 1887 | static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 1888 | struct list_head *invalid_list) |
1d9dc7e0 | 1889 | { |
9a43c5d9 PB |
1890 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1891 | return __kvm_sync_page(vcpu, sp, invalid_list); | |
1d9dc7e0 XG |
1892 | } |
1893 | ||
9f1a122f | 1894 | /* @gfn should be write-protected at the call site */ |
2a74003a PB |
1895 | static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn, |
1896 | struct list_head *invalid_list) | |
9f1a122f | 1897 | { |
9f1a122f | 1898 | struct kvm_mmu_page *s; |
2a74003a | 1899 | bool ret = false; |
9f1a122f | 1900 | |
b67bfe0d | 1901 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
7ae680eb | 1902 | if (!s->unsync) |
9f1a122f XG |
1903 | continue; |
1904 | ||
3bae0459 | 1905 | WARN_ON(s->role.level != PG_LEVEL_4K); |
2a74003a | 1906 | ret |= kvm_sync_page(vcpu, s, invalid_list); |
9f1a122f XG |
1907 | } |
1908 | ||
2a74003a | 1909 | return ret; |
9f1a122f XG |
1910 | } |
1911 | ||
60c8aec6 | 1912 | struct mmu_page_path { |
2a7266a8 YZ |
1913 | struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL]; |
1914 | unsigned int idx[PT64_ROOT_MAX_LEVEL]; | |
4731d4c7 MT |
1915 | }; |
1916 | ||
60c8aec6 | 1917 | #define for_each_sp(pvec, sp, parents, i) \ |
0a47cd85 | 1918 | for (i = mmu_pages_first(&pvec, &parents); \ |
60c8aec6 MT |
1919 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ |
1920 | i = mmu_pages_next(&pvec, &parents, i)) | |
1921 | ||
cded19f3 HE |
1922 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1923 | struct mmu_page_path *parents, | |
1924 | int i) | |
60c8aec6 MT |
1925 | { |
1926 | int n; | |
1927 | ||
1928 | for (n = i+1; n < pvec->nr; n++) { | |
1929 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
0a47cd85 PB |
1930 | unsigned idx = pvec->page[n].idx; |
1931 | int level = sp->role.level; | |
60c8aec6 | 1932 | |
0a47cd85 | 1933 | parents->idx[level-1] = idx; |
3bae0459 | 1934 | if (level == PG_LEVEL_4K) |
0a47cd85 | 1935 | break; |
60c8aec6 | 1936 | |
0a47cd85 | 1937 | parents->parent[level-2] = sp; |
60c8aec6 MT |
1938 | } |
1939 | ||
1940 | return n; | |
1941 | } | |
1942 | ||
0a47cd85 PB |
1943 | static int mmu_pages_first(struct kvm_mmu_pages *pvec, |
1944 | struct mmu_page_path *parents) | |
1945 | { | |
1946 | struct kvm_mmu_page *sp; | |
1947 | int level; | |
1948 | ||
1949 | if (pvec->nr == 0) | |
1950 | return 0; | |
1951 | ||
e23d3fef XG |
1952 | WARN_ON(pvec->page[0].idx != INVALID_INDEX); |
1953 | ||
0a47cd85 PB |
1954 | sp = pvec->page[0].sp; |
1955 | level = sp->role.level; | |
3bae0459 | 1956 | WARN_ON(level == PG_LEVEL_4K); |
0a47cd85 PB |
1957 | |
1958 | parents->parent[level-2] = sp; | |
1959 | ||
1960 | /* Also set up a sentinel. Further entries in pvec are all | |
1961 | * children of sp, so this element is never overwritten. | |
1962 | */ | |
1963 | parents->parent[level-1] = NULL; | |
1964 | return mmu_pages_next(pvec, parents, 0); | |
1965 | } | |
1966 | ||
cded19f3 | 1967 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1968 | { |
60c8aec6 MT |
1969 | struct kvm_mmu_page *sp; |
1970 | unsigned int level = 0; | |
1971 | ||
1972 | do { | |
1973 | unsigned int idx = parents->idx[level]; | |
60c8aec6 MT |
1974 | sp = parents->parent[level]; |
1975 | if (!sp) | |
1976 | return; | |
1977 | ||
e23d3fef | 1978 | WARN_ON(idx == INVALID_INDEX); |
fd951457 | 1979 | clear_unsync_child_bit(sp, idx); |
60c8aec6 | 1980 | level++; |
0a47cd85 | 1981 | } while (!sp->unsync_children); |
60c8aec6 | 1982 | } |
4731d4c7 | 1983 | |
60c8aec6 MT |
1984 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1985 | struct kvm_mmu_page *parent) | |
1986 | { | |
1987 | int i; | |
1988 | struct kvm_mmu_page *sp; | |
1989 | struct mmu_page_path parents; | |
1990 | struct kvm_mmu_pages pages; | |
d98ba053 | 1991 | LIST_HEAD(invalid_list); |
50c9e6f3 | 1992 | bool flush = false; |
60c8aec6 | 1993 | |
60c8aec6 | 1994 | while (mmu_unsync_walk(parent, &pages)) { |
2f84569f | 1995 | bool protected = false; |
b1a36821 MT |
1996 | |
1997 | for_each_sp(pages, sp, parents, i) | |
54bf36aa | 1998 | protected |= rmap_write_protect(vcpu, sp->gfn); |
b1a36821 | 1999 | |
50c9e6f3 | 2000 | if (protected) { |
b1a36821 | 2001 | kvm_flush_remote_tlbs(vcpu->kvm); |
50c9e6f3 PB |
2002 | flush = false; |
2003 | } | |
b1a36821 | 2004 | |
60c8aec6 | 2005 | for_each_sp(pages, sp, parents, i) { |
1f50f1b3 | 2006 | flush |= kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
2007 | mmu_pages_clear_parents(&parents); |
2008 | } | |
50c9e6f3 PB |
2009 | if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) { |
2010 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
2011 | cond_resched_lock(&vcpu->kvm->mmu_lock); | |
2012 | flush = false; | |
2013 | } | |
60c8aec6 | 2014 | } |
50c9e6f3 PB |
2015 | |
2016 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
4731d4c7 MT |
2017 | } |
2018 | ||
a30f47cb XG |
2019 | static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp) |
2020 | { | |
e5691a81 | 2021 | atomic_set(&sp->write_flooding_count, 0); |
a30f47cb XG |
2022 | } |
2023 | ||
2024 | static void clear_sp_write_flooding_count(u64 *spte) | |
2025 | { | |
57354682 | 2026 | __clear_sp_write_flooding_count(sptep_to_sp(spte)); |
a30f47cb XG |
2027 | } |
2028 | ||
cea0f0e7 AK |
2029 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
2030 | gfn_t gfn, | |
2031 | gva_t gaddr, | |
2032 | unsigned level, | |
f6e2c02b | 2033 | int direct, |
0a2b64c5 | 2034 | unsigned int access) |
cea0f0e7 | 2035 | { |
fb58a9c3 | 2036 | bool direct_mmu = vcpu->arch.mmu->direct_map; |
cea0f0e7 | 2037 | union kvm_mmu_page_role role; |
ac101b7c | 2038 | struct hlist_head *sp_list; |
cea0f0e7 | 2039 | unsigned quadrant; |
9f1a122f | 2040 | struct kvm_mmu_page *sp; |
9f1a122f | 2041 | bool need_sync = false; |
2a74003a | 2042 | bool flush = false; |
f3414bc7 | 2043 | int collisions = 0; |
2a74003a | 2044 | LIST_HEAD(invalid_list); |
cea0f0e7 | 2045 | |
36d9594d | 2046 | role = vcpu->arch.mmu->mmu_role.base; |
cea0f0e7 | 2047 | role.level = level; |
f6e2c02b | 2048 | role.direct = direct; |
84b0c8c6 | 2049 | if (role.direct) |
47c42e6b | 2050 | role.gpte_is_8_bytes = true; |
41074d07 | 2051 | role.access = access; |
fb58a9c3 | 2052 | if (!direct_mmu && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) { |
cea0f0e7 AK |
2053 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
2054 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
2055 | role.quadrant = quadrant; | |
2056 | } | |
ac101b7c SC |
2057 | |
2058 | sp_list = &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]; | |
2059 | for_each_valid_sp(vcpu->kvm, sp, sp_list) { | |
f3414bc7 DM |
2060 | if (sp->gfn != gfn) { |
2061 | collisions++; | |
2062 | continue; | |
2063 | } | |
2064 | ||
7ae680eb XG |
2065 | if (!need_sync && sp->unsync) |
2066 | need_sync = true; | |
4731d4c7 | 2067 | |
7ae680eb XG |
2068 | if (sp->role.word != role.word) |
2069 | continue; | |
4731d4c7 | 2070 | |
fb58a9c3 SC |
2071 | if (direct_mmu) |
2072 | goto trace_get_page; | |
2073 | ||
2a74003a PB |
2074 | if (sp->unsync) { |
2075 | /* The page is good, but __kvm_sync_page might still end | |
2076 | * up zapping it. If so, break in order to rebuild it. | |
2077 | */ | |
2078 | if (!__kvm_sync_page(vcpu, sp, &invalid_list)) | |
2079 | break; | |
2080 | ||
2081 | WARN_ON(!list_empty(&invalid_list)); | |
8c8560b8 | 2082 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
2a74003a | 2083 | } |
e02aa901 | 2084 | |
98bba238 | 2085 | if (sp->unsync_children) |
f6f6195b | 2086 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
e02aa901 | 2087 | |
a30f47cb | 2088 | __clear_sp_write_flooding_count(sp); |
fb58a9c3 SC |
2089 | |
2090 | trace_get_page: | |
7ae680eb | 2091 | trace_kvm_mmu_get_page(sp, false); |
f3414bc7 | 2092 | goto out; |
7ae680eb | 2093 | } |
47005792 | 2094 | |
dfc5aa00 | 2095 | ++vcpu->kvm->stat.mmu_cache_miss; |
47005792 TY |
2096 | |
2097 | sp = kvm_mmu_alloc_page(vcpu, direct); | |
2098 | ||
4db35314 AK |
2099 | sp->gfn = gfn; |
2100 | sp->role = role; | |
ac101b7c | 2101 | hlist_add_head(&sp->hash_link, sp_list); |
f6e2c02b | 2102 | if (!direct) { |
56ca57f9 XG |
2103 | /* |
2104 | * we should do write protection before syncing pages | |
2105 | * otherwise the content of the synced shadow page may | |
2106 | * be inconsistent with guest page table. | |
2107 | */ | |
2108 | account_shadowed(vcpu->kvm, sp); | |
3bae0459 | 2109 | if (level == PG_LEVEL_4K && rmap_write_protect(vcpu, gfn)) |
c3134ce2 | 2110 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1); |
9f1a122f | 2111 | |
3bae0459 | 2112 | if (level > PG_LEVEL_4K && need_sync) |
2a74003a | 2113 | flush |= kvm_sync_pages(vcpu, gfn, &invalid_list); |
4731d4c7 | 2114 | } |
f691fe1d | 2115 | trace_kvm_mmu_get_page(sp, true); |
2a74003a PB |
2116 | |
2117 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
f3414bc7 DM |
2118 | out: |
2119 | if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions) | |
2120 | vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions; | |
4db35314 | 2121 | return sp; |
cea0f0e7 AK |
2122 | } |
2123 | ||
7eb77e9f JS |
2124 | static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator, |
2125 | struct kvm_vcpu *vcpu, hpa_t root, | |
2126 | u64 addr) | |
2d11123a AK |
2127 | { |
2128 | iterator->addr = addr; | |
7eb77e9f | 2129 | iterator->shadow_addr = root; |
44dd3ffa | 2130 | iterator->level = vcpu->arch.mmu->shadow_root_level; |
81407ca5 | 2131 | |
2a7266a8 | 2132 | if (iterator->level == PT64_ROOT_4LEVEL && |
44dd3ffa VK |
2133 | vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL && |
2134 | !vcpu->arch.mmu->direct_map) | |
81407ca5 JR |
2135 | --iterator->level; |
2136 | ||
2d11123a | 2137 | if (iterator->level == PT32E_ROOT_LEVEL) { |
7eb77e9f JS |
2138 | /* |
2139 | * prev_root is currently only used for 64-bit hosts. So only | |
2140 | * the active root_hpa is valid here. | |
2141 | */ | |
44dd3ffa | 2142 | BUG_ON(root != vcpu->arch.mmu->root_hpa); |
7eb77e9f | 2143 | |
2d11123a | 2144 | iterator->shadow_addr |
44dd3ffa | 2145 | = vcpu->arch.mmu->pae_root[(addr >> 30) & 3]; |
2d11123a AK |
2146 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; |
2147 | --iterator->level; | |
2148 | if (!iterator->shadow_addr) | |
2149 | iterator->level = 0; | |
2150 | } | |
2151 | } | |
2152 | ||
7eb77e9f JS |
2153 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
2154 | struct kvm_vcpu *vcpu, u64 addr) | |
2155 | { | |
44dd3ffa | 2156 | shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa, |
7eb77e9f JS |
2157 | addr); |
2158 | } | |
2159 | ||
2d11123a AK |
2160 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) |
2161 | { | |
3bae0459 | 2162 | if (iterator->level < PG_LEVEL_4K) |
2d11123a | 2163 | return false; |
4d88954d | 2164 | |
2d11123a AK |
2165 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
2166 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
2167 | return true; | |
2168 | } | |
2169 | ||
c2a2ac2b XG |
2170 | static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator, |
2171 | u64 spte) | |
2d11123a | 2172 | { |
c2a2ac2b | 2173 | if (is_last_spte(spte, iterator->level)) { |
052331be XG |
2174 | iterator->level = 0; |
2175 | return; | |
2176 | } | |
2177 | ||
c2a2ac2b | 2178 | iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK; |
2d11123a AK |
2179 | --iterator->level; |
2180 | } | |
2181 | ||
c2a2ac2b XG |
2182 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) |
2183 | { | |
bb606a9b | 2184 | __shadow_walk_next(iterator, *iterator->sptep); |
c2a2ac2b XG |
2185 | } |
2186 | ||
cc4674d0 BG |
2187 | static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep, |
2188 | struct kvm_mmu_page *sp) | |
2189 | { | |
2190 | u64 spte; | |
2191 | ||
2192 | BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK); | |
2193 | ||
2194 | spte = make_nonleaf_spte(sp->spt, sp_ad_disabled(sp)); | |
2195 | ||
1df9f2dc | 2196 | mmu_spte_set(sptep, spte); |
98bba238 TY |
2197 | |
2198 | mmu_page_add_parent_pte(vcpu, sp, sptep); | |
2199 | ||
2200 | if (sp->unsync_children || sp->unsync) | |
2201 | mark_unsync(sptep); | |
32ef26a3 AK |
2202 | } |
2203 | ||
a357bd22 AK |
2204 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
2205 | unsigned direct_access) | |
2206 | { | |
2207 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
2208 | struct kvm_mmu_page *child; | |
2209 | ||
2210 | /* | |
2211 | * For the direct sp, if the guest pte's dirty bit | |
2212 | * changed form clean to dirty, it will corrupt the | |
2213 | * sp's access: allow writable in the read-only sp, | |
2214 | * so we should update the spte at this point to get | |
2215 | * a new sp with the correct access. | |
2216 | */ | |
e47c4aee | 2217 | child = to_shadow_page(*sptep & PT64_BASE_ADDR_MASK); |
a357bd22 AK |
2218 | if (child->role.access == direct_access) |
2219 | return; | |
2220 | ||
bcdd9a93 | 2221 | drop_parent_pte(child, sptep); |
c3134ce2 | 2222 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1); |
a357bd22 AK |
2223 | } |
2224 | } | |
2225 | ||
2de4085c BG |
2226 | /* Returns the number of zapped non-leaf child shadow pages. */ |
2227 | static int mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, | |
2228 | u64 *spte, struct list_head *invalid_list) | |
38e3b2b2 XG |
2229 | { |
2230 | u64 pte; | |
2231 | struct kvm_mmu_page *child; | |
2232 | ||
2233 | pte = *spte; | |
2234 | if (is_shadow_present_pte(pte)) { | |
505aef8f | 2235 | if (is_last_spte(pte, sp->role.level)) { |
c3707958 | 2236 | drop_spte(kvm, spte); |
505aef8f XG |
2237 | if (is_large_pte(pte)) |
2238 | --kvm->stat.lpages; | |
2239 | } else { | |
e47c4aee | 2240 | child = to_shadow_page(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2241 | drop_parent_pte(child, spte); |
2de4085c BG |
2242 | |
2243 | /* | |
2244 | * Recursively zap nested TDP SPs, parentless SPs are | |
2245 | * unlikely to be used again in the near future. This | |
2246 | * avoids retaining a large number of stale nested SPs. | |
2247 | */ | |
2248 | if (tdp_enabled && invalid_list && | |
2249 | child->role.guest_mode && !child->parent_ptes.val) | |
2250 | return kvm_mmu_prepare_zap_page(kvm, child, | |
2251 | invalid_list); | |
38e3b2b2 | 2252 | } |
ace569e0 | 2253 | } else if (is_mmio_spte(pte)) { |
ce88decf | 2254 | mmu_spte_clear_no_track(spte); |
ace569e0 | 2255 | } |
2de4085c | 2256 | return 0; |
38e3b2b2 XG |
2257 | } |
2258 | ||
2de4085c BG |
2259 | static int kvm_mmu_page_unlink_children(struct kvm *kvm, |
2260 | struct kvm_mmu_page *sp, | |
2261 | struct list_head *invalid_list) | |
a436036b | 2262 | { |
2de4085c | 2263 | int zapped = 0; |
697fe2e2 | 2264 | unsigned i; |
697fe2e2 | 2265 | |
38e3b2b2 | 2266 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
2de4085c BG |
2267 | zapped += mmu_page_zap_pte(kvm, sp, sp->spt + i, invalid_list); |
2268 | ||
2269 | return zapped; | |
a436036b AK |
2270 | } |
2271 | ||
31aa2b44 | 2272 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b | 2273 | { |
1e3f42f0 TY |
2274 | u64 *sptep; |
2275 | struct rmap_iterator iter; | |
a436036b | 2276 | |
018aabb5 | 2277 | while ((sptep = rmap_get_first(&sp->parent_ptes, &iter))) |
1e3f42f0 | 2278 | drop_parent_pte(sp, sptep); |
31aa2b44 AK |
2279 | } |
2280 | ||
60c8aec6 | 2281 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
2282 | struct kvm_mmu_page *parent, |
2283 | struct list_head *invalid_list) | |
4731d4c7 | 2284 | { |
60c8aec6 MT |
2285 | int i, zapped = 0; |
2286 | struct mmu_page_path parents; | |
2287 | struct kvm_mmu_pages pages; | |
4731d4c7 | 2288 | |
3bae0459 | 2289 | if (parent->role.level == PG_LEVEL_4K) |
4731d4c7 | 2290 | return 0; |
60c8aec6 | 2291 | |
60c8aec6 MT |
2292 | while (mmu_unsync_walk(parent, &pages)) { |
2293 | struct kvm_mmu_page *sp; | |
2294 | ||
2295 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 2296 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 2297 | mmu_pages_clear_parents(&parents); |
77662e00 | 2298 | zapped++; |
60c8aec6 | 2299 | } |
60c8aec6 MT |
2300 | } |
2301 | ||
2302 | return zapped; | |
4731d4c7 MT |
2303 | } |
2304 | ||
83cdb568 SC |
2305 | static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm, |
2306 | struct kvm_mmu_page *sp, | |
2307 | struct list_head *invalid_list, | |
2308 | int *nr_zapped) | |
31aa2b44 | 2309 | { |
83cdb568 | 2310 | bool list_unstable; |
f691fe1d | 2311 | |
7775834a | 2312 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 2313 | ++kvm->stat.mmu_shadow_zapped; |
83cdb568 | 2314 | *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list); |
2de4085c | 2315 | *nr_zapped += kvm_mmu_page_unlink_children(kvm, sp, invalid_list); |
31aa2b44 | 2316 | kvm_mmu_unlink_parents(kvm, sp); |
5304b8d3 | 2317 | |
83cdb568 SC |
2318 | /* Zapping children means active_mmu_pages has become unstable. */ |
2319 | list_unstable = *nr_zapped; | |
2320 | ||
f6e2c02b | 2321 | if (!sp->role.invalid && !sp->role.direct) |
3ed1a478 | 2322 | unaccount_shadowed(kvm, sp); |
5304b8d3 | 2323 | |
4731d4c7 MT |
2324 | if (sp->unsync) |
2325 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 2326 | if (!sp->root_count) { |
54a4f023 | 2327 | /* Count self */ |
83cdb568 | 2328 | (*nr_zapped)++; |
f95eec9b SC |
2329 | |
2330 | /* | |
2331 | * Already invalid pages (previously active roots) are not on | |
2332 | * the active page list. See list_del() in the "else" case of | |
2333 | * !sp->root_count. | |
2334 | */ | |
2335 | if (sp->role.invalid) | |
2336 | list_add(&sp->link, invalid_list); | |
2337 | else | |
2338 | list_move(&sp->link, invalid_list); | |
aa6bd187 | 2339 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 2340 | } else { |
f95eec9b SC |
2341 | /* |
2342 | * Remove the active root from the active page list, the root | |
2343 | * will be explicitly freed when the root_count hits zero. | |
2344 | */ | |
2345 | list_del(&sp->link); | |
05988d72 | 2346 | |
10605204 SC |
2347 | /* |
2348 | * Obsolete pages cannot be used on any vCPUs, see the comment | |
2349 | * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also | |
2350 | * treats invalid shadow pages as being obsolete. | |
2351 | */ | |
2352 | if (!is_obsolete_sp(kvm, sp)) | |
05988d72 | 2353 | kvm_reload_remote_mmus(kvm); |
2e53d63a | 2354 | } |
7775834a | 2355 | |
b8e8c830 PB |
2356 | if (sp->lpage_disallowed) |
2357 | unaccount_huge_nx_page(kvm, sp); | |
2358 | ||
7775834a | 2359 | sp->role.invalid = 1; |
83cdb568 SC |
2360 | return list_unstable; |
2361 | } | |
2362 | ||
2363 | static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, | |
2364 | struct list_head *invalid_list) | |
2365 | { | |
2366 | int nr_zapped; | |
2367 | ||
2368 | __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped); | |
2369 | return nr_zapped; | |
a436036b AK |
2370 | } |
2371 | ||
7775834a XG |
2372 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
2373 | struct list_head *invalid_list) | |
2374 | { | |
945315b9 | 2375 | struct kvm_mmu_page *sp, *nsp; |
7775834a XG |
2376 | |
2377 | if (list_empty(invalid_list)) | |
2378 | return; | |
2379 | ||
c142786c | 2380 | /* |
9753f529 LT |
2381 | * We need to make sure everyone sees our modifications to |
2382 | * the page tables and see changes to vcpu->mode here. The barrier | |
2383 | * in the kvm_flush_remote_tlbs() achieves this. This pairs | |
2384 | * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end. | |
2385 | * | |
2386 | * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit | |
2387 | * guest mode and/or lockless shadow page table walks. | |
c142786c AK |
2388 | */ |
2389 | kvm_flush_remote_tlbs(kvm); | |
c2a2ac2b | 2390 | |
945315b9 | 2391 | list_for_each_entry_safe(sp, nsp, invalid_list, link) { |
7775834a | 2392 | WARN_ON(!sp->role.invalid || sp->root_count); |
aa6bd187 | 2393 | kvm_mmu_free_page(sp); |
945315b9 | 2394 | } |
7775834a XG |
2395 | } |
2396 | ||
6b82ef2c SC |
2397 | static unsigned long kvm_mmu_zap_oldest_mmu_pages(struct kvm *kvm, |
2398 | unsigned long nr_to_zap) | |
5da59607 | 2399 | { |
6b82ef2c SC |
2400 | unsigned long total_zapped = 0; |
2401 | struct kvm_mmu_page *sp, *tmp; | |
ba7888dd | 2402 | LIST_HEAD(invalid_list); |
6b82ef2c SC |
2403 | bool unstable; |
2404 | int nr_zapped; | |
5da59607 TY |
2405 | |
2406 | if (list_empty(&kvm->arch.active_mmu_pages)) | |
ba7888dd SC |
2407 | return 0; |
2408 | ||
6b82ef2c SC |
2409 | restart: |
2410 | list_for_each_entry_safe(sp, tmp, &kvm->arch.active_mmu_pages, link) { | |
2411 | /* | |
2412 | * Don't zap active root pages, the page itself can't be freed | |
2413 | * and zapping it will just force vCPUs to realloc and reload. | |
2414 | */ | |
2415 | if (sp->root_count) | |
2416 | continue; | |
2417 | ||
2418 | unstable = __kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, | |
2419 | &nr_zapped); | |
2420 | total_zapped += nr_zapped; | |
2421 | if (total_zapped >= nr_to_zap) | |
ba7888dd SC |
2422 | break; |
2423 | ||
6b82ef2c SC |
2424 | if (unstable) |
2425 | goto restart; | |
ba7888dd | 2426 | } |
5da59607 | 2427 | |
6b82ef2c SC |
2428 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
2429 | ||
2430 | kvm->stat.mmu_recycled += total_zapped; | |
2431 | return total_zapped; | |
2432 | } | |
2433 | ||
afe8d7e6 SC |
2434 | static inline unsigned long kvm_mmu_available_pages(struct kvm *kvm) |
2435 | { | |
2436 | if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages) | |
2437 | return kvm->arch.n_max_mmu_pages - | |
2438 | kvm->arch.n_used_mmu_pages; | |
2439 | ||
2440 | return 0; | |
5da59607 TY |
2441 | } |
2442 | ||
ba7888dd SC |
2443 | static int make_mmu_pages_available(struct kvm_vcpu *vcpu) |
2444 | { | |
6b82ef2c | 2445 | unsigned long avail = kvm_mmu_available_pages(vcpu->kvm); |
ba7888dd | 2446 | |
6b82ef2c | 2447 | if (likely(avail >= KVM_MIN_FREE_MMU_PAGES)) |
ba7888dd SC |
2448 | return 0; |
2449 | ||
6b82ef2c | 2450 | kvm_mmu_zap_oldest_mmu_pages(vcpu->kvm, KVM_REFILL_PAGES - avail); |
ba7888dd SC |
2451 | |
2452 | if (!kvm_mmu_available_pages(vcpu->kvm)) | |
2453 | return -ENOSPC; | |
2454 | return 0; | |
2455 | } | |
2456 | ||
82ce2c96 IE |
2457 | /* |
2458 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 2459 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 2460 | */ |
bc8a3d89 | 2461 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages) |
82ce2c96 | 2462 | { |
b34cb590 TY |
2463 | spin_lock(&kvm->mmu_lock); |
2464 | ||
49d5ca26 | 2465 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
6b82ef2c SC |
2466 | kvm_mmu_zap_oldest_mmu_pages(kvm, kvm->arch.n_used_mmu_pages - |
2467 | goal_nr_mmu_pages); | |
82ce2c96 | 2468 | |
49d5ca26 | 2469 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 2470 | } |
82ce2c96 | 2471 | |
49d5ca26 | 2472 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
b34cb590 TY |
2473 | |
2474 | spin_unlock(&kvm->mmu_lock); | |
82ce2c96 IE |
2475 | } |
2476 | ||
1cb3f3ae | 2477 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 2478 | { |
4db35314 | 2479 | struct kvm_mmu_page *sp; |
d98ba053 | 2480 | LIST_HEAD(invalid_list); |
a436036b AK |
2481 | int r; |
2482 | ||
9ad17b10 | 2483 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 2484 | r = 0; |
1cb3f3ae | 2485 | spin_lock(&kvm->mmu_lock); |
b67bfe0d | 2486 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn) { |
9ad17b10 | 2487 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
2488 | sp->role.word); |
2489 | r = 1; | |
f41d335a | 2490 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 2491 | } |
d98ba053 | 2492 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
1cb3f3ae XG |
2493 | spin_unlock(&kvm->mmu_lock); |
2494 | ||
a436036b | 2495 | return r; |
cea0f0e7 | 2496 | } |
1cb3f3ae | 2497 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page); |
cea0f0e7 | 2498 | |
5c520e90 | 2499 | static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
9cf5cf5a XG |
2500 | { |
2501 | trace_kvm_mmu_unsync_page(sp); | |
2502 | ++vcpu->kvm->stat.mmu_unsync; | |
2503 | sp->unsync = 1; | |
2504 | ||
2505 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
2506 | } |
2507 | ||
5a9624af PB |
2508 | bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, |
2509 | bool can_unsync) | |
4731d4c7 | 2510 | { |
5c520e90 | 2511 | struct kvm_mmu_page *sp; |
4731d4c7 | 2512 | |
3d0c27ad XG |
2513 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) |
2514 | return true; | |
9cf5cf5a | 2515 | |
5c520e90 | 2516 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
36a2e677 | 2517 | if (!can_unsync) |
3d0c27ad | 2518 | return true; |
36a2e677 | 2519 | |
5c520e90 XG |
2520 | if (sp->unsync) |
2521 | continue; | |
9cf5cf5a | 2522 | |
3bae0459 | 2523 | WARN_ON(sp->role.level != PG_LEVEL_4K); |
5c520e90 | 2524 | kvm_unsync_page(vcpu, sp); |
4731d4c7 | 2525 | } |
3d0c27ad | 2526 | |
578e1c4d JS |
2527 | /* |
2528 | * We need to ensure that the marking of unsync pages is visible | |
2529 | * before the SPTE is updated to allow writes because | |
2530 | * kvm_mmu_sync_roots() checks the unsync flags without holding | |
2531 | * the MMU lock and so can race with this. If the SPTE was updated | |
2532 | * before the page had been marked as unsync-ed, something like the | |
2533 | * following could happen: | |
2534 | * | |
2535 | * CPU 1 CPU 2 | |
2536 | * --------------------------------------------------------------------- | |
2537 | * 1.2 Host updates SPTE | |
2538 | * to be writable | |
2539 | * 2.1 Guest writes a GPTE for GVA X. | |
2540 | * (GPTE being in the guest page table shadowed | |
2541 | * by the SP from CPU 1.) | |
2542 | * This reads SPTE during the page table walk. | |
2543 | * Since SPTE.W is read as 1, there is no | |
2544 | * fault. | |
2545 | * | |
2546 | * 2.2 Guest issues TLB flush. | |
2547 | * That causes a VM Exit. | |
2548 | * | |
2549 | * 2.3 kvm_mmu_sync_pages() reads sp->unsync. | |
2550 | * Since it is false, so it just returns. | |
2551 | * | |
2552 | * 2.4 Guest accesses GVA X. | |
2553 | * Since the mapping in the SP was not updated, | |
2554 | * so the old mapping for GVA X incorrectly | |
2555 | * gets used. | |
2556 | * 1.1 Host marks SP | |
2557 | * as unsync | |
2558 | * (sp->unsync = true) | |
2559 | * | |
2560 | * The write barrier below ensures that 1.1 happens before 1.2 and thus | |
2561 | * the situation in 2.4 does not arise. The implicit barrier in 2.2 | |
2562 | * pairs with this write barrier. | |
2563 | */ | |
2564 | smp_wmb(); | |
2565 | ||
3d0c27ad | 2566 | return false; |
4731d4c7 MT |
2567 | } |
2568 | ||
799a4190 BG |
2569 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
2570 | unsigned int pte_access, int level, | |
2571 | gfn_t gfn, kvm_pfn_t pfn, bool speculative, | |
2572 | bool can_unsync, bool host_writable) | |
2573 | { | |
2574 | u64 spte; | |
2575 | struct kvm_mmu_page *sp; | |
2576 | int ret; | |
2577 | ||
2578 | if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access)) | |
2579 | return 0; | |
2580 | ||
2581 | sp = sptep_to_sp(sptep); | |
2582 | ||
2583 | ret = make_spte(vcpu, pte_access, level, gfn, pfn, *sptep, speculative, | |
2584 | can_unsync, host_writable, sp_ad_disabled(sp), &spte); | |
2585 | ||
2586 | if (spte & PT_WRITABLE_MASK) | |
2587 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
2588 | ||
12703759 SC |
2589 | if (*sptep == spte) |
2590 | ret |= SET_SPTE_SPURIOUS; | |
2591 | else if (mmu_spte_update(sptep, spte)) | |
5ce4786f | 2592 | ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH; |
1e73f9dd MT |
2593 | return ret; |
2594 | } | |
2595 | ||
0a2b64c5 | 2596 | static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
e88b8093 | 2597 | unsigned int pte_access, bool write_fault, int level, |
0a2b64c5 BG |
2598 | gfn_t gfn, kvm_pfn_t pfn, bool speculative, |
2599 | bool host_writable) | |
1e73f9dd MT |
2600 | { |
2601 | int was_rmapped = 0; | |
53a27b39 | 2602 | int rmap_count; |
5ce4786f | 2603 | int set_spte_ret; |
c4371c2a | 2604 | int ret = RET_PF_FIXED; |
c2a4eadf | 2605 | bool flush = false; |
1e73f9dd | 2606 | |
f7616203 XG |
2607 | pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__, |
2608 | *sptep, write_fault, gfn); | |
1e73f9dd | 2609 | |
afd28fe1 | 2610 | if (is_shadow_present_pte(*sptep)) { |
1e73f9dd MT |
2611 | /* |
2612 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2613 | * the parent of the now unreachable PTE. | |
2614 | */ | |
3bae0459 | 2615 | if (level > PG_LEVEL_4K && !is_large_pte(*sptep)) { |
1e73f9dd | 2616 | struct kvm_mmu_page *child; |
d555c333 | 2617 | u64 pte = *sptep; |
1e73f9dd | 2618 | |
e47c4aee | 2619 | child = to_shadow_page(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2620 | drop_parent_pte(child, sptep); |
c2a4eadf | 2621 | flush = true; |
d555c333 | 2622 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2623 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2624 | spte_to_pfn(*sptep), pfn); |
c3707958 | 2625 | drop_spte(vcpu->kvm, sptep); |
c2a4eadf | 2626 | flush = true; |
6bed6b9e JR |
2627 | } else |
2628 | was_rmapped = 1; | |
1e73f9dd | 2629 | } |
852e3c19 | 2630 | |
5ce4786f JS |
2631 | set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn, |
2632 | speculative, true, host_writable); | |
2633 | if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) { | |
1e73f9dd | 2634 | if (write_fault) |
9b8ebbdb | 2635 | ret = RET_PF_EMULATE; |
8c8560b8 | 2636 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
a378b4e6 | 2637 | } |
c3134ce2 | 2638 | |
c2a4eadf | 2639 | if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush) |
c3134ce2 LT |
2640 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, |
2641 | KVM_PAGES_PER_HPAGE(level)); | |
1e73f9dd | 2642 | |
029499b4 | 2643 | if (unlikely(is_mmio_spte(*sptep))) |
9b8ebbdb | 2644 | ret = RET_PF_EMULATE; |
ce88decf | 2645 | |
12703759 SC |
2646 | /* |
2647 | * The fault is fully spurious if and only if the new SPTE and old SPTE | |
2648 | * are identical, and emulation is not required. | |
2649 | */ | |
2650 | if ((set_spte_ret & SET_SPTE_SPURIOUS) && ret == RET_PF_FIXED) { | |
2651 | WARN_ON_ONCE(!was_rmapped); | |
2652 | return RET_PF_SPURIOUS; | |
2653 | } | |
2654 | ||
d555c333 | 2655 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
335e192a | 2656 | trace_kvm_mmu_set_spte(level, gfn, sptep); |
d555c333 | 2657 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2658 | ++vcpu->kvm->stat.lpages; |
2659 | ||
ffb61bb3 | 2660 | if (is_shadow_present_pte(*sptep)) { |
ffb61bb3 XG |
2661 | if (!was_rmapped) { |
2662 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
2663 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
2664 | rmap_recycle(vcpu, sptep, gfn); | |
2665 | } | |
1c4f1fd6 | 2666 | } |
cb9aaa30 | 2667 | |
9b8ebbdb | 2668 | return ret; |
1c4f1fd6 AK |
2669 | } |
2670 | ||
ba049e93 | 2671 | static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
957ed9ef XG |
2672 | bool no_dirty_log) |
2673 | { | |
2674 | struct kvm_memory_slot *slot; | |
957ed9ef | 2675 | |
5d163b1c | 2676 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
903816fa | 2677 | if (!slot) |
6c8ee57b | 2678 | return KVM_PFN_ERR_FAULT; |
957ed9ef | 2679 | |
037d92dc | 2680 | return gfn_to_pfn_memslot_atomic(slot, gfn); |
957ed9ef XG |
2681 | } |
2682 | ||
2683 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
2684 | struct kvm_mmu_page *sp, | |
2685 | u64 *start, u64 *end) | |
2686 | { | |
2687 | struct page *pages[PTE_PREFETCH_NUM]; | |
d9ef13c2 | 2688 | struct kvm_memory_slot *slot; |
0a2b64c5 | 2689 | unsigned int access = sp->role.access; |
957ed9ef XG |
2690 | int i, ret; |
2691 | gfn_t gfn; | |
2692 | ||
2693 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
d9ef13c2 PB |
2694 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK); |
2695 | if (!slot) | |
957ed9ef XG |
2696 | return -1; |
2697 | ||
d9ef13c2 | 2698 | ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start); |
957ed9ef XG |
2699 | if (ret <= 0) |
2700 | return -1; | |
2701 | ||
43fdcda9 | 2702 | for (i = 0; i < ret; i++, gfn++, start++) { |
e88b8093 | 2703 | mmu_set_spte(vcpu, start, access, false, sp->role.level, gfn, |
029499b4 | 2704 | page_to_pfn(pages[i]), true, true); |
43fdcda9 JS |
2705 | put_page(pages[i]); |
2706 | } | |
957ed9ef XG |
2707 | |
2708 | return 0; | |
2709 | } | |
2710 | ||
2711 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2712 | struct kvm_mmu_page *sp, u64 *sptep) | |
2713 | { | |
2714 | u64 *spte, *start = NULL; | |
2715 | int i; | |
2716 | ||
2717 | WARN_ON(!sp->role.direct); | |
2718 | ||
2719 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2720 | spte = sp->spt + i; | |
2721 | ||
2722 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 2723 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
2724 | if (!start) |
2725 | continue; | |
2726 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2727 | break; | |
2728 | start = NULL; | |
2729 | } else if (!start) | |
2730 | start = spte; | |
2731 | } | |
2732 | } | |
2733 | ||
2734 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2735 | { | |
2736 | struct kvm_mmu_page *sp; | |
2737 | ||
57354682 | 2738 | sp = sptep_to_sp(sptep); |
ac8d57e5 | 2739 | |
957ed9ef | 2740 | /* |
ac8d57e5 PF |
2741 | * Without accessed bits, there's no way to distinguish between |
2742 | * actually accessed translations and prefetched, so disable pte | |
2743 | * prefetch if accessed bits aren't available. | |
957ed9ef | 2744 | */ |
ac8d57e5 | 2745 | if (sp_ad_disabled(sp)) |
957ed9ef XG |
2746 | return; |
2747 | ||
3bae0459 | 2748 | if (sp->role.level > PG_LEVEL_4K) |
957ed9ef XG |
2749 | return; |
2750 | ||
2751 | __direct_pte_prefetch(vcpu, sp, sptep); | |
2752 | } | |
2753 | ||
db543216 | 2754 | static int host_pfn_mapping_level(struct kvm_vcpu *vcpu, gfn_t gfn, |
293e306e | 2755 | kvm_pfn_t pfn, struct kvm_memory_slot *slot) |
db543216 | 2756 | { |
db543216 SC |
2757 | unsigned long hva; |
2758 | pte_t *pte; | |
2759 | int level; | |
2760 | ||
e851265a | 2761 | if (!PageCompound(pfn_to_page(pfn)) && !kvm_is_zone_device_pfn(pfn)) |
3bae0459 | 2762 | return PG_LEVEL_4K; |
db543216 | 2763 | |
293e306e SC |
2764 | /* |
2765 | * Note, using the already-retrieved memslot and __gfn_to_hva_memslot() | |
2766 | * is not solely for performance, it's also necessary to avoid the | |
2767 | * "writable" check in __gfn_to_hva_many(), which will always fail on | |
2768 | * read-only memslots due to gfn_to_hva() assuming writes. Earlier | |
2769 | * page fault steps have already verified the guest isn't writing a | |
2770 | * read-only memslot. | |
2771 | */ | |
db543216 SC |
2772 | hva = __gfn_to_hva_memslot(slot, gfn); |
2773 | ||
2774 | pte = lookup_address_in_mm(vcpu->kvm->mm, hva, &level); | |
2775 | if (unlikely(!pte)) | |
3bae0459 | 2776 | return PG_LEVEL_4K; |
db543216 SC |
2777 | |
2778 | return level; | |
2779 | } | |
2780 | ||
bb18842e BG |
2781 | int kvm_mmu_hugepage_adjust(struct kvm_vcpu *vcpu, gfn_t gfn, |
2782 | int max_level, kvm_pfn_t *pfnp, | |
2783 | bool huge_page_disallowed, int *req_level) | |
0885904d | 2784 | { |
293e306e | 2785 | struct kvm_memory_slot *slot; |
2c0629f4 | 2786 | struct kvm_lpage_info *linfo; |
0885904d | 2787 | kvm_pfn_t pfn = *pfnp; |
17eff019 | 2788 | kvm_pfn_t mask; |
83f06fa7 | 2789 | int level; |
17eff019 | 2790 | |
3cf06612 SC |
2791 | *req_level = PG_LEVEL_4K; |
2792 | ||
3bae0459 SC |
2793 | if (unlikely(max_level == PG_LEVEL_4K)) |
2794 | return PG_LEVEL_4K; | |
17eff019 | 2795 | |
e851265a | 2796 | if (is_error_noslot_pfn(pfn) || kvm_is_reserved_pfn(pfn)) |
3bae0459 | 2797 | return PG_LEVEL_4K; |
17eff019 | 2798 | |
293e306e SC |
2799 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, true); |
2800 | if (!slot) | |
3bae0459 | 2801 | return PG_LEVEL_4K; |
293e306e | 2802 | |
1d92d2e8 | 2803 | max_level = min(max_level, max_huge_page_level); |
3bae0459 | 2804 | for ( ; max_level > PG_LEVEL_4K; max_level--) { |
2c0629f4 SC |
2805 | linfo = lpage_info_slot(gfn, slot, max_level); |
2806 | if (!linfo->disallow_lpage) | |
293e306e SC |
2807 | break; |
2808 | } | |
2809 | ||
3bae0459 SC |
2810 | if (max_level == PG_LEVEL_4K) |
2811 | return PG_LEVEL_4K; | |
293e306e SC |
2812 | |
2813 | level = host_pfn_mapping_level(vcpu, gfn, pfn, slot); | |
3bae0459 | 2814 | if (level == PG_LEVEL_4K) |
83f06fa7 | 2815 | return level; |
17eff019 | 2816 | |
3cf06612 SC |
2817 | *req_level = level = min(level, max_level); |
2818 | ||
2819 | /* | |
2820 | * Enforce the iTLB multihit workaround after capturing the requested | |
2821 | * level, which will be used to do precise, accurate accounting. | |
2822 | */ | |
2823 | if (huge_page_disallowed) | |
2824 | return PG_LEVEL_4K; | |
0885904d SC |
2825 | |
2826 | /* | |
17eff019 SC |
2827 | * mmu_notifier_retry() was successful and mmu_lock is held, so |
2828 | * the pmd can't be split from under us. | |
0885904d | 2829 | */ |
17eff019 SC |
2830 | mask = KVM_PAGES_PER_HPAGE(level) - 1; |
2831 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
2832 | *pfnp = pfn & ~mask; | |
83f06fa7 SC |
2833 | |
2834 | return level; | |
0885904d SC |
2835 | } |
2836 | ||
bb18842e BG |
2837 | void disallowed_hugepage_adjust(u64 spte, gfn_t gfn, int cur_level, |
2838 | kvm_pfn_t *pfnp, int *goal_levelp) | |
b8e8c830 | 2839 | { |
bb18842e | 2840 | int level = *goal_levelp; |
b8e8c830 | 2841 | |
7d945312 | 2842 | if (cur_level == level && level > PG_LEVEL_4K && |
b8e8c830 PB |
2843 | is_shadow_present_pte(spte) && |
2844 | !is_large_pte(spte)) { | |
2845 | /* | |
2846 | * A small SPTE exists for this pfn, but FNAME(fetch) | |
2847 | * and __direct_map would like to create a large PTE | |
2848 | * instead: just force them to go down another level, | |
2849 | * patching back for them into pfn the next 9 bits of | |
2850 | * the address. | |
2851 | */ | |
7d945312 BG |
2852 | u64 page_mask = KVM_PAGES_PER_HPAGE(level) - |
2853 | KVM_PAGES_PER_HPAGE(level - 1); | |
b8e8c830 | 2854 | *pfnp |= gfn & page_mask; |
bb18842e | 2855 | (*goal_levelp)--; |
b8e8c830 PB |
2856 | } |
2857 | } | |
2858 | ||
6c2fd34f | 2859 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, |
83f06fa7 | 2860 | int map_writable, int max_level, kvm_pfn_t pfn, |
6c2fd34f | 2861 | bool prefault, bool is_tdp) |
140754bc | 2862 | { |
6c2fd34f SC |
2863 | bool nx_huge_page_workaround_enabled = is_nx_huge_page_enabled(); |
2864 | bool write = error_code & PFERR_WRITE_MASK; | |
2865 | bool exec = error_code & PFERR_FETCH_MASK; | |
2866 | bool huge_page_disallowed = exec && nx_huge_page_workaround_enabled; | |
3fcf2d1b | 2867 | struct kvm_shadow_walk_iterator it; |
140754bc | 2868 | struct kvm_mmu_page *sp; |
3cf06612 | 2869 | int level, req_level, ret; |
3fcf2d1b PB |
2870 | gfn_t gfn = gpa >> PAGE_SHIFT; |
2871 | gfn_t base_gfn = gfn; | |
6aa8b732 | 2872 | |
0c7a98e3 | 2873 | if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa))) |
3fcf2d1b | 2874 | return RET_PF_RETRY; |
989c6b34 | 2875 | |
3cf06612 SC |
2876 | level = kvm_mmu_hugepage_adjust(vcpu, gfn, max_level, &pfn, |
2877 | huge_page_disallowed, &req_level); | |
4cd071d1 | 2878 | |
335e192a | 2879 | trace_kvm_mmu_spte_requested(gpa, level, pfn); |
3fcf2d1b | 2880 | for_each_shadow_entry(vcpu, gpa, it) { |
b8e8c830 PB |
2881 | /* |
2882 | * We cannot overwrite existing page tables with an NX | |
2883 | * large page, as the leaf could be executable. | |
2884 | */ | |
dcc70651 | 2885 | if (nx_huge_page_workaround_enabled) |
7d945312 BG |
2886 | disallowed_hugepage_adjust(*it.sptep, gfn, it.level, |
2887 | &pfn, &level); | |
b8e8c830 | 2888 | |
3fcf2d1b PB |
2889 | base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
2890 | if (it.level == level) | |
9f652d21 | 2891 | break; |
6aa8b732 | 2892 | |
3fcf2d1b PB |
2893 | drop_large_spte(vcpu, it.sptep); |
2894 | if (!is_shadow_present_pte(*it.sptep)) { | |
2895 | sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr, | |
2896 | it.level - 1, true, ACC_ALL); | |
c9fa0b3b | 2897 | |
3fcf2d1b | 2898 | link_shadow_page(vcpu, it.sptep, sp); |
5bcaf3e1 SC |
2899 | if (is_tdp && huge_page_disallowed && |
2900 | req_level >= it.level) | |
b8e8c830 | 2901 | account_huge_nx_page(vcpu->kvm, sp); |
9f652d21 AK |
2902 | } |
2903 | } | |
3fcf2d1b PB |
2904 | |
2905 | ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL, | |
2906 | write, level, base_gfn, pfn, prefault, | |
2907 | map_writable); | |
12703759 SC |
2908 | if (ret == RET_PF_SPURIOUS) |
2909 | return ret; | |
2910 | ||
3fcf2d1b PB |
2911 | direct_pte_prefetch(vcpu, it.sptep); |
2912 | ++vcpu->stat.pf_fixed; | |
2913 | return ret; | |
6aa8b732 AK |
2914 | } |
2915 | ||
77db5cbd | 2916 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 2917 | { |
585a8b9b | 2918 | send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk); |
bf998156 HY |
2919 | } |
2920 | ||
ba049e93 | 2921 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn) |
bf998156 | 2922 | { |
4d8b81ab XG |
2923 | /* |
2924 | * Do not cache the mmio info caused by writing the readonly gfn | |
2925 | * into the spte otherwise read access on readonly gfn also can | |
2926 | * caused mmio page fault and treat it as mmio access. | |
4d8b81ab XG |
2927 | */ |
2928 | if (pfn == KVM_PFN_ERR_RO_FAULT) | |
9b8ebbdb | 2929 | return RET_PF_EMULATE; |
4d8b81ab | 2930 | |
e6c1502b | 2931 | if (pfn == KVM_PFN_ERR_HWPOISON) { |
54bf36aa | 2932 | kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current); |
9b8ebbdb | 2933 | return RET_PF_RETRY; |
d7c55201 | 2934 | } |
edba23e5 | 2935 | |
2c151b25 | 2936 | return -EFAULT; |
bf998156 HY |
2937 | } |
2938 | ||
d7c55201 | 2939 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, |
0a2b64c5 BG |
2940 | kvm_pfn_t pfn, unsigned int access, |
2941 | int *ret_val) | |
d7c55201 | 2942 | { |
d7c55201 | 2943 | /* The pfn is invalid, report the error! */ |
81c52c56 | 2944 | if (unlikely(is_error_pfn(pfn))) { |
d7c55201 | 2945 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); |
798e88b3 | 2946 | return true; |
d7c55201 XG |
2947 | } |
2948 | ||
ce88decf | 2949 | if (unlikely(is_noslot_pfn(pfn))) |
4af77151 SC |
2950 | vcpu_cache_mmio_info(vcpu, gva, gfn, |
2951 | access & shadow_mmio_access_mask); | |
d7c55201 | 2952 | |
798e88b3 | 2953 | return false; |
d7c55201 XG |
2954 | } |
2955 | ||
e5552fd2 | 2956 | static bool page_fault_can_be_fast(u32 error_code) |
c7ba5b48 | 2957 | { |
1c118b82 XG |
2958 | /* |
2959 | * Do not fix the mmio spte with invalid generation number which | |
2960 | * need to be updated by slow page fault path. | |
2961 | */ | |
2962 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
2963 | return false; | |
2964 | ||
f160c7b7 JS |
2965 | /* See if the page fault is due to an NX violation */ |
2966 | if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)) | |
2967 | == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)))) | |
2968 | return false; | |
2969 | ||
c7ba5b48 | 2970 | /* |
f160c7b7 JS |
2971 | * #PF can be fast if: |
2972 | * 1. The shadow page table entry is not present, which could mean that | |
2973 | * the fault is potentially caused by access tracking (if enabled). | |
2974 | * 2. The shadow page table entry is present and the fault | |
2975 | * is caused by write-protect, that means we just need change the W | |
2976 | * bit of the spte which can be done out of mmu-lock. | |
2977 | * | |
2978 | * However, if access tracking is disabled we know that a non-present | |
2979 | * page must be a genuine page fault where we have to create a new SPTE. | |
2980 | * So, if access tracking is disabled, we return true only for write | |
2981 | * accesses to a present page. | |
c7ba5b48 | 2982 | */ |
c7ba5b48 | 2983 | |
f160c7b7 JS |
2984 | return shadow_acc_track_mask != 0 || |
2985 | ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)) | |
2986 | == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)); | |
c7ba5b48 XG |
2987 | } |
2988 | ||
97dceba2 JS |
2989 | /* |
2990 | * Returns true if the SPTE was fixed successfully. Otherwise, | |
2991 | * someone else modified the SPTE from its original value. | |
2992 | */ | |
c7ba5b48 | 2993 | static bool |
92a476cb | 2994 | fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d3e328f2 | 2995 | u64 *sptep, u64 old_spte, u64 new_spte) |
c7ba5b48 | 2996 | { |
c7ba5b48 XG |
2997 | gfn_t gfn; |
2998 | ||
2999 | WARN_ON(!sp->role.direct); | |
3000 | ||
9b51a630 KH |
3001 | /* |
3002 | * Theoretically we could also set dirty bit (and flush TLB) here in | |
3003 | * order to eliminate unnecessary PML logging. See comments in | |
3004 | * set_spte. But fast_page_fault is very unlikely to happen with PML | |
3005 | * enabled, so we do not do this. This might result in the same GPA | |
3006 | * to be logged in PML buffer again when the write really happens, and | |
3007 | * eventually to be called by mark_page_dirty twice. But it's also no | |
3008 | * harm. This also avoids the TLB flush needed after setting dirty bit | |
3009 | * so non-PML cases won't be impacted. | |
3010 | * | |
3011 | * Compare with set_spte where instead shadow_dirty_mask is set. | |
3012 | */ | |
f160c7b7 | 3013 | if (cmpxchg64(sptep, old_spte, new_spte) != old_spte) |
97dceba2 JS |
3014 | return false; |
3015 | ||
d3e328f2 | 3016 | if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) { |
f160c7b7 JS |
3017 | /* |
3018 | * The gfn of direct spte is stable since it is | |
3019 | * calculated by sp->gfn. | |
3020 | */ | |
3021 | gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt); | |
3022 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
3023 | } | |
c7ba5b48 XG |
3024 | |
3025 | return true; | |
3026 | } | |
3027 | ||
d3e328f2 JS |
3028 | static bool is_access_allowed(u32 fault_err_code, u64 spte) |
3029 | { | |
3030 | if (fault_err_code & PFERR_FETCH_MASK) | |
3031 | return is_executable_pte(spte); | |
3032 | ||
3033 | if (fault_err_code & PFERR_WRITE_MASK) | |
3034 | return is_writable_pte(spte); | |
3035 | ||
3036 | /* Fault was on Read access */ | |
3037 | return spte & PT_PRESENT_MASK; | |
3038 | } | |
3039 | ||
c7ba5b48 | 3040 | /* |
c4371c2a | 3041 | * Returns one of RET_PF_INVALID, RET_PF_FIXED or RET_PF_SPURIOUS. |
c7ba5b48 | 3042 | */ |
c4371c2a SC |
3043 | static int fast_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
3044 | u32 error_code) | |
c7ba5b48 XG |
3045 | { |
3046 | struct kvm_shadow_walk_iterator iterator; | |
92a476cb | 3047 | struct kvm_mmu_page *sp; |
c4371c2a | 3048 | int ret = RET_PF_INVALID; |
c7ba5b48 | 3049 | u64 spte = 0ull; |
97dceba2 | 3050 | uint retry_count = 0; |
c7ba5b48 | 3051 | |
e5552fd2 | 3052 | if (!page_fault_can_be_fast(error_code)) |
c4371c2a | 3053 | return ret; |
c7ba5b48 XG |
3054 | |
3055 | walk_shadow_page_lockless_begin(vcpu); | |
c7ba5b48 | 3056 | |
97dceba2 | 3057 | do { |
d3e328f2 | 3058 | u64 new_spte; |
c7ba5b48 | 3059 | |
736c291c | 3060 | for_each_shadow_entry_lockless(vcpu, cr2_or_gpa, iterator, spte) |
f9fa2509 | 3061 | if (!is_shadow_present_pte(spte)) |
d162f30a JS |
3062 | break; |
3063 | ||
57354682 | 3064 | sp = sptep_to_sp(iterator.sptep); |
97dceba2 JS |
3065 | if (!is_last_spte(spte, sp->role.level)) |
3066 | break; | |
c7ba5b48 | 3067 | |
97dceba2 | 3068 | /* |
f160c7b7 JS |
3069 | * Check whether the memory access that caused the fault would |
3070 | * still cause it if it were to be performed right now. If not, | |
3071 | * then this is a spurious fault caused by TLB lazily flushed, | |
3072 | * or some other CPU has already fixed the PTE after the | |
3073 | * current CPU took the fault. | |
97dceba2 JS |
3074 | * |
3075 | * Need not check the access of upper level table entries since | |
3076 | * they are always ACC_ALL. | |
3077 | */ | |
d3e328f2 | 3078 | if (is_access_allowed(error_code, spte)) { |
c4371c2a | 3079 | ret = RET_PF_SPURIOUS; |
d3e328f2 JS |
3080 | break; |
3081 | } | |
f160c7b7 | 3082 | |
d3e328f2 JS |
3083 | new_spte = spte; |
3084 | ||
3085 | if (is_access_track_spte(spte)) | |
3086 | new_spte = restore_acc_track_spte(new_spte); | |
3087 | ||
3088 | /* | |
3089 | * Currently, to simplify the code, write-protection can | |
3090 | * be removed in the fast path only if the SPTE was | |
3091 | * write-protected for dirty-logging or access tracking. | |
3092 | */ | |
3093 | if ((error_code & PFERR_WRITE_MASK) && | |
e6302698 | 3094 | spte_can_locklessly_be_made_writable(spte)) { |
d3e328f2 | 3095 | new_spte |= PT_WRITABLE_MASK; |
f160c7b7 JS |
3096 | |
3097 | /* | |
d3e328f2 JS |
3098 | * Do not fix write-permission on the large spte. Since |
3099 | * we only dirty the first page into the dirty-bitmap in | |
3100 | * fast_pf_fix_direct_spte(), other pages are missed | |
3101 | * if its slot has dirty logging enabled. | |
3102 | * | |
3103 | * Instead, we let the slow page fault path create a | |
3104 | * normal spte to fix the access. | |
3105 | * | |
3106 | * See the comments in kvm_arch_commit_memory_region(). | |
f160c7b7 | 3107 | */ |
3bae0459 | 3108 | if (sp->role.level > PG_LEVEL_4K) |
f160c7b7 | 3109 | break; |
97dceba2 | 3110 | } |
c7ba5b48 | 3111 | |
f160c7b7 | 3112 | /* Verify that the fault can be handled in the fast path */ |
d3e328f2 JS |
3113 | if (new_spte == spte || |
3114 | !is_access_allowed(error_code, new_spte)) | |
97dceba2 JS |
3115 | break; |
3116 | ||
3117 | /* | |
3118 | * Currently, fast page fault only works for direct mapping | |
3119 | * since the gfn is not stable for indirect shadow page. See | |
3ecad8c2 | 3120 | * Documentation/virt/kvm/locking.rst to get more detail. |
97dceba2 | 3121 | */ |
c4371c2a SC |
3122 | if (fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte, |
3123 | new_spte)) { | |
3124 | ret = RET_PF_FIXED; | |
97dceba2 | 3125 | break; |
c4371c2a | 3126 | } |
97dceba2 JS |
3127 | |
3128 | if (++retry_count > 4) { | |
3129 | printk_once(KERN_WARNING | |
3130 | "kvm: Fast #PF retrying more than 4 times.\n"); | |
3131 | break; | |
3132 | } | |
3133 | ||
97dceba2 | 3134 | } while (true); |
c126d94f | 3135 | |
736c291c | 3136 | trace_fast_page_fault(vcpu, cr2_or_gpa, error_code, iterator.sptep, |
c4371c2a | 3137 | spte, ret); |
c7ba5b48 XG |
3138 | walk_shadow_page_lockless_end(vcpu); |
3139 | ||
c4371c2a | 3140 | return ret; |
c7ba5b48 XG |
3141 | } |
3142 | ||
74b566e6 JS |
3143 | static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa, |
3144 | struct list_head *invalid_list) | |
17ac10ad | 3145 | { |
4db35314 | 3146 | struct kvm_mmu_page *sp; |
17ac10ad | 3147 | |
74b566e6 | 3148 | if (!VALID_PAGE(*root_hpa)) |
7b53aa56 | 3149 | return; |
35af577a | 3150 | |
e47c4aee | 3151 | sp = to_shadow_page(*root_hpa & PT64_BASE_ADDR_MASK); |
02c00b3a BG |
3152 | |
3153 | if (kvm_mmu_put_root(kvm, sp)) { | |
3154 | if (sp->tdp_mmu_page) | |
3155 | kvm_tdp_mmu_free_root(kvm, sp); | |
3156 | else if (sp->role.invalid) | |
3157 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); | |
3158 | } | |
17ac10ad | 3159 | |
74b566e6 JS |
3160 | *root_hpa = INVALID_PAGE; |
3161 | } | |
3162 | ||
08fb59d8 | 3163 | /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */ |
6a82cd1c VK |
3164 | void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
3165 | ulong roots_to_free) | |
74b566e6 | 3166 | { |
4d710de9 | 3167 | struct kvm *kvm = vcpu->kvm; |
74b566e6 JS |
3168 | int i; |
3169 | LIST_HEAD(invalid_list); | |
08fb59d8 | 3170 | bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT; |
74b566e6 | 3171 | |
b94742c9 | 3172 | BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG); |
74b566e6 | 3173 | |
08fb59d8 | 3174 | /* Before acquiring the MMU lock, see if we need to do any real work. */ |
b94742c9 JS |
3175 | if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) { |
3176 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
3177 | if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) && | |
3178 | VALID_PAGE(mmu->prev_roots[i].hpa)) | |
3179 | break; | |
3180 | ||
3181 | if (i == KVM_MMU_NUM_PREV_ROOTS) | |
3182 | return; | |
3183 | } | |
35af577a | 3184 | |
4d710de9 | 3185 | spin_lock(&kvm->mmu_lock); |
17ac10ad | 3186 | |
b94742c9 JS |
3187 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) |
3188 | if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) | |
4d710de9 | 3189 | mmu_free_root_page(kvm, &mmu->prev_roots[i].hpa, |
b94742c9 | 3190 | &invalid_list); |
7c390d35 | 3191 | |
08fb59d8 JS |
3192 | if (free_active_root) { |
3193 | if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL && | |
3194 | (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) { | |
4d710de9 | 3195 | mmu_free_root_page(kvm, &mmu->root_hpa, &invalid_list); |
08fb59d8 JS |
3196 | } else { |
3197 | for (i = 0; i < 4; ++i) | |
3198 | if (mmu->pae_root[i] != 0) | |
4d710de9 | 3199 | mmu_free_root_page(kvm, |
08fb59d8 JS |
3200 | &mmu->pae_root[i], |
3201 | &invalid_list); | |
3202 | mmu->root_hpa = INVALID_PAGE; | |
3203 | } | |
be01e8e2 | 3204 | mmu->root_pgd = 0; |
17ac10ad | 3205 | } |
74b566e6 | 3206 | |
4d710de9 SC |
3207 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
3208 | spin_unlock(&kvm->mmu_lock); | |
17ac10ad | 3209 | } |
74b566e6 | 3210 | EXPORT_SYMBOL_GPL(kvm_mmu_free_roots); |
17ac10ad | 3211 | |
8986ecc0 MT |
3212 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
3213 | { | |
3214 | int ret = 0; | |
3215 | ||
995decb6 | 3216 | if (!kvm_vcpu_is_visible_gfn(vcpu, root_gfn)) { |
a8eeb04a | 3217 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
3218 | ret = 1; |
3219 | } | |
3220 | ||
3221 | return ret; | |
3222 | } | |
3223 | ||
8123f265 SC |
3224 | static hpa_t mmu_alloc_root(struct kvm_vcpu *vcpu, gfn_t gfn, gva_t gva, |
3225 | u8 level, bool direct) | |
651dd37a JR |
3226 | { |
3227 | struct kvm_mmu_page *sp; | |
8123f265 SC |
3228 | |
3229 | spin_lock(&vcpu->kvm->mmu_lock); | |
3230 | ||
3231 | if (make_mmu_pages_available(vcpu)) { | |
3232 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3233 | return INVALID_PAGE; | |
3234 | } | |
3235 | sp = kvm_mmu_get_page(vcpu, gfn, gva, level, direct, ACC_ALL); | |
3236 | ++sp->root_count; | |
3237 | ||
3238 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3239 | return __pa(sp->spt); | |
3240 | } | |
3241 | ||
3242 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) | |
3243 | { | |
3244 | u8 shadow_root_level = vcpu->arch.mmu->shadow_root_level; | |
3245 | hpa_t root; | |
7ebaf15e | 3246 | unsigned i; |
651dd37a | 3247 | |
02c00b3a BG |
3248 | if (vcpu->kvm->arch.tdp_mmu_enabled) { |
3249 | root = kvm_tdp_mmu_get_vcpu_root_hpa(vcpu); | |
3250 | ||
3251 | if (!VALID_PAGE(root)) | |
3252 | return -ENOSPC; | |
3253 | vcpu->arch.mmu->root_hpa = root; | |
3254 | } else if (shadow_root_level >= PT64_ROOT_4LEVEL) { | |
3255 | root = mmu_alloc_root(vcpu, 0, 0, shadow_root_level, | |
3256 | true); | |
3257 | ||
8123f265 | 3258 | if (!VALID_PAGE(root)) |
ed52870f | 3259 | return -ENOSPC; |
8123f265 SC |
3260 | vcpu->arch.mmu->root_hpa = root; |
3261 | } else if (shadow_root_level == PT32E_ROOT_LEVEL) { | |
651dd37a | 3262 | for (i = 0; i < 4; ++i) { |
8123f265 | 3263 | MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu->pae_root[i])); |
651dd37a | 3264 | |
8123f265 SC |
3265 | root = mmu_alloc_root(vcpu, i << (30 - PAGE_SHIFT), |
3266 | i << 30, PT32_ROOT_LEVEL, true); | |
3267 | if (!VALID_PAGE(root)) | |
ed52870f | 3268 | return -ENOSPC; |
44dd3ffa | 3269 | vcpu->arch.mmu->pae_root[i] = root | PT_PRESENT_MASK; |
651dd37a | 3270 | } |
44dd3ffa | 3271 | vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root); |
651dd37a JR |
3272 | } else |
3273 | BUG(); | |
3651c7fc | 3274 | |
be01e8e2 SC |
3275 | /* root_pgd is ignored for direct MMUs. */ |
3276 | vcpu->arch.mmu->root_pgd = 0; | |
651dd37a JR |
3277 | |
3278 | return 0; | |
3279 | } | |
3280 | ||
3281 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 3282 | { |
81407ca5 | 3283 | u64 pdptr, pm_mask; |
be01e8e2 | 3284 | gfn_t root_gfn, root_pgd; |
8123f265 | 3285 | hpa_t root; |
81407ca5 | 3286 | int i; |
3bb65a22 | 3287 | |
be01e8e2 SC |
3288 | root_pgd = vcpu->arch.mmu->get_guest_pgd(vcpu); |
3289 | root_gfn = root_pgd >> PAGE_SHIFT; | |
17ac10ad | 3290 | |
651dd37a JR |
3291 | if (mmu_check_root(vcpu, root_gfn)) |
3292 | return 1; | |
3293 | ||
3294 | /* | |
3295 | * Do we shadow a long mode page table? If so we need to | |
3296 | * write-protect the guests page table root. | |
3297 | */ | |
44dd3ffa | 3298 | if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) { |
8123f265 | 3299 | MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu->root_hpa)); |
651dd37a | 3300 | |
8123f265 SC |
3301 | root = mmu_alloc_root(vcpu, root_gfn, 0, |
3302 | vcpu->arch.mmu->shadow_root_level, false); | |
3303 | if (!VALID_PAGE(root)) | |
ed52870f | 3304 | return -ENOSPC; |
44dd3ffa | 3305 | vcpu->arch.mmu->root_hpa = root; |
be01e8e2 | 3306 | goto set_root_pgd; |
17ac10ad | 3307 | } |
f87f9288 | 3308 | |
651dd37a JR |
3309 | /* |
3310 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
3311 | * or a PAE 3-level page table. In either case we need to be aware that |
3312 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 3313 | */ |
81407ca5 | 3314 | pm_mask = PT_PRESENT_MASK; |
44dd3ffa | 3315 | if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL) |
81407ca5 JR |
3316 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; |
3317 | ||
17ac10ad | 3318 | for (i = 0; i < 4; ++i) { |
8123f265 | 3319 | MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu->pae_root[i])); |
44dd3ffa VK |
3320 | if (vcpu->arch.mmu->root_level == PT32E_ROOT_LEVEL) { |
3321 | pdptr = vcpu->arch.mmu->get_pdptr(vcpu, i); | |
812f30b2 | 3322 | if (!(pdptr & PT_PRESENT_MASK)) { |
44dd3ffa | 3323 | vcpu->arch.mmu->pae_root[i] = 0; |
417726a3 AK |
3324 | continue; |
3325 | } | |
6de4f3ad | 3326 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
3327 | if (mmu_check_root(vcpu, root_gfn)) |
3328 | return 1; | |
5a7388c2 | 3329 | } |
8facbbff | 3330 | |
8123f265 SC |
3331 | root = mmu_alloc_root(vcpu, root_gfn, i << 30, |
3332 | PT32_ROOT_LEVEL, false); | |
3333 | if (!VALID_PAGE(root)) | |
3334 | return -ENOSPC; | |
44dd3ffa | 3335 | vcpu->arch.mmu->pae_root[i] = root | pm_mask; |
17ac10ad | 3336 | } |
44dd3ffa | 3337 | vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root); |
81407ca5 JR |
3338 | |
3339 | /* | |
3340 | * If we shadow a 32 bit page table with a long mode page | |
3341 | * table we enter this path. | |
3342 | */ | |
44dd3ffa VK |
3343 | if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL) { |
3344 | if (vcpu->arch.mmu->lm_root == NULL) { | |
81407ca5 JR |
3345 | /* |
3346 | * The additional page necessary for this is only | |
3347 | * allocated on demand. | |
3348 | */ | |
3349 | ||
3350 | u64 *lm_root; | |
3351 | ||
254272ce | 3352 | lm_root = (void*)get_zeroed_page(GFP_KERNEL_ACCOUNT); |
81407ca5 JR |
3353 | if (lm_root == NULL) |
3354 | return 1; | |
3355 | ||
44dd3ffa | 3356 | lm_root[0] = __pa(vcpu->arch.mmu->pae_root) | pm_mask; |
81407ca5 | 3357 | |
44dd3ffa | 3358 | vcpu->arch.mmu->lm_root = lm_root; |
81407ca5 JR |
3359 | } |
3360 | ||
44dd3ffa | 3361 | vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->lm_root); |
81407ca5 JR |
3362 | } |
3363 | ||
be01e8e2 SC |
3364 | set_root_pgd: |
3365 | vcpu->arch.mmu->root_pgd = root_pgd; | |
ad7dc69a | 3366 | |
8986ecc0 | 3367 | return 0; |
17ac10ad AK |
3368 | } |
3369 | ||
651dd37a JR |
3370 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
3371 | { | |
44dd3ffa | 3372 | if (vcpu->arch.mmu->direct_map) |
651dd37a JR |
3373 | return mmu_alloc_direct_roots(vcpu); |
3374 | else | |
3375 | return mmu_alloc_shadow_roots(vcpu); | |
3376 | } | |
3377 | ||
578e1c4d | 3378 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) |
0ba73cda MT |
3379 | { |
3380 | int i; | |
3381 | struct kvm_mmu_page *sp; | |
3382 | ||
44dd3ffa | 3383 | if (vcpu->arch.mmu->direct_map) |
81407ca5 JR |
3384 | return; |
3385 | ||
44dd3ffa | 3386 | if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) |
0ba73cda | 3387 | return; |
6903074c | 3388 | |
56f17dd3 | 3389 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); |
578e1c4d | 3390 | |
44dd3ffa VK |
3391 | if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) { |
3392 | hpa_t root = vcpu->arch.mmu->root_hpa; | |
e47c4aee | 3393 | sp = to_shadow_page(root); |
578e1c4d JS |
3394 | |
3395 | /* | |
3396 | * Even if another CPU was marking the SP as unsync-ed | |
3397 | * simultaneously, any guest page table changes are not | |
3398 | * guaranteed to be visible anyway until this VCPU issues a TLB | |
3399 | * flush strictly after those changes are made. We only need to | |
3400 | * ensure that the other CPU sets these flags before any actual | |
3401 | * changes to the page tables are made. The comments in | |
3402 | * mmu_need_write_protect() describe what could go wrong if this | |
3403 | * requirement isn't satisfied. | |
3404 | */ | |
3405 | if (!smp_load_acquire(&sp->unsync) && | |
3406 | !smp_load_acquire(&sp->unsync_children)) | |
3407 | return; | |
3408 | ||
3409 | spin_lock(&vcpu->kvm->mmu_lock); | |
3410 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); | |
3411 | ||
0ba73cda | 3412 | mmu_sync_children(vcpu, sp); |
578e1c4d | 3413 | |
0375f7fa | 3414 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
578e1c4d | 3415 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
3416 | return; |
3417 | } | |
578e1c4d JS |
3418 | |
3419 | spin_lock(&vcpu->kvm->mmu_lock); | |
3420 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); | |
3421 | ||
0ba73cda | 3422 | for (i = 0; i < 4; ++i) { |
44dd3ffa | 3423 | hpa_t root = vcpu->arch.mmu->pae_root[i]; |
0ba73cda | 3424 | |
8986ecc0 | 3425 | if (root && VALID_PAGE(root)) { |
0ba73cda | 3426 | root &= PT64_BASE_ADDR_MASK; |
e47c4aee | 3427 | sp = to_shadow_page(root); |
0ba73cda MT |
3428 | mmu_sync_children(vcpu, sp); |
3429 | } | |
3430 | } | |
0ba73cda | 3431 | |
578e1c4d | 3432 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
6cffe8ca | 3433 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda | 3434 | } |
bfd0a56b | 3435 | EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots); |
0ba73cda | 3436 | |
736c291c | 3437 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gpa_t vaddr, |
ab9ae313 | 3438 | u32 access, struct x86_exception *exception) |
6aa8b732 | 3439 | { |
ab9ae313 AK |
3440 | if (exception) |
3441 | exception->error_code = 0; | |
6aa8b732 AK |
3442 | return vaddr; |
3443 | } | |
3444 | ||
736c291c | 3445 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gpa_t vaddr, |
ab9ae313 AK |
3446 | u32 access, |
3447 | struct x86_exception *exception) | |
6539e738 | 3448 | { |
ab9ae313 AK |
3449 | if (exception) |
3450 | exception->error_code = 0; | |
54987b7a | 3451 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception); |
6539e738 JR |
3452 | } |
3453 | ||
d625b155 XG |
3454 | static bool |
3455 | __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level) | |
3456 | { | |
b5c3c1b3 | 3457 | int bit7 = (pte >> 7) & 1; |
d625b155 | 3458 | |
b5c3c1b3 | 3459 | return pte & rsvd_check->rsvd_bits_mask[bit7][level-1]; |
d625b155 XG |
3460 | } |
3461 | ||
b5c3c1b3 | 3462 | static bool __is_bad_mt_xwr(struct rsvd_bits_validate *rsvd_check, u64 pte) |
d625b155 | 3463 | { |
b5c3c1b3 | 3464 | return rsvd_check->bad_mt_xwr & BIT_ULL(pte & 0x3f); |
d625b155 XG |
3465 | } |
3466 | ||
ded58749 | 3467 | static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf | 3468 | { |
9034e6e8 PB |
3469 | /* |
3470 | * A nested guest cannot use the MMIO cache if it is using nested | |
3471 | * page tables, because cr2 is a nGPA while the cache stores GPAs. | |
3472 | */ | |
3473 | if (mmu_is_nested(vcpu)) | |
3474 | return false; | |
3475 | ||
ce88decf XG |
3476 | if (direct) |
3477 | return vcpu_match_mmio_gpa(vcpu, addr); | |
3478 | ||
3479 | return vcpu_match_mmio_gva(vcpu, addr); | |
3480 | } | |
3481 | ||
95fb5b02 BG |
3482 | /* |
3483 | * Return the level of the lowest level SPTE added to sptes. | |
3484 | * That SPTE may be non-present. | |
3485 | */ | |
3486 | static int get_walk(struct kvm_vcpu *vcpu, u64 addr, u64 *sptes) | |
ce88decf XG |
3487 | { |
3488 | struct kvm_shadow_walk_iterator iterator; | |
95fb5b02 BG |
3489 | int leaf = vcpu->arch.mmu->root_level; |
3490 | u64 spte; | |
ce88decf | 3491 | |
37f6a4e2 | 3492 | |
ce88decf | 3493 | walk_shadow_page_lockless_begin(vcpu); |
47ab8751 | 3494 | |
95fb5b02 | 3495 | for (shadow_walk_init(&iterator, vcpu, addr); |
47ab8751 XG |
3496 | shadow_walk_okay(&iterator); |
3497 | __shadow_walk_next(&iterator, spte)) { | |
95fb5b02 | 3498 | leaf = iterator.level; |
47ab8751 XG |
3499 | spte = mmu_spte_get_lockless(iterator.sptep); |
3500 | ||
3501 | sptes[leaf - 1] = spte; | |
3502 | ||
ce88decf XG |
3503 | if (!is_shadow_present_pte(spte)) |
3504 | break; | |
47ab8751 | 3505 | |
95fb5b02 BG |
3506 | } |
3507 | ||
3508 | walk_shadow_page_lockless_end(vcpu); | |
3509 | ||
3510 | return leaf; | |
3511 | } | |
3512 | ||
3513 | /* return true if reserved bit is detected on spte. */ | |
3514 | static bool get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep) | |
3515 | { | |
3516 | u64 sptes[PT64_ROOT_MAX_LEVEL]; | |
3517 | struct rsvd_bits_validate *rsvd_check; | |
3518 | int root = vcpu->arch.mmu->root_level; | |
3519 | int leaf; | |
3520 | int level; | |
3521 | bool reserved = false; | |
3522 | ||
3523 | if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) { | |
3524 | *sptep = 0ull; | |
3525 | return reserved; | |
3526 | } | |
3527 | ||
3528 | if (is_tdp_mmu_root(vcpu->kvm, vcpu->arch.mmu->root_hpa)) | |
3529 | leaf = kvm_tdp_mmu_get_walk(vcpu, addr, sptes); | |
3530 | else | |
3531 | leaf = get_walk(vcpu, addr, sptes); | |
3532 | ||
3533 | rsvd_check = &vcpu->arch.mmu->shadow_zero_check; | |
3534 | ||
3535 | for (level = root; level >= leaf; level--) { | |
3536 | if (!is_shadow_present_pte(sptes[level - 1])) | |
3537 | break; | |
b5c3c1b3 SC |
3538 | /* |
3539 | * Use a bitwise-OR instead of a logical-OR to aggregate the | |
3540 | * reserved bit and EPT's invalid memtype/XWR checks to avoid | |
3541 | * adding a Jcc in the loop. | |
3542 | */ | |
95fb5b02 BG |
3543 | reserved |= __is_bad_mt_xwr(rsvd_check, sptes[level - 1]) | |
3544 | __is_rsvd_bits_set(rsvd_check, sptes[level - 1], | |
3545 | level); | |
47ab8751 XG |
3546 | } |
3547 | ||
47ab8751 XG |
3548 | if (reserved) { |
3549 | pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n", | |
3550 | __func__, addr); | |
95fb5b02 | 3551 | for (level = root; level >= leaf; level--) |
47ab8751 | 3552 | pr_err("------ spte 0x%llx level %d.\n", |
95fb5b02 | 3553 | sptes[level - 1], level); |
47ab8751 | 3554 | } |
ddce6208 | 3555 | |
95fb5b02 BG |
3556 | *sptep = sptes[leaf - 1]; |
3557 | ||
47ab8751 | 3558 | return reserved; |
ce88decf XG |
3559 | } |
3560 | ||
e08d26f0 | 3561 | static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf XG |
3562 | { |
3563 | u64 spte; | |
47ab8751 | 3564 | bool reserved; |
ce88decf | 3565 | |
ded58749 | 3566 | if (mmio_info_in_cache(vcpu, addr, direct)) |
9b8ebbdb | 3567 | return RET_PF_EMULATE; |
ce88decf | 3568 | |
95fb5b02 | 3569 | reserved = get_mmio_spte(vcpu, addr, &spte); |
450869d6 | 3570 | if (WARN_ON(reserved)) |
9b8ebbdb | 3571 | return -EINVAL; |
ce88decf XG |
3572 | |
3573 | if (is_mmio_spte(spte)) { | |
3574 | gfn_t gfn = get_mmio_spte_gfn(spte); | |
0a2b64c5 | 3575 | unsigned int access = get_mmio_spte_access(spte); |
ce88decf | 3576 | |
54bf36aa | 3577 | if (!check_mmio_spte(vcpu, spte)) |
9b8ebbdb | 3578 | return RET_PF_INVALID; |
f8f55942 | 3579 | |
ce88decf XG |
3580 | if (direct) |
3581 | addr = 0; | |
4f022648 XG |
3582 | |
3583 | trace_handle_mmio_page_fault(addr, gfn, access); | |
ce88decf | 3584 | vcpu_cache_mmio_info(vcpu, addr, gfn, access); |
9b8ebbdb | 3585 | return RET_PF_EMULATE; |
ce88decf XG |
3586 | } |
3587 | ||
ce88decf XG |
3588 | /* |
3589 | * If the page table is zapped by other cpus, let CPU fault again on | |
3590 | * the address. | |
3591 | */ | |
9b8ebbdb | 3592 | return RET_PF_RETRY; |
ce88decf | 3593 | } |
ce88decf | 3594 | |
3d0c27ad XG |
3595 | static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu, |
3596 | u32 error_code, gfn_t gfn) | |
3597 | { | |
3598 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3599 | return false; | |
3600 | ||
3601 | if (!(error_code & PFERR_PRESENT_MASK) || | |
3602 | !(error_code & PFERR_WRITE_MASK)) | |
3603 | return false; | |
3604 | ||
3605 | /* | |
3606 | * guest is writing the page which is write tracked which can | |
3607 | * not be fixed by page fault handler. | |
3608 | */ | |
3609 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) | |
3610 | return true; | |
3611 | ||
3612 | return false; | |
3613 | } | |
3614 | ||
e5691a81 XG |
3615 | static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr) |
3616 | { | |
3617 | struct kvm_shadow_walk_iterator iterator; | |
3618 | u64 spte; | |
3619 | ||
e5691a81 XG |
3620 | walk_shadow_page_lockless_begin(vcpu); |
3621 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { | |
3622 | clear_sp_write_flooding_count(iterator.sptep); | |
3623 | if (!is_shadow_present_pte(spte)) | |
3624 | break; | |
3625 | } | |
3626 | walk_shadow_page_lockless_end(vcpu); | |
3627 | } | |
3628 | ||
e8c22266 VK |
3629 | static bool kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
3630 | gfn_t gfn) | |
af585b92 GN |
3631 | { |
3632 | struct kvm_arch_async_pf arch; | |
fb67e14f | 3633 | |
7c90705b | 3634 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 3635 | arch.gfn = gfn; |
44dd3ffa | 3636 | arch.direct_map = vcpu->arch.mmu->direct_map; |
d8dd54e0 | 3637 | arch.cr3 = vcpu->arch.mmu->get_guest_pgd(vcpu); |
af585b92 | 3638 | |
9f1a8526 SC |
3639 | return kvm_setup_async_pf(vcpu, cr2_or_gpa, |
3640 | kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch); | |
af585b92 GN |
3641 | } |
3642 | ||
78b2c54a | 3643 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
9f1a8526 SC |
3644 | gpa_t cr2_or_gpa, kvm_pfn_t *pfn, bool write, |
3645 | bool *writable) | |
af585b92 | 3646 | { |
c36b7150 | 3647 | struct kvm_memory_slot *slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
af585b92 GN |
3648 | bool async; |
3649 | ||
c36b7150 PB |
3650 | /* Don't expose private memslots to L2. */ |
3651 | if (is_guest_mode(vcpu) && !kvm_is_visible_memslot(slot)) { | |
3a2936de | 3652 | *pfn = KVM_PFN_NOSLOT; |
c583eed6 | 3653 | *writable = false; |
3a2936de JM |
3654 | return false; |
3655 | } | |
3656 | ||
3520469d PB |
3657 | async = false; |
3658 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable); | |
af585b92 GN |
3659 | if (!async) |
3660 | return false; /* *pfn has correct page already */ | |
3661 | ||
9bc1f09f | 3662 | if (!prefault && kvm_can_do_async_pf(vcpu)) { |
9f1a8526 | 3663 | trace_kvm_try_async_get_page(cr2_or_gpa, gfn); |
af585b92 | 3664 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
9f1a8526 | 3665 | trace_kvm_async_pf_doublefault(cr2_or_gpa, gfn); |
af585b92 GN |
3666 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); |
3667 | return true; | |
9f1a8526 | 3668 | } else if (kvm_arch_setup_async_pf(vcpu, cr2_or_gpa, gfn)) |
af585b92 GN |
3669 | return true; |
3670 | } | |
3671 | ||
3520469d | 3672 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable); |
af585b92 GN |
3673 | return false; |
3674 | } | |
3675 | ||
0f90e1c1 SC |
3676 | static int direct_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, |
3677 | bool prefault, int max_level, bool is_tdp) | |
6aa8b732 | 3678 | { |
367fd790 | 3679 | bool write = error_code & PFERR_WRITE_MASK; |
0f90e1c1 | 3680 | bool map_writable; |
6aa8b732 | 3681 | |
0f90e1c1 SC |
3682 | gfn_t gfn = gpa >> PAGE_SHIFT; |
3683 | unsigned long mmu_seq; | |
3684 | kvm_pfn_t pfn; | |
83f06fa7 | 3685 | int r; |
ce88decf | 3686 | |
3d0c27ad | 3687 | if (page_fault_handle_page_track(vcpu, error_code, gfn)) |
9b8ebbdb | 3688 | return RET_PF_EMULATE; |
ce88decf | 3689 | |
bb18842e BG |
3690 | if (!is_tdp_mmu_root(vcpu->kvm, vcpu->arch.mmu->root_hpa)) { |
3691 | r = fast_page_fault(vcpu, gpa, error_code); | |
3692 | if (r != RET_PF_INVALID) | |
3693 | return r; | |
3694 | } | |
83291445 | 3695 | |
378f5cd6 | 3696 | r = mmu_topup_memory_caches(vcpu, false); |
e2dec939 AK |
3697 | if (r) |
3698 | return r; | |
714b93da | 3699 | |
367fd790 SC |
3700 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
3701 | smp_rmb(); | |
3702 | ||
3703 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable)) | |
3704 | return RET_PF_RETRY; | |
3705 | ||
0f90e1c1 | 3706 | if (handle_abnormal_pfn(vcpu, is_tdp ? 0 : gpa, gfn, pfn, ACC_ALL, &r)) |
367fd790 | 3707 | return r; |
6aa8b732 | 3708 | |
367fd790 SC |
3709 | r = RET_PF_RETRY; |
3710 | spin_lock(&vcpu->kvm->mmu_lock); | |
3711 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) | |
3712 | goto out_unlock; | |
7bd7ded6 SC |
3713 | r = make_mmu_pages_available(vcpu); |
3714 | if (r) | |
367fd790 | 3715 | goto out_unlock; |
bb18842e BG |
3716 | |
3717 | if (is_tdp_mmu_root(vcpu->kvm, vcpu->arch.mmu->root_hpa)) | |
3718 | r = kvm_tdp_mmu_map(vcpu, gpa, error_code, map_writable, max_level, | |
3719 | pfn, prefault); | |
3720 | else | |
3721 | r = __direct_map(vcpu, gpa, error_code, map_writable, max_level, pfn, | |
3722 | prefault, is_tdp); | |
0f90e1c1 | 3723 | |
367fd790 SC |
3724 | out_unlock: |
3725 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3726 | kvm_release_pfn_clean(pfn); | |
3727 | return r; | |
6aa8b732 AK |
3728 | } |
3729 | ||
0f90e1c1 SC |
3730 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, |
3731 | u32 error_code, bool prefault) | |
3732 | { | |
3733 | pgprintk("%s: gva %lx error %x\n", __func__, gpa, error_code); | |
3734 | ||
3735 | /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */ | |
3736 | return direct_page_fault(vcpu, gpa & PAGE_MASK, error_code, prefault, | |
3bae0459 | 3737 | PG_LEVEL_2M, false); |
0f90e1c1 SC |
3738 | } |
3739 | ||
1261bfa3 | 3740 | int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code, |
d0006530 | 3741 | u64 fault_address, char *insn, int insn_len) |
1261bfa3 WL |
3742 | { |
3743 | int r = 1; | |
9ce372b3 | 3744 | u32 flags = vcpu->arch.apf.host_apf_flags; |
1261bfa3 | 3745 | |
736c291c SC |
3746 | #ifndef CONFIG_X86_64 |
3747 | /* A 64-bit CR2 should be impossible on 32-bit KVM. */ | |
3748 | if (WARN_ON_ONCE(fault_address >> 32)) | |
3749 | return -EFAULT; | |
3750 | #endif | |
3751 | ||
c595ceee | 3752 | vcpu->arch.l1tf_flush_l1d = true; |
9ce372b3 | 3753 | if (!flags) { |
1261bfa3 WL |
3754 | trace_kvm_page_fault(fault_address, error_code); |
3755 | ||
d0006530 | 3756 | if (kvm_event_needs_reinjection(vcpu)) |
1261bfa3 WL |
3757 | kvm_mmu_unprotect_page_virt(vcpu, fault_address); |
3758 | r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn, | |
3759 | insn_len); | |
9ce372b3 | 3760 | } else if (flags & KVM_PV_REASON_PAGE_NOT_PRESENT) { |
68fd66f1 | 3761 | vcpu->arch.apf.host_apf_flags = 0; |
1261bfa3 | 3762 | local_irq_disable(); |
6bca69ad | 3763 | kvm_async_pf_task_wait_schedule(fault_address); |
1261bfa3 | 3764 | local_irq_enable(); |
9ce372b3 VK |
3765 | } else { |
3766 | WARN_ONCE(1, "Unexpected host async PF flags: %x\n", flags); | |
1261bfa3 | 3767 | } |
9ce372b3 | 3768 | |
1261bfa3 WL |
3769 | return r; |
3770 | } | |
3771 | EXPORT_SYMBOL_GPL(kvm_handle_page_fault); | |
3772 | ||
7a02674d SC |
3773 | int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, |
3774 | bool prefault) | |
fb72d167 | 3775 | { |
cb9b88c6 | 3776 | int max_level; |
fb72d167 | 3777 | |
e662ec3e | 3778 | for (max_level = KVM_MAX_HUGEPAGE_LEVEL; |
3bae0459 | 3779 | max_level > PG_LEVEL_4K; |
cb9b88c6 SC |
3780 | max_level--) { |
3781 | int page_num = KVM_PAGES_PER_HPAGE(max_level); | |
0f90e1c1 | 3782 | gfn_t base = (gpa >> PAGE_SHIFT) & ~(page_num - 1); |
ce88decf | 3783 | |
cb9b88c6 SC |
3784 | if (kvm_mtrr_check_gfn_range_consistency(vcpu, base, page_num)) |
3785 | break; | |
fd136902 | 3786 | } |
852e3c19 | 3787 | |
0f90e1c1 SC |
3788 | return direct_page_fault(vcpu, gpa, error_code, prefault, |
3789 | max_level, true); | |
fb72d167 JR |
3790 | } |
3791 | ||
8a3c1a33 PB |
3792 | static void nonpaging_init_context(struct kvm_vcpu *vcpu, |
3793 | struct kvm_mmu *context) | |
6aa8b732 | 3794 | { |
6aa8b732 | 3795 | context->page_fault = nonpaging_page_fault; |
6aa8b732 | 3796 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
e8bc217a | 3797 | context->sync_page = nonpaging_sync_page; |
5efac074 | 3798 | context->invlpg = NULL; |
0f53b5b1 | 3799 | context->update_pte = nonpaging_update_pte; |
cea0f0e7 | 3800 | context->root_level = 0; |
6aa8b732 | 3801 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
c5a78f2b | 3802 | context->direct_map = true; |
2d48a985 | 3803 | context->nx = false; |
6aa8b732 AK |
3804 | } |
3805 | ||
be01e8e2 | 3806 | static inline bool is_root_usable(struct kvm_mmu_root_info *root, gpa_t pgd, |
0be44352 SC |
3807 | union kvm_mmu_page_role role) |
3808 | { | |
be01e8e2 | 3809 | return (role.direct || pgd == root->pgd) && |
e47c4aee SC |
3810 | VALID_PAGE(root->hpa) && to_shadow_page(root->hpa) && |
3811 | role.word == to_shadow_page(root->hpa)->role.word; | |
0be44352 SC |
3812 | } |
3813 | ||
b94742c9 | 3814 | /* |
be01e8e2 | 3815 | * Find out if a previously cached root matching the new pgd/role is available. |
b94742c9 JS |
3816 | * The current root is also inserted into the cache. |
3817 | * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is | |
3818 | * returned. | |
3819 | * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and | |
3820 | * false is returned. This root should now be freed by the caller. | |
3821 | */ | |
be01e8e2 | 3822 | static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_pgd, |
b94742c9 JS |
3823 | union kvm_mmu_page_role new_role) |
3824 | { | |
3825 | uint i; | |
3826 | struct kvm_mmu_root_info root; | |
44dd3ffa | 3827 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
b94742c9 | 3828 | |
be01e8e2 | 3829 | root.pgd = mmu->root_pgd; |
b94742c9 JS |
3830 | root.hpa = mmu->root_hpa; |
3831 | ||
be01e8e2 | 3832 | if (is_root_usable(&root, new_pgd, new_role)) |
0be44352 SC |
3833 | return true; |
3834 | ||
b94742c9 JS |
3835 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { |
3836 | swap(root, mmu->prev_roots[i]); | |
3837 | ||
be01e8e2 | 3838 | if (is_root_usable(&root, new_pgd, new_role)) |
b94742c9 JS |
3839 | break; |
3840 | } | |
3841 | ||
3842 | mmu->root_hpa = root.hpa; | |
be01e8e2 | 3843 | mmu->root_pgd = root.pgd; |
b94742c9 JS |
3844 | |
3845 | return i < KVM_MMU_NUM_PREV_ROOTS; | |
3846 | } | |
3847 | ||
be01e8e2 | 3848 | static bool fast_pgd_switch(struct kvm_vcpu *vcpu, gpa_t new_pgd, |
b869855b | 3849 | union kvm_mmu_page_role new_role) |
6aa8b732 | 3850 | { |
44dd3ffa | 3851 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
7c390d35 JS |
3852 | |
3853 | /* | |
3854 | * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid | |
3855 | * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs | |
3856 | * later if necessary. | |
3857 | */ | |
3858 | if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL && | |
b869855b | 3859 | mmu->root_level >= PT64_ROOT_4LEVEL) |
fe9304d3 | 3860 | return cached_root_available(vcpu, new_pgd, new_role); |
7c390d35 JS |
3861 | |
3862 | return false; | |
6aa8b732 AK |
3863 | } |
3864 | ||
be01e8e2 | 3865 | static void __kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd, |
ade61e28 | 3866 | union kvm_mmu_page_role new_role, |
4a632ac6 | 3867 | bool skip_tlb_flush, bool skip_mmu_sync) |
6aa8b732 | 3868 | { |
be01e8e2 | 3869 | if (!fast_pgd_switch(vcpu, new_pgd, new_role)) { |
b869855b SC |
3870 | kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, KVM_MMU_ROOT_CURRENT); |
3871 | return; | |
3872 | } | |
3873 | ||
3874 | /* | |
3875 | * It's possible that the cached previous root page is obsolete because | |
3876 | * of a change in the MMU generation number. However, changing the | |
3877 | * generation number is accompanied by KVM_REQ_MMU_RELOAD, which will | |
3878 | * free the root set here and allocate a new one. | |
3879 | */ | |
3880 | kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu); | |
3881 | ||
71fe7013 | 3882 | if (!skip_mmu_sync || force_flush_and_sync_on_reuse) |
b869855b | 3883 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
71fe7013 | 3884 | if (!skip_tlb_flush || force_flush_and_sync_on_reuse) |
b869855b | 3885 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
b869855b SC |
3886 | |
3887 | /* | |
3888 | * The last MMIO access's GVA and GPA are cached in the VCPU. When | |
3889 | * switching to a new CR3, that GVA->GPA mapping may no longer be | |
3890 | * valid. So clear any cached MMIO info even when we don't need to sync | |
3891 | * the shadow page tables. | |
3892 | */ | |
3893 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); | |
3894 | ||
daa5b6c1 BG |
3895 | /* |
3896 | * If this is a direct root page, it doesn't have a write flooding | |
3897 | * count. Otherwise, clear the write flooding count. | |
3898 | */ | |
3899 | if (!new_role.direct) | |
3900 | __clear_sp_write_flooding_count( | |
3901 | to_shadow_page(vcpu->arch.mmu->root_hpa)); | |
6aa8b732 AK |
3902 | } |
3903 | ||
be01e8e2 | 3904 | void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd, bool skip_tlb_flush, |
4a632ac6 | 3905 | bool skip_mmu_sync) |
0aab33e4 | 3906 | { |
be01e8e2 | 3907 | __kvm_mmu_new_pgd(vcpu, new_pgd, kvm_mmu_calc_root_page_role(vcpu), |
4a632ac6 | 3908 | skip_tlb_flush, skip_mmu_sync); |
0aab33e4 | 3909 | } |
be01e8e2 | 3910 | EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd); |
0aab33e4 | 3911 | |
5777ed34 JR |
3912 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
3913 | { | |
9f8fe504 | 3914 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
3915 | } |
3916 | ||
54bf36aa | 3917 | static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
0a2b64c5 | 3918 | unsigned int access, int *nr_present) |
ce88decf XG |
3919 | { |
3920 | if (unlikely(is_mmio_spte(*sptep))) { | |
3921 | if (gfn != get_mmio_spte_gfn(*sptep)) { | |
3922 | mmu_spte_clear_no_track(sptep); | |
3923 | return true; | |
3924 | } | |
3925 | ||
3926 | (*nr_present)++; | |
54bf36aa | 3927 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
3928 | return true; |
3929 | } | |
3930 | ||
3931 | return false; | |
3932 | } | |
3933 | ||
6bb69c9b PB |
3934 | static inline bool is_last_gpte(struct kvm_mmu *mmu, |
3935 | unsigned level, unsigned gpte) | |
6fd01b71 | 3936 | { |
6bb69c9b PB |
3937 | /* |
3938 | * The RHS has bit 7 set iff level < mmu->last_nonleaf_level. | |
3939 | * If it is clear, there are no large pages at this level, so clear | |
3940 | * PT_PAGE_SIZE_MASK in gpte if that is the case. | |
3941 | */ | |
3942 | gpte &= level - mmu->last_nonleaf_level; | |
3943 | ||
829ee279 | 3944 | /* |
3bae0459 SC |
3945 | * PG_LEVEL_4K always terminates. The RHS has bit 7 set |
3946 | * iff level <= PG_LEVEL_4K, which for our purpose means | |
3947 | * level == PG_LEVEL_4K; set PT_PAGE_SIZE_MASK in gpte then. | |
829ee279 | 3948 | */ |
3bae0459 | 3949 | gpte |= level - PG_LEVEL_4K - 1; |
829ee279 | 3950 | |
6bb69c9b | 3951 | return gpte & PT_PAGE_SIZE_MASK; |
6fd01b71 AK |
3952 | } |
3953 | ||
37406aaa NHE |
3954 | #define PTTYPE_EPT 18 /* arbitrary */ |
3955 | #define PTTYPE PTTYPE_EPT | |
3956 | #include "paging_tmpl.h" | |
3957 | #undef PTTYPE | |
3958 | ||
6aa8b732 AK |
3959 | #define PTTYPE 64 |
3960 | #include "paging_tmpl.h" | |
3961 | #undef PTTYPE | |
3962 | ||
3963 | #define PTTYPE 32 | |
3964 | #include "paging_tmpl.h" | |
3965 | #undef PTTYPE | |
3966 | ||
6dc98b86 XG |
3967 | static void |
3968 | __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, | |
3969 | struct rsvd_bits_validate *rsvd_check, | |
3970 | int maxphyaddr, int level, bool nx, bool gbpages, | |
6fec2144 | 3971 | bool pse, bool amd) |
82725b20 | 3972 | { |
82725b20 | 3973 | u64 exb_bit_rsvd = 0; |
5f7dde7b | 3974 | u64 gbpages_bit_rsvd = 0; |
a0c0feb5 | 3975 | u64 nonleaf_bit8_rsvd = 0; |
82725b20 | 3976 | |
a0a64f50 | 3977 | rsvd_check->bad_mt_xwr = 0; |
25d92081 | 3978 | |
6dc98b86 | 3979 | if (!nx) |
82725b20 | 3980 | exb_bit_rsvd = rsvd_bits(63, 63); |
6dc98b86 | 3981 | if (!gbpages) |
5f7dde7b | 3982 | gbpages_bit_rsvd = rsvd_bits(7, 7); |
a0c0feb5 PB |
3983 | |
3984 | /* | |
3985 | * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for | |
3986 | * leaf entries) on AMD CPUs only. | |
3987 | */ | |
6fec2144 | 3988 | if (amd) |
a0c0feb5 PB |
3989 | nonleaf_bit8_rsvd = rsvd_bits(8, 8); |
3990 | ||
6dc98b86 | 3991 | switch (level) { |
82725b20 DE |
3992 | case PT32_ROOT_LEVEL: |
3993 | /* no rsvd bits for 2 level 4K page table entries */ | |
a0a64f50 XG |
3994 | rsvd_check->rsvd_bits_mask[0][1] = 0; |
3995 | rsvd_check->rsvd_bits_mask[0][0] = 0; | |
3996 | rsvd_check->rsvd_bits_mask[1][0] = | |
3997 | rsvd_check->rsvd_bits_mask[0][0]; | |
f815bce8 | 3998 | |
6dc98b86 | 3999 | if (!pse) { |
a0a64f50 | 4000 | rsvd_check->rsvd_bits_mask[1][1] = 0; |
f815bce8 XG |
4001 | break; |
4002 | } | |
4003 | ||
82725b20 DE |
4004 | if (is_cpuid_PSE36()) |
4005 | /* 36bits PSE 4MB page */ | |
a0a64f50 | 4006 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); |
82725b20 DE |
4007 | else |
4008 | /* 32 bits PSE 4MB page */ | |
a0a64f50 | 4009 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); |
82725b20 DE |
4010 | break; |
4011 | case PT32E_ROOT_LEVEL: | |
a0a64f50 | 4012 | rsvd_check->rsvd_bits_mask[0][2] = |
20c466b5 | 4013 | rsvd_bits(maxphyaddr, 63) | |
cd9ae5fe | 4014 | rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */ |
a0a64f50 | 4015 | rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 4016 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
a0a64f50 | 4017 | rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
82725b20 | 4018 | rsvd_bits(maxphyaddr, 62); /* PTE */ |
a0a64f50 | 4019 | rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
82725b20 DE |
4020 | rsvd_bits(maxphyaddr, 62) | |
4021 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
4022 | rsvd_check->rsvd_bits_mask[1][0] = |
4023 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 | 4024 | break; |
855feb67 YZ |
4025 | case PT64_ROOT_5LEVEL: |
4026 | rsvd_check->rsvd_bits_mask[0][4] = exb_bit_rsvd | | |
4027 | nonleaf_bit8_rsvd | rsvd_bits(7, 7) | | |
4028 | rsvd_bits(maxphyaddr, 51); | |
4029 | rsvd_check->rsvd_bits_mask[1][4] = | |
4030 | rsvd_check->rsvd_bits_mask[0][4]; | |
df561f66 | 4031 | fallthrough; |
2a7266a8 | 4032 | case PT64_ROOT_4LEVEL: |
a0a64f50 XG |
4033 | rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd | |
4034 | nonleaf_bit8_rsvd | rsvd_bits(7, 7) | | |
4c26b4cd | 4035 | rsvd_bits(maxphyaddr, 51); |
a0a64f50 | 4036 | rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd | |
5ecad245 | 4037 | gbpages_bit_rsvd | |
82725b20 | 4038 | rsvd_bits(maxphyaddr, 51); |
a0a64f50 XG |
4039 | rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4040 | rsvd_bits(maxphyaddr, 51); | |
4041 | rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd | | |
4042 | rsvd_bits(maxphyaddr, 51); | |
4043 | rsvd_check->rsvd_bits_mask[1][3] = | |
4044 | rsvd_check->rsvd_bits_mask[0][3]; | |
4045 | rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd | | |
5f7dde7b | 4046 | gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) | |
e04da980 | 4047 | rsvd_bits(13, 29); |
a0a64f50 | 4048 | rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
4049 | rsvd_bits(maxphyaddr, 51) | |
4050 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
4051 | rsvd_check->rsvd_bits_mask[1][0] = |
4052 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 DE |
4053 | break; |
4054 | } | |
4055 | } | |
4056 | ||
6dc98b86 XG |
4057 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
4058 | struct kvm_mmu *context) | |
4059 | { | |
4060 | __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check, | |
4061 | cpuid_maxphyaddr(vcpu), context->root_level, | |
d6321d49 RK |
4062 | context->nx, |
4063 | guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES), | |
23493d0a SC |
4064 | is_pse(vcpu), |
4065 | guest_cpuid_is_amd_or_hygon(vcpu)); | |
6dc98b86 XG |
4066 | } |
4067 | ||
81b8eebb XG |
4068 | static void |
4069 | __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check, | |
4070 | int maxphyaddr, bool execonly) | |
25d92081 | 4071 | { |
951f9fd7 | 4072 | u64 bad_mt_xwr; |
25d92081 | 4073 | |
855feb67 YZ |
4074 | rsvd_check->rsvd_bits_mask[0][4] = |
4075 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7); | |
a0a64f50 | 4076 | rsvd_check->rsvd_bits_mask[0][3] = |
25d92081 | 4077 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7); |
a0a64f50 | 4078 | rsvd_check->rsvd_bits_mask[0][2] = |
25d92081 | 4079 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); |
a0a64f50 | 4080 | rsvd_check->rsvd_bits_mask[0][1] = |
25d92081 | 4081 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); |
a0a64f50 | 4082 | rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51); |
25d92081 YZ |
4083 | |
4084 | /* large page */ | |
855feb67 | 4085 | rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4]; |
a0a64f50 XG |
4086 | rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3]; |
4087 | rsvd_check->rsvd_bits_mask[1][2] = | |
25d92081 | 4088 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29); |
a0a64f50 | 4089 | rsvd_check->rsvd_bits_mask[1][1] = |
25d92081 | 4090 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20); |
a0a64f50 | 4091 | rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0]; |
25d92081 | 4092 | |
951f9fd7 PB |
4093 | bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */ |
4094 | bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */ | |
4095 | bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */ | |
4096 | bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */ | |
4097 | bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */ | |
4098 | if (!execonly) { | |
4099 | /* bits 0..2 must not be 100 unless VMX capabilities allow it */ | |
4100 | bad_mt_xwr |= REPEAT_BYTE(1ull << 4); | |
25d92081 | 4101 | } |
951f9fd7 | 4102 | rsvd_check->bad_mt_xwr = bad_mt_xwr; |
25d92081 YZ |
4103 | } |
4104 | ||
81b8eebb XG |
4105 | static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu, |
4106 | struct kvm_mmu *context, bool execonly) | |
4107 | { | |
4108 | __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check, | |
4109 | cpuid_maxphyaddr(vcpu), execonly); | |
4110 | } | |
4111 | ||
c258b62b XG |
4112 | /* |
4113 | * the page table on host is the shadow page table for the page | |
4114 | * table in guest or amd nested guest, its mmu features completely | |
4115 | * follow the features in guest. | |
4116 | */ | |
4117 | void | |
4118 | reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context) | |
4119 | { | |
36d9594d VK |
4120 | bool uses_nx = context->nx || |
4121 | context->mmu_role.base.smep_andnot_wp; | |
ea2800dd BS |
4122 | struct rsvd_bits_validate *shadow_zero_check; |
4123 | int i; | |
5f0b8199 | 4124 | |
6fec2144 PB |
4125 | /* |
4126 | * Passing "true" to the last argument is okay; it adds a check | |
4127 | * on bit 8 of the SPTEs which KVM doesn't use anyway. | |
4128 | */ | |
ea2800dd BS |
4129 | shadow_zero_check = &context->shadow_zero_check; |
4130 | __reset_rsvds_bits_mask(vcpu, shadow_zero_check, | |
f3ecb59d | 4131 | shadow_phys_bits, |
5f0b8199 | 4132 | context->shadow_root_level, uses_nx, |
d6321d49 RK |
4133 | guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES), |
4134 | is_pse(vcpu), true); | |
ea2800dd BS |
4135 | |
4136 | if (!shadow_me_mask) | |
4137 | return; | |
4138 | ||
4139 | for (i = context->shadow_root_level; --i >= 0;) { | |
4140 | shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask; | |
4141 | shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask; | |
4142 | } | |
4143 | ||
c258b62b XG |
4144 | } |
4145 | EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask); | |
4146 | ||
6fec2144 PB |
4147 | static inline bool boot_cpu_is_amd(void) |
4148 | { | |
4149 | WARN_ON_ONCE(!tdp_enabled); | |
4150 | return shadow_x_mask == 0; | |
4151 | } | |
4152 | ||
c258b62b XG |
4153 | /* |
4154 | * the direct page table on host, use as much mmu features as | |
4155 | * possible, however, kvm currently does not do execution-protection. | |
4156 | */ | |
4157 | static void | |
4158 | reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4159 | struct kvm_mmu *context) | |
4160 | { | |
ea2800dd BS |
4161 | struct rsvd_bits_validate *shadow_zero_check; |
4162 | int i; | |
4163 | ||
4164 | shadow_zero_check = &context->shadow_zero_check; | |
4165 | ||
6fec2144 | 4166 | if (boot_cpu_is_amd()) |
ea2800dd | 4167 | __reset_rsvds_bits_mask(vcpu, shadow_zero_check, |
f3ecb59d | 4168 | shadow_phys_bits, |
c258b62b | 4169 | context->shadow_root_level, false, |
b8291adc BP |
4170 | boot_cpu_has(X86_FEATURE_GBPAGES), |
4171 | true, true); | |
c258b62b | 4172 | else |
ea2800dd | 4173 | __reset_rsvds_bits_mask_ept(shadow_zero_check, |
f3ecb59d | 4174 | shadow_phys_bits, |
c258b62b XG |
4175 | false); |
4176 | ||
ea2800dd BS |
4177 | if (!shadow_me_mask) |
4178 | return; | |
4179 | ||
4180 | for (i = context->shadow_root_level; --i >= 0;) { | |
4181 | shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask; | |
4182 | shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask; | |
4183 | } | |
c258b62b XG |
4184 | } |
4185 | ||
4186 | /* | |
4187 | * as the comments in reset_shadow_zero_bits_mask() except it | |
4188 | * is the shadow page table for intel nested guest. | |
4189 | */ | |
4190 | static void | |
4191 | reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4192 | struct kvm_mmu *context, bool execonly) | |
4193 | { | |
4194 | __reset_rsvds_bits_mask_ept(&context->shadow_zero_check, | |
f3ecb59d | 4195 | shadow_phys_bits, execonly); |
c258b62b XG |
4196 | } |
4197 | ||
09f037aa PB |
4198 | #define BYTE_MASK(access) \ |
4199 | ((1 & (access) ? 2 : 0) | \ | |
4200 | (2 & (access) ? 4 : 0) | \ | |
4201 | (3 & (access) ? 8 : 0) | \ | |
4202 | (4 & (access) ? 16 : 0) | \ | |
4203 | (5 & (access) ? 32 : 0) | \ | |
4204 | (6 & (access) ? 64 : 0) | \ | |
4205 | (7 & (access) ? 128 : 0)) | |
4206 | ||
4207 | ||
edc90b7d XG |
4208 | static void update_permission_bitmask(struct kvm_vcpu *vcpu, |
4209 | struct kvm_mmu *mmu, bool ept) | |
97d64b78 | 4210 | { |
09f037aa PB |
4211 | unsigned byte; |
4212 | ||
4213 | const u8 x = BYTE_MASK(ACC_EXEC_MASK); | |
4214 | const u8 w = BYTE_MASK(ACC_WRITE_MASK); | |
4215 | const u8 u = BYTE_MASK(ACC_USER_MASK); | |
4216 | ||
4217 | bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0; | |
4218 | bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0; | |
4219 | bool cr0_wp = is_write_protection(vcpu); | |
97d64b78 | 4220 | |
97d64b78 | 4221 | for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) { |
09f037aa PB |
4222 | unsigned pfec = byte << 1; |
4223 | ||
97ec8c06 | 4224 | /* |
09f037aa PB |
4225 | * Each "*f" variable has a 1 bit for each UWX value |
4226 | * that causes a fault with the given PFEC. | |
97ec8c06 | 4227 | */ |
97d64b78 | 4228 | |
09f037aa | 4229 | /* Faults from writes to non-writable pages */ |
a6a6d3b1 | 4230 | u8 wf = (pfec & PFERR_WRITE_MASK) ? (u8)~w : 0; |
09f037aa | 4231 | /* Faults from user mode accesses to supervisor pages */ |
a6a6d3b1 | 4232 | u8 uf = (pfec & PFERR_USER_MASK) ? (u8)~u : 0; |
09f037aa | 4233 | /* Faults from fetches of non-executable pages*/ |
a6a6d3b1 | 4234 | u8 ff = (pfec & PFERR_FETCH_MASK) ? (u8)~x : 0; |
09f037aa PB |
4235 | /* Faults from kernel mode fetches of user pages */ |
4236 | u8 smepf = 0; | |
4237 | /* Faults from kernel mode accesses of user pages */ | |
4238 | u8 smapf = 0; | |
4239 | ||
4240 | if (!ept) { | |
4241 | /* Faults from kernel mode accesses to user pages */ | |
4242 | u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u; | |
4243 | ||
4244 | /* Not really needed: !nx will cause pte.nx to fault */ | |
4245 | if (!mmu->nx) | |
4246 | ff = 0; | |
4247 | ||
4248 | /* Allow supervisor writes if !cr0.wp */ | |
4249 | if (!cr0_wp) | |
4250 | wf = (pfec & PFERR_USER_MASK) ? wf : 0; | |
4251 | ||
4252 | /* Disallow supervisor fetches of user code if cr4.smep */ | |
4253 | if (cr4_smep) | |
4254 | smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0; | |
4255 | ||
4256 | /* | |
4257 | * SMAP:kernel-mode data accesses from user-mode | |
4258 | * mappings should fault. A fault is considered | |
4259 | * as a SMAP violation if all of the following | |
39337ad1 | 4260 | * conditions are true: |
09f037aa PB |
4261 | * - X86_CR4_SMAP is set in CR4 |
4262 | * - A user page is accessed | |
4263 | * - The access is not a fetch | |
4264 | * - Page fault in kernel mode | |
4265 | * - if CPL = 3 or X86_EFLAGS_AC is clear | |
4266 | * | |
4267 | * Here, we cover the first three conditions. | |
4268 | * The fourth is computed dynamically in permission_fault(); | |
4269 | * PFERR_RSVD_MASK bit will be set in PFEC if the access is | |
4270 | * *not* subject to SMAP restrictions. | |
4271 | */ | |
4272 | if (cr4_smap) | |
4273 | smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf; | |
97d64b78 | 4274 | } |
09f037aa PB |
4275 | |
4276 | mmu->permissions[byte] = ff | uf | wf | smepf | smapf; | |
97d64b78 AK |
4277 | } |
4278 | } | |
4279 | ||
2d344105 HH |
4280 | /* |
4281 | * PKU is an additional mechanism by which the paging controls access to | |
4282 | * user-mode addresses based on the value in the PKRU register. Protection | |
4283 | * key violations are reported through a bit in the page fault error code. | |
4284 | * Unlike other bits of the error code, the PK bit is not known at the | |
4285 | * call site of e.g. gva_to_gpa; it must be computed directly in | |
4286 | * permission_fault based on two bits of PKRU, on some machine state (CR4, | |
4287 | * CR0, EFER, CPL), and on other bits of the error code and the page tables. | |
4288 | * | |
4289 | * In particular the following conditions come from the error code, the | |
4290 | * page tables and the machine state: | |
4291 | * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1 | |
4292 | * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch) | |
4293 | * - PK is always zero if U=0 in the page tables | |
4294 | * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access. | |
4295 | * | |
4296 | * The PKRU bitmask caches the result of these four conditions. The error | |
4297 | * code (minus the P bit) and the page table's U bit form an index into the | |
4298 | * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed | |
4299 | * with the two bits of the PKRU register corresponding to the protection key. | |
4300 | * For the first three conditions above the bits will be 00, thus masking | |
4301 | * away both AD and WD. For all reads or if the last condition holds, WD | |
4302 | * only will be masked away. | |
4303 | */ | |
4304 | static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
4305 | bool ept) | |
4306 | { | |
4307 | unsigned bit; | |
4308 | bool wp; | |
4309 | ||
4310 | if (ept) { | |
4311 | mmu->pkru_mask = 0; | |
4312 | return; | |
4313 | } | |
4314 | ||
4315 | /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */ | |
4316 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) { | |
4317 | mmu->pkru_mask = 0; | |
4318 | return; | |
4319 | } | |
4320 | ||
4321 | wp = is_write_protection(vcpu); | |
4322 | ||
4323 | for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) { | |
4324 | unsigned pfec, pkey_bits; | |
4325 | bool check_pkey, check_write, ff, uf, wf, pte_user; | |
4326 | ||
4327 | pfec = bit << 1; | |
4328 | ff = pfec & PFERR_FETCH_MASK; | |
4329 | uf = pfec & PFERR_USER_MASK; | |
4330 | wf = pfec & PFERR_WRITE_MASK; | |
4331 | ||
4332 | /* PFEC.RSVD is replaced by ACC_USER_MASK. */ | |
4333 | pte_user = pfec & PFERR_RSVD_MASK; | |
4334 | ||
4335 | /* | |
4336 | * Only need to check the access which is not an | |
4337 | * instruction fetch and is to a user page. | |
4338 | */ | |
4339 | check_pkey = (!ff && pte_user); | |
4340 | /* | |
4341 | * write access is controlled by PKRU if it is a | |
4342 | * user access or CR0.WP = 1. | |
4343 | */ | |
4344 | check_write = check_pkey && wf && (uf || wp); | |
4345 | ||
4346 | /* PKRU.AD stops both read and write access. */ | |
4347 | pkey_bits = !!check_pkey; | |
4348 | /* PKRU.WD stops write access. */ | |
4349 | pkey_bits |= (!!check_write) << 1; | |
4350 | ||
4351 | mmu->pkru_mask |= (pkey_bits & 3) << pfec; | |
4352 | } | |
4353 | } | |
4354 | ||
6bb69c9b | 4355 | static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
6fd01b71 | 4356 | { |
6bb69c9b PB |
4357 | unsigned root_level = mmu->root_level; |
4358 | ||
4359 | mmu->last_nonleaf_level = root_level; | |
4360 | if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu)) | |
4361 | mmu->last_nonleaf_level++; | |
6fd01b71 AK |
4362 | } |
4363 | ||
8a3c1a33 PB |
4364 | static void paging64_init_context_common(struct kvm_vcpu *vcpu, |
4365 | struct kvm_mmu *context, | |
4366 | int level) | |
6aa8b732 | 4367 | { |
2d48a985 | 4368 | context->nx = is_nx(vcpu); |
4d6931c3 | 4369 | context->root_level = level; |
2d48a985 | 4370 | |
4d6931c3 | 4371 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 4372 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4373 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4374 | update_last_nonleaf_level(vcpu, context); |
6aa8b732 | 4375 | |
fa4a2c08 | 4376 | MMU_WARN_ON(!is_pae(vcpu)); |
6aa8b732 | 4377 | context->page_fault = paging64_page_fault; |
6aa8b732 | 4378 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 4379 | context->sync_page = paging64_sync_page; |
a7052897 | 4380 | context->invlpg = paging64_invlpg; |
0f53b5b1 | 4381 | context->update_pte = paging64_update_pte; |
17ac10ad | 4382 | context->shadow_root_level = level; |
c5a78f2b | 4383 | context->direct_map = false; |
6aa8b732 AK |
4384 | } |
4385 | ||
8a3c1a33 PB |
4386 | static void paging64_init_context(struct kvm_vcpu *vcpu, |
4387 | struct kvm_mmu *context) | |
17ac10ad | 4388 | { |
855feb67 YZ |
4389 | int root_level = is_la57_mode(vcpu) ? |
4390 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4391 | ||
4392 | paging64_init_context_common(vcpu, context, root_level); | |
17ac10ad AK |
4393 | } |
4394 | ||
8a3c1a33 PB |
4395 | static void paging32_init_context(struct kvm_vcpu *vcpu, |
4396 | struct kvm_mmu *context) | |
6aa8b732 | 4397 | { |
2d48a985 | 4398 | context->nx = false; |
4d6931c3 | 4399 | context->root_level = PT32_ROOT_LEVEL; |
2d48a985 | 4400 | |
4d6931c3 | 4401 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 4402 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4403 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4404 | update_last_nonleaf_level(vcpu, context); |
6aa8b732 | 4405 | |
6aa8b732 | 4406 | context->page_fault = paging32_page_fault; |
6aa8b732 | 4407 | context->gva_to_gpa = paging32_gva_to_gpa; |
e8bc217a | 4408 | context->sync_page = paging32_sync_page; |
a7052897 | 4409 | context->invlpg = paging32_invlpg; |
0f53b5b1 | 4410 | context->update_pte = paging32_update_pte; |
6aa8b732 | 4411 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
c5a78f2b | 4412 | context->direct_map = false; |
6aa8b732 AK |
4413 | } |
4414 | ||
8a3c1a33 PB |
4415 | static void paging32E_init_context(struct kvm_vcpu *vcpu, |
4416 | struct kvm_mmu *context) | |
6aa8b732 | 4417 | { |
8a3c1a33 | 4418 | paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
4419 | } |
4420 | ||
a336282d VK |
4421 | static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu) |
4422 | { | |
4423 | union kvm_mmu_extended_role ext = {0}; | |
4424 | ||
7dcd5755 | 4425 | ext.cr0_pg = !!is_paging(vcpu); |
0699c64a | 4426 | ext.cr4_pae = !!is_pae(vcpu); |
a336282d VK |
4427 | ext.cr4_smep = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
4428 | ext.cr4_smap = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMAP); | |
4429 | ext.cr4_pse = !!is_pse(vcpu); | |
4430 | ext.cr4_pke = !!kvm_read_cr4_bits(vcpu, X86_CR4_PKE); | |
de3ccd26 | 4431 | ext.maxphyaddr = cpuid_maxphyaddr(vcpu); |
a336282d VK |
4432 | |
4433 | ext.valid = 1; | |
4434 | ||
4435 | return ext; | |
4436 | } | |
4437 | ||
7dcd5755 VK |
4438 | static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu, |
4439 | bool base_only) | |
4440 | { | |
4441 | union kvm_mmu_role role = {0}; | |
4442 | ||
4443 | role.base.access = ACC_ALL; | |
4444 | role.base.nxe = !!is_nx(vcpu); | |
7dcd5755 VK |
4445 | role.base.cr0_wp = is_write_protection(vcpu); |
4446 | role.base.smm = is_smm(vcpu); | |
4447 | role.base.guest_mode = is_guest_mode(vcpu); | |
4448 | ||
4449 | if (base_only) | |
4450 | return role; | |
4451 | ||
4452 | role.ext = kvm_calc_mmu_role_ext(vcpu); | |
4453 | ||
4454 | return role; | |
4455 | } | |
4456 | ||
d468d94b SC |
4457 | static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu *vcpu) |
4458 | { | |
4459 | /* Use 5-level TDP if and only if it's useful/necessary. */ | |
83013059 | 4460 | if (max_tdp_level == 5 && cpuid_maxphyaddr(vcpu) <= 48) |
d468d94b SC |
4461 | return 4; |
4462 | ||
83013059 | 4463 | return max_tdp_level; |
d468d94b SC |
4464 | } |
4465 | ||
7dcd5755 VK |
4466 | static union kvm_mmu_role |
4467 | kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only) | |
9fa72119 | 4468 | { |
7dcd5755 | 4469 | union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only); |
9fa72119 | 4470 | |
7dcd5755 | 4471 | role.base.ad_disabled = (shadow_accessed_mask == 0); |
d468d94b | 4472 | role.base.level = kvm_mmu_get_tdp_level(vcpu); |
7dcd5755 | 4473 | role.base.direct = true; |
47c42e6b | 4474 | role.base.gpte_is_8_bytes = true; |
9fa72119 JS |
4475 | |
4476 | return role; | |
4477 | } | |
4478 | ||
8a3c1a33 | 4479 | static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 4480 | { |
8c008659 | 4481 | struct kvm_mmu *context = &vcpu->arch.root_mmu; |
7dcd5755 VK |
4482 | union kvm_mmu_role new_role = |
4483 | kvm_calc_tdp_mmu_root_page_role(vcpu, false); | |
fb72d167 | 4484 | |
7dcd5755 VK |
4485 | if (new_role.as_u64 == context->mmu_role.as_u64) |
4486 | return; | |
4487 | ||
4488 | context->mmu_role.as_u64 = new_role.as_u64; | |
7a02674d | 4489 | context->page_fault = kvm_tdp_page_fault; |
e8bc217a | 4490 | context->sync_page = nonpaging_sync_page; |
5efac074 | 4491 | context->invlpg = NULL; |
0f53b5b1 | 4492 | context->update_pte = nonpaging_update_pte; |
d468d94b | 4493 | context->shadow_root_level = kvm_mmu_get_tdp_level(vcpu); |
c5a78f2b | 4494 | context->direct_map = true; |
d8dd54e0 | 4495 | context->get_guest_pgd = get_cr3; |
e4e517b4 | 4496 | context->get_pdptr = kvm_pdptr_read; |
cb659db8 | 4497 | context->inject_page_fault = kvm_inject_page_fault; |
fb72d167 JR |
4498 | |
4499 | if (!is_paging(vcpu)) { | |
2d48a985 | 4500 | context->nx = false; |
fb72d167 JR |
4501 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
4502 | context->root_level = 0; | |
4503 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 4504 | context->nx = is_nx(vcpu); |
855feb67 YZ |
4505 | context->root_level = is_la57_mode(vcpu) ? |
4506 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4d6931c3 DB |
4507 | reset_rsvds_bits_mask(vcpu, context); |
4508 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4509 | } else if (is_pae(vcpu)) { |
2d48a985 | 4510 | context->nx = is_nx(vcpu); |
fb72d167 | 4511 | context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 DB |
4512 | reset_rsvds_bits_mask(vcpu, context); |
4513 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4514 | } else { |
2d48a985 | 4515 | context->nx = false; |
fb72d167 | 4516 | context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 DB |
4517 | reset_rsvds_bits_mask(vcpu, context); |
4518 | context->gva_to_gpa = paging32_gva_to_gpa; | |
fb72d167 JR |
4519 | } |
4520 | ||
25d92081 | 4521 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4522 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4523 | update_last_nonleaf_level(vcpu, context); |
c258b62b | 4524 | reset_tdp_shadow_zero_bits_mask(vcpu, context); |
fb72d167 JR |
4525 | } |
4526 | ||
7dcd5755 | 4527 | static union kvm_mmu_role |
59505b55 | 4528 | kvm_calc_shadow_root_page_role_common(struct kvm_vcpu *vcpu, bool base_only) |
7dcd5755 VK |
4529 | { |
4530 | union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only); | |
4531 | ||
4532 | role.base.smep_andnot_wp = role.ext.cr4_smep && | |
4533 | !is_write_protection(vcpu); | |
4534 | role.base.smap_andnot_wp = role.ext.cr4_smap && | |
4535 | !is_write_protection(vcpu); | |
47c42e6b | 4536 | role.base.gpte_is_8_bytes = !!is_pae(vcpu); |
9fa72119 | 4537 | |
59505b55 SC |
4538 | return role; |
4539 | } | |
4540 | ||
4541 | static union kvm_mmu_role | |
4542 | kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only) | |
4543 | { | |
4544 | union kvm_mmu_role role = | |
4545 | kvm_calc_shadow_root_page_role_common(vcpu, base_only); | |
4546 | ||
4547 | role.base.direct = !is_paging(vcpu); | |
4548 | ||
9fa72119 | 4549 | if (!is_long_mode(vcpu)) |
7dcd5755 | 4550 | role.base.level = PT32E_ROOT_LEVEL; |
9fa72119 | 4551 | else if (is_la57_mode(vcpu)) |
7dcd5755 | 4552 | role.base.level = PT64_ROOT_5LEVEL; |
9fa72119 | 4553 | else |
7dcd5755 | 4554 | role.base.level = PT64_ROOT_4LEVEL; |
9fa72119 JS |
4555 | |
4556 | return role; | |
4557 | } | |
4558 | ||
8c008659 PB |
4559 | static void shadow_mmu_init_context(struct kvm_vcpu *vcpu, struct kvm_mmu *context, |
4560 | u32 cr0, u32 cr4, u32 efer, | |
4561 | union kvm_mmu_role new_role) | |
9fa72119 | 4562 | { |
929d1cfa | 4563 | if (!(cr0 & X86_CR0_PG)) |
8a3c1a33 | 4564 | nonpaging_init_context(vcpu, context); |
929d1cfa | 4565 | else if (efer & EFER_LMA) |
8a3c1a33 | 4566 | paging64_init_context(vcpu, context); |
929d1cfa | 4567 | else if (cr4 & X86_CR4_PAE) |
8a3c1a33 | 4568 | paging32E_init_context(vcpu, context); |
6aa8b732 | 4569 | else |
8a3c1a33 | 4570 | paging32_init_context(vcpu, context); |
a770f6f2 | 4571 | |
7dcd5755 | 4572 | context->mmu_role.as_u64 = new_role.as_u64; |
c258b62b | 4573 | reset_shadow_zero_bits_mask(vcpu, context); |
52fde8df | 4574 | } |
0f04a2ac VK |
4575 | |
4576 | static void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, u32 cr0, u32 cr4, u32 efer) | |
4577 | { | |
8c008659 | 4578 | struct kvm_mmu *context = &vcpu->arch.root_mmu; |
0f04a2ac VK |
4579 | union kvm_mmu_role new_role = |
4580 | kvm_calc_shadow_mmu_root_page_role(vcpu, false); | |
4581 | ||
4582 | if (new_role.as_u64 != context->mmu_role.as_u64) | |
8c008659 | 4583 | shadow_mmu_init_context(vcpu, context, cr0, cr4, efer, new_role); |
0f04a2ac VK |
4584 | } |
4585 | ||
59505b55 SC |
4586 | static union kvm_mmu_role |
4587 | kvm_calc_shadow_npt_root_page_role(struct kvm_vcpu *vcpu) | |
4588 | { | |
4589 | union kvm_mmu_role role = | |
4590 | kvm_calc_shadow_root_page_role_common(vcpu, false); | |
4591 | ||
4592 | role.base.direct = false; | |
d468d94b | 4593 | role.base.level = kvm_mmu_get_tdp_level(vcpu); |
59505b55 SC |
4594 | |
4595 | return role; | |
4596 | } | |
4597 | ||
0f04a2ac VK |
4598 | void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, u32 cr0, u32 cr4, u32 efer, |
4599 | gpa_t nested_cr3) | |
4600 | { | |
8c008659 | 4601 | struct kvm_mmu *context = &vcpu->arch.guest_mmu; |
59505b55 | 4602 | union kvm_mmu_role new_role = kvm_calc_shadow_npt_root_page_role(vcpu); |
0f04a2ac | 4603 | |
096586fd SC |
4604 | context->shadow_root_level = new_role.base.level; |
4605 | ||
a506fdd2 VK |
4606 | __kvm_mmu_new_pgd(vcpu, nested_cr3, new_role.base, false, false); |
4607 | ||
0f04a2ac | 4608 | if (new_role.as_u64 != context->mmu_role.as_u64) |
8c008659 | 4609 | shadow_mmu_init_context(vcpu, context, cr0, cr4, efer, new_role); |
0f04a2ac VK |
4610 | } |
4611 | EXPORT_SYMBOL_GPL(kvm_init_shadow_npt_mmu); | |
52fde8df | 4612 | |
a336282d VK |
4613 | static union kvm_mmu_role |
4614 | kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty, | |
bb1fcc70 | 4615 | bool execonly, u8 level) |
9fa72119 | 4616 | { |
552c69b1 | 4617 | union kvm_mmu_role role = {0}; |
14c07ad8 | 4618 | |
47c42e6b SC |
4619 | /* SMM flag is inherited from root_mmu */ |
4620 | role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm; | |
9fa72119 | 4621 | |
bb1fcc70 | 4622 | role.base.level = level; |
47c42e6b | 4623 | role.base.gpte_is_8_bytes = true; |
a336282d VK |
4624 | role.base.direct = false; |
4625 | role.base.ad_disabled = !accessed_dirty; | |
4626 | role.base.guest_mode = true; | |
4627 | role.base.access = ACC_ALL; | |
9fa72119 | 4628 | |
47c42e6b SC |
4629 | /* |
4630 | * WP=1 and NOT_WP=1 is an impossible combination, use WP and the | |
4631 | * SMAP variation to denote shadow EPT entries. | |
4632 | */ | |
4633 | role.base.cr0_wp = true; | |
4634 | role.base.smap_andnot_wp = true; | |
4635 | ||
552c69b1 | 4636 | role.ext = kvm_calc_mmu_role_ext(vcpu); |
a336282d | 4637 | role.ext.execonly = execonly; |
9fa72119 JS |
4638 | |
4639 | return role; | |
4640 | } | |
4641 | ||
ae1e2d10 | 4642 | void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly, |
50c28f21 | 4643 | bool accessed_dirty, gpa_t new_eptp) |
155a97a3 | 4644 | { |
8c008659 | 4645 | struct kvm_mmu *context = &vcpu->arch.guest_mmu; |
bb1fcc70 | 4646 | u8 level = vmx_eptp_page_walk_level(new_eptp); |
a336282d VK |
4647 | union kvm_mmu_role new_role = |
4648 | kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty, | |
bb1fcc70 | 4649 | execonly, level); |
a336282d | 4650 | |
be01e8e2 | 4651 | __kvm_mmu_new_pgd(vcpu, new_eptp, new_role.base, true, true); |
a336282d | 4652 | |
a336282d VK |
4653 | if (new_role.as_u64 == context->mmu_role.as_u64) |
4654 | return; | |
ad896af0 | 4655 | |
bb1fcc70 | 4656 | context->shadow_root_level = level; |
155a97a3 NHE |
4657 | |
4658 | context->nx = true; | |
ae1e2d10 | 4659 | context->ept_ad = accessed_dirty; |
155a97a3 NHE |
4660 | context->page_fault = ept_page_fault; |
4661 | context->gva_to_gpa = ept_gva_to_gpa; | |
4662 | context->sync_page = ept_sync_page; | |
4663 | context->invlpg = ept_invlpg; | |
4664 | context->update_pte = ept_update_pte; | |
bb1fcc70 | 4665 | context->root_level = level; |
155a97a3 | 4666 | context->direct_map = false; |
a336282d | 4667 | context->mmu_role.as_u64 = new_role.as_u64; |
3dc773e7 | 4668 | |
155a97a3 | 4669 | update_permission_bitmask(vcpu, context, true); |
2d344105 | 4670 | update_pkru_bitmask(vcpu, context, true); |
fd19d3b4 | 4671 | update_last_nonleaf_level(vcpu, context); |
155a97a3 | 4672 | reset_rsvds_bits_mask_ept(vcpu, context, execonly); |
c258b62b | 4673 | reset_ept_shadow_zero_bits_mask(vcpu, context, execonly); |
155a97a3 NHE |
4674 | } |
4675 | EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu); | |
4676 | ||
8a3c1a33 | 4677 | static void init_kvm_softmmu(struct kvm_vcpu *vcpu) |
52fde8df | 4678 | { |
8c008659 | 4679 | struct kvm_mmu *context = &vcpu->arch.root_mmu; |
ad896af0 | 4680 | |
929d1cfa PB |
4681 | kvm_init_shadow_mmu(vcpu, |
4682 | kvm_read_cr0_bits(vcpu, X86_CR0_PG), | |
4683 | kvm_read_cr4_bits(vcpu, X86_CR4_PAE), | |
4684 | vcpu->arch.efer); | |
4685 | ||
d8dd54e0 | 4686 | context->get_guest_pgd = get_cr3; |
ad896af0 PB |
4687 | context->get_pdptr = kvm_pdptr_read; |
4688 | context->inject_page_fault = kvm_inject_page_fault; | |
6aa8b732 AK |
4689 | } |
4690 | ||
8a3c1a33 | 4691 | static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
02f59dc9 | 4692 | { |
bf627a92 | 4693 | union kvm_mmu_role new_role = kvm_calc_mmu_role_common(vcpu, false); |
02f59dc9 JR |
4694 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; |
4695 | ||
bf627a92 VK |
4696 | if (new_role.as_u64 == g_context->mmu_role.as_u64) |
4697 | return; | |
4698 | ||
4699 | g_context->mmu_role.as_u64 = new_role.as_u64; | |
d8dd54e0 | 4700 | g_context->get_guest_pgd = get_cr3; |
e4e517b4 | 4701 | g_context->get_pdptr = kvm_pdptr_read; |
02f59dc9 JR |
4702 | g_context->inject_page_fault = kvm_inject_page_fault; |
4703 | ||
5efac074 PB |
4704 | /* |
4705 | * L2 page tables are never shadowed, so there is no need to sync | |
4706 | * SPTEs. | |
4707 | */ | |
4708 | g_context->invlpg = NULL; | |
4709 | ||
02f59dc9 | 4710 | /* |
44dd3ffa | 4711 | * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using |
0af2593b DM |
4712 | * L1's nested page tables (e.g. EPT12). The nested translation |
4713 | * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using | |
4714 | * L2's page tables as the first level of translation and L1's | |
4715 | * nested page tables as the second level of translation. Basically | |
4716 | * the gva_to_gpa functions between mmu and nested_mmu are swapped. | |
02f59dc9 JR |
4717 | */ |
4718 | if (!is_paging(vcpu)) { | |
2d48a985 | 4719 | g_context->nx = false; |
02f59dc9 JR |
4720 | g_context->root_level = 0; |
4721 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
4722 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 4723 | g_context->nx = is_nx(vcpu); |
855feb67 YZ |
4724 | g_context->root_level = is_la57_mode(vcpu) ? |
4725 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4d6931c3 | 4726 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4727 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
4728 | } else if (is_pae(vcpu)) { | |
2d48a985 | 4729 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 4730 | g_context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 | 4731 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4732 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
4733 | } else { | |
2d48a985 | 4734 | g_context->nx = false; |
02f59dc9 | 4735 | g_context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 | 4736 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4737 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; |
4738 | } | |
4739 | ||
25d92081 | 4740 | update_permission_bitmask(vcpu, g_context, false); |
2d344105 | 4741 | update_pkru_bitmask(vcpu, g_context, false); |
6bb69c9b | 4742 | update_last_nonleaf_level(vcpu, g_context); |
02f59dc9 JR |
4743 | } |
4744 | ||
1c53da3f | 4745 | void kvm_init_mmu(struct kvm_vcpu *vcpu, bool reset_roots) |
fb72d167 | 4746 | { |
1c53da3f | 4747 | if (reset_roots) { |
b94742c9 JS |
4748 | uint i; |
4749 | ||
44dd3ffa | 4750 | vcpu->arch.mmu->root_hpa = INVALID_PAGE; |
b94742c9 JS |
4751 | |
4752 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
44dd3ffa | 4753 | vcpu->arch.mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID; |
1c53da3f JS |
4754 | } |
4755 | ||
02f59dc9 | 4756 | if (mmu_is_nested(vcpu)) |
e0c6db3e | 4757 | init_kvm_nested_mmu(vcpu); |
02f59dc9 | 4758 | else if (tdp_enabled) |
e0c6db3e | 4759 | init_kvm_tdp_mmu(vcpu); |
fb72d167 | 4760 | else |
e0c6db3e | 4761 | init_kvm_softmmu(vcpu); |
fb72d167 | 4762 | } |
1c53da3f | 4763 | EXPORT_SYMBOL_GPL(kvm_init_mmu); |
fb72d167 | 4764 | |
9fa72119 JS |
4765 | static union kvm_mmu_page_role |
4766 | kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu) | |
4767 | { | |
7dcd5755 VK |
4768 | union kvm_mmu_role role; |
4769 | ||
9fa72119 | 4770 | if (tdp_enabled) |
7dcd5755 | 4771 | role = kvm_calc_tdp_mmu_root_page_role(vcpu, true); |
9fa72119 | 4772 | else |
7dcd5755 VK |
4773 | role = kvm_calc_shadow_mmu_root_page_role(vcpu, true); |
4774 | ||
4775 | return role.base; | |
9fa72119 | 4776 | } |
fb72d167 | 4777 | |
8a3c1a33 | 4778 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu) |
6aa8b732 | 4779 | { |
95f93af4 | 4780 | kvm_mmu_unload(vcpu); |
1c53da3f | 4781 | kvm_init_mmu(vcpu, true); |
17c3ba9d | 4782 | } |
8668a3c4 | 4783 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
4784 | |
4785 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 4786 | { |
714b93da AK |
4787 | int r; |
4788 | ||
378f5cd6 | 4789 | r = mmu_topup_memory_caches(vcpu, !vcpu->arch.mmu->direct_map); |
17c3ba9d AK |
4790 | if (r) |
4791 | goto out; | |
8986ecc0 | 4792 | r = mmu_alloc_roots(vcpu); |
e2858b4a | 4793 | kvm_mmu_sync_roots(vcpu); |
8986ecc0 MT |
4794 | if (r) |
4795 | goto out; | |
727a7e27 | 4796 | kvm_mmu_load_pgd(vcpu); |
8c8560b8 | 4797 | kvm_x86_ops.tlb_flush_current(vcpu); |
714b93da AK |
4798 | out: |
4799 | return r; | |
6aa8b732 | 4800 | } |
17c3ba9d AK |
4801 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
4802 | ||
4803 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
4804 | { | |
14c07ad8 VK |
4805 | kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL); |
4806 | WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa)); | |
4807 | kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL); | |
4808 | WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa)); | |
17c3ba9d | 4809 | } |
4b16184c | 4810 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 4811 | |
0028425f | 4812 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
7c562522 XG |
4813 | struct kvm_mmu_page *sp, u64 *spte, |
4814 | const void *new) | |
0028425f | 4815 | { |
3bae0459 | 4816 | if (sp->role.level != PG_LEVEL_4K) { |
7e4e4056 JR |
4817 | ++vcpu->kvm->stat.mmu_pde_zapped; |
4818 | return; | |
30945387 | 4819 | } |
0028425f | 4820 | |
4cee5764 | 4821 | ++vcpu->kvm->stat.mmu_pte_updated; |
44dd3ffa | 4822 | vcpu->arch.mmu->update_pte(vcpu, sp, spte, new); |
0028425f AK |
4823 | } |
4824 | ||
79539cec AK |
4825 | static bool need_remote_flush(u64 old, u64 new) |
4826 | { | |
4827 | if (!is_shadow_present_pte(old)) | |
4828 | return false; | |
4829 | if (!is_shadow_present_pte(new)) | |
4830 | return true; | |
4831 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
4832 | return true; | |
53166229 GN |
4833 | old ^= shadow_nx_mask; |
4834 | new ^= shadow_nx_mask; | |
79539cec AK |
4835 | return (old & ~new & PT64_PERM_MASK) != 0; |
4836 | } | |
4837 | ||
889e5cbc | 4838 | static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, |
0e0fee5c | 4839 | int *bytes) |
da4a00f0 | 4840 | { |
0e0fee5c | 4841 | u64 gentry = 0; |
889e5cbc | 4842 | int r; |
72016f3a | 4843 | |
72016f3a AK |
4844 | /* |
4845 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
4846 | * as the current vcpu paging mode since we update the sptes only |
4847 | * when they have the same mode. | |
72016f3a | 4848 | */ |
889e5cbc | 4849 | if (is_pae(vcpu) && *bytes == 4) { |
72016f3a | 4850 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
889e5cbc XG |
4851 | *gpa &= ~(gpa_t)7; |
4852 | *bytes = 8; | |
08e850c6 AK |
4853 | } |
4854 | ||
0e0fee5c JS |
4855 | if (*bytes == 4 || *bytes == 8) { |
4856 | r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes); | |
4857 | if (r) | |
4858 | gentry = 0; | |
72016f3a AK |
4859 | } |
4860 | ||
889e5cbc XG |
4861 | return gentry; |
4862 | } | |
4863 | ||
4864 | /* | |
4865 | * If we're seeing too many writes to a page, it may no longer be a page table, | |
4866 | * or we may be forking, in which case it is better to unmap the page. | |
4867 | */ | |
a138fe75 | 4868 | static bool detect_write_flooding(struct kvm_mmu_page *sp) |
889e5cbc | 4869 | { |
a30f47cb XG |
4870 | /* |
4871 | * Skip write-flooding detected for the sp whose level is 1, because | |
4872 | * it can become unsync, then the guest page is not write-protected. | |
4873 | */ | |
3bae0459 | 4874 | if (sp->role.level == PG_LEVEL_4K) |
a30f47cb | 4875 | return false; |
3246af0e | 4876 | |
e5691a81 XG |
4877 | atomic_inc(&sp->write_flooding_count); |
4878 | return atomic_read(&sp->write_flooding_count) >= 3; | |
889e5cbc XG |
4879 | } |
4880 | ||
4881 | /* | |
4882 | * Misaligned accesses are too much trouble to fix up; also, they usually | |
4883 | * indicate a page is not used as a page table. | |
4884 | */ | |
4885 | static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa, | |
4886 | int bytes) | |
4887 | { | |
4888 | unsigned offset, pte_size, misaligned; | |
4889 | ||
4890 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
4891 | gpa, bytes, sp->role.word); | |
4892 | ||
4893 | offset = offset_in_page(gpa); | |
47c42e6b | 4894 | pte_size = sp->role.gpte_is_8_bytes ? 8 : 4; |
5d9ca30e XG |
4895 | |
4896 | /* | |
4897 | * Sometimes, the OS only writes the last one bytes to update status | |
4898 | * bits, for example, in linux, andb instruction is used in clear_bit(). | |
4899 | */ | |
4900 | if (!(offset & (pte_size - 1)) && bytes == 1) | |
4901 | return false; | |
4902 | ||
889e5cbc XG |
4903 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
4904 | misaligned |= bytes < 4; | |
4905 | ||
4906 | return misaligned; | |
4907 | } | |
4908 | ||
4909 | static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte) | |
4910 | { | |
4911 | unsigned page_offset, quadrant; | |
4912 | u64 *spte; | |
4913 | int level; | |
4914 | ||
4915 | page_offset = offset_in_page(gpa); | |
4916 | level = sp->role.level; | |
4917 | *nspte = 1; | |
47c42e6b | 4918 | if (!sp->role.gpte_is_8_bytes) { |
889e5cbc XG |
4919 | page_offset <<= 1; /* 32->64 */ |
4920 | /* | |
4921 | * A 32-bit pde maps 4MB while the shadow pdes map | |
4922 | * only 2MB. So we need to double the offset again | |
4923 | * and zap two pdes instead of one. | |
4924 | */ | |
4925 | if (level == PT32_ROOT_LEVEL) { | |
4926 | page_offset &= ~7; /* kill rounding error */ | |
4927 | page_offset <<= 1; | |
4928 | *nspte = 2; | |
4929 | } | |
4930 | quadrant = page_offset >> PAGE_SHIFT; | |
4931 | page_offset &= ~PAGE_MASK; | |
4932 | if (quadrant != sp->role.quadrant) | |
4933 | return NULL; | |
4934 | } | |
4935 | ||
4936 | spte = &sp->spt[page_offset / sizeof(*spte)]; | |
4937 | return spte; | |
4938 | } | |
4939 | ||
a102a674 SC |
4940 | /* |
4941 | * Ignore various flags when determining if a SPTE can be immediately | |
4942 | * overwritten for the current MMU. | |
4943 | * - level: explicitly checked in mmu_pte_write_new_pte(), and will never | |
4944 | * match the current MMU role, as MMU's level tracks the root level. | |
4945 | * - access: updated based on the new guest PTE | |
4946 | * - quadrant: handled by get_written_sptes() | |
4947 | * - invalid: always false (loop only walks valid shadow pages) | |
4948 | */ | |
4949 | static const union kvm_mmu_page_role role_ign = { | |
4950 | .level = 0xf, | |
4951 | .access = 0x7, | |
4952 | .quadrant = 0x3, | |
4953 | .invalid = 0x1, | |
4954 | }; | |
4955 | ||
13d268ca | 4956 | static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
d126363d JS |
4957 | const u8 *new, int bytes, |
4958 | struct kvm_page_track_notifier_node *node) | |
889e5cbc XG |
4959 | { |
4960 | gfn_t gfn = gpa >> PAGE_SHIFT; | |
889e5cbc | 4961 | struct kvm_mmu_page *sp; |
889e5cbc XG |
4962 | LIST_HEAD(invalid_list); |
4963 | u64 entry, gentry, *spte; | |
4964 | int npte; | |
b8c67b7a | 4965 | bool remote_flush, local_flush; |
889e5cbc XG |
4966 | |
4967 | /* | |
4968 | * If we don't have indirect shadow pages, it means no page is | |
4969 | * write-protected, so we can exit simply. | |
4970 | */ | |
6aa7de05 | 4971 | if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) |
889e5cbc XG |
4972 | return; |
4973 | ||
b8c67b7a | 4974 | remote_flush = local_flush = false; |
889e5cbc XG |
4975 | |
4976 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); | |
4977 | ||
889e5cbc XG |
4978 | /* |
4979 | * No need to care whether allocation memory is successful | |
4980 | * or not since pte prefetch is skiped if it does not have | |
4981 | * enough objects in the cache. | |
4982 | */ | |
378f5cd6 | 4983 | mmu_topup_memory_caches(vcpu, true); |
889e5cbc XG |
4984 | |
4985 | spin_lock(&vcpu->kvm->mmu_lock); | |
0e0fee5c JS |
4986 | |
4987 | gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes); | |
4988 | ||
889e5cbc | 4989 | ++vcpu->kvm->stat.mmu_pte_write; |
0375f7fa | 4990 | kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
889e5cbc | 4991 | |
b67bfe0d | 4992 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
a30f47cb | 4993 | if (detect_write_misaligned(sp, gpa, bytes) || |
a138fe75 | 4994 | detect_write_flooding(sp)) { |
b8c67b7a | 4995 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
4cee5764 | 4996 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
4997 | continue; |
4998 | } | |
889e5cbc XG |
4999 | |
5000 | spte = get_written_sptes(sp, gpa, &npte); | |
5001 | if (!spte) | |
5002 | continue; | |
5003 | ||
0671a8e7 | 5004 | local_flush = true; |
ac1b714e | 5005 | while (npte--) { |
36d9594d VK |
5006 | u32 base_role = vcpu->arch.mmu->mmu_role.base.word; |
5007 | ||
79539cec | 5008 | entry = *spte; |
2de4085c | 5009 | mmu_page_zap_pte(vcpu->kvm, sp, spte, NULL); |
fa1de2bf | 5010 | if (gentry && |
a102a674 SC |
5011 | !((sp->role.word ^ base_role) & ~role_ign.word) && |
5012 | rmap_can_add(vcpu)) | |
7c562522 | 5013 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
9bb4f6b1 | 5014 | if (need_remote_flush(entry, *spte)) |
0671a8e7 | 5015 | remote_flush = true; |
ac1b714e | 5016 | ++spte; |
9b7a0325 | 5017 | } |
9b7a0325 | 5018 | } |
b8c67b7a | 5019 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush); |
0375f7fa | 5020 | kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 5021 | spin_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
5022 | } |
5023 | ||
a436036b AK |
5024 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
5025 | { | |
10589a46 MT |
5026 | gpa_t gpa; |
5027 | int r; | |
a436036b | 5028 | |
44dd3ffa | 5029 | if (vcpu->arch.mmu->direct_map) |
60f24784 AK |
5030 | return 0; |
5031 | ||
1871c602 | 5032 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 5033 | |
10589a46 | 5034 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
1cb3f3ae | 5035 | |
10589a46 | 5036 | return r; |
a436036b | 5037 | } |
577bdc49 | 5038 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 5039 | |
736c291c | 5040 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code, |
dc25e89e | 5041 | void *insn, int insn_len) |
3067714c | 5042 | { |
92daa48b | 5043 | int r, emulation_type = EMULTYPE_PF; |
44dd3ffa | 5044 | bool direct = vcpu->arch.mmu->direct_map; |
3067714c | 5045 | |
6948199a | 5046 | if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa))) |
ddce6208 SC |
5047 | return RET_PF_RETRY; |
5048 | ||
9b8ebbdb | 5049 | r = RET_PF_INVALID; |
e9ee956e | 5050 | if (unlikely(error_code & PFERR_RSVD_MASK)) { |
736c291c | 5051 | r = handle_mmio_page_fault(vcpu, cr2_or_gpa, direct); |
472faffa | 5052 | if (r == RET_PF_EMULATE) |
e9ee956e | 5053 | goto emulate; |
e9ee956e | 5054 | } |
3067714c | 5055 | |
9b8ebbdb | 5056 | if (r == RET_PF_INVALID) { |
7a02674d SC |
5057 | r = kvm_mmu_do_page_fault(vcpu, cr2_or_gpa, |
5058 | lower_32_bits(error_code), false); | |
7b367bc9 SC |
5059 | if (WARN_ON_ONCE(r == RET_PF_INVALID)) |
5060 | return -EIO; | |
9b8ebbdb PB |
5061 | } |
5062 | ||
3067714c | 5063 | if (r < 0) |
e9ee956e | 5064 | return r; |
83a2ba4c SC |
5065 | if (r != RET_PF_EMULATE) |
5066 | return 1; | |
3067714c | 5067 | |
14727754 TL |
5068 | /* |
5069 | * Before emulating the instruction, check if the error code | |
5070 | * was due to a RO violation while translating the guest page. | |
5071 | * This can occur when using nested virtualization with nested | |
5072 | * paging in both guests. If true, we simply unprotect the page | |
5073 | * and resume the guest. | |
14727754 | 5074 | */ |
44dd3ffa | 5075 | if (vcpu->arch.mmu->direct_map && |
eebed243 | 5076 | (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) { |
736c291c | 5077 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2_or_gpa)); |
14727754 TL |
5078 | return 1; |
5079 | } | |
5080 | ||
472faffa SC |
5081 | /* |
5082 | * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still | |
5083 | * optimistically try to just unprotect the page and let the processor | |
5084 | * re-execute the instruction that caused the page fault. Do not allow | |
5085 | * retrying MMIO emulation, as it's not only pointless but could also | |
5086 | * cause us to enter an infinite loop because the processor will keep | |
6c3dfeb6 SC |
5087 | * faulting on the non-existent MMIO address. Retrying an instruction |
5088 | * from a nested guest is also pointless and dangerous as we are only | |
5089 | * explicitly shadowing L1's page tables, i.e. unprotecting something | |
5090 | * for L1 isn't going to magically fix whatever issue cause L2 to fail. | |
472faffa | 5091 | */ |
736c291c | 5092 | if (!mmio_info_in_cache(vcpu, cr2_or_gpa, direct) && !is_guest_mode(vcpu)) |
92daa48b | 5093 | emulation_type |= EMULTYPE_ALLOW_RETRY_PF; |
e9ee956e | 5094 | emulate: |
736c291c | 5095 | return x86_emulate_instruction(vcpu, cr2_or_gpa, emulation_type, insn, |
60fc3d02 | 5096 | insn_len); |
3067714c AK |
5097 | } |
5098 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
5099 | ||
5efac074 PB |
5100 | void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
5101 | gva_t gva, hpa_t root_hpa) | |
a7052897 | 5102 | { |
b94742c9 | 5103 | int i; |
7eb77e9f | 5104 | |
5efac074 PB |
5105 | /* It's actually a GPA for vcpu->arch.guest_mmu. */ |
5106 | if (mmu != &vcpu->arch.guest_mmu) { | |
5107 | /* INVLPG on a non-canonical address is a NOP according to the SDM. */ | |
5108 | if (is_noncanonical_address(gva, vcpu)) | |
5109 | return; | |
5110 | ||
5111 | kvm_x86_ops.tlb_flush_gva(vcpu, gva); | |
5112 | } | |
5113 | ||
5114 | if (!mmu->invlpg) | |
faff8758 JS |
5115 | return; |
5116 | ||
5efac074 PB |
5117 | if (root_hpa == INVALID_PAGE) { |
5118 | mmu->invlpg(vcpu, gva, mmu->root_hpa); | |
956bf353 | 5119 | |
5efac074 PB |
5120 | /* |
5121 | * INVLPG is required to invalidate any global mappings for the VA, | |
5122 | * irrespective of PCID. Since it would take us roughly similar amount | |
5123 | * of work to determine whether any of the prev_root mappings of the VA | |
5124 | * is marked global, or to just sync it blindly, so we might as well | |
5125 | * just always sync it. | |
5126 | * | |
5127 | * Mappings not reachable via the current cr3 or the prev_roots will be | |
5128 | * synced when switching to that cr3, so nothing needs to be done here | |
5129 | * for them. | |
5130 | */ | |
5131 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
5132 | if (VALID_PAGE(mmu->prev_roots[i].hpa)) | |
5133 | mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa); | |
5134 | } else { | |
5135 | mmu->invlpg(vcpu, gva, root_hpa); | |
5136 | } | |
5137 | } | |
5138 | EXPORT_SYMBOL_GPL(kvm_mmu_invalidate_gva); | |
956bf353 | 5139 | |
5efac074 PB |
5140 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
5141 | { | |
5142 | kvm_mmu_invalidate_gva(vcpu, vcpu->arch.mmu, gva, INVALID_PAGE); | |
a7052897 MT |
5143 | ++vcpu->stat.invlpg; |
5144 | } | |
5145 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
5146 | ||
5efac074 | 5147 | |
eb4b248e JS |
5148 | void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid) |
5149 | { | |
44dd3ffa | 5150 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
faff8758 | 5151 | bool tlb_flush = false; |
b94742c9 | 5152 | uint i; |
eb4b248e JS |
5153 | |
5154 | if (pcid == kvm_get_active_pcid(vcpu)) { | |
7eb77e9f | 5155 | mmu->invlpg(vcpu, gva, mmu->root_hpa); |
faff8758 | 5156 | tlb_flush = true; |
eb4b248e JS |
5157 | } |
5158 | ||
b94742c9 JS |
5159 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { |
5160 | if (VALID_PAGE(mmu->prev_roots[i].hpa) && | |
be01e8e2 | 5161 | pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd)) { |
b94742c9 JS |
5162 | mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa); |
5163 | tlb_flush = true; | |
5164 | } | |
956bf353 | 5165 | } |
ade61e28 | 5166 | |
faff8758 | 5167 | if (tlb_flush) |
afaf0b2f | 5168 | kvm_x86_ops.tlb_flush_gva(vcpu, gva); |
faff8758 | 5169 | |
eb4b248e JS |
5170 | ++vcpu->stat.invlpg; |
5171 | ||
5172 | /* | |
b94742c9 JS |
5173 | * Mappings not reachable via the current cr3 or the prev_roots will be |
5174 | * synced when switching to that cr3, so nothing needs to be done here | |
5175 | * for them. | |
eb4b248e JS |
5176 | */ |
5177 | } | |
5178 | EXPORT_SYMBOL_GPL(kvm_mmu_invpcid_gva); | |
5179 | ||
83013059 SC |
5180 | void kvm_configure_mmu(bool enable_tdp, int tdp_max_root_level, |
5181 | int tdp_huge_page_level) | |
18552672 | 5182 | { |
bde77235 | 5183 | tdp_enabled = enable_tdp; |
83013059 | 5184 | max_tdp_level = tdp_max_root_level; |
703c335d SC |
5185 | |
5186 | /* | |
1d92d2e8 | 5187 | * max_huge_page_level reflects KVM's MMU capabilities irrespective |
703c335d SC |
5188 | * of kernel support, e.g. KVM may be capable of using 1GB pages when |
5189 | * the kernel is not. But, KVM never creates a page size greater than | |
5190 | * what is used by the kernel for any given HVA, i.e. the kernel's | |
5191 | * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust(). | |
5192 | */ | |
5193 | if (tdp_enabled) | |
1d92d2e8 | 5194 | max_huge_page_level = tdp_huge_page_level; |
703c335d | 5195 | else if (boot_cpu_has(X86_FEATURE_GBPAGES)) |
1d92d2e8 | 5196 | max_huge_page_level = PG_LEVEL_1G; |
703c335d | 5197 | else |
1d92d2e8 | 5198 | max_huge_page_level = PG_LEVEL_2M; |
18552672 | 5199 | } |
bde77235 | 5200 | EXPORT_SYMBOL_GPL(kvm_configure_mmu); |
85875a13 SC |
5201 | |
5202 | /* The return value indicates if tlb flush on all vcpus is needed. */ | |
5203 | typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head); | |
5204 | ||
5205 | /* The caller should hold mmu-lock before calling this function. */ | |
5206 | static __always_inline bool | |
5207 | slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5208 | slot_level_handler fn, int start_level, int end_level, | |
5209 | gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb) | |
5210 | { | |
5211 | struct slot_rmap_walk_iterator iterator; | |
5212 | bool flush = false; | |
5213 | ||
5214 | for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn, | |
5215 | end_gfn, &iterator) { | |
5216 | if (iterator.rmap) | |
5217 | flush |= fn(kvm, iterator.rmap); | |
5218 | ||
5219 | if (need_resched() || spin_needbreak(&kvm->mmu_lock)) { | |
5220 | if (flush && lock_flush_tlb) { | |
f285c633 BG |
5221 | kvm_flush_remote_tlbs_with_address(kvm, |
5222 | start_gfn, | |
5223 | iterator.gfn - start_gfn + 1); | |
85875a13 SC |
5224 | flush = false; |
5225 | } | |
5226 | cond_resched_lock(&kvm->mmu_lock); | |
5227 | } | |
5228 | } | |
5229 | ||
5230 | if (flush && lock_flush_tlb) { | |
f285c633 BG |
5231 | kvm_flush_remote_tlbs_with_address(kvm, start_gfn, |
5232 | end_gfn - start_gfn + 1); | |
85875a13 SC |
5233 | flush = false; |
5234 | } | |
5235 | ||
5236 | return flush; | |
5237 | } | |
5238 | ||
5239 | static __always_inline bool | |
5240 | slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5241 | slot_level_handler fn, int start_level, int end_level, | |
5242 | bool lock_flush_tlb) | |
5243 | { | |
5244 | return slot_handle_level_range(kvm, memslot, fn, start_level, | |
5245 | end_level, memslot->base_gfn, | |
5246 | memslot->base_gfn + memslot->npages - 1, | |
5247 | lock_flush_tlb); | |
5248 | } | |
5249 | ||
5250 | static __always_inline bool | |
5251 | slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5252 | slot_level_handler fn, bool lock_flush_tlb) | |
5253 | { | |
3bae0459 | 5254 | return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K, |
e662ec3e | 5255 | KVM_MAX_HUGEPAGE_LEVEL, lock_flush_tlb); |
85875a13 SC |
5256 | } |
5257 | ||
5258 | static __always_inline bool | |
5259 | slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5260 | slot_level_handler fn, bool lock_flush_tlb) | |
5261 | { | |
3bae0459 | 5262 | return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K + 1, |
e662ec3e | 5263 | KVM_MAX_HUGEPAGE_LEVEL, lock_flush_tlb); |
85875a13 SC |
5264 | } |
5265 | ||
5266 | static __always_inline bool | |
5267 | slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
5268 | slot_level_handler fn, bool lock_flush_tlb) | |
5269 | { | |
3bae0459 SC |
5270 | return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K, |
5271 | PG_LEVEL_4K, lock_flush_tlb); | |
85875a13 SC |
5272 | } |
5273 | ||
1cfff4d9 | 5274 | static void free_mmu_pages(struct kvm_mmu *mmu) |
6aa8b732 | 5275 | { |
1cfff4d9 JP |
5276 | free_page((unsigned long)mmu->pae_root); |
5277 | free_page((unsigned long)mmu->lm_root); | |
6aa8b732 AK |
5278 | } |
5279 | ||
04d28e37 | 5280 | static int __kvm_mmu_create(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
6aa8b732 | 5281 | { |
17ac10ad | 5282 | struct page *page; |
6aa8b732 AK |
5283 | int i; |
5284 | ||
04d28e37 SC |
5285 | mmu->root_hpa = INVALID_PAGE; |
5286 | mmu->root_pgd = 0; | |
5287 | mmu->translate_gpa = translate_gpa; | |
5288 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
5289 | mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID; | |
5290 | ||
17ac10ad | 5291 | /* |
b6b80c78 SC |
5292 | * When using PAE paging, the four PDPTEs are treated as 'root' pages, |
5293 | * while the PDP table is a per-vCPU construct that's allocated at MMU | |
5294 | * creation. When emulating 32-bit mode, cr3 is only 32 bits even on | |
5295 | * x86_64. Therefore we need to allocate the PDP table in the first | |
5296 | * 4GB of memory, which happens to fit the DMA32 zone. Except for | |
5297 | * SVM's 32-bit NPT support, TDP paging doesn't use PAE paging and can | |
5298 | * skip allocating the PDP table. | |
17ac10ad | 5299 | */ |
d468d94b | 5300 | if (tdp_enabled && kvm_mmu_get_tdp_level(vcpu) > PT32E_ROOT_LEVEL) |
b6b80c78 SC |
5301 | return 0; |
5302 | ||
254272ce | 5303 | page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32); |
17ac10ad | 5304 | if (!page) |
d7fa6ab2 WY |
5305 | return -ENOMEM; |
5306 | ||
1cfff4d9 | 5307 | mmu->pae_root = page_address(page); |
17ac10ad | 5308 | for (i = 0; i < 4; ++i) |
1cfff4d9 | 5309 | mmu->pae_root[i] = INVALID_PAGE; |
17ac10ad | 5310 | |
6aa8b732 | 5311 | return 0; |
6aa8b732 AK |
5312 | } |
5313 | ||
8018c27b | 5314 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 5315 | { |
1cfff4d9 | 5316 | int ret; |
b94742c9 | 5317 | |
5962bfb7 | 5318 | vcpu->arch.mmu_pte_list_desc_cache.kmem_cache = pte_list_desc_cache; |
5f6078f9 SC |
5319 | vcpu->arch.mmu_pte_list_desc_cache.gfp_zero = __GFP_ZERO; |
5320 | ||
5962bfb7 | 5321 | vcpu->arch.mmu_page_header_cache.kmem_cache = mmu_page_header_cache; |
5f6078f9 | 5322 | vcpu->arch.mmu_page_header_cache.gfp_zero = __GFP_ZERO; |
5962bfb7 | 5323 | |
96880883 SC |
5324 | vcpu->arch.mmu_shadow_page_cache.gfp_zero = __GFP_ZERO; |
5325 | ||
44dd3ffa VK |
5326 | vcpu->arch.mmu = &vcpu->arch.root_mmu; |
5327 | vcpu->arch.walk_mmu = &vcpu->arch.root_mmu; | |
6aa8b732 | 5328 | |
14c07ad8 | 5329 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; |
1cfff4d9 | 5330 | |
04d28e37 | 5331 | ret = __kvm_mmu_create(vcpu, &vcpu->arch.guest_mmu); |
1cfff4d9 JP |
5332 | if (ret) |
5333 | return ret; | |
5334 | ||
04d28e37 | 5335 | ret = __kvm_mmu_create(vcpu, &vcpu->arch.root_mmu); |
1cfff4d9 JP |
5336 | if (ret) |
5337 | goto fail_allocate_root; | |
5338 | ||
5339 | return ret; | |
5340 | fail_allocate_root: | |
5341 | free_mmu_pages(&vcpu->arch.guest_mmu); | |
5342 | return ret; | |
6aa8b732 AK |
5343 | } |
5344 | ||
fbb158cb | 5345 | #define BATCH_ZAP_PAGES 10 |
002c5f73 SC |
5346 | static void kvm_zap_obsolete_pages(struct kvm *kvm) |
5347 | { | |
5348 | struct kvm_mmu_page *sp, *node; | |
fbb158cb | 5349 | int nr_zapped, batch = 0; |
002c5f73 SC |
5350 | |
5351 | restart: | |
5352 | list_for_each_entry_safe_reverse(sp, node, | |
5353 | &kvm->arch.active_mmu_pages, link) { | |
5354 | /* | |
5355 | * No obsolete valid page exists before a newly created page | |
5356 | * since active_mmu_pages is a FIFO list. | |
5357 | */ | |
5358 | if (!is_obsolete_sp(kvm, sp)) | |
5359 | break; | |
5360 | ||
5361 | /* | |
f95eec9b SC |
5362 | * Invalid pages should never land back on the list of active |
5363 | * pages. Skip the bogus page, otherwise we'll get stuck in an | |
5364 | * infinite loop if the page gets put back on the list (again). | |
002c5f73 | 5365 | */ |
f95eec9b | 5366 | if (WARN_ON(sp->role.invalid)) |
002c5f73 SC |
5367 | continue; |
5368 | ||
4506ecf4 SC |
5369 | /* |
5370 | * No need to flush the TLB since we're only zapping shadow | |
5371 | * pages with an obsolete generation number and all vCPUS have | |
5372 | * loaded a new root, i.e. the shadow pages being zapped cannot | |
5373 | * be in active use by the guest. | |
5374 | */ | |
fbb158cb | 5375 | if (batch >= BATCH_ZAP_PAGES && |
4506ecf4 | 5376 | cond_resched_lock(&kvm->mmu_lock)) { |
fbb158cb | 5377 | batch = 0; |
002c5f73 SC |
5378 | goto restart; |
5379 | } | |
5380 | ||
10605204 SC |
5381 | if (__kvm_mmu_prepare_zap_page(kvm, sp, |
5382 | &kvm->arch.zapped_obsolete_pages, &nr_zapped)) { | |
fbb158cb | 5383 | batch += nr_zapped; |
002c5f73 | 5384 | goto restart; |
fbb158cb | 5385 | } |
002c5f73 SC |
5386 | } |
5387 | ||
4506ecf4 SC |
5388 | /* |
5389 | * Trigger a remote TLB flush before freeing the page tables to ensure | |
5390 | * KVM is not in the middle of a lockless shadow page table walk, which | |
5391 | * may reference the pages. | |
5392 | */ | |
10605204 | 5393 | kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages); |
002c5f73 SC |
5394 | } |
5395 | ||
5396 | /* | |
5397 | * Fast invalidate all shadow pages and use lock-break technique | |
5398 | * to zap obsolete pages. | |
5399 | * | |
5400 | * It's required when memslot is being deleted or VM is being | |
5401 | * destroyed, in these cases, we should ensure that KVM MMU does | |
5402 | * not use any resource of the being-deleted slot or all slots | |
5403 | * after calling the function. | |
5404 | */ | |
5405 | static void kvm_mmu_zap_all_fast(struct kvm *kvm) | |
5406 | { | |
ca333add SC |
5407 | lockdep_assert_held(&kvm->slots_lock); |
5408 | ||
002c5f73 | 5409 | spin_lock(&kvm->mmu_lock); |
14a3c4f4 | 5410 | trace_kvm_mmu_zap_all_fast(kvm); |
ca333add SC |
5411 | |
5412 | /* | |
5413 | * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is | |
5414 | * held for the entire duration of zapping obsolete pages, it's | |
5415 | * impossible for there to be multiple invalid generations associated | |
5416 | * with *valid* shadow pages at any given time, i.e. there is exactly | |
5417 | * one valid generation and (at most) one invalid generation. | |
5418 | */ | |
5419 | kvm->arch.mmu_valid_gen = kvm->arch.mmu_valid_gen ? 0 : 1; | |
002c5f73 | 5420 | |
4506ecf4 SC |
5421 | /* |
5422 | * Notify all vcpus to reload its shadow page table and flush TLB. | |
5423 | * Then all vcpus will switch to new shadow page table with the new | |
5424 | * mmu_valid_gen. | |
5425 | * | |
5426 | * Note: we need to do this under the protection of mmu_lock, | |
5427 | * otherwise, vcpu would purge shadow page but miss tlb flush. | |
5428 | */ | |
5429 | kvm_reload_remote_mmus(kvm); | |
5430 | ||
002c5f73 | 5431 | kvm_zap_obsolete_pages(kvm); |
faaf05b0 BG |
5432 | |
5433 | if (kvm->arch.tdp_mmu_enabled) | |
5434 | kvm_tdp_mmu_zap_all(kvm); | |
5435 | ||
002c5f73 SC |
5436 | spin_unlock(&kvm->mmu_lock); |
5437 | } | |
5438 | ||
10605204 SC |
5439 | static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm) |
5440 | { | |
5441 | return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages)); | |
5442 | } | |
5443 | ||
b5f5fdca | 5444 | static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm, |
d126363d JS |
5445 | struct kvm_memory_slot *slot, |
5446 | struct kvm_page_track_notifier_node *node) | |
b5f5fdca | 5447 | { |
002c5f73 | 5448 | kvm_mmu_zap_all_fast(kvm); |
1bad2b2a XG |
5449 | } |
5450 | ||
13d268ca | 5451 | void kvm_mmu_init_vm(struct kvm *kvm) |
1bad2b2a | 5452 | { |
13d268ca | 5453 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; |
1bad2b2a | 5454 | |
fe5db27d BG |
5455 | kvm_mmu_init_tdp_mmu(kvm); |
5456 | ||
13d268ca | 5457 | node->track_write = kvm_mmu_pte_write; |
b5f5fdca | 5458 | node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot; |
13d268ca | 5459 | kvm_page_track_register_notifier(kvm, node); |
1bad2b2a XG |
5460 | } |
5461 | ||
13d268ca | 5462 | void kvm_mmu_uninit_vm(struct kvm *kvm) |
1bad2b2a | 5463 | { |
13d268ca | 5464 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; |
1bad2b2a | 5465 | |
13d268ca | 5466 | kvm_page_track_unregister_notifier(kvm, node); |
fe5db27d BG |
5467 | |
5468 | kvm_mmu_uninit_tdp_mmu(kvm); | |
1bad2b2a XG |
5469 | } |
5470 | ||
efdfe536 XG |
5471 | void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end) |
5472 | { | |
5473 | struct kvm_memslots *slots; | |
5474 | struct kvm_memory_slot *memslot; | |
9da0e4d5 | 5475 | int i; |
faaf05b0 | 5476 | bool flush; |
efdfe536 XG |
5477 | |
5478 | spin_lock(&kvm->mmu_lock); | |
9da0e4d5 PB |
5479 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
5480 | slots = __kvm_memslots(kvm, i); | |
5481 | kvm_for_each_memslot(memslot, slots) { | |
5482 | gfn_t start, end; | |
5483 | ||
5484 | start = max(gfn_start, memslot->base_gfn); | |
5485 | end = min(gfn_end, memslot->base_gfn + memslot->npages); | |
5486 | if (start >= end) | |
5487 | continue; | |
efdfe536 | 5488 | |
92da008f | 5489 | slot_handle_level_range(kvm, memslot, kvm_zap_rmapp, |
3bae0459 | 5490 | PG_LEVEL_4K, |
e662ec3e | 5491 | KVM_MAX_HUGEPAGE_LEVEL, |
92da008f | 5492 | start, end - 1, true); |
9da0e4d5 | 5493 | } |
efdfe536 XG |
5494 | } |
5495 | ||
faaf05b0 BG |
5496 | if (kvm->arch.tdp_mmu_enabled) { |
5497 | flush = kvm_tdp_mmu_zap_gfn_range(kvm, gfn_start, gfn_end); | |
5498 | if (flush) | |
5499 | kvm_flush_remote_tlbs(kvm); | |
5500 | } | |
5501 | ||
efdfe536 XG |
5502 | spin_unlock(&kvm->mmu_lock); |
5503 | } | |
5504 | ||
018aabb5 TY |
5505 | static bool slot_rmap_write_protect(struct kvm *kvm, |
5506 | struct kvm_rmap_head *rmap_head) | |
d77aa73c | 5507 | { |
018aabb5 | 5508 | return __rmap_write_protect(kvm, rmap_head, false); |
d77aa73c XG |
5509 | } |
5510 | ||
1c91cad4 | 5511 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, |
3c9bd400 JZ |
5512 | struct kvm_memory_slot *memslot, |
5513 | int start_level) | |
6aa8b732 | 5514 | { |
d77aa73c | 5515 | bool flush; |
6aa8b732 | 5516 | |
9d1beefb | 5517 | spin_lock(&kvm->mmu_lock); |
3c9bd400 | 5518 | flush = slot_handle_level(kvm, memslot, slot_rmap_write_protect, |
e662ec3e | 5519 | start_level, KVM_MAX_HUGEPAGE_LEVEL, false); |
a6a0b05d BG |
5520 | if (kvm->arch.tdp_mmu_enabled) |
5521 | flush |= kvm_tdp_mmu_wrprot_slot(kvm, memslot, PG_LEVEL_4K); | |
9d1beefb | 5522 | spin_unlock(&kvm->mmu_lock); |
198c74f4 | 5523 | |
198c74f4 XG |
5524 | /* |
5525 | * We can flush all the TLBs out of the mmu lock without TLB | |
5526 | * corruption since we just change the spte from writable to | |
5527 | * readonly so that we only need to care the case of changing | |
5528 | * spte from present to present (changing the spte from present | |
5529 | * to nonpresent will flush all the TLBs immediately), in other | |
5530 | * words, the only case we care is mmu_spte_update() where we | |
bdd303cb | 5531 | * have checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE |
198c74f4 XG |
5532 | * instead of PT_WRITABLE_MASK, that means it does not depend |
5533 | * on PT_WRITABLE_MASK anymore. | |
5534 | */ | |
d91ffee9 | 5535 | if (flush) |
7f42aa76 | 5536 | kvm_arch_flush_remote_tlbs_memslot(kvm, memslot); |
6aa8b732 | 5537 | } |
37a7d8b0 | 5538 | |
3ea3b7fa | 5539 | static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm, |
018aabb5 | 5540 | struct kvm_rmap_head *rmap_head) |
3ea3b7fa WL |
5541 | { |
5542 | u64 *sptep; | |
5543 | struct rmap_iterator iter; | |
5544 | int need_tlb_flush = 0; | |
ba049e93 | 5545 | kvm_pfn_t pfn; |
3ea3b7fa WL |
5546 | struct kvm_mmu_page *sp; |
5547 | ||
0d536790 | 5548 | restart: |
018aabb5 | 5549 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
57354682 | 5550 | sp = sptep_to_sp(sptep); |
3ea3b7fa WL |
5551 | pfn = spte_to_pfn(*sptep); |
5552 | ||
5553 | /* | |
decf6333 XG |
5554 | * We cannot do huge page mapping for indirect shadow pages, |
5555 | * which are found on the last rmap (level = 1) when not using | |
5556 | * tdp; such shadow pages are synced with the page table in | |
5557 | * the guest, and the guest page table is using 4K page size | |
5558 | * mapping if the indirect sp has level = 1. | |
3ea3b7fa | 5559 | */ |
a78986aa | 5560 | if (sp->role.direct && !kvm_is_reserved_pfn(pfn) && |
e851265a SC |
5561 | (kvm_is_zone_device_pfn(pfn) || |
5562 | PageCompound(pfn_to_page(pfn)))) { | |
e7912386 | 5563 | pte_list_remove(rmap_head, sptep); |
40ef75a7 LT |
5564 | |
5565 | if (kvm_available_flush_tlb_with_range()) | |
5566 | kvm_flush_remote_tlbs_with_address(kvm, sp->gfn, | |
5567 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
5568 | else | |
5569 | need_tlb_flush = 1; | |
5570 | ||
0d536790 XG |
5571 | goto restart; |
5572 | } | |
3ea3b7fa WL |
5573 | } |
5574 | ||
5575 | return need_tlb_flush; | |
5576 | } | |
5577 | ||
5578 | void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, | |
f36f3f28 | 5579 | const struct kvm_memory_slot *memslot) |
3ea3b7fa | 5580 | { |
f36f3f28 | 5581 | /* FIXME: const-ify all uses of struct kvm_memory_slot. */ |
3ea3b7fa | 5582 | spin_lock(&kvm->mmu_lock); |
f36f3f28 PB |
5583 | slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot, |
5584 | kvm_mmu_zap_collapsible_spte, true); | |
14881998 BG |
5585 | |
5586 | if (kvm->arch.tdp_mmu_enabled) | |
5587 | kvm_tdp_mmu_zap_collapsible_sptes(kvm, memslot); | |
3ea3b7fa WL |
5588 | spin_unlock(&kvm->mmu_lock); |
5589 | } | |
5590 | ||
b3594ffb SC |
5591 | void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm, |
5592 | struct kvm_memory_slot *memslot) | |
5593 | { | |
5594 | /* | |
7f42aa76 SC |
5595 | * All current use cases for flushing the TLBs for a specific memslot |
5596 | * are related to dirty logging, and do the TLB flush out of mmu_lock. | |
5597 | * The interaction between the various operations on memslot must be | |
5598 | * serialized by slots_locks to ensure the TLB flush from one operation | |
5599 | * is observed by any other operation on the same memslot. | |
b3594ffb SC |
5600 | */ |
5601 | lockdep_assert_held(&kvm->slots_lock); | |
cec37648 SC |
5602 | kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn, |
5603 | memslot->npages); | |
b3594ffb SC |
5604 | } |
5605 | ||
f4b4b180 KH |
5606 | void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, |
5607 | struct kvm_memory_slot *memslot) | |
5608 | { | |
d77aa73c | 5609 | bool flush; |
f4b4b180 KH |
5610 | |
5611 | spin_lock(&kvm->mmu_lock); | |
d77aa73c | 5612 | flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false); |
a6a0b05d BG |
5613 | if (kvm->arch.tdp_mmu_enabled) |
5614 | flush |= kvm_tdp_mmu_clear_dirty_slot(kvm, memslot); | |
f4b4b180 KH |
5615 | spin_unlock(&kvm->mmu_lock); |
5616 | ||
f4b4b180 KH |
5617 | /* |
5618 | * It's also safe to flush TLBs out of mmu lock here as currently this | |
5619 | * function is only used for dirty logging, in which case flushing TLB | |
5620 | * out of mmu lock also guarantees no dirty pages will be lost in | |
5621 | * dirty_bitmap. | |
5622 | */ | |
5623 | if (flush) | |
7f42aa76 | 5624 | kvm_arch_flush_remote_tlbs_memslot(kvm, memslot); |
f4b4b180 KH |
5625 | } |
5626 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty); | |
5627 | ||
5628 | void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, | |
5629 | struct kvm_memory_slot *memslot) | |
5630 | { | |
d77aa73c | 5631 | bool flush; |
f4b4b180 KH |
5632 | |
5633 | spin_lock(&kvm->mmu_lock); | |
d77aa73c XG |
5634 | flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect, |
5635 | false); | |
a6a0b05d BG |
5636 | if (kvm->arch.tdp_mmu_enabled) |
5637 | flush |= kvm_tdp_mmu_wrprot_slot(kvm, memslot, PG_LEVEL_2M); | |
f4b4b180 KH |
5638 | spin_unlock(&kvm->mmu_lock); |
5639 | ||
f4b4b180 | 5640 | if (flush) |
7f42aa76 | 5641 | kvm_arch_flush_remote_tlbs_memslot(kvm, memslot); |
f4b4b180 KH |
5642 | } |
5643 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access); | |
5644 | ||
5645 | void kvm_mmu_slot_set_dirty(struct kvm *kvm, | |
5646 | struct kvm_memory_slot *memslot) | |
5647 | { | |
d77aa73c | 5648 | bool flush; |
f4b4b180 KH |
5649 | |
5650 | spin_lock(&kvm->mmu_lock); | |
d77aa73c | 5651 | flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false); |
a6a0b05d BG |
5652 | if (kvm->arch.tdp_mmu_enabled) |
5653 | flush |= kvm_tdp_mmu_slot_set_dirty(kvm, memslot); | |
f4b4b180 KH |
5654 | spin_unlock(&kvm->mmu_lock); |
5655 | ||
f4b4b180 | 5656 | if (flush) |
7f42aa76 | 5657 | kvm_arch_flush_remote_tlbs_memslot(kvm, memslot); |
f4b4b180 KH |
5658 | } |
5659 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty); | |
5660 | ||
92f58b5c | 5661 | void kvm_mmu_zap_all(struct kvm *kvm) |
5304b8d3 XG |
5662 | { |
5663 | struct kvm_mmu_page *sp, *node; | |
7390de1e | 5664 | LIST_HEAD(invalid_list); |
83cdb568 | 5665 | int ign; |
5304b8d3 | 5666 | |
7390de1e | 5667 | spin_lock(&kvm->mmu_lock); |
5304b8d3 | 5668 | restart: |
8a674adc | 5669 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) { |
f95eec9b | 5670 | if (WARN_ON(sp->role.invalid)) |
4771450c | 5671 | continue; |
92f58b5c | 5672 | if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign)) |
5304b8d3 | 5673 | goto restart; |
24efe61f | 5674 | if (cond_resched_lock(&kvm->mmu_lock)) |
5304b8d3 XG |
5675 | goto restart; |
5676 | } | |
5677 | ||
4771450c | 5678 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
faaf05b0 BG |
5679 | |
5680 | if (kvm->arch.tdp_mmu_enabled) | |
5681 | kvm_tdp_mmu_zap_all(kvm); | |
5682 | ||
5304b8d3 XG |
5683 | spin_unlock(&kvm->mmu_lock); |
5684 | } | |
5685 | ||
15248258 | 5686 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen) |
f8f55942 | 5687 | { |
164bf7e5 | 5688 | WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS); |
e1359e2b | 5689 | |
164bf7e5 | 5690 | gen &= MMIO_SPTE_GEN_MASK; |
e1359e2b | 5691 | |
f8f55942 | 5692 | /* |
e1359e2b SC |
5693 | * Generation numbers are incremented in multiples of the number of |
5694 | * address spaces in order to provide unique generations across all | |
5695 | * address spaces. Strip what is effectively the address space | |
5696 | * modifier prior to checking for a wrap of the MMIO generation so | |
5697 | * that a wrap in any address space is detected. | |
5698 | */ | |
5699 | gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1); | |
5700 | ||
f8f55942 | 5701 | /* |
e1359e2b | 5702 | * The very rare case: if the MMIO generation number has wrapped, |
f8f55942 | 5703 | * zap all shadow pages. |
f8f55942 | 5704 | */ |
e1359e2b | 5705 | if (unlikely(gen == 0)) { |
ae0f5499 | 5706 | kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n"); |
92f58b5c | 5707 | kvm_mmu_zap_all_fast(kvm); |
7a2e8aaf | 5708 | } |
f8f55942 XG |
5709 | } |
5710 | ||
70534a73 DC |
5711 | static unsigned long |
5712 | mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) | |
3ee16c81 IE |
5713 | { |
5714 | struct kvm *kvm; | |
1495f230 | 5715 | int nr_to_scan = sc->nr_to_scan; |
70534a73 | 5716 | unsigned long freed = 0; |
3ee16c81 | 5717 | |
0d9ce162 | 5718 | mutex_lock(&kvm_lock); |
3ee16c81 IE |
5719 | |
5720 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
3d56cbdf | 5721 | int idx; |
d98ba053 | 5722 | LIST_HEAD(invalid_list); |
3ee16c81 | 5723 | |
35f2d16b TY |
5724 | /* |
5725 | * Never scan more than sc->nr_to_scan VM instances. | |
5726 | * Will not hit this condition practically since we do not try | |
5727 | * to shrink more than one VM and it is very unlikely to see | |
5728 | * !n_used_mmu_pages so many times. | |
5729 | */ | |
5730 | if (!nr_to_scan--) | |
5731 | break; | |
19526396 GN |
5732 | /* |
5733 | * n_used_mmu_pages is accessed without holding kvm->mmu_lock | |
5734 | * here. We may skip a VM instance errorneosly, but we do not | |
5735 | * want to shrink a VM that only started to populate its MMU | |
5736 | * anyway. | |
5737 | */ | |
10605204 SC |
5738 | if (!kvm->arch.n_used_mmu_pages && |
5739 | !kvm_has_zapped_obsolete_pages(kvm)) | |
19526396 | 5740 | continue; |
19526396 | 5741 | |
f656ce01 | 5742 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 5743 | spin_lock(&kvm->mmu_lock); |
3ee16c81 | 5744 | |
10605204 SC |
5745 | if (kvm_has_zapped_obsolete_pages(kvm)) { |
5746 | kvm_mmu_commit_zap_page(kvm, | |
5747 | &kvm->arch.zapped_obsolete_pages); | |
5748 | goto unlock; | |
5749 | } | |
5750 | ||
ebdb292d | 5751 | freed = kvm_mmu_zap_oldest_mmu_pages(kvm, sc->nr_to_scan); |
19526396 | 5752 | |
10605204 | 5753 | unlock: |
3ee16c81 | 5754 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 5755 | srcu_read_unlock(&kvm->srcu, idx); |
19526396 | 5756 | |
70534a73 DC |
5757 | /* |
5758 | * unfair on small ones | |
5759 | * per-vm shrinkers cry out | |
5760 | * sadness comes quickly | |
5761 | */ | |
19526396 GN |
5762 | list_move_tail(&kvm->vm_list, &vm_list); |
5763 | break; | |
3ee16c81 | 5764 | } |
3ee16c81 | 5765 | |
0d9ce162 | 5766 | mutex_unlock(&kvm_lock); |
70534a73 | 5767 | return freed; |
70534a73 DC |
5768 | } |
5769 | ||
5770 | static unsigned long | |
5771 | mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc) | |
5772 | { | |
45221ab6 | 5773 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); |
3ee16c81 IE |
5774 | } |
5775 | ||
5776 | static struct shrinker mmu_shrinker = { | |
70534a73 DC |
5777 | .count_objects = mmu_shrink_count, |
5778 | .scan_objects = mmu_shrink_scan, | |
3ee16c81 IE |
5779 | .seeks = DEFAULT_SEEKS * 10, |
5780 | }; | |
5781 | ||
2ddfd20e | 5782 | static void mmu_destroy_caches(void) |
b5a33a75 | 5783 | { |
c1bd743e TH |
5784 | kmem_cache_destroy(pte_list_desc_cache); |
5785 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
5786 | } |
5787 | ||
7b6f8a06 KH |
5788 | static void kvm_set_mmio_spte_mask(void) |
5789 | { | |
5790 | u64 mask; | |
7b6f8a06 KH |
5791 | |
5792 | /* | |
6129ed87 SC |
5793 | * Set a reserved PA bit in MMIO SPTEs to generate page faults with |
5794 | * PFEC.RSVD=1 on MMIO accesses. 64-bit PTEs (PAE, x86-64, and EPT | |
5795 | * paging) support a maximum of 52 bits of PA, i.e. if the CPU supports | |
5796 | * 52-bit physical addresses then there are no reserved PA bits in the | |
5797 | * PTEs and so the reserved PA approach must be disabled. | |
7b6f8a06 | 5798 | */ |
6129ed87 SC |
5799 | if (shadow_phys_bits < 52) |
5800 | mask = BIT_ULL(51) | PT_PRESENT_MASK; | |
5801 | else | |
5802 | mask = 0; | |
7b6f8a06 | 5803 | |
e7581cac | 5804 | kvm_mmu_set_mmio_spte_mask(mask, ACC_WRITE_MASK | ACC_USER_MASK); |
7b6f8a06 KH |
5805 | } |
5806 | ||
b8e8c830 PB |
5807 | static bool get_nx_auto_mode(void) |
5808 | { | |
5809 | /* Return true when CPU has the bug, and mitigations are ON */ | |
5810 | return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT) && !cpu_mitigations_off(); | |
5811 | } | |
5812 | ||
5813 | static void __set_nx_huge_pages(bool val) | |
5814 | { | |
5815 | nx_huge_pages = itlb_multihit_kvm_mitigation = val; | |
5816 | } | |
5817 | ||
5818 | static int set_nx_huge_pages(const char *val, const struct kernel_param *kp) | |
5819 | { | |
5820 | bool old_val = nx_huge_pages; | |
5821 | bool new_val; | |
5822 | ||
5823 | /* In "auto" mode deploy workaround only if CPU has the bug. */ | |
5824 | if (sysfs_streq(val, "off")) | |
5825 | new_val = 0; | |
5826 | else if (sysfs_streq(val, "force")) | |
5827 | new_val = 1; | |
5828 | else if (sysfs_streq(val, "auto")) | |
5829 | new_val = get_nx_auto_mode(); | |
5830 | else if (strtobool(val, &new_val) < 0) | |
5831 | return -EINVAL; | |
5832 | ||
5833 | __set_nx_huge_pages(new_val); | |
5834 | ||
5835 | if (new_val != old_val) { | |
5836 | struct kvm *kvm; | |
b8e8c830 PB |
5837 | |
5838 | mutex_lock(&kvm_lock); | |
5839 | ||
5840 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
ed69a6cb | 5841 | mutex_lock(&kvm->slots_lock); |
b8e8c830 | 5842 | kvm_mmu_zap_all_fast(kvm); |
ed69a6cb | 5843 | mutex_unlock(&kvm->slots_lock); |
1aa9b957 JS |
5844 | |
5845 | wake_up_process(kvm->arch.nx_lpage_recovery_thread); | |
b8e8c830 PB |
5846 | } |
5847 | mutex_unlock(&kvm_lock); | |
5848 | } | |
5849 | ||
5850 | return 0; | |
5851 | } | |
5852 | ||
b5a33a75 AK |
5853 | int kvm_mmu_module_init(void) |
5854 | { | |
ab271bd4 AB |
5855 | int ret = -ENOMEM; |
5856 | ||
b8e8c830 PB |
5857 | if (nx_huge_pages == -1) |
5858 | __set_nx_huge_pages(get_nx_auto_mode()); | |
5859 | ||
36d9594d VK |
5860 | /* |
5861 | * MMU roles use union aliasing which is, generally speaking, an | |
5862 | * undefined behavior. However, we supposedly know how compilers behave | |
5863 | * and the current status quo is unlikely to change. Guardians below are | |
5864 | * supposed to let us know if the assumption becomes false. | |
5865 | */ | |
5866 | BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32)); | |
5867 | BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32)); | |
5868 | BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64)); | |
5869 | ||
28a1f3ac | 5870 | kvm_mmu_reset_all_pte_masks(); |
f160c7b7 | 5871 | |
7b6f8a06 KH |
5872 | kvm_set_mmio_spte_mask(); |
5873 | ||
53c07b18 XG |
5874 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
5875 | sizeof(struct pte_list_desc), | |
46bea48a | 5876 | 0, SLAB_ACCOUNT, NULL); |
53c07b18 | 5877 | if (!pte_list_desc_cache) |
ab271bd4 | 5878 | goto out; |
b5a33a75 | 5879 | |
d3d25b04 AK |
5880 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
5881 | sizeof(struct kvm_mmu_page), | |
46bea48a | 5882 | 0, SLAB_ACCOUNT, NULL); |
d3d25b04 | 5883 | if (!mmu_page_header_cache) |
ab271bd4 | 5884 | goto out; |
d3d25b04 | 5885 | |
908c7f19 | 5886 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL)) |
ab271bd4 | 5887 | goto out; |
45bf21a8 | 5888 | |
ab271bd4 AB |
5889 | ret = register_shrinker(&mmu_shrinker); |
5890 | if (ret) | |
5891 | goto out; | |
3ee16c81 | 5892 | |
b5a33a75 AK |
5893 | return 0; |
5894 | ||
ab271bd4 | 5895 | out: |
3ee16c81 | 5896 | mmu_destroy_caches(); |
ab271bd4 | 5897 | return ret; |
b5a33a75 AK |
5898 | } |
5899 | ||
3ad82a7e | 5900 | /* |
39337ad1 | 5901 | * Calculate mmu pages needed for kvm. |
3ad82a7e | 5902 | */ |
bc8a3d89 | 5903 | unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm) |
3ad82a7e | 5904 | { |
bc8a3d89 BG |
5905 | unsigned long nr_mmu_pages; |
5906 | unsigned long nr_pages = 0; | |
bc6678a3 | 5907 | struct kvm_memslots *slots; |
be6ba0f0 | 5908 | struct kvm_memory_slot *memslot; |
9da0e4d5 | 5909 | int i; |
3ad82a7e | 5910 | |
9da0e4d5 PB |
5911 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
5912 | slots = __kvm_memslots(kvm, i); | |
90d83dc3 | 5913 | |
9da0e4d5 PB |
5914 | kvm_for_each_memslot(memslot, slots) |
5915 | nr_pages += memslot->npages; | |
5916 | } | |
3ad82a7e ZX |
5917 | |
5918 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
bc8a3d89 | 5919 | nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES); |
3ad82a7e ZX |
5920 | |
5921 | return nr_mmu_pages; | |
5922 | } | |
5923 | ||
c42fffe3 XG |
5924 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
5925 | { | |
95f93af4 | 5926 | kvm_mmu_unload(vcpu); |
1cfff4d9 JP |
5927 | free_mmu_pages(&vcpu->arch.root_mmu); |
5928 | free_mmu_pages(&vcpu->arch.guest_mmu); | |
c42fffe3 | 5929 | mmu_free_memory_caches(vcpu); |
b034cf01 XG |
5930 | } |
5931 | ||
b034cf01 XG |
5932 | void kvm_mmu_module_exit(void) |
5933 | { | |
5934 | mmu_destroy_caches(); | |
5935 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
5936 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
5937 | mmu_audit_disable(); |
5938 | } | |
1aa9b957 JS |
5939 | |
5940 | static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp) | |
5941 | { | |
5942 | unsigned int old_val; | |
5943 | int err; | |
5944 | ||
5945 | old_val = nx_huge_pages_recovery_ratio; | |
5946 | err = param_set_uint(val, kp); | |
5947 | if (err) | |
5948 | return err; | |
5949 | ||
5950 | if (READ_ONCE(nx_huge_pages) && | |
5951 | !old_val && nx_huge_pages_recovery_ratio) { | |
5952 | struct kvm *kvm; | |
5953 | ||
5954 | mutex_lock(&kvm_lock); | |
5955 | ||
5956 | list_for_each_entry(kvm, &vm_list, vm_list) | |
5957 | wake_up_process(kvm->arch.nx_lpage_recovery_thread); | |
5958 | ||
5959 | mutex_unlock(&kvm_lock); | |
5960 | } | |
5961 | ||
5962 | return err; | |
5963 | } | |
5964 | ||
5965 | static void kvm_recover_nx_lpages(struct kvm *kvm) | |
5966 | { | |
5967 | int rcu_idx; | |
5968 | struct kvm_mmu_page *sp; | |
5969 | unsigned int ratio; | |
5970 | LIST_HEAD(invalid_list); | |
5971 | ulong to_zap; | |
5972 | ||
5973 | rcu_idx = srcu_read_lock(&kvm->srcu); | |
5974 | spin_lock(&kvm->mmu_lock); | |
5975 | ||
5976 | ratio = READ_ONCE(nx_huge_pages_recovery_ratio); | |
5977 | to_zap = ratio ? DIV_ROUND_UP(kvm->stat.nx_lpage_splits, ratio) : 0; | |
7d919c7a SC |
5978 | for ( ; to_zap; --to_zap) { |
5979 | if (list_empty(&kvm->arch.lpage_disallowed_mmu_pages)) | |
5980 | break; | |
5981 | ||
1aa9b957 JS |
5982 | /* |
5983 | * We use a separate list instead of just using active_mmu_pages | |
5984 | * because the number of lpage_disallowed pages is expected to | |
5985 | * be relatively small compared to the total. | |
5986 | */ | |
5987 | sp = list_first_entry(&kvm->arch.lpage_disallowed_mmu_pages, | |
5988 | struct kvm_mmu_page, | |
5989 | lpage_disallowed_link); | |
5990 | WARN_ON_ONCE(!sp->lpage_disallowed); | |
29cf0f50 BG |
5991 | if (sp->tdp_mmu_page) |
5992 | kvm_tdp_mmu_zap_gfn_range(kvm, sp->gfn, | |
5993 | sp->gfn + KVM_PAGES_PER_HPAGE(sp->role.level)); | |
5994 | else { | |
5995 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); | |
5996 | WARN_ON_ONCE(sp->lpage_disallowed); | |
5997 | } | |
1aa9b957 | 5998 | |
7d919c7a | 5999 | if (need_resched() || spin_needbreak(&kvm->mmu_lock)) { |
1aa9b957 | 6000 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
7d919c7a | 6001 | cond_resched_lock(&kvm->mmu_lock); |
1aa9b957 JS |
6002 | } |
6003 | } | |
e8950569 | 6004 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
1aa9b957 JS |
6005 | |
6006 | spin_unlock(&kvm->mmu_lock); | |
6007 | srcu_read_unlock(&kvm->srcu, rcu_idx); | |
6008 | } | |
6009 | ||
6010 | static long get_nx_lpage_recovery_timeout(u64 start_time) | |
6011 | { | |
6012 | return READ_ONCE(nx_huge_pages) && READ_ONCE(nx_huge_pages_recovery_ratio) | |
6013 | ? start_time + 60 * HZ - get_jiffies_64() | |
6014 | : MAX_SCHEDULE_TIMEOUT; | |
6015 | } | |
6016 | ||
6017 | static int kvm_nx_lpage_recovery_worker(struct kvm *kvm, uintptr_t data) | |
6018 | { | |
6019 | u64 start_time; | |
6020 | long remaining_time; | |
6021 | ||
6022 | while (true) { | |
6023 | start_time = get_jiffies_64(); | |
6024 | remaining_time = get_nx_lpage_recovery_timeout(start_time); | |
6025 | ||
6026 | set_current_state(TASK_INTERRUPTIBLE); | |
6027 | while (!kthread_should_stop() && remaining_time > 0) { | |
6028 | schedule_timeout(remaining_time); | |
6029 | remaining_time = get_nx_lpage_recovery_timeout(start_time); | |
6030 | set_current_state(TASK_INTERRUPTIBLE); | |
6031 | } | |
6032 | ||
6033 | set_current_state(TASK_RUNNING); | |
6034 | ||
6035 | if (kthread_should_stop()) | |
6036 | return 0; | |
6037 | ||
6038 | kvm_recover_nx_lpages(kvm); | |
6039 | } | |
6040 | } | |
6041 | ||
6042 | int kvm_mmu_post_init_vm(struct kvm *kvm) | |
6043 | { | |
6044 | int err; | |
6045 | ||
6046 | err = kvm_vm_create_worker_thread(kvm, kvm_nx_lpage_recovery_worker, 0, | |
6047 | "kvm-nx-lpage-recovery", | |
6048 | &kvm->arch.nx_lpage_recovery_thread); | |
6049 | if (!err) | |
6050 | kthread_unpark(kvm->arch.nx_lpage_recovery_thread); | |
6051 | ||
6052 | return err; | |
6053 | } | |
6054 | ||
6055 | void kvm_mmu_pre_destroy_vm(struct kvm *kvm) | |
6056 | { | |
6057 | if (kvm->arch.nx_lpage_recovery_thread) | |
6058 | kthread_stop(kvm->arch.nx_lpage_recovery_thread); | |
6059 | } |