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KVM: Document KVM_SET_BOOT_CPU_ID
[mirror_ubuntu-jammy-kernel.git] / arch / x86 / kvm / mmu.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 *
11 * Authors:
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Avi Kivity <avi@qumranet.com>
14 *
15 * This work is licensed under the terms of the GNU GPL, version 2. See
16 * the COPYING file in the top-level directory.
17 *
18 */
e495606d 19
1d737c8a 20#include "mmu.h"
836a1b3c 21#include "x86.h"
6de4f3ad 22#include "kvm_cache_regs.h"
e495606d 23
edf88417 24#include <linux/kvm_host.h>
6aa8b732
AK		 25#include <linux/types.h>
26#include <linux/string.h>
6aa8b732
AK		 27#include <linux/mm.h>
28#include <linux/highmem.h>
29#include <linux/module.h>
448353ca 30#include <linux/swap.h>
05da4558 31#include <linux/hugetlb.h>
2f333bcb 32#include <linux/compiler.h>
bc6678a3 33#include <linux/srcu.h>
5a0e3ad6 34#include <linux/slab.h>
bf998156 35#include <linux/uaccess.h>
6aa8b732 36
e495606d
AK		 37#include <asm/page.h>
38#include <asm/cmpxchg.h>
4e542370 39#include <asm/io.h>
13673a90 40#include <asm/vmx.h>
6aa8b732 41
18552672
JR		 42/*
43 * When setting this variable to true it enables Two-Dimensional-Paging
44 * where the hardware walks 2 page tables:
45 * 1. the guest-virtual to guest-physical
46 * 2. while doing 1. it walks guest-physical to host-physical
47 * If the hardware supports that we don't need to do shadow paging.
48 */
2f333bcb 49bool tdp_enabled = false;
18552672 50
37a7d8b0
AK		 51#undef MMU_DEBUG
52
53#undef AUDIT
54
55#ifdef AUDIT
56static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg);
57#else
58static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) {}
59#endif
60
61#ifdef MMU_DEBUG
62
63#define pgprintk(x...) do { if (dbg) printk(x); } while (0)
64#define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
65
66#else
67
68#define pgprintk(x...) do { } while (0)
69#define rmap_printk(x...) do { } while (0)
70
71#endif
72
73#if defined(MMU_DEBUG) || defined(AUDIT)
6ada8cca
AK		 74static int dbg = 0;
75module_param(dbg, bool, 0644);
37a7d8b0 76#endif
6aa8b732 77
582801a9
MT		 78static int oos_shadow = 1;
79module_param(oos_shadow, bool, 0644);
80
d6c69ee9
YD		 81#ifndef MMU_DEBUG
82#define ASSERT(x) do { } while (0)
83#else
6aa8b732
AK		 84#define ASSERT(x) \
85 if (!(x)) { \
86 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
87 __FILE__, __LINE__, #x); \
88 }
d6c69ee9 89#endif
6aa8b732 90
6aa8b732
AK		 91#define PT_FIRST_AVAIL_BITS_SHIFT 9
92#define PT64_SECOND_AVAIL_BITS_SHIFT 52
93
6aa8b732
AK		 94#define VALID_PAGE(x) ((x) != INVALID_PAGE)
95
96#define PT64_LEVEL_BITS 9
97
98#define PT64_LEVEL_SHIFT(level) \
d77c26fc 99 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
6aa8b732
AK		 100
101#define PT64_LEVEL_MASK(level) \
102 (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level))
103
104#define PT64_INDEX(address, level)\
105 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
106
107
108#define PT32_LEVEL_BITS 10
109
110#define PT32_LEVEL_SHIFT(level) \
d77c26fc 111 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
6aa8b732
AK		 112
113#define PT32_LEVEL_MASK(level) \
114 (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level))
e04da980
JR		 115#define PT32_LVL_OFFSET_MASK(level) \
116 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
117 * PT32_LEVEL_BITS))) - 1))
6aa8b732
AK		 118
119#define PT32_INDEX(address, level)\
120 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
121
122
27aba766 123#define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
6aa8b732
AK		 124#define PT64_DIR_BASE_ADDR_MASK \
125 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
e04da980
JR		 126#define PT64_LVL_ADDR_MASK(level) \
127 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
128 * PT64_LEVEL_BITS))) - 1))
129#define PT64_LVL_OFFSET_MASK(level) \
130 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
131 * PT64_LEVEL_BITS))) - 1))
6aa8b732
AK		 132
133#define PT32_BASE_ADDR_MASK PAGE_MASK
134#define PT32_DIR_BASE_ADDR_MASK \
135 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
e04da980
JR		 136#define PT32_LVL_ADDR_MASK(level) \
137 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
138 * PT32_LEVEL_BITS))) - 1))
6aa8b732 139
79539cec
AK		 140#define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
141 | PT64_NX_MASK)
6aa8b732 142
cd4a4e53
AK		 143#define RMAP_EXT 4
144
fe135d2c
AK		 145#define ACC_EXEC_MASK 1
146#define ACC_WRITE_MASK PT_WRITABLE_MASK
147#define ACC_USER_MASK PT_USER_MASK
148#define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
149
90bb6fc5
AK		 150#include <trace/events/kvm.h>
151
07420171
AK		 152#define CREATE_TRACE_POINTS
153#include "mmutrace.h"
154
1403283a
IE		 155#define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
156
135f8c2b
AK		 157#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
158
cd4a4e53 159struct kvm_rmap_desc {
d555c333 160 u64 *sptes[RMAP_EXT];
cd4a4e53
AK		 161 struct kvm_rmap_desc *more;
162};
163
2d11123a
AK		 164struct kvm_shadow_walk_iterator {
165 u64 addr;
166 hpa_t shadow_addr;
167 int level;
168 u64 *sptep;
169 unsigned index;
170};
171
172#define for_each_shadow_entry(_vcpu, _addr, _walker) \
173 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
174 shadow_walk_okay(&(_walker)); \
175 shadow_walk_next(&(_walker)))
176
6b18493d 177typedef int (*mmu_parent_walk_fn) (struct kvm_mmu_page *sp);
ad8cfbe3 178
b5a33a75
AK		 179static struct kmem_cache *pte_chain_cache;
180static struct kmem_cache *rmap_desc_cache;
d3d25b04 181static struct kmem_cache *mmu_page_header_cache;
b5a33a75 182
c7addb90
AK		 183static u64 __read_mostly shadow_trap_nonpresent_pte;
184static u64 __read_mostly shadow_notrap_nonpresent_pte;
7b52345e
SY		 185static u64 __read_mostly shadow_base_present_pte;
186static u64 __read_mostly shadow_nx_mask;
187static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
188static u64 __read_mostly shadow_user_mask;
189static u64 __read_mostly shadow_accessed_mask;
190static u64 __read_mostly shadow_dirty_mask;
c7addb90 191
82725b20
DE		 192static inline u64 rsvd_bits(int s, int e)
193{
194 return ((1ULL << (e - s + 1)) - 1) << s;
195}
196
c7addb90
AK		 197void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
198{
199 shadow_trap_nonpresent_pte = trap_pte;
200 shadow_notrap_nonpresent_pte = notrap_pte;
201}
202EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes);
203
7b52345e
SY		 204void kvm_mmu_set_base_ptes(u64 base_pte)
205{
206 shadow_base_present_pte = base_pte;
207}
208EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes);
209
210void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
4b12f0de 211 u64 dirty_mask, u64 nx_mask, u64 x_mask)
7b52345e
SY		 212{
213 shadow_user_mask = user_mask;
214 shadow_accessed_mask = accessed_mask;
215 shadow_dirty_mask = dirty_mask;
216 shadow_nx_mask = nx_mask;
217 shadow_x_mask = x_mask;
218}
219EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
220
3dbe1415 221static bool is_write_protection(struct kvm_vcpu *vcpu)
6aa8b732 222{
4d4ec087 223 return kvm_read_cr0_bits(vcpu, X86_CR0_WP);
6aa8b732
AK		 224}
225
226static int is_cpuid_PSE36(void)
227{
228 return 1;
229}
230
73b1087e
AK		 231static int is_nx(struct kvm_vcpu *vcpu)
232{
f6801dff 233 return vcpu->arch.efer & EFER_NX;
73b1087e
AK		 234}
235
c7addb90
AK		 236static int is_shadow_present_pte(u64 pte)
237{
c7addb90
AK		 238 return pte != shadow_trap_nonpresent_pte
239 && pte != shadow_notrap_nonpresent_pte;
240}
241
05da4558
MT		 242static int is_large_pte(u64 pte)
243{
244 return pte & PT_PAGE_SIZE_MASK;
245}
246
8dae4445 247static int is_writable_pte(unsigned long pte)
6aa8b732
AK		 248{
249 return pte & PT_WRITABLE_MASK;
250}
251
43a3795a 252static int is_dirty_gpte(unsigned long pte)
e3c5e7ec 253{
439e218a 254 return pte & PT_DIRTY_MASK;
e3c5e7ec
AK		 255}
256
43a3795a 257static int is_rmap_spte(u64 pte)
cd4a4e53 258{
4b1a80fa 259 return is_shadow_present_pte(pte);
cd4a4e53
AK		 260}
261
776e6633
MT		 262static int is_last_spte(u64 pte, int level)
263{
264 if (level == PT_PAGE_TABLE_LEVEL)
265 return 1;
852e3c19 266 if (is_large_pte(pte))
776e6633
MT		 267 return 1;
268 return 0;
269}
270
35149e21 271static pfn_t spte_to_pfn(u64 pte)
0b49ea86 272{
35149e21 273 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
0b49ea86
AK		 274}
275
da928521
AK		 276static gfn_t pse36_gfn_delta(u32 gpte)
277{
278 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
279
280 return (gpte & PT32_DIR_PSE36_MASK) << shift;
281}
282
d555c333 283static void __set_spte(u64 *sptep, u64 spte)
e663ee64
AK		 284{
285#ifdef CONFIG_X86_64
286 set_64bit((unsigned long *)sptep, spte);
287#else
288 set_64bit((unsigned long long *)sptep, spte);
289#endif
290}
291
e2dec939 292static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
2e3e5882 293 struct kmem_cache *base_cache, int min)
714b93da
AK		 294{
295 void *obj;
296
297 if (cache->nobjs >= min)
e2dec939 298 return 0;
714b93da 299 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 300 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
714b93da 301 if (!obj)
e2dec939 302 return -ENOMEM;
714b93da
AK		 303 cache->objects[cache->nobjs++] = obj;
304 }
e2dec939 305 return 0;
714b93da
AK		 306}
307
308static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc)
309{
310 while (mc->nobjs)
311 kfree(mc->objects[--mc->nobjs]);
312}
313
c1158e63 314static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
2e3e5882 315 int min)
c1158e63
AK		 316{
317 struct page *page;
318
319 if (cache->nobjs >= min)
320 return 0;
321 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 322 page = alloc_page(GFP_KERNEL);
c1158e63
AK		 323 if (!page)
324 return -ENOMEM;
c1158e63
AK		 325 cache->objects[cache->nobjs++] = page_address(page);
326 }
327 return 0;
328}
329
330static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
331{
332 while (mc->nobjs)
c4d198d5 333 free_page((unsigned long)mc->objects[--mc->nobjs]);
c1158e63
AK		 334}
335
2e3e5882 336static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
714b93da 337{
e2dec939
AK		 338 int r;
339
ad312c7c 340 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache,
2e3e5882 341 pte_chain_cache, 4);
e2dec939
AK		 342 if (r)
343 goto out;
ad312c7c 344 r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache,
c41ef344 345 rmap_desc_cache, 4);
d3d25b04
AK		 346 if (r)
347 goto out;
ad312c7c 348 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
d3d25b04
AK		 349 if (r)
350 goto out;
ad312c7c 351 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
2e3e5882 352 mmu_page_header_cache, 4);
e2dec939
AK		 353out:
354 return r;
714b93da
AK		 355}
356
357static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
358{
ad312c7c
ZX		 359 mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache);
360 mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache);
361 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
362 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
714b93da
AK		 363}
364
365static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
366 size_t size)
367{
368 void *p;
369
370 BUG_ON(!mc->nobjs);
371 p = mc->objects[--mc->nobjs];
714b93da
AK		 372 return p;
373}
374
714b93da
AK		 375static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu)
376{
ad312c7c 377 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache,
714b93da
AK		 378 sizeof(struct kvm_pte_chain));
379}
380
90cb0529 381static void mmu_free_pte_chain(struct kvm_pte_chain *pc)
714b93da 382{
90cb0529 383 kfree(pc);
714b93da
AK		 384}
385
386static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu)
387{
ad312c7c 388 return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache,
714b93da
AK		 389 sizeof(struct kvm_rmap_desc));
390}
391
90cb0529 392static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd)
714b93da 393{
90cb0529 394 kfree(rd);
714b93da
AK		 395}
396
05da4558
MT		 397/*
398 * Return the pointer to the largepage write count for a given
399 * gfn, handling slots that are not large page aligned.
400 */
d25797b2
JR		 401static int *slot_largepage_idx(gfn_t gfn,
402 struct kvm_memory_slot *slot,
403 int level)
05da4558
MT		 404{
405 unsigned long idx;
406
d25797b2
JR		 407 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
408 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
409 return &slot->lpage_info[level - 2][idx].write_count;
05da4558
MT		 410}
411
412static void account_shadowed(struct kvm *kvm, gfn_t gfn)
413{
d25797b2 414 struct kvm_memory_slot *slot;
05da4558 415 int *write_count;
d25797b2 416 int i;
05da4558 417
2843099f 418 gfn = unalias_gfn(kvm, gfn);
d25797b2
JR		 419
420 slot = gfn_to_memslot_unaliased(kvm, gfn);
421 for (i = PT_DIRECTORY_LEVEL;
422 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
423 write_count = slot_largepage_idx(gfn, slot, i);
424 *write_count += 1;
425 }
05da4558
MT		 426}
427
428static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
429{
d25797b2 430 struct kvm_memory_slot *slot;
05da4558 431 int *write_count;
d25797b2 432 int i;
05da4558 433
2843099f 434 gfn = unalias_gfn(kvm, gfn);
77a1a715 435 slot = gfn_to_memslot_unaliased(kvm, gfn);
d25797b2
JR		 436 for (i = PT_DIRECTORY_LEVEL;
437 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
d25797b2
JR		 438 write_count = slot_largepage_idx(gfn, slot, i);
439 *write_count -= 1;
440 WARN_ON(*write_count < 0);
441 }
05da4558
MT		 442}
443
d25797b2
JR		 444static int has_wrprotected_page(struct kvm *kvm,
445 gfn_t gfn,
446 int level)
05da4558 447{
2843099f 448 struct kvm_memory_slot *slot;
05da4558
MT		 449 int *largepage_idx;
450
2843099f
IE		 451 gfn = unalias_gfn(kvm, gfn);
452 slot = gfn_to_memslot_unaliased(kvm, gfn);
05da4558 453 if (slot) {
d25797b2 454 largepage_idx = slot_largepage_idx(gfn, slot, level);
05da4558
MT		 455 return *largepage_idx;
456 }
457
458 return 1;
459}
460
d25797b2 461static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
05da4558 462{
8f0b1ab6 463 unsigned long page_size;
d25797b2 464 int i, ret = 0;
05da4558 465
8f0b1ab6 466 page_size = kvm_host_page_size(kvm, gfn);
05da4558 467
d25797b2
JR		 468 for (i = PT_PAGE_TABLE_LEVEL;
469 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
470 if (page_size >= KVM_HPAGE_SIZE(i))
471 ret = i;
472 else
473 break;
474 }
475
4c2155ce 476 return ret;
05da4558
MT		 477}
478
d25797b2 479static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
05da4558
MT		 480{
481 struct kvm_memory_slot *slot;
878403b7 482 int host_level, level, max_level;
05da4558
MT		 483
484 slot = gfn_to_memslot(vcpu->kvm, large_gfn);
485 if (slot && slot->dirty_bitmap)
d25797b2 486 return PT_PAGE_TABLE_LEVEL;
05da4558 487
d25797b2
JR		 488 host_level = host_mapping_level(vcpu->kvm, large_gfn);
489
490 if (host_level == PT_PAGE_TABLE_LEVEL)
491 return host_level;
492
878403b7
SY		 493 max_level = kvm_x86_ops->get_lpage_level() < host_level ?
494 kvm_x86_ops->get_lpage_level() : host_level;
495
496 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
d25797b2
JR		 497 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
498 break;
d25797b2
JR		 499
500 return level - 1;
05da4558
MT		 501}
502
290fc38d
IE		 503/*
504 * Take gfn and return the reverse mapping to it.
505 * Note: gfn must be unaliased before this function get called
506 */
507
44ad9944 508static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
290fc38d
IE		 509{
510 struct kvm_memory_slot *slot;
05da4558 511 unsigned long idx;
290fc38d
IE		 512
513 slot = gfn_to_memslot(kvm, gfn);
44ad9944 514 if (likely(level == PT_PAGE_TABLE_LEVEL))
05da4558
MT		 515 return &slot->rmap[gfn - slot->base_gfn];
516
44ad9944
JR		 517 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
518 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
05da4558 519
44ad9944 520 return &slot->lpage_info[level - 2][idx].rmap_pde;
290fc38d
IE		 521}
522
cd4a4e53
AK		 523/*
524 * Reverse mapping data structures:
525 *
290fc38d
IE		 526 * If rmapp bit zero is zero, then rmapp point to the shadw page table entry
527 * that points to page_address(page).
cd4a4e53 528 *
290fc38d
IE		 529 * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc
530 * containing more mappings.
53a27b39
MT		 531 *
532 * Returns the number of rmap entries before the spte was added or zero if
533 * the spte was not added.
534 *
cd4a4e53 535 */
44ad9944 536static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
cd4a4e53 537{
4db35314 538 struct kvm_mmu_page *sp;
cd4a4e53 539 struct kvm_rmap_desc *desc;
290fc38d 540 unsigned long *rmapp;
53a27b39 541 int i, count = 0;
cd4a4e53 542
43a3795a 543 if (!is_rmap_spte(*spte))
53a27b39 544 return count;
290fc38d 545 gfn = unalias_gfn(vcpu->kvm, gfn);
4db35314
AK		 546 sp = page_header(__pa(spte));
547 sp->gfns[spte - sp->spt] = gfn;
44ad9944 548 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
290fc38d 549 if (!*rmapp) {
cd4a4e53 550 rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte);
290fc38d
IE		 551 *rmapp = (unsigned long)spte;
552 } else if (!(*rmapp & 1)) {
cd4a4e53 553 rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte);
714b93da 554 desc = mmu_alloc_rmap_desc(vcpu);
d555c333
AK		 555 desc->sptes[0] = (u64 *)*rmapp;
556 desc->sptes[1] = spte;
290fc38d 557 *rmapp = (unsigned long)desc | 1;
cd4a4e53
AK		 558 } else {
559 rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte);
290fc38d 560 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
d555c333 561 while (desc->sptes[RMAP_EXT-1] && desc->more) {
cd4a4e53 562 desc = desc->more;
53a27b39
MT		 563 count += RMAP_EXT;
564 }
d555c333 565 if (desc->sptes[RMAP_EXT-1]) {
714b93da 566 desc->more = mmu_alloc_rmap_desc(vcpu);
cd4a4e53
AK		 567 desc = desc->more;
568 }
d555c333 569 for (i = 0; desc->sptes[i]; ++i)
cd4a4e53 570 ;
d555c333 571 desc->sptes[i] = spte;
cd4a4e53 572 }
53a27b39 573 return count;
cd4a4e53
AK		 574}
575
290fc38d 576static void rmap_desc_remove_entry(unsigned long *rmapp,
cd4a4e53
AK		 577 struct kvm_rmap_desc *desc,
578 int i,
579 struct kvm_rmap_desc *prev_desc)
580{
581 int j;
582
d555c333 583 for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j)
cd4a4e53 584 ;
d555c333
AK		 585 desc->sptes[i] = desc->sptes[j];
586 desc->sptes[j] = NULL;
cd4a4e53
AK		 587 if (j != 0)
588 return;
589 if (!prev_desc && !desc->more)
d555c333 590 *rmapp = (unsigned long)desc->sptes[0];
cd4a4e53
AK		 591 else
592 if (prev_desc)
593 prev_desc->more = desc->more;
594 else
290fc38d 595 *rmapp = (unsigned long)desc->more | 1;
90cb0529 596 mmu_free_rmap_desc(desc);
cd4a4e53
AK		 597}
598
290fc38d 599static void rmap_remove(struct kvm *kvm, u64 *spte)
cd4a4e53 600{
cd4a4e53
AK		 601 struct kvm_rmap_desc *desc;
602 struct kvm_rmap_desc *prev_desc;
4db35314 603 struct kvm_mmu_page *sp;
35149e21 604 pfn_t pfn;
290fc38d 605 unsigned long *rmapp;
cd4a4e53
AK		 606 int i;
607
43a3795a 608 if (!is_rmap_spte(*spte))
cd4a4e53 609 return;
4db35314 610 sp = page_header(__pa(spte));
35149e21 611 pfn = spte_to_pfn(*spte);
7b52345e 612 if (*spte & shadow_accessed_mask)
35149e21 613 kvm_set_pfn_accessed(pfn);
8dae4445 614 if (is_writable_pte(*spte))
acb66dd0 615 kvm_set_pfn_dirty(pfn);
44ad9944 616 rmapp = gfn_to_rmap(kvm, sp->gfns[spte - sp->spt], sp->role.level);
290fc38d 617 if (!*rmapp) {
cd4a4e53
AK		 618 printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte);
619 BUG();
290fc38d 620 } else if (!(*rmapp & 1)) {
cd4a4e53 621 rmap_printk("rmap_remove: %p %llx 1->0\n", spte, *spte);
290fc38d 622 if ((u64 *)*rmapp != spte) {
cd4a4e53
AK		 623 printk(KERN_ERR "rmap_remove: %p %llx 1->BUG\n",
624 spte, *spte);
625 BUG();
626 }
290fc38d 627 *rmapp = 0;
cd4a4e53
AK		 628 } else {
629 rmap_printk("rmap_remove: %p %llx many->many\n", spte, *spte);
290fc38d 630 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
cd4a4e53
AK		 631 prev_desc = NULL;
632 while (desc) {
d555c333
AK		 633 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i)
634 if (desc->sptes[i] == spte) {
290fc38d 635 rmap_desc_remove_entry(rmapp,
714b93da 636 desc, i,
cd4a4e53
AK		 637 prev_desc);
638 return;
639 }
640 prev_desc = desc;
641 desc = desc->more;
642 }
186a3e52 643 pr_err("rmap_remove: %p %llx many->many\n", spte, *spte);
cd4a4e53
AK		 644 BUG();
645 }
646}
647
98348e95 648static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
374cbac0 649{
374cbac0 650 struct kvm_rmap_desc *desc;
98348e95
IE		 651 u64 *prev_spte;
652 int i;
653
654 if (!*rmapp)
655 return NULL;
656 else if (!(*rmapp & 1)) {
657 if (!spte)
658 return (u64 *)*rmapp;
659 return NULL;
660 }
661 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
98348e95
IE		 662 prev_spte = NULL;
663 while (desc) {
d555c333 664 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) {
98348e95 665 if (prev_spte == spte)
d555c333
AK		 666 return desc->sptes[i];
667 prev_spte = desc->sptes[i];
98348e95
IE		 668 }
669 desc = desc->more;
670 }
671 return NULL;
672}
673
b1a36821 674static int rmap_write_protect(struct kvm *kvm, u64 gfn)
98348e95 675{
290fc38d 676 unsigned long *rmapp;
374cbac0 677 u64 *spte;
44ad9944 678 int i, write_protected = 0;
374cbac0 679
4a4c9924 680 gfn = unalias_gfn(kvm, gfn);
44ad9944 681 rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
374cbac0 682
98348e95
IE		 683 spte = rmap_next(kvm, rmapp, NULL);
684 while (spte) {
374cbac0 685 BUG_ON(!spte);
374cbac0 686 BUG_ON(!(*spte & PT_PRESENT_MASK));
374cbac0 687 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
8dae4445 688 if (is_writable_pte(*spte)) {
d555c333 689 __set_spte(spte, *spte & ~PT_WRITABLE_MASK);
caa5b8a5
ED		 690 write_protected = 1;
691 }
9647c14c 692 spte = rmap_next(kvm, rmapp, spte);
374cbac0 693 }
855149aa 694 if (write_protected) {
35149e21 695 pfn_t pfn;
855149aa
IE		 696
697 spte = rmap_next(kvm, rmapp, NULL);
35149e21
AL		 698 pfn = spte_to_pfn(*spte);
699 kvm_set_pfn_dirty(pfn);
855149aa
IE		 700 }
701
05da4558 702 /* check for huge page mappings */
44ad9944
JR		 703 for (i = PT_DIRECTORY_LEVEL;
704 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
705 rmapp = gfn_to_rmap(kvm, gfn, i);
706 spte = rmap_next(kvm, rmapp, NULL);
707 while (spte) {
708 BUG_ON(!spte);
709 BUG_ON(!(*spte & PT_PRESENT_MASK));
710 BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
711 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
8dae4445 712 if (is_writable_pte(*spte)) {
44ad9944
JR		 713 rmap_remove(kvm, spte);
714 --kvm->stat.lpages;
715 __set_spte(spte, shadow_trap_nonpresent_pte);
716 spte = NULL;
717 write_protected = 1;
718 }
719 spte = rmap_next(kvm, rmapp, spte);
05da4558 720 }
05da4558
MT		 721 }
722
b1a36821 723 return write_protected;
374cbac0
AK		 724}
725
8a8365c5
FD		 726static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
727 unsigned long data)
e930bffe
AA		 728{
729 u64 *spte;
730 int need_tlb_flush = 0;
731
732 while ((spte = rmap_next(kvm, rmapp, NULL))) {
733 BUG_ON(!(*spte & PT_PRESENT_MASK));
734 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
735 rmap_remove(kvm, spte);
d555c333 736 __set_spte(spte, shadow_trap_nonpresent_pte);
e930bffe
AA		 737 need_tlb_flush = 1;
738 }
739 return need_tlb_flush;
740}
741
8a8365c5
FD		 742static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
743 unsigned long data)
3da0dd43
IE		 744{
745 int need_flush = 0;
746 u64 *spte, new_spte;
747 pte_t *ptep = (pte_t *)data;
748 pfn_t new_pfn;
749
750 WARN_ON(pte_huge(*ptep));
751 new_pfn = pte_pfn(*ptep);
752 spte = rmap_next(kvm, rmapp, NULL);
753 while (spte) {
754 BUG_ON(!is_shadow_present_pte(*spte));
755 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
756 need_flush = 1;
757 if (pte_write(*ptep)) {
758 rmap_remove(kvm, spte);
759 __set_spte(spte, shadow_trap_nonpresent_pte);
760 spte = rmap_next(kvm, rmapp, NULL);
761 } else {
762 new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
763 new_spte |= (u64)new_pfn << PAGE_SHIFT;
764
765 new_spte &= ~PT_WRITABLE_MASK;
766 new_spte &= ~SPTE_HOST_WRITEABLE;
8dae4445 767 if (is_writable_pte(*spte))
3da0dd43
IE		 768 kvm_set_pfn_dirty(spte_to_pfn(*spte));
769 __set_spte(spte, new_spte);
770 spte = rmap_next(kvm, rmapp, spte);
771 }
772 }
773 if (need_flush)
774 kvm_flush_remote_tlbs(kvm);
775
776 return 0;
777}
778
8a8365c5
FD		 779static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
780 unsigned long data,
3da0dd43 781 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
8a8365c5 782 unsigned long data))
e930bffe 783{
852e3c19 784 int i, j;
90bb6fc5 785 int ret;
e930bffe 786 int retval = 0;
bc6678a3
MT		 787 struct kvm_memslots *slots;
788
90d83dc3 789 slots = kvm_memslots(kvm);
e930bffe 790
46a26bf5
MT		 791 for (i = 0; i < slots->nmemslots; i++) {
792 struct kvm_memory_slot *memslot = &slots->memslots[i];
e930bffe
AA		 793 unsigned long start = memslot->userspace_addr;
794 unsigned long end;
795
e930bffe
AA		 796 end = start + (memslot->npages << PAGE_SHIFT);
797 if (hva >= start && hva < end) {
798 gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
852e3c19 799
90bb6fc5 800 ret = handler(kvm, &memslot->rmap[gfn_offset], data);
852e3c19
JR		 801
802 for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
803 int idx = gfn_offset;
804 idx /= KVM_PAGES_PER_HPAGE(PT_DIRECTORY_LEVEL + j);
90bb6fc5 805 ret |= handler(kvm,
3da0dd43
IE		 806 &memslot->lpage_info[j][idx].rmap_pde,
807 data);
852e3c19 808 }
90bb6fc5
AK		 809 trace_kvm_age_page(hva, memslot, ret);
810 retval |= ret;
e930bffe
AA		 811 }
812 }
813
814 return retval;
815}
816
817int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
818{
3da0dd43
IE		 819 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
820}
821
822void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
823{
8a8365c5 824 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
e930bffe
AA		 825}
826
8a8365c5
FD		 827static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
828 unsigned long data)
e930bffe
AA		 829{
830 u64 *spte;
831 int young = 0;
832
6316e1c8
RR		 833 /*
834 * Emulate the accessed bit for EPT, by checking if this page has
835 * an EPT mapping, and clearing it if it does. On the next access,
836 * a new EPT mapping will be established.
837 * This has some overhead, but not as much as the cost of swapping
838 * out actively used pages or breaking up actively used hugepages.
839 */
534e38b4 840 if (!shadow_accessed_mask)
6316e1c8 841 return kvm_unmap_rmapp(kvm, rmapp, data);
534e38b4 842
e930bffe
AA		 843 spte = rmap_next(kvm, rmapp, NULL);
844 while (spte) {
845 int _young;
846 u64 _spte = *spte;
847 BUG_ON(!(_spte & PT_PRESENT_MASK));
848 _young = _spte & PT_ACCESSED_MASK;
849 if (_young) {
850 young = 1;
851 clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
852 }
853 spte = rmap_next(kvm, rmapp, spte);
854 }
855 return young;
856}
857
53a27b39
MT		 858#define RMAP_RECYCLE_THRESHOLD 1000
859
852e3c19 860static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
53a27b39
MT		 861{
862 unsigned long *rmapp;
852e3c19
JR		 863 struct kvm_mmu_page *sp;
864
865 sp = page_header(__pa(spte));
53a27b39
MT		 866
867 gfn = unalias_gfn(vcpu->kvm, gfn);
852e3c19 868 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
53a27b39 869
3da0dd43 870 kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
53a27b39
MT		 871 kvm_flush_remote_tlbs(vcpu->kvm);
872}
873
e930bffe
AA		 874int kvm_age_hva(struct kvm *kvm, unsigned long hva)
875{
3da0dd43 876 return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
e930bffe
AA		 877}
878
d6c69ee9 879#ifdef MMU_DEBUG
47ad8e68 880static int is_empty_shadow_page(u64 *spt)
6aa8b732 881{
139bdb2d
AK		 882 u64 *pos;
883 u64 *end;
884
47ad8e68 885 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
3c915510 886 if (is_shadow_present_pte(*pos)) {
b8688d51 887 printk(KERN_ERR "%s: %p %llx\n", __func__,
139bdb2d 888 pos, *pos);
6aa8b732 889 return 0;
139bdb2d 890 }
6aa8b732
AK		 891 return 1;
892}
d6c69ee9 893#endif
6aa8b732 894
4db35314 895static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp)
260746c0 896{
4db35314
AK		 897 ASSERT(is_empty_shadow_page(sp->spt));
898 list_del(&sp->link);
899 __free_page(virt_to_page(sp->spt));
900 __free_page(virt_to_page(sp->gfns));
901 kfree(sp);
f05e70ac 902 ++kvm->arch.n_free_mmu_pages;
260746c0
AK		 903}
904
cea0f0e7
AK		 905static unsigned kvm_page_table_hashfn(gfn_t gfn)
906{
1ae0a13d 907 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
cea0f0e7
AK		 908}
909
25c0de2c
AK		 910static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
911 u64 *parent_pte)
6aa8b732 912{
4db35314 913 struct kvm_mmu_page *sp;
6aa8b732 914
ad312c7c
ZX		 915 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp);
916 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
917 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
4db35314 918 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
f05e70ac 919 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
291f26bc 920 bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
4db35314
AK		 921 sp->multimapped = 0;
922 sp->parent_pte = parent_pte;
f05e70ac 923 --vcpu->kvm->arch.n_free_mmu_pages;
4db35314 924 return sp;
6aa8b732
AK		 925}
926
714b93da 927static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
4db35314 928 struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7
AK		 929{
930 struct kvm_pte_chain *pte_chain;
931 struct hlist_node *node;
932 int i;
933
934 if (!parent_pte)
935 return;
4db35314
AK		 936 if (!sp->multimapped) {
937 u64 *old = sp->parent_pte;
cea0f0e7
AK		 938
939 if (!old) {
4db35314 940 sp->parent_pte = parent_pte;
cea0f0e7
AK		 941 return;
942 }
4db35314 943 sp->multimapped = 1;
714b93da 944 pte_chain = mmu_alloc_pte_chain(vcpu);
4db35314
AK		 945 INIT_HLIST_HEAD(&sp->parent_ptes);
946 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK		 947 pte_chain->parent_ptes[0] = old;
948 }
4db35314 949 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) {
cea0f0e7
AK		 950 if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1])
951 continue;
952 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i)
953 if (!pte_chain->parent_ptes[i]) {
954 pte_chain->parent_ptes[i] = parent_pte;
955 return;
956 }
957 }
714b93da 958 pte_chain = mmu_alloc_pte_chain(vcpu);
cea0f0e7 959 BUG_ON(!pte_chain);
4db35314 960 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK		 961 pte_chain->parent_ptes[0] = parent_pte;
962}
963
4db35314 964static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
cea0f0e7
AK		 965 u64 *parent_pte)
966{
967 struct kvm_pte_chain *pte_chain;
968 struct hlist_node *node;
969 int i;
970
4db35314
AK		 971 if (!sp->multimapped) {
972 BUG_ON(sp->parent_pte != parent_pte);
973 sp->parent_pte = NULL;
cea0f0e7
AK		 974 return;
975 }
4db35314 976 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
cea0f0e7
AK		 977 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
978 if (!pte_chain->parent_ptes[i])
979 break;
980 if (pte_chain->parent_ptes[i] != parent_pte)
981 continue;
697fe2e2
AK		 982 while (i + 1 < NR_PTE_CHAIN_ENTRIES
983 && pte_chain->parent_ptes[i + 1]) {
cea0f0e7
AK		 984 pte_chain->parent_ptes[i]
985 = pte_chain->parent_ptes[i + 1];
986 ++i;
987 }
988 pte_chain->parent_ptes[i] = NULL;
697fe2e2
AK		 989 if (i == 0) {
990 hlist_del(&pte_chain->link);
90cb0529 991 mmu_free_pte_chain(pte_chain);
4db35314
AK		 992 if (hlist_empty(&sp->parent_ptes)) {
993 sp->multimapped = 0;
994 sp->parent_pte = NULL;
697fe2e2
AK		 995 }
996 }
cea0f0e7
AK		 997 return;
998 }
999 BUG();
1000}
1001
ad8cfbe3 1002
6b18493d 1003static void mmu_parent_walk(struct kvm_mmu_page *sp, mmu_parent_walk_fn fn)
ad8cfbe3
MT		 1004{
1005 struct kvm_pte_chain *pte_chain;
1006 struct hlist_node *node;
1007 struct kvm_mmu_page *parent_sp;
1008 int i;
1009
1010 if (!sp->multimapped && sp->parent_pte) {
1011 parent_sp = page_header(__pa(sp->parent_pte));
6b18493d
XG		 1012 fn(parent_sp);
1013 mmu_parent_walk(parent_sp, fn);
ad8cfbe3
MT		 1014 return;
1015 }
1016 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1017 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1018 if (!pte_chain->parent_ptes[i])
1019 break;
1020 parent_sp = page_header(__pa(pte_chain->parent_ptes[i]));
6b18493d
XG		 1021 fn(parent_sp);
1022 mmu_parent_walk(parent_sp, fn);
ad8cfbe3
MT		 1023 }
1024}
1025
0074ff63
MT		 1026static void kvm_mmu_update_unsync_bitmap(u64 *spte)
1027{
1028 unsigned int index;
1029 struct kvm_mmu_page *sp = page_header(__pa(spte));
1030
1031 index = spte - sp->spt;
60c8aec6
MT		 1032 if (!__test_and_set_bit(index, sp->unsync_child_bitmap))
1033 sp->unsync_children++;
1034 WARN_ON(!sp->unsync_children);
0074ff63
MT		 1035}
1036
1037static void kvm_mmu_update_parents_unsync(struct kvm_mmu_page *sp)
1038{
1039 struct kvm_pte_chain *pte_chain;
1040 struct hlist_node *node;
1041 int i;
1042
1043 if (!sp->parent_pte)
1044 return;
1045
1046 if (!sp->multimapped) {
1047 kvm_mmu_update_unsync_bitmap(sp->parent_pte);
1048 return;
1049 }
1050
1051 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1052 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1053 if (!pte_chain->parent_ptes[i])
1054 break;
1055 kvm_mmu_update_unsync_bitmap(pte_chain->parent_ptes[i]);
1056 }
1057}
1058
6b18493d 1059static int unsync_walk_fn(struct kvm_mmu_page *sp)
0074ff63 1060{
0074ff63
MT		 1061 kvm_mmu_update_parents_unsync(sp);
1062 return 1;
1063}
1064
6b18493d 1065static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
0074ff63 1066{
6b18493d 1067 mmu_parent_walk(sp, unsync_walk_fn);
0074ff63
MT		 1068 kvm_mmu_update_parents_unsync(sp);
1069}
1070
d761a501
AK		 1071static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu,
1072 struct kvm_mmu_page *sp)
1073{
1074 int i;
1075
1076 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1077 sp->spt[i] = shadow_trap_nonpresent_pte;
1078}
1079
e8bc217a
MT		 1080static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1081 struct kvm_mmu_page *sp)
1082{
1083 return 1;
1084}
1085
a7052897
MT		 1086static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1087{
1088}
1089
60c8aec6
MT		 1090#define KVM_PAGE_ARRAY_NR 16
1091
1092struct kvm_mmu_pages {
1093 struct mmu_page_and_offset {
1094 struct kvm_mmu_page *sp;
1095 unsigned int idx;
1096 } page[KVM_PAGE_ARRAY_NR];
1097 unsigned int nr;
1098};
1099
0074ff63
MT		 1100#define for_each_unsync_children(bitmap, idx) \
1101 for (idx = find_first_bit(bitmap, 512); \
1102 idx < 512; \
1103 idx = find_next_bit(bitmap, 512, idx+1))
1104
cded19f3
HE		 1105static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1106 int idx)
4731d4c7 1107{
60c8aec6 1108 int i;
4731d4c7 1109
60c8aec6
MT		 1110 if (sp->unsync)
1111 for (i=0; i < pvec->nr; i++)
1112 if (pvec->page[i].sp == sp)
1113 return 0;
1114
1115 pvec->page[pvec->nr].sp = sp;
1116 pvec->page[pvec->nr].idx = idx;
1117 pvec->nr++;
1118 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1119}
1120
1121static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1122 struct kvm_mmu_pages *pvec)
1123{
1124 int i, ret, nr_unsync_leaf = 0;
4731d4c7 1125
0074ff63 1126 for_each_unsync_children(sp->unsync_child_bitmap, i) {
4731d4c7
MT		 1127 u64 ent = sp->spt[i];
1128
87917239 1129 if (is_shadow_present_pte(ent) && !is_large_pte(ent)) {
4731d4c7
MT		 1130 struct kvm_mmu_page *child;
1131 child = page_header(ent & PT64_BASE_ADDR_MASK);
1132
1133 if (child->unsync_children) {
60c8aec6
MT		 1134 if (mmu_pages_add(pvec, child, i))
1135 return -ENOSPC;
1136
1137 ret = __mmu_unsync_walk(child, pvec);
1138 if (!ret)
1139 __clear_bit(i, sp->unsync_child_bitmap);
1140 else if (ret > 0)
1141 nr_unsync_leaf += ret;
1142 else
4731d4c7
MT		 1143 return ret;
1144 }
1145
1146 if (child->unsync) {
60c8aec6
MT		 1147 nr_unsync_leaf++;
1148 if (mmu_pages_add(pvec, child, i))
1149 return -ENOSPC;
4731d4c7
MT		 1150 }
1151 }
1152 }
1153
0074ff63 1154 if (find_first_bit(sp->unsync_child_bitmap, 512) == 512)
4731d4c7
MT		 1155 sp->unsync_children = 0;
1156
60c8aec6
MT		 1157 return nr_unsync_leaf;
1158}
1159
1160static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1161 struct kvm_mmu_pages *pvec)
1162{
1163 if (!sp->unsync_children)
1164 return 0;
1165
1166 mmu_pages_add(pvec, sp, 0);
1167 return __mmu_unsync_walk(sp, pvec);
4731d4c7
MT		 1168}
1169
4db35314 1170static struct kvm_mmu_page *kvm_mmu_lookup_page(struct kvm *kvm, gfn_t gfn)
cea0f0e7
AK		 1171{
1172 unsigned index;
1173 struct hlist_head *bucket;
4db35314 1174 struct kvm_mmu_page *sp;
cea0f0e7
AK		 1175 struct hlist_node *node;
1176
b8688d51 1177 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
1ae0a13d 1178 index = kvm_page_table_hashfn(gfn);
f05e70ac 1179 bucket = &kvm->arch.mmu_page_hash[index];
4db35314 1180 hlist_for_each_entry(sp, node, bucket, hash_link)
f6e2c02b 1181 if (sp->gfn == gfn && !sp->role.direct
2e53d63a 1182 && !sp->role.invalid) {
cea0f0e7 1183 pgprintk("%s: found role %x\n",
b8688d51 1184 __func__, sp->role.word);
4db35314 1185 return sp;
cea0f0e7
AK		 1186 }
1187 return NULL;
1188}
1189
4731d4c7
MT		 1190static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1191{
1192 WARN_ON(!sp->unsync);
5e1b3ddb 1193 trace_kvm_mmu_sync_page(sp);
4731d4c7
MT		 1194 sp->unsync = 0;
1195 --kvm->stat.mmu_unsync;
1196}
1197
1198static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp);
1199
1200static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1201{
5b7e0102 1202 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
4731d4c7
MT		 1203 kvm_mmu_zap_page(vcpu->kvm, sp);
1204 return 1;
1205 }
1206
b1a36821
MT		 1207 if (rmap_write_protect(vcpu->kvm, sp->gfn))
1208 kvm_flush_remote_tlbs(vcpu->kvm);
0c0f40bd 1209 kvm_unlink_unsync_page(vcpu->kvm, sp);
4731d4c7
MT		 1210 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1211 kvm_mmu_zap_page(vcpu->kvm, sp);
1212 return 1;
1213 }
1214
1215 kvm_mmu_flush_tlb(vcpu);
4731d4c7
MT		 1216 return 0;
1217}
1218
60c8aec6
MT		 1219struct mmu_page_path {
1220 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1221 unsigned int idx[PT64_ROOT_LEVEL-1];
4731d4c7
MT		 1222};
1223
60c8aec6
MT		 1224#define for_each_sp(pvec, sp, parents, i) \
1225 for (i = mmu_pages_next(&pvec, &parents, -1), \
1226 sp = pvec.page[i].sp; \
1227 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1228 i = mmu_pages_next(&pvec, &parents, i))
1229
cded19f3
HE		 1230static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1231 struct mmu_page_path *parents,
1232 int i)
60c8aec6
MT		 1233{
1234 int n;
1235
1236 for (n = i+1; n < pvec->nr; n++) {
1237 struct kvm_mmu_page *sp = pvec->page[n].sp;
1238
1239 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1240 parents->idx[0] = pvec->page[n].idx;
1241 return n;
1242 }
1243
1244 parents->parent[sp->role.level-2] = sp;
1245 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1246 }
1247
1248 return n;
1249}
1250
cded19f3 1251static void mmu_pages_clear_parents(struct mmu_page_path *parents)
4731d4c7 1252{
60c8aec6
MT		 1253 struct kvm_mmu_page *sp;
1254 unsigned int level = 0;
1255
1256 do {
1257 unsigned int idx = parents->idx[level];
4731d4c7 1258
60c8aec6
MT		 1259 sp = parents->parent[level];
1260 if (!sp)
1261 return;
1262
1263 --sp->unsync_children;
1264 WARN_ON((int)sp->unsync_children < 0);
1265 __clear_bit(idx, sp->unsync_child_bitmap);
1266 level++;
1267 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
4731d4c7
MT		 1268}
1269
60c8aec6
MT		 1270static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1271 struct mmu_page_path *parents,
1272 struct kvm_mmu_pages *pvec)
4731d4c7 1273{
60c8aec6
MT		 1274 parents->parent[parent->role.level-1] = NULL;
1275 pvec->nr = 0;
1276}
4731d4c7 1277
60c8aec6
MT		 1278static void mmu_sync_children(struct kvm_vcpu *vcpu,
1279 struct kvm_mmu_page *parent)
1280{
1281 int i;
1282 struct kvm_mmu_page *sp;
1283 struct mmu_page_path parents;
1284 struct kvm_mmu_pages pages;
1285
1286 kvm_mmu_pages_init(parent, &parents, &pages);
1287 while (mmu_unsync_walk(parent, &pages)) {
b1a36821
MT		 1288 int protected = 0;
1289
1290 for_each_sp(pages, sp, parents, i)
1291 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1292
1293 if (protected)
1294 kvm_flush_remote_tlbs(vcpu->kvm);
1295
60c8aec6
MT		 1296 for_each_sp(pages, sp, parents, i) {
1297 kvm_sync_page(vcpu, sp);
1298 mmu_pages_clear_parents(&parents);
1299 }
4731d4c7 1300 cond_resched_lock(&vcpu->kvm->mmu_lock);
60c8aec6
MT		 1301 kvm_mmu_pages_init(parent, &parents, &pages);
1302 }
4731d4c7
MT		 1303}
1304
cea0f0e7
AK		 1305static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1306 gfn_t gfn,
1307 gva_t gaddr,
1308 unsigned level,
f6e2c02b 1309 int direct,
41074d07 1310 unsigned access,
f7d9c7b7 1311 u64 *parent_pte)
cea0f0e7
AK		 1312{
1313 union kvm_mmu_page_role role;
1314 unsigned index;
1315 unsigned quadrant;
1316 struct hlist_head *bucket;
4db35314 1317 struct kvm_mmu_page *sp;
4731d4c7 1318 struct hlist_node *node, *tmp;
cea0f0e7 1319
a770f6f2 1320 role = vcpu->arch.mmu.base_role;
cea0f0e7 1321 role.level = level;
f6e2c02b 1322 role.direct = direct;
84b0c8c6 1323 if (role.direct)
5b7e0102 1324 role.cr4_pae = 0;
41074d07 1325 role.access = access;
ad312c7c 1326 if (vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
cea0f0e7
AK		 1327 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1328 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1329 role.quadrant = quadrant;
1330 }
1ae0a13d 1331 index = kvm_page_table_hashfn(gfn);
f05e70ac 1332 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
4731d4c7
MT		 1333 hlist_for_each_entry_safe(sp, node, tmp, bucket, hash_link)
1334 if (sp->gfn == gfn) {
1335 if (sp->unsync)
1336 if (kvm_sync_page(vcpu, sp))
1337 continue;
1338
1339 if (sp->role.word != role.word)
1340 continue;
1341
4db35314 1342 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
0074ff63
MT		 1343 if (sp->unsync_children) {
1344 set_bit(KVM_REQ_MMU_SYNC, &vcpu->requests);
6b18493d 1345 kvm_mmu_mark_parents_unsync(sp);
0074ff63 1346 }
f691fe1d 1347 trace_kvm_mmu_get_page(sp, false);
4db35314 1348 return sp;
cea0f0e7 1349 }
dfc5aa00 1350 ++vcpu->kvm->stat.mmu_cache_miss;
4db35314
AK		 1351 sp = kvm_mmu_alloc_page(vcpu, parent_pte);
1352 if (!sp)
1353 return sp;
4db35314
AK		 1354 sp->gfn = gfn;
1355 sp->role = role;
1356 hlist_add_head(&sp->hash_link, bucket);
f6e2c02b 1357 if (!direct) {
b1a36821
MT		 1358 if (rmap_write_protect(vcpu->kvm, gfn))
1359 kvm_flush_remote_tlbs(vcpu->kvm);
4731d4c7
MT		 1360 account_shadowed(vcpu->kvm, gfn);
1361 }
131d8279
AK		 1362 if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte)
1363 vcpu->arch.mmu.prefetch_page(vcpu, sp);
1364 else
1365 nonpaging_prefetch_page(vcpu, sp);
f691fe1d 1366 trace_kvm_mmu_get_page(sp, true);
4db35314 1367 return sp;
cea0f0e7
AK		 1368}
1369
2d11123a
AK		 1370static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1371 struct kvm_vcpu *vcpu, u64 addr)
1372{
1373 iterator->addr = addr;
1374 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1375 iterator->level = vcpu->arch.mmu.shadow_root_level;
1376 if (iterator->level == PT32E_ROOT_LEVEL) {
1377 iterator->shadow_addr
1378 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1379 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1380 --iterator->level;
1381 if (!iterator->shadow_addr)
1382 iterator->level = 0;
1383 }
1384}
1385
1386static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1387{
1388 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1389 return false;
4d88954d
MT		 1390
1391 if (iterator->level == PT_PAGE_TABLE_LEVEL)
1392 if (is_large_pte(*iterator->sptep))
1393 return false;
1394
2d11123a
AK		 1395 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1396 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1397 return true;
1398}
1399
1400static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1401{
1402 iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK;
1403 --iterator->level;
1404}
1405
90cb0529 1406static void kvm_mmu_page_unlink_children(struct kvm *kvm,
4db35314 1407 struct kvm_mmu_page *sp)
a436036b 1408{
697fe2e2
AK		 1409 unsigned i;
1410 u64 *pt;
1411 u64 ent;
1412
4db35314 1413 pt = sp->spt;
697fe2e2 1414
697fe2e2
AK		 1415 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1416 ent = pt[i];
1417
05da4558 1418 if (is_shadow_present_pte(ent)) {
776e6633 1419 if (!is_last_spte(ent, sp->role.level)) {
05da4558
MT		 1420 ent &= PT64_BASE_ADDR_MASK;
1421 mmu_page_remove_parent_pte(page_header(ent),
1422 &pt[i]);
1423 } else {
776e6633
MT		 1424 if (is_large_pte(ent))
1425 --kvm->stat.lpages;
05da4558
MT		 1426 rmap_remove(kvm, &pt[i]);
1427 }
1428 }
c7addb90 1429 pt[i] = shadow_trap_nonpresent_pte;
697fe2e2 1430 }
a436036b
AK		 1431}
1432
4db35314 1433static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7 1434{
4db35314 1435 mmu_page_remove_parent_pte(sp, parent_pte);
a436036b
AK		 1436}
1437
12b7d28f
AK		 1438static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1439{
1440 int i;
988a2cae 1441 struct kvm_vcpu *vcpu;
12b7d28f 1442
988a2cae
GN		 1443 kvm_for_each_vcpu(i, vcpu, kvm)
1444 vcpu->arch.last_pte_updated = NULL;
12b7d28f
AK		 1445}
1446
31aa2b44 1447static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
a436036b
AK		 1448{
1449 u64 *parent_pte;
1450
4db35314
AK		 1451 while (sp->multimapped || sp->parent_pte) {
1452 if (!sp->multimapped)
1453 parent_pte = sp->parent_pte;
a436036b
AK		 1454 else {
1455 struct kvm_pte_chain *chain;
1456
4db35314 1457 chain = container_of(sp->parent_ptes.first,
a436036b
AK		 1458 struct kvm_pte_chain, link);
1459 parent_pte = chain->parent_ptes[0];
1460 }
697fe2e2 1461 BUG_ON(!parent_pte);
4db35314 1462 kvm_mmu_put_page(sp, parent_pte);
d555c333 1463 __set_spte(parent_pte, shadow_trap_nonpresent_pte);
a436036b 1464 }
31aa2b44
AK		 1465}
1466
60c8aec6
MT		 1467static int mmu_zap_unsync_children(struct kvm *kvm,
1468 struct kvm_mmu_page *parent)
4731d4c7 1469{
60c8aec6
MT		 1470 int i, zapped = 0;
1471 struct mmu_page_path parents;
1472 struct kvm_mmu_pages pages;
4731d4c7 1473
60c8aec6 1474 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
4731d4c7 1475 return 0;
60c8aec6
MT		 1476
1477 kvm_mmu_pages_init(parent, &parents, &pages);
1478 while (mmu_unsync_walk(parent, &pages)) {
1479 struct kvm_mmu_page *sp;
1480
1481 for_each_sp(pages, sp, parents, i) {
1482 kvm_mmu_zap_page(kvm, sp);
1483 mmu_pages_clear_parents(&parents);
77662e00 1484 zapped++;
60c8aec6 1485 }
60c8aec6
MT		 1486 kvm_mmu_pages_init(parent, &parents, &pages);
1487 }
1488
1489 return zapped;
4731d4c7
MT		 1490}
1491
07385413 1492static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp)
31aa2b44 1493{
4731d4c7 1494 int ret;
f691fe1d
AK		 1495
1496 trace_kvm_mmu_zap_page(sp);
31aa2b44 1497 ++kvm->stat.mmu_shadow_zapped;
4731d4c7 1498 ret = mmu_zap_unsync_children(kvm, sp);
4db35314 1499 kvm_mmu_page_unlink_children(kvm, sp);
31aa2b44 1500 kvm_mmu_unlink_parents(kvm, sp);
5b5c6a5a 1501 kvm_flush_remote_tlbs(kvm);
f6e2c02b 1502 if (!sp->role.invalid && !sp->role.direct)
5b5c6a5a 1503 unaccount_shadowed(kvm, sp->gfn);
4731d4c7
MT		 1504 if (sp->unsync)
1505 kvm_unlink_unsync_page(kvm, sp);
4db35314 1506 if (!sp->root_count) {
54a4f023
GJ		 1507 /* Count self */
1508 ret++;
4db35314
AK		 1509 hlist_del(&sp->hash_link);
1510 kvm_mmu_free_page(kvm, sp);
2e53d63a 1511 } else {
2e53d63a 1512 sp->role.invalid = 1;
5b5c6a5a 1513 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2e53d63a
MT		 1514 kvm_reload_remote_mmus(kvm);
1515 }
12b7d28f 1516 kvm_mmu_reset_last_pte_updated(kvm);
4731d4c7 1517 return ret;
a436036b
AK		 1518}
1519
82ce2c96
IE		 1520/*
1521 * Changing the number of mmu pages allocated to the vm
1522 * Note: if kvm_nr_mmu_pages is too small, you will get dead lock
1523 */
1524void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages)
1525{
025dbbf3
MT		 1526 int used_pages;
1527
1528 used_pages = kvm->arch.n_alloc_mmu_pages - kvm->arch.n_free_mmu_pages;
1529 used_pages = max(0, used_pages);
1530
82ce2c96
IE		 1531 /*
1532 * If we set the number of mmu pages to be smaller be than the
1533 * number of actived pages , we must to free some mmu pages before we
1534 * change the value
1535 */
1536
025dbbf3 1537 if (used_pages > kvm_nr_mmu_pages) {
77662e00
XG		 1538 while (used_pages > kvm_nr_mmu_pages &&
1539 !list_empty(&kvm->arch.active_mmu_pages)) {
82ce2c96
IE		 1540 struct kvm_mmu_page *page;
1541
f05e70ac 1542 page = container_of(kvm->arch.active_mmu_pages.prev,
82ce2c96 1543 struct kvm_mmu_page, link);
77662e00 1544 used_pages -= kvm_mmu_zap_page(kvm, page);
82ce2c96 1545 }
77662e00 1546 kvm_nr_mmu_pages = used_pages;
f05e70ac 1547 kvm->arch.n_free_mmu_pages = 0;
82ce2c96
IE		 1548 }
1549 else
f05e70ac
ZX		 1550 kvm->arch.n_free_mmu_pages += kvm_nr_mmu_pages
1551 - kvm->arch.n_alloc_mmu_pages;
82ce2c96 1552
f05e70ac 1553 kvm->arch.n_alloc_mmu_pages = kvm_nr_mmu_pages;
82ce2c96
IE		 1554}
1555
f67a46f4 1556static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
a436036b
AK		 1557{
1558 unsigned index;
1559 struct hlist_head *bucket;
4db35314 1560 struct kvm_mmu_page *sp;
a436036b
AK		 1561 struct hlist_node *node, *n;
1562 int r;
1563
b8688d51 1564 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
a436036b 1565 r = 0;
1ae0a13d 1566 index = kvm_page_table_hashfn(gfn);
f05e70ac 1567 bucket = &kvm->arch.mmu_page_hash[index];
3246af0e 1568restart:
4db35314 1569 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link)
f6e2c02b 1570 if (sp->gfn == gfn && !sp->role.direct) {
b8688d51 1571 pgprintk("%s: gfn %lx role %x\n", __func__, gfn,
4db35314 1572 sp->role.word);
a436036b 1573 r = 1;
07385413 1574 if (kvm_mmu_zap_page(kvm, sp))
3246af0e 1575 goto restart;
a436036b
AK		 1576 }
1577 return r;
cea0f0e7
AK		 1578}
1579
f67a46f4 1580static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
97a0a01e 1581{
4677a3b6
AK		 1582 unsigned index;
1583 struct hlist_head *bucket;
4db35314 1584 struct kvm_mmu_page *sp;
4677a3b6 1585 struct hlist_node *node, *nn;
97a0a01e 1586
4677a3b6
AK		 1587 index = kvm_page_table_hashfn(gfn);
1588 bucket = &kvm->arch.mmu_page_hash[index];
3246af0e 1589restart:
4677a3b6 1590 hlist_for_each_entry_safe(sp, node, nn, bucket, hash_link) {
f6e2c02b 1591 if (sp->gfn == gfn && !sp->role.direct
4677a3b6
AK		 1592 && !sp->role.invalid) {
1593 pgprintk("%s: zap %lx %x\n",
1594 __func__, gfn, sp->role.word);
77662e00 1595 if (kvm_mmu_zap_page(kvm, sp))
3246af0e 1596 goto restart;
4677a3b6 1597 }
97a0a01e
AK		 1598 }
1599}
1600
38c335f1 1601static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
6aa8b732 1602{
bc6678a3 1603 int slot = memslot_id(kvm, gfn);
4db35314 1604 struct kvm_mmu_page *sp = page_header(__pa(pte));
6aa8b732 1605
291f26bc 1606 __set_bit(slot, sp->slot_bitmap);
6aa8b732
AK		 1607}
1608
6844dec6
MT		 1609static void mmu_convert_notrap(struct kvm_mmu_page *sp)
1610{
1611 int i;
1612 u64 *pt = sp->spt;
1613
1614 if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte)
1615 return;
1616
1617 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1618 if (pt[i] == shadow_notrap_nonpresent_pte)
d555c333 1619 __set_spte(&pt[i], shadow_trap_nonpresent_pte);
6844dec6
MT		 1620 }
1621}
1622
74be52e3
SY		 1623/*
1624 * The function is based on mtrr_type_lookup() in
1625 * arch/x86/kernel/cpu/mtrr/generic.c
1626 */
1627static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
1628 u64 start, u64 end)
1629{
1630 int i;
1631 u64 base, mask;
1632 u8 prev_match, curr_match;
1633 int num_var_ranges = KVM_NR_VAR_MTRR;
1634
1635 if (!mtrr_state->enabled)
1636 return 0xFF;
1637
1638 /* Make end inclusive end, instead of exclusive */
1639 end--;
1640
1641 /* Look in fixed ranges. Just return the type as per start */
1642 if (mtrr_state->have_fixed && (start < 0x100000)) {
1643 int idx;
1644
1645 if (start < 0x80000) {
1646 idx = 0;
1647 idx += (start >> 16);
1648 return mtrr_state->fixed_ranges[idx];
1649 } else if (start < 0xC0000) {
1650 idx = 1 * 8;
1651 idx += ((start - 0x80000) >> 14);
1652 return mtrr_state->fixed_ranges[idx];
1653 } else if (start < 0x1000000) {
1654 idx = 3 * 8;
1655 idx += ((start - 0xC0000) >> 12);
1656 return mtrr_state->fixed_ranges[idx];
1657 }
1658 }
1659
1660 /*
1661 * Look in variable ranges
1662 * Look of multiple ranges matching this address and pick type
1663 * as per MTRR precedence
1664 */
1665 if (!(mtrr_state->enabled & 2))
1666 return mtrr_state->def_type;
1667
1668 prev_match = 0xFF;
1669 for (i = 0; i < num_var_ranges; ++i) {
1670 unsigned short start_state, end_state;
1671
1672 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
1673 continue;
1674
1675 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
1676 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
1677 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
1678 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
1679
1680 start_state = ((start & mask) == (base & mask));
1681 end_state = ((end & mask) == (base & mask));
1682 if (start_state != end_state)
1683 return 0xFE;
1684
1685 if ((start & mask) != (base & mask))
1686 continue;
1687
1688 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
1689 if (prev_match == 0xFF) {
1690 prev_match = curr_match;
1691 continue;
1692 }
1693
1694 if (prev_match == MTRR_TYPE_UNCACHABLE ||
1695 curr_match == MTRR_TYPE_UNCACHABLE)
1696 return MTRR_TYPE_UNCACHABLE;
1697
1698 if ((prev_match == MTRR_TYPE_WRBACK &&
1699 curr_match == MTRR_TYPE_WRTHROUGH) ||
1700 (prev_match == MTRR_TYPE_WRTHROUGH &&
1701 curr_match == MTRR_TYPE_WRBACK)) {
1702 prev_match = MTRR_TYPE_WRTHROUGH;
1703 curr_match = MTRR_TYPE_WRTHROUGH;
1704 }
1705
1706 if (prev_match != curr_match)
1707 return MTRR_TYPE_UNCACHABLE;
1708 }
1709
1710 if (prev_match != 0xFF)
1711 return prev_match;
1712
1713 return mtrr_state->def_type;
1714}
1715
4b12f0de 1716u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
74be52e3
SY		 1717{
1718 u8 mtrr;
1719
1720 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
1721 (gfn << PAGE_SHIFT) + PAGE_SIZE);
1722 if (mtrr == 0xfe || mtrr == 0xff)
1723 mtrr = MTRR_TYPE_WRBACK;
1724 return mtrr;
1725}
4b12f0de 1726EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
74be52e3 1727
4731d4c7
MT		 1728static int kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1729{
1730 unsigned index;
1731 struct hlist_head *bucket;
1732 struct kvm_mmu_page *s;
1733 struct hlist_node *node, *n;
1734
1735 index = kvm_page_table_hashfn(sp->gfn);
1736 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
1737 /* don't unsync if pagetable is shadowed with multiple roles */
1738 hlist_for_each_entry_safe(s, node, n, bucket, hash_link) {
f6e2c02b 1739 if (s->gfn != sp->gfn || s->role.direct)
4731d4c7
MT		 1740 continue;
1741 if (s->role.word != sp->role.word)
1742 return 1;
1743 }
5e1b3ddb 1744 trace_kvm_mmu_unsync_page(sp);
4731d4c7
MT		 1745 ++vcpu->kvm->stat.mmu_unsync;
1746 sp->unsync = 1;
6cffe8ca 1747
6b18493d 1748 kvm_mmu_mark_parents_unsync(sp);
6cffe8ca 1749
4731d4c7
MT		 1750 mmu_convert_notrap(sp);
1751 return 0;
1752}
1753
1754static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
1755 bool can_unsync)
1756{
1757 struct kvm_mmu_page *shadow;
1758
1759 shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
1760 if (shadow) {
1761 if (shadow->role.level != PT_PAGE_TABLE_LEVEL)
1762 return 1;
1763 if (shadow->unsync)
1764 return 0;
582801a9 1765 if (can_unsync && oos_shadow)
4731d4c7
MT		 1766 return kvm_unsync_page(vcpu, shadow);
1767 return 1;
1768 }
1769 return 0;
1770}
1771
d555c333 1772static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd 1773 unsigned pte_access, int user_fault,
852e3c19 1774 int write_fault, int dirty, int level,
c2d0ee46 1775 gfn_t gfn, pfn_t pfn, bool speculative,
1403283a 1776 bool can_unsync, bool reset_host_protection)
1c4f1fd6
AK		 1777{
1778 u64 spte;
1e73f9dd 1779 int ret = 0;
64d4d521 1780
1c4f1fd6
AK		 1781 /*
1782 * We don't set the accessed bit, since we sometimes want to see
1783 * whether the guest actually used the pte (in order to detect
1784 * demand paging).
1785 */
7b52345e 1786 spte = shadow_base_present_pte | shadow_dirty_mask;
947da538 1787 if (!speculative)
3201b5d9 1788 spte |= shadow_accessed_mask;
1c4f1fd6
AK		 1789 if (!dirty)
1790 pte_access &= ~ACC_WRITE_MASK;
7b52345e
SY		 1791 if (pte_access & ACC_EXEC_MASK)
1792 spte |= shadow_x_mask;
1793 else
1794 spte |= shadow_nx_mask;
1c4f1fd6 1795 if (pte_access & ACC_USER_MASK)
7b52345e 1796 spte |= shadow_user_mask;
852e3c19 1797 if (level > PT_PAGE_TABLE_LEVEL)
05da4558 1798 spte |= PT_PAGE_SIZE_MASK;
4b12f0de
SY		 1799 if (tdp_enabled)
1800 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
1801 kvm_is_mmio_pfn(pfn));
1c4f1fd6 1802
1403283a
IE		 1803 if (reset_host_protection)
1804 spte |= SPTE_HOST_WRITEABLE;
1805
35149e21 1806 spte |= (u64)pfn << PAGE_SHIFT;
1c4f1fd6
AK		 1807
1808 if ((pte_access & ACC_WRITE_MASK)
1809 || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
1c4f1fd6 1810
852e3c19
JR		 1811 if (level > PT_PAGE_TABLE_LEVEL &&
1812 has_wrprotected_page(vcpu->kvm, gfn, level)) {
38187c83
MT		 1813 ret = 1;
1814 spte = shadow_trap_nonpresent_pte;
1815 goto set_pte;
1816 }
1817
1c4f1fd6 1818 spte |= PT_WRITABLE_MASK;
1c4f1fd6 1819
69325a12
AK		 1820 if (!tdp_enabled && !(pte_access & ACC_WRITE_MASK))
1821 spte &= ~PT_USER_MASK;
1822
ecc5589f
MT		 1823 /*
1824 * Optimization: for pte sync, if spte was writable the hash
1825 * lookup is unnecessary (and expensive). Write protection
1826 * is responsibility of mmu_get_page / kvm_sync_page.
1827 * Same reasoning can be applied to dirty page accounting.
1828 */
8dae4445 1829 if (!can_unsync && is_writable_pte(*sptep))
ecc5589f
MT		 1830 goto set_pte;
1831
4731d4c7 1832 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
1c4f1fd6 1833 pgprintk("%s: found shadow page for %lx, marking ro\n",
b8688d51 1834 __func__, gfn);
1e73f9dd 1835 ret = 1;
1c4f1fd6 1836 pte_access &= ~ACC_WRITE_MASK;
8dae4445 1837 if (is_writable_pte(spte))
1c4f1fd6 1838 spte &= ~PT_WRITABLE_MASK;
1c4f1fd6
AK		 1839 }
1840 }
1841
1c4f1fd6
AK		 1842 if (pte_access & ACC_WRITE_MASK)
1843 mark_page_dirty(vcpu->kvm, gfn);
1844
38187c83 1845set_pte:
d555c333 1846 __set_spte(sptep, spte);
1e73f9dd
MT		 1847 return ret;
1848}
1849
d555c333 1850static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd
MT		 1851 unsigned pt_access, unsigned pte_access,
1852 int user_fault, int write_fault, int dirty,
852e3c19 1853 int *ptwrite, int level, gfn_t gfn,
1403283a
IE		 1854 pfn_t pfn, bool speculative,
1855 bool reset_host_protection)
1e73f9dd
MT		 1856{
1857 int was_rmapped = 0;
8dae4445 1858 int was_writable = is_writable_pte(*sptep);
53a27b39 1859 int rmap_count;
1e73f9dd
MT		 1860
1861 pgprintk("%s: spte %llx access %x write_fault %d"
1862 " user_fault %d gfn %lx\n",
d555c333 1863 __func__, *sptep, pt_access,
1e73f9dd
MT		 1864 write_fault, user_fault, gfn);
1865
d555c333 1866 if (is_rmap_spte(*sptep)) {
1e73f9dd
MT		 1867 /*
1868 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
1869 * the parent of the now unreachable PTE.
1870 */
852e3c19
JR		 1871 if (level > PT_PAGE_TABLE_LEVEL &&
1872 !is_large_pte(*sptep)) {
1e73f9dd 1873 struct kvm_mmu_page *child;
d555c333 1874 u64 pte = *sptep;
1e73f9dd
MT		 1875
1876 child = page_header(pte & PT64_BASE_ADDR_MASK);
d555c333 1877 mmu_page_remove_parent_pte(child, sptep);
3be2264b
MT		 1878 __set_spte(sptep, shadow_trap_nonpresent_pte);
1879 kvm_flush_remote_tlbs(vcpu->kvm);
d555c333 1880 } else if (pfn != spte_to_pfn(*sptep)) {
1e73f9dd 1881 pgprintk("hfn old %lx new %lx\n",
d555c333
AK		 1882 spte_to_pfn(*sptep), pfn);
1883 rmap_remove(vcpu->kvm, sptep);
91546356
XG		 1884 __set_spte(sptep, shadow_trap_nonpresent_pte);
1885 kvm_flush_remote_tlbs(vcpu->kvm);
6bed6b9e
JR		 1886 } else
1887 was_rmapped = 1;
1e73f9dd 1888 }
852e3c19 1889
d555c333 1890 if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
1403283a
IE		 1891 dirty, level, gfn, pfn, speculative, true,
1892 reset_host_protection)) {
1e73f9dd
MT		 1893 if (write_fault)
1894 *ptwrite = 1;
a378b4e6
MT		 1895 kvm_x86_ops->tlb_flush(vcpu);
1896 }
1e73f9dd 1897
d555c333 1898 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
1e73f9dd 1899 pgprintk("instantiating %s PTE (%s) at %ld (%llx) addr %p\n",
d555c333 1900 is_large_pte(*sptep)? "2MB" : "4kB",
a205bc19
JR		 1901 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
1902 *sptep, sptep);
d555c333 1903 if (!was_rmapped && is_large_pte(*sptep))
05da4558
MT		 1904 ++vcpu->kvm->stat.lpages;
1905
d555c333 1906 page_header_update_slot(vcpu->kvm, sptep, gfn);
1c4f1fd6 1907 if (!was_rmapped) {
44ad9944 1908 rmap_count = rmap_add(vcpu, sptep, gfn);
acb66dd0 1909 kvm_release_pfn_clean(pfn);
53a27b39 1910 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
852e3c19 1911 rmap_recycle(vcpu, sptep, gfn);
75e68e60 1912 } else {
8dae4445 1913 if (was_writable)
35149e21 1914 kvm_release_pfn_dirty(pfn);
75e68e60 1915 else
35149e21 1916 kvm_release_pfn_clean(pfn);
1c4f1fd6 1917 }
1b7fcd32 1918 if (speculative) {
d555c333 1919 vcpu->arch.last_pte_updated = sptep;
1b7fcd32
AK		 1920 vcpu->arch.last_pte_gfn = gfn;
1921 }
1c4f1fd6
AK		 1922}
1923
6aa8b732
AK		 1924static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
1925{
1926}
1927
9f652d21 1928static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
852e3c19 1929 int level, gfn_t gfn, pfn_t pfn)
140754bc 1930{
9f652d21 1931 struct kvm_shadow_walk_iterator iterator;
140754bc 1932 struct kvm_mmu_page *sp;
9f652d21 1933 int pt_write = 0;
140754bc 1934 gfn_t pseudo_gfn;
6aa8b732 1935
9f652d21 1936 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
852e3c19 1937 if (iterator.level == level) {
9f652d21
AK		 1938 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL,
1939 0, write, 1, &pt_write,
1403283a 1940 level, gfn, pfn, false, true);
9f652d21
AK		 1941 ++vcpu->stat.pf_fixed;
1942 break;
6aa8b732
AK		 1943 }
1944
9f652d21
AK		 1945 if (*iterator.sptep == shadow_trap_nonpresent_pte) {
1946 pseudo_gfn = (iterator.addr & PT64_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
1947 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
1948 iterator.level - 1,
1949 1, ACC_ALL, iterator.sptep);
1950 if (!sp) {
1951 pgprintk("nonpaging_map: ENOMEM\n");
1952 kvm_release_pfn_clean(pfn);
1953 return -ENOMEM;
1954 }
140754bc 1955
d555c333
AK		 1956 __set_spte(iterator.sptep,
1957 __pa(sp->spt)
1958 | PT_PRESENT_MASK | PT_WRITABLE_MASK
1959 | shadow_user_mask | shadow_x_mask);
9f652d21
AK		 1960 }
1961 }
1962 return pt_write;
6aa8b732
AK		 1963}
1964
bf998156
HY		 1965static void kvm_send_hwpoison_signal(struct kvm *kvm, gfn_t gfn)
1966{
1967 char buf[1];
1968 void __user *hva;
1969 int r;
1970
1971 /* Touch the page, so send SIGBUS */
1972 hva = (void __user *)gfn_to_hva(kvm, gfn);
1973 r = copy_from_user(buf, hva, 1);
1974}
1975
1976static int kvm_handle_bad_page(struct kvm *kvm, gfn_t gfn, pfn_t pfn)
1977{
1978 kvm_release_pfn_clean(pfn);
1979 if (is_hwpoison_pfn(pfn)) {
1980 kvm_send_hwpoison_signal(kvm, gfn);
1981 return 0;
1982 }
1983 return 1;
1984}
1985
10589a46
MT		 1986static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
1987{
1988 int r;
852e3c19 1989 int level;
35149e21 1990 pfn_t pfn;
e930bffe 1991 unsigned long mmu_seq;
aaee2c94 1992
852e3c19
JR		 1993 level = mapping_level(vcpu, gfn);
1994
1995 /*
1996 * This path builds a PAE pagetable - so we can map 2mb pages at
1997 * maximum. Therefore check if the level is larger than that.
1998 */
1999 if (level > PT_DIRECTORY_LEVEL)
2000 level = PT_DIRECTORY_LEVEL;
2001
2002 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
05da4558 2003
e930bffe 2004 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2005 smp_rmb();
35149e21 2006 pfn = gfn_to_pfn(vcpu->kvm, gfn);
aaee2c94 2007
d196e343 2008 /* mmio */
bf998156
HY		 2009 if (is_error_pfn(pfn))
2010 return kvm_handle_bad_page(vcpu->kvm, gfn, pfn);
d196e343 2011
aaee2c94 2012 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2013 if (mmu_notifier_retry(vcpu, mmu_seq))
2014 goto out_unlock;
eb787d10 2015 kvm_mmu_free_some_pages(vcpu);
852e3c19 2016 r = __direct_map(vcpu, v, write, level, gfn, pfn);
aaee2c94
MT		 2017 spin_unlock(&vcpu->kvm->mmu_lock);
2018
aaee2c94 2019
10589a46 2020 return r;
e930bffe
AA		 2021
2022out_unlock:
2023 spin_unlock(&vcpu->kvm->mmu_lock);
2024 kvm_release_pfn_clean(pfn);
2025 return 0;
10589a46
MT		 2026}
2027
2028
17ac10ad
AK		 2029static void mmu_free_roots(struct kvm_vcpu *vcpu)
2030{
2031 int i;
4db35314 2032 struct kvm_mmu_page *sp;
17ac10ad 2033
ad312c7c 2034 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
7b53aa56 2035 return;
aaee2c94 2036 spin_lock(&vcpu->kvm->mmu_lock);
ad312c7c
ZX		 2037 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2038 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad 2039
4db35314
AK		 2040 sp = page_header(root);
2041 --sp->root_count;
2e53d63a
MT		 2042 if (!sp->root_count && sp->role.invalid)
2043 kvm_mmu_zap_page(vcpu->kvm, sp);
ad312c7c 2044 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
aaee2c94 2045 spin_unlock(&vcpu->kvm->mmu_lock);
17ac10ad
AK		 2046 return;
2047 }
17ac10ad 2048 for (i = 0; i < 4; ++i) {
ad312c7c 2049 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad 2050
417726a3 2051 if (root) {
417726a3 2052 root &= PT64_BASE_ADDR_MASK;
4db35314
AK		 2053 sp = page_header(root);
2054 --sp->root_count;
2e53d63a
MT		 2055 if (!sp->root_count && sp->role.invalid)
2056 kvm_mmu_zap_page(vcpu->kvm, sp);
417726a3 2057 }
ad312c7c 2058 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2059 }
aaee2c94 2060 spin_unlock(&vcpu->kvm->mmu_lock);
ad312c7c 2061 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
17ac10ad
AK		 2062}
2063
8986ecc0
MT		 2064static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2065{
2066 int ret = 0;
2067
2068 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2069 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2070 ret = 1;
2071 }
2072
2073 return ret;
2074}
2075
2076static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
17ac10ad
AK		 2077{
2078 int i;
cea0f0e7 2079 gfn_t root_gfn;
4db35314 2080 struct kvm_mmu_page *sp;
f6e2c02b 2081 int direct = 0;
6de4f3ad 2082 u64 pdptr;
3bb65a22 2083
ad312c7c 2084 root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT;
17ac10ad 2085
ad312c7c
ZX		 2086 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2087 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad
AK		 2088
2089 ASSERT(!VALID_PAGE(root));
8986ecc0
MT		 2090 if (mmu_check_root(vcpu, root_gfn))
2091 return 1;
5a7388c2
EN		 2092 if (tdp_enabled) {
2093 direct = 1;
2094 root_gfn = 0;
2095 }
8facbbff 2096 spin_lock(&vcpu->kvm->mmu_lock);
4db35314 2097 sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
f6e2c02b 2098 PT64_ROOT_LEVEL, direct,
fb72d167 2099 ACC_ALL, NULL);
4db35314
AK		 2100 root = __pa(sp->spt);
2101 ++sp->root_count;
8facbbff 2102 spin_unlock(&vcpu->kvm->mmu_lock);
ad312c7c 2103 vcpu->arch.mmu.root_hpa = root;
8986ecc0 2104 return 0;
17ac10ad 2105 }
f6e2c02b 2106 direct = !is_paging(vcpu);
17ac10ad 2107 for (i = 0; i < 4; ++i) {
ad312c7c 2108 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad
AK		 2109
2110 ASSERT(!VALID_PAGE(root));
ad312c7c 2111 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
6de4f3ad 2112 pdptr = kvm_pdptr_read(vcpu, i);
43a3795a 2113 if (!is_present_gpte(pdptr)) {
ad312c7c 2114 vcpu->arch.mmu.pae_root[i] = 0;
417726a3
AK		 2115 continue;
2116 }
6de4f3ad 2117 root_gfn = pdptr >> PAGE_SHIFT;
ad312c7c 2118 } else if (vcpu->arch.mmu.root_level == 0)
cea0f0e7 2119 root_gfn = 0;
8986ecc0
MT		 2120 if (mmu_check_root(vcpu, root_gfn))
2121 return 1;
5a7388c2
EN		 2122 if (tdp_enabled) {
2123 direct = 1;
2124 root_gfn = i << 30;
2125 }
8facbbff 2126 spin_lock(&vcpu->kvm->mmu_lock);
4db35314 2127 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
f6e2c02b 2128 PT32_ROOT_LEVEL, direct,
f7d9c7b7 2129 ACC_ALL, NULL);
4db35314
AK		 2130 root = __pa(sp->spt);
2131 ++sp->root_count;
8facbbff
AK		 2132 spin_unlock(&vcpu->kvm->mmu_lock);
2133
ad312c7c 2134 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
17ac10ad 2135 }
ad312c7c 2136 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
8986ecc0 2137 return 0;
17ac10ad
AK		 2138}
2139
0ba73cda
MT		 2140static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2141{
2142 int i;
2143 struct kvm_mmu_page *sp;
2144
2145 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2146 return;
2147 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2148 hpa_t root = vcpu->arch.mmu.root_hpa;
2149 sp = page_header(root);
2150 mmu_sync_children(vcpu, sp);
2151 return;
2152 }
2153 for (i = 0; i < 4; ++i) {
2154 hpa_t root = vcpu->arch.mmu.pae_root[i];
2155
8986ecc0 2156 if (root && VALID_PAGE(root)) {
0ba73cda
MT		 2157 root &= PT64_BASE_ADDR_MASK;
2158 sp = page_header(root);
2159 mmu_sync_children(vcpu, sp);
2160 }
2161 }
2162}
2163
2164void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2165{
2166 spin_lock(&vcpu->kvm->mmu_lock);
2167 mmu_sync_roots(vcpu);
6cffe8ca 2168 spin_unlock(&vcpu->kvm->mmu_lock);
0ba73cda
MT		 2169}
2170
1871c602
GN		 2171static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
2172 u32 access, u32 *error)
6aa8b732 2173{
1871c602
GN		 2174 if (error)
2175 *error = 0;
6aa8b732
AK		 2176 return vaddr;
2177}
2178
2179static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3f3e7124 2180 u32 error_code)
6aa8b732 2181{
e833240f 2182 gfn_t gfn;
e2dec939 2183 int r;
6aa8b732 2184
b8688d51 2185 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
e2dec939
AK		 2186 r = mmu_topup_memory_caches(vcpu);
2187 if (r)
2188 return r;
714b93da 2189
6aa8b732 2190 ASSERT(vcpu);
ad312c7c 2191 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2192
e833240f 2193 gfn = gva >> PAGE_SHIFT;
6aa8b732 2194
e833240f
AK		 2195 return nonpaging_map(vcpu, gva & PAGE_MASK,
2196 error_code & PFERR_WRITE_MASK, gfn);
6aa8b732
AK		 2197}
2198
fb72d167
JR		 2199static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa,
2200 u32 error_code)
2201{
35149e21 2202 pfn_t pfn;
fb72d167 2203 int r;
852e3c19 2204 int level;
05da4558 2205 gfn_t gfn = gpa >> PAGE_SHIFT;
e930bffe 2206 unsigned long mmu_seq;
fb72d167
JR		 2207
2208 ASSERT(vcpu);
2209 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2210
2211 r = mmu_topup_memory_caches(vcpu);
2212 if (r)
2213 return r;
2214
852e3c19
JR		 2215 level = mapping_level(vcpu, gfn);
2216
2217 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2218
e930bffe 2219 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2220 smp_rmb();
35149e21 2221 pfn = gfn_to_pfn(vcpu->kvm, gfn);
bf998156
HY		 2222 if (is_error_pfn(pfn))
2223 return kvm_handle_bad_page(vcpu->kvm, gfn, pfn);
fb72d167 2224 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2225 if (mmu_notifier_retry(vcpu, mmu_seq))
2226 goto out_unlock;
fb72d167
JR		 2227 kvm_mmu_free_some_pages(vcpu);
2228 r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK,
852e3c19 2229 level, gfn, pfn);
fb72d167 2230 spin_unlock(&vcpu->kvm->mmu_lock);
fb72d167
JR		 2231
2232 return r;
e930bffe
AA		 2233
2234out_unlock:
2235 spin_unlock(&vcpu->kvm->mmu_lock);
2236 kvm_release_pfn_clean(pfn);
2237 return 0;
fb72d167
JR		 2238}
2239
6aa8b732
AK		 2240static void nonpaging_free(struct kvm_vcpu *vcpu)
2241{
17ac10ad 2242 mmu_free_roots(vcpu);
6aa8b732
AK		 2243}
2244
2245static int nonpaging_init_context(struct kvm_vcpu *vcpu)
2246{
ad312c7c 2247 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK		 2248
2249 context->new_cr3 = nonpaging_new_cr3;
2250 context->page_fault = nonpaging_page_fault;
6aa8b732
AK		 2251 context->gva_to_gpa = nonpaging_gva_to_gpa;
2252 context->free = nonpaging_free;
c7addb90 2253 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2254 context->sync_page = nonpaging_sync_page;
a7052897 2255 context->invlpg = nonpaging_invlpg;
cea0f0e7 2256 context->root_level = 0;
6aa8b732 2257 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2258 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2259 return 0;
2260}
2261
d835dfec 2262void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
6aa8b732 2263{
1165f5fe 2264 ++vcpu->stat.tlb_flush;
cbdd1bea 2265 kvm_x86_ops->tlb_flush(vcpu);
6aa8b732
AK		 2266}
2267
2268static void paging_new_cr3(struct kvm_vcpu *vcpu)
2269{
b8688d51 2270 pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3);
cea0f0e7 2271 mmu_free_roots(vcpu);
6aa8b732
AK		 2272}
2273
6aa8b732
AK		 2274static void inject_page_fault(struct kvm_vcpu *vcpu,
2275 u64 addr,
2276 u32 err_code)
2277{
c3c91fee 2278 kvm_inject_page_fault(vcpu, addr, err_code);
6aa8b732
AK		 2279}
2280
6aa8b732
AK		 2281static void paging_free(struct kvm_vcpu *vcpu)
2282{
2283 nonpaging_free(vcpu);
2284}
2285
82725b20
DE		 2286static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level)
2287{
2288 int bit7;
2289
2290 bit7 = (gpte >> 7) & 1;
2291 return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1]) != 0;
2292}
2293
6aa8b732
AK		 2294#define PTTYPE 64
2295#include "paging_tmpl.h"
2296#undef PTTYPE
2297
2298#define PTTYPE 32
2299#include "paging_tmpl.h"
2300#undef PTTYPE
2301
82725b20
DE		 2302static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level)
2303{
2304 struct kvm_mmu *context = &vcpu->arch.mmu;
2305 int maxphyaddr = cpuid_maxphyaddr(vcpu);
2306 u64 exb_bit_rsvd = 0;
2307
2308 if (!is_nx(vcpu))
2309 exb_bit_rsvd = rsvd_bits(63, 63);
2310 switch (level) {
2311 case PT32_ROOT_LEVEL:
2312 /* no rsvd bits for 2 level 4K page table entries */
2313 context->rsvd_bits_mask[0][1] = 0;
2314 context->rsvd_bits_mask[0][0] = 0;
f815bce8
XG		 2315 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
2316
2317 if (!is_pse(vcpu)) {
2318 context->rsvd_bits_mask[1][1] = 0;
2319 break;
2320 }
2321
82725b20
DE		 2322 if (is_cpuid_PSE36())
2323 /* 36bits PSE 4MB page */
2324 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
2325 else
2326 /* 32 bits PSE 4MB page */
2327 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
82725b20
DE		 2328 break;
2329 case PT32E_ROOT_LEVEL:
20c466b5
DE		 2330 context->rsvd_bits_mask[0][2] =
2331 rsvd_bits(maxphyaddr, 63) |
2332 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
82725b20 2333 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2334 rsvd_bits(maxphyaddr, 62); /* PDE */
82725b20
DE		 2335 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2336 rsvd_bits(maxphyaddr, 62); /* PTE */
2337 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2338 rsvd_bits(maxphyaddr, 62) |
2339 rsvd_bits(13, 20); /* large page */
f815bce8 2340 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
82725b20
DE		 2341 break;
2342 case PT64_ROOT_LEVEL:
2343 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
2344 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2345 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
2346 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2347 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2348 rsvd_bits(maxphyaddr, 51);
82725b20
DE		 2349 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2350 rsvd_bits(maxphyaddr, 51);
2351 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
e04da980
JR		 2352 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
2353 rsvd_bits(maxphyaddr, 51) |
2354 rsvd_bits(13, 29);
82725b20 2355 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4c26b4cd
SY		 2356 rsvd_bits(maxphyaddr, 51) |
2357 rsvd_bits(13, 20); /* large page */
f815bce8 2358 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
82725b20
DE		 2359 break;
2360 }
2361}
2362
17ac10ad 2363static int paging64_init_context_common(struct kvm_vcpu *vcpu, int level)
6aa8b732 2364{
ad312c7c 2365 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK		 2366
2367 ASSERT(is_pae(vcpu));
2368 context->new_cr3 = paging_new_cr3;
2369 context->page_fault = paging64_page_fault;
6aa8b732 2370 context->gva_to_gpa = paging64_gva_to_gpa;
c7addb90 2371 context->prefetch_page = paging64_prefetch_page;
e8bc217a 2372 context->sync_page = paging64_sync_page;
a7052897 2373 context->invlpg = paging64_invlpg;
6aa8b732 2374 context->free = paging_free;
17ac10ad
AK		 2375 context->root_level = level;
2376 context->shadow_root_level = level;
17c3ba9d 2377 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2378 return 0;
2379}
2380
17ac10ad
AK		 2381static int paging64_init_context(struct kvm_vcpu *vcpu)
2382{
82725b20 2383 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
17ac10ad
AK		 2384 return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL);
2385}
2386
6aa8b732
AK		 2387static int paging32_init_context(struct kvm_vcpu *vcpu)
2388{
ad312c7c 2389 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732 2390
82725b20 2391 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
6aa8b732
AK		 2392 context->new_cr3 = paging_new_cr3;
2393 context->page_fault = paging32_page_fault;
6aa8b732
AK		 2394 context->gva_to_gpa = paging32_gva_to_gpa;
2395 context->free = paging_free;
c7addb90 2396 context->prefetch_page = paging32_prefetch_page;
e8bc217a 2397 context->sync_page = paging32_sync_page;
a7052897 2398 context->invlpg = paging32_invlpg;
6aa8b732
AK		 2399 context->root_level = PT32_ROOT_LEVEL;
2400 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2401 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2402 return 0;
2403}
2404
2405static int paging32E_init_context(struct kvm_vcpu *vcpu)
2406{
82725b20 2407 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
17ac10ad 2408 return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL);
6aa8b732
AK		 2409}
2410
fb72d167
JR		 2411static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
2412{
2413 struct kvm_mmu *context = &vcpu->arch.mmu;
2414
2415 context->new_cr3 = nonpaging_new_cr3;
2416 context->page_fault = tdp_page_fault;
2417 context->free = nonpaging_free;
2418 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2419 context->sync_page = nonpaging_sync_page;
a7052897 2420 context->invlpg = nonpaging_invlpg;
67253af5 2421 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
fb72d167
JR		 2422 context->root_hpa = INVALID_PAGE;
2423
2424 if (!is_paging(vcpu)) {
2425 context->gva_to_gpa = nonpaging_gva_to_gpa;
2426 context->root_level = 0;
2427 } else if (is_long_mode(vcpu)) {
82725b20 2428 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
fb72d167
JR		 2429 context->gva_to_gpa = paging64_gva_to_gpa;
2430 context->root_level = PT64_ROOT_LEVEL;
2431 } else if (is_pae(vcpu)) {
82725b20 2432 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
fb72d167
JR		 2433 context->gva_to_gpa = paging64_gva_to_gpa;
2434 context->root_level = PT32E_ROOT_LEVEL;
2435 } else {
82725b20 2436 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
fb72d167
JR		 2437 context->gva_to_gpa = paging32_gva_to_gpa;
2438 context->root_level = PT32_ROOT_LEVEL;
2439 }
2440
2441 return 0;
2442}
2443
2444static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
6aa8b732 2445{
a770f6f2
AK		 2446 int r;
2447
6aa8b732 2448 ASSERT(vcpu);
ad312c7c 2449 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732
AK		 2450
2451 if (!is_paging(vcpu))
a770f6f2 2452 r = nonpaging_init_context(vcpu);
a9058ecd 2453 else if (is_long_mode(vcpu))
a770f6f2 2454 r = paging64_init_context(vcpu);
6aa8b732 2455 else if (is_pae(vcpu))
a770f6f2 2456 r = paging32E_init_context(vcpu);
6aa8b732 2457 else
a770f6f2
AK		 2458 r = paging32_init_context(vcpu);
2459
5b7e0102 2460 vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3dbe1415 2461 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
a770f6f2
AK		 2462
2463 return r;
6aa8b732
AK		 2464}
2465
fb72d167
JR		 2466static int init_kvm_mmu(struct kvm_vcpu *vcpu)
2467{
35149e21
AL		 2468 vcpu->arch.update_pte.pfn = bad_pfn;
2469
fb72d167
JR		 2470 if (tdp_enabled)
2471 return init_kvm_tdp_mmu(vcpu);
2472 else
2473 return init_kvm_softmmu(vcpu);
2474}
2475
6aa8b732
AK		 2476static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
2477{
2478 ASSERT(vcpu);
ad312c7c
ZX		 2479 if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) {
2480 vcpu->arch.mmu.free(vcpu);
2481 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
6aa8b732
AK		 2482 }
2483}
2484
2485int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
17c3ba9d
AK		 2486{
2487 destroy_kvm_mmu(vcpu);
2488 return init_kvm_mmu(vcpu);
2489}
8668a3c4 2490EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
17c3ba9d
AK		 2491
2492int kvm_mmu_load(struct kvm_vcpu *vcpu)
6aa8b732 2493{
714b93da
AK		 2494 int r;
2495
e2dec939 2496 r = mmu_topup_memory_caches(vcpu);
17c3ba9d
AK		 2497 if (r)
2498 goto out;
aaee2c94 2499 spin_lock(&vcpu->kvm->mmu_lock);
eb787d10 2500 kvm_mmu_free_some_pages(vcpu);
8facbbff 2501 spin_unlock(&vcpu->kvm->mmu_lock);
8986ecc0 2502 r = mmu_alloc_roots(vcpu);
8facbbff 2503 spin_lock(&vcpu->kvm->mmu_lock);
0ba73cda 2504 mmu_sync_roots(vcpu);
aaee2c94 2505 spin_unlock(&vcpu->kvm->mmu_lock);
8986ecc0
MT		 2506 if (r)
2507 goto out;
3662cb1c 2508 /* set_cr3() should ensure TLB has been flushed */
ad312c7c 2509 kvm_x86_ops->set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
714b93da
AK		 2510out:
2511 return r;
6aa8b732 2512}
17c3ba9d
AK		 2513EXPORT_SYMBOL_GPL(kvm_mmu_load);
2514
2515void kvm_mmu_unload(struct kvm_vcpu *vcpu)
2516{
2517 mmu_free_roots(vcpu);
2518}
6aa8b732 2519
09072daf 2520static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu,
4db35314 2521 struct kvm_mmu_page *sp,
ac1b714e
AK		 2522 u64 *spte)
2523{
2524 u64 pte;
2525 struct kvm_mmu_page *child;
2526
2527 pte = *spte;
c7addb90 2528 if (is_shadow_present_pte(pte)) {
776e6633 2529 if (is_last_spte(pte, sp->role.level))
290fc38d 2530 rmap_remove(vcpu->kvm, spte);
ac1b714e
AK		 2531 else {
2532 child = page_header(pte & PT64_BASE_ADDR_MASK);
90cb0529 2533 mmu_page_remove_parent_pte(child, spte);
ac1b714e
AK		 2534 }
2535 }
d555c333 2536 __set_spte(spte, shadow_trap_nonpresent_pte);
05da4558
MT		 2537 if (is_large_pte(pte))
2538 --vcpu->kvm->stat.lpages;
ac1b714e
AK		 2539}
2540
0028425f 2541static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4db35314 2542 struct kvm_mmu_page *sp,
0028425f 2543 u64 *spte,
489f1d65 2544 const void *new)
0028425f 2545{
30945387 2546 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
7e4e4056
JR		 2547 ++vcpu->kvm->stat.mmu_pde_zapped;
2548 return;
30945387 2549 }
0028425f 2550
4cee5764 2551 ++vcpu->kvm->stat.mmu_pte_updated;
5b7e0102 2552 if (!sp->role.cr4_pae)
489f1d65 2553 paging32_update_pte(vcpu, sp, spte, new);
0028425f 2554 else
489f1d65 2555 paging64_update_pte(vcpu, sp, spte, new);
0028425f
AK		 2556}
2557
79539cec
AK		 2558static bool need_remote_flush(u64 old, u64 new)
2559{
2560 if (!is_shadow_present_pte(old))
2561 return false;
2562 if (!is_shadow_present_pte(new))
2563 return true;
2564 if ((old ^ new) & PT64_BASE_ADDR_MASK)
2565 return true;
2566 old ^= PT64_NX_MASK;
2567 new ^= PT64_NX_MASK;
2568 return (old & ~new & PT64_PERM_MASK) != 0;
2569}
2570
2571static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, u64 old, u64 new)
2572{
2573 if (need_remote_flush(old, new))
2574 kvm_flush_remote_tlbs(vcpu->kvm);
2575 else
2576 kvm_mmu_flush_tlb(vcpu);
2577}
2578
12b7d28f
AK		 2579static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
2580{
ad312c7c 2581 u64 *spte = vcpu->arch.last_pte_updated;
12b7d28f 2582
7b52345e 2583 return !!(spte && (*spte & shadow_accessed_mask));
12b7d28f
AK		 2584}
2585
d7824fff 2586static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
72016f3a 2587 u64 gpte)
d7824fff
AK		 2588{
2589 gfn_t gfn;
35149e21 2590 pfn_t pfn;
d7824fff 2591
43a3795a 2592 if (!is_present_gpte(gpte))
d7824fff
AK		 2593 return;
2594 gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
72dc67a6 2595
e930bffe 2596 vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2597 smp_rmb();
35149e21 2598 pfn = gfn_to_pfn(vcpu->kvm, gfn);
72dc67a6 2599
35149e21
AL		 2600 if (is_error_pfn(pfn)) {
2601 kvm_release_pfn_clean(pfn);
d196e343
AK		 2602 return;
2603 }
d7824fff 2604 vcpu->arch.update_pte.gfn = gfn;
35149e21 2605 vcpu->arch.update_pte.pfn = pfn;
d7824fff
AK		 2606}
2607
1b7fcd32
AK		 2608static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
2609{
2610 u64 *spte = vcpu->arch.last_pte_updated;
2611
2612 if (spte
2613 && vcpu->arch.last_pte_gfn == gfn
2614 && shadow_accessed_mask
2615 && !(*spte & shadow_accessed_mask)
2616 && is_shadow_present_pte(*spte))
2617 set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
2618}
2619
09072daf 2620void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
ad218f85
MT		 2621 const u8 *new, int bytes,
2622 bool guest_initiated)
da4a00f0 2623{
9b7a0325 2624 gfn_t gfn = gpa >> PAGE_SHIFT;
4db35314 2625 struct kvm_mmu_page *sp;
0e7bc4b9 2626 struct hlist_node *node, *n;
9b7a0325
AK		 2627 struct hlist_head *bucket;
2628 unsigned index;
489f1d65 2629 u64 entry, gentry;
9b7a0325 2630 u64 *spte;
9b7a0325 2631 unsigned offset = offset_in_page(gpa);
0e7bc4b9 2632 unsigned pte_size;
9b7a0325 2633 unsigned page_offset;
0e7bc4b9 2634 unsigned misaligned;
fce0657f 2635 unsigned quadrant;
9b7a0325 2636 int level;
86a5ba02 2637 int flooded = 0;
ac1b714e 2638 int npte;
489f1d65 2639 int r;
08e850c6 2640 int invlpg_counter;
9b7a0325 2641
b8688d51 2642 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
72016f3a 2643
08e850c6 2644 invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter);
72016f3a
AK		 2645
2646 /*
2647 * Assume that the pte write on a page table of the same type
2648 * as the current vcpu paging mode. This is nearly always true
2649 * (might be false while changing modes). Note it is verified later
2650 * by update_pte().
2651 */
08e850c6 2652 if ((is_pae(vcpu) && bytes == 4) || !new) {
72016f3a 2653 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
08e850c6
AK		 2654 if (is_pae(vcpu)) {
2655 gpa &= ~(gpa_t)7;
2656 bytes = 8;
2657 }
2658 r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8));
72016f3a
AK		 2659 if (r)
2660 gentry = 0;
08e850c6
AK		 2661 new = (const u8 *)&gentry;
2662 }
2663
2664 switch (bytes) {
2665 case 4:
2666 gentry = *(const u32 *)new;
2667 break;
2668 case 8:
2669 gentry = *(const u64 *)new;
2670 break;
2671 default:
2672 gentry = 0;
2673 break;
72016f3a
AK		 2674 }
2675
2676 mmu_guess_page_from_pte_write(vcpu, gpa, gentry);
aaee2c94 2677 spin_lock(&vcpu->kvm->mmu_lock);
08e850c6
AK		 2678 if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter)
2679 gentry = 0;
1b7fcd32 2680 kvm_mmu_access_page(vcpu, gfn);
eb787d10 2681 kvm_mmu_free_some_pages(vcpu);
4cee5764 2682 ++vcpu->kvm->stat.mmu_pte_write;
c7addb90 2683 kvm_mmu_audit(vcpu, "pre pte write");
ad218f85
MT		 2684 if (guest_initiated) {
2685 if (gfn == vcpu->arch.last_pt_write_gfn
2686 && !last_updated_pte_accessed(vcpu)) {
2687 ++vcpu->arch.last_pt_write_count;
2688 if (vcpu->arch.last_pt_write_count >= 3)
2689 flooded = 1;
2690 } else {
2691 vcpu->arch.last_pt_write_gfn = gfn;
2692 vcpu->arch.last_pt_write_count = 1;
2693 vcpu->arch.last_pte_updated = NULL;
2694 }
86a5ba02 2695 }
1ae0a13d 2696 index = kvm_page_table_hashfn(gfn);
f05e70ac 2697 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
3246af0e
XG		 2698
2699restart:
4db35314 2700 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link) {
f6e2c02b 2701 if (sp->gfn != gfn || sp->role.direct || sp->role.invalid)
9b7a0325 2702 continue;
5b7e0102 2703 pte_size = sp->role.cr4_pae ? 8 : 4;
0e7bc4b9 2704 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
e925c5ba 2705 misaligned |= bytes < 4;
86a5ba02 2706 if (misaligned || flooded) {
0e7bc4b9
AK		 2707 /*
2708 * Misaligned accesses are too much trouble to fix
2709 * up; also, they usually indicate a page is not used
2710 * as a page table.
86a5ba02
AK		 2711 *
2712 * If we're seeing too many writes to a page,
2713 * it may no longer be a page table, or we may be
2714 * forking, in which case it is better to unmap the
2715 * page.
0e7bc4b9
AK		 2716 */
2717 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4db35314 2718 gpa, bytes, sp->role.word);
07385413 2719 if (kvm_mmu_zap_page(vcpu->kvm, sp))
3246af0e 2720 goto restart;
4cee5764 2721 ++vcpu->kvm->stat.mmu_flooded;
0e7bc4b9
AK		 2722 continue;
2723 }
9b7a0325 2724 page_offset = offset;
4db35314 2725 level = sp->role.level;
ac1b714e 2726 npte = 1;
5b7e0102 2727 if (!sp->role.cr4_pae) {
ac1b714e
AK		 2728 page_offset <<= 1; /* 32->64 */
2729 /*
2730 * A 32-bit pde maps 4MB while the shadow pdes map
2731 * only 2MB. So we need to double the offset again
2732 * and zap two pdes instead of one.
2733 */
2734 if (level == PT32_ROOT_LEVEL) {
6b8d0f9b 2735 page_offset &= ~7; /* kill rounding error */
ac1b714e
AK		 2736 page_offset <<= 1;
2737 npte = 2;
2738 }
fce0657f 2739 quadrant = page_offset >> PAGE_SHIFT;
9b7a0325 2740 page_offset &= ~PAGE_MASK;
4db35314 2741 if (quadrant != sp->role.quadrant)
fce0657f 2742 continue;
9b7a0325 2743 }
4db35314 2744 spte = &sp->spt[page_offset / sizeof(*spte)];
ac1b714e 2745 while (npte--) {
79539cec 2746 entry = *spte;
4db35314 2747 mmu_pte_write_zap_pte(vcpu, sp, spte);
72016f3a
AK		 2748 if (gentry)
2749 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
79539cec 2750 mmu_pte_write_flush_tlb(vcpu, entry, *spte);
ac1b714e 2751 ++spte;
9b7a0325 2752 }
9b7a0325 2753 }
c7addb90 2754 kvm_mmu_audit(vcpu, "post pte write");
aaee2c94 2755 spin_unlock(&vcpu->kvm->mmu_lock);
35149e21
AL		 2756 if (!is_error_pfn(vcpu->arch.update_pte.pfn)) {
2757 kvm_release_pfn_clean(vcpu->arch.update_pte.pfn);
2758 vcpu->arch.update_pte.pfn = bad_pfn;
d7824fff 2759 }
da4a00f0
AK		 2760}
2761
a436036b
AK		 2762int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2763{
10589a46
MT		 2764 gpa_t gpa;
2765 int r;
a436036b 2766
60f24784
AK		 2767 if (tdp_enabled)
2768 return 0;
2769
1871c602 2770 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
10589a46 2771
aaee2c94 2772 spin_lock(&vcpu->kvm->mmu_lock);
10589a46 2773 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
aaee2c94 2774 spin_unlock(&vcpu->kvm->mmu_lock);
10589a46 2775 return r;
a436036b 2776}
577bdc49 2777EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
a436036b 2778
22d95b12 2779void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
ebeace86 2780{
3b80fffe
IE		 2781 while (vcpu->kvm->arch.n_free_mmu_pages < KVM_REFILL_PAGES &&
2782 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
4db35314 2783 struct kvm_mmu_page *sp;
ebeace86 2784
f05e70ac 2785 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
4db35314
AK		 2786 struct kvm_mmu_page, link);
2787 kvm_mmu_zap_page(vcpu->kvm, sp);
4cee5764 2788 ++vcpu->kvm->stat.mmu_recycled;
ebeace86
AK		 2789 }
2790}
ebeace86 2791
3067714c
AK		 2792int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code)
2793{
2794 int r;
2795 enum emulation_result er;
2796
ad312c7c 2797 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code);
3067714c
AK		 2798 if (r < 0)
2799 goto out;
2800
2801 if (!r) {
2802 r = 1;
2803 goto out;
2804 }
2805
b733bfb5
AK		 2806 r = mmu_topup_memory_caches(vcpu);
2807 if (r)
2808 goto out;
2809
851ba692 2810 er = emulate_instruction(vcpu, cr2, error_code, 0);
3067714c
AK		 2811
2812 switch (er) {
2813 case EMULATE_DONE:
2814 return 1;
2815 case EMULATE_DO_MMIO:
2816 ++vcpu->stat.mmio_exits;
2817 return 0;
2818 case EMULATE_FAIL:
3f5d18a9
AK		 2819 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2820 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
a9c7399d 2821 vcpu->run->internal.ndata = 0;
3f5d18a9 2822 return 0;
3067714c
AK		 2823 default:
2824 BUG();
2825 }
2826out:
3067714c
AK		 2827 return r;
2828}
2829EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
2830
a7052897
MT		 2831void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
2832{
a7052897 2833 vcpu->arch.mmu.invlpg(vcpu, gva);
a7052897
MT		 2834 kvm_mmu_flush_tlb(vcpu);
2835 ++vcpu->stat.invlpg;
2836}
2837EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
2838
18552672
JR		 2839void kvm_enable_tdp(void)
2840{
2841 tdp_enabled = true;
2842}
2843EXPORT_SYMBOL_GPL(kvm_enable_tdp);
2844
5f4cb662
JR		 2845void kvm_disable_tdp(void)
2846{
2847 tdp_enabled = false;
2848}
2849EXPORT_SYMBOL_GPL(kvm_disable_tdp);
2850
6aa8b732
AK		 2851static void free_mmu_pages(struct kvm_vcpu *vcpu)
2852{
ad312c7c 2853 free_page((unsigned long)vcpu->arch.mmu.pae_root);
6aa8b732
AK		 2854}
2855
2856static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
2857{
17ac10ad 2858 struct page *page;
6aa8b732
AK		 2859 int i;
2860
2861 ASSERT(vcpu);
2862
17ac10ad
AK		 2863 /*
2864 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
2865 * Therefore we need to allocate shadow page tables in the first
2866 * 4GB of memory, which happens to fit the DMA32 zone.
2867 */
2868 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
2869 if (!page)
d7fa6ab2
WY		 2870 return -ENOMEM;
2871
ad312c7c 2872 vcpu->arch.mmu.pae_root = page_address(page);
17ac10ad 2873 for (i = 0; i < 4; ++i)
ad312c7c 2874 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2875
6aa8b732 2876 return 0;
6aa8b732
AK		 2877}
2878
8018c27b 2879int kvm_mmu_create(struct kvm_vcpu *vcpu)
6aa8b732 2880{
6aa8b732 2881 ASSERT(vcpu);
ad312c7c 2882 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2883
8018c27b
IM		 2884 return alloc_mmu_pages(vcpu);
2885}
6aa8b732 2886
8018c27b
IM		 2887int kvm_mmu_setup(struct kvm_vcpu *vcpu)
2888{
2889 ASSERT(vcpu);
ad312c7c 2890 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2c264957 2891
8018c27b 2892 return init_kvm_mmu(vcpu);
6aa8b732
AK		 2893}
2894
2895void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
2896{
2897 ASSERT(vcpu);
2898
2899 destroy_kvm_mmu(vcpu);
2900 free_mmu_pages(vcpu);
714b93da 2901 mmu_free_memory_caches(vcpu);
6aa8b732
AK		 2902}
2903
90cb0529 2904void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
6aa8b732 2905{
4db35314 2906 struct kvm_mmu_page *sp;
6aa8b732 2907
f05e70ac 2908 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
6aa8b732
AK		 2909 int i;
2910 u64 *pt;
2911
291f26bc 2912 if (!test_bit(slot, sp->slot_bitmap))
6aa8b732
AK		 2913 continue;
2914
4db35314 2915 pt = sp->spt;
6aa8b732
AK		 2916 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2917 /* avoid RMW */
9647c14c 2918 if (pt[i] & PT_WRITABLE_MASK)
6aa8b732 2919 pt[i] &= ~PT_WRITABLE_MASK;
6aa8b732 2920 }
171d595d 2921 kvm_flush_remote_tlbs(kvm);
6aa8b732 2922}
37a7d8b0 2923
90cb0529 2924void kvm_mmu_zap_all(struct kvm *kvm)
e0fa826f 2925{
4db35314 2926 struct kvm_mmu_page *sp, *node;
e0fa826f 2927
aaee2c94 2928 spin_lock(&kvm->mmu_lock);
3246af0e 2929restart:
f05e70ac 2930 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
07385413 2931 if (kvm_mmu_zap_page(kvm, sp))
3246af0e
XG		 2932 goto restart;
2933
aaee2c94 2934 spin_unlock(&kvm->mmu_lock);
e0fa826f 2935
90cb0529 2936 kvm_flush_remote_tlbs(kvm);
e0fa826f
DL		 2937}
2938
d35b8dd9 2939static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm)
3ee16c81
IE		 2940{
2941 struct kvm_mmu_page *page;
2942
2943 page = container_of(kvm->arch.active_mmu_pages.prev,
2944 struct kvm_mmu_page, link);
54a4f023 2945 return kvm_mmu_zap_page(kvm, page);
3ee16c81
IE		 2946}
2947
7f8275d0 2948static int mmu_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
3ee16c81
IE		 2949{
2950 struct kvm *kvm;
2951 struct kvm *kvm_freed = NULL;
2952 int cache_count = 0;
2953
2954 spin_lock(&kvm_lock);
2955
2956 list_for_each_entry(kvm, &vm_list, vm_list) {
d35b8dd9 2957 int npages, idx, freed_pages;
3ee16c81 2958
f656ce01 2959 idx = srcu_read_lock(&kvm->srcu);
3ee16c81
IE		 2960 spin_lock(&kvm->mmu_lock);
2961 npages = kvm->arch.n_alloc_mmu_pages -
2962 kvm->arch.n_free_mmu_pages;
2963 cache_count += npages;
2964 if (!kvm_freed && nr_to_scan > 0 && npages > 0) {
d35b8dd9
GJ		 2965 freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm);
2966 cache_count -= freed_pages;
3ee16c81
IE		 2967 kvm_freed = kvm;
2968 }
2969 nr_to_scan--;
2970
2971 spin_unlock(&kvm->mmu_lock);
f656ce01 2972 srcu_read_unlock(&kvm->srcu, idx);
3ee16c81
IE		 2973 }
2974 if (kvm_freed)
2975 list_move_tail(&kvm_freed->vm_list, &vm_list);
2976
2977 spin_unlock(&kvm_lock);
2978
2979 return cache_count;
2980}
2981
2982static struct shrinker mmu_shrinker = {
2983 .shrink = mmu_shrink,
2984 .seeks = DEFAULT_SEEKS * 10,
2985};
2986
2ddfd20e 2987static void mmu_destroy_caches(void)
b5a33a75
AK		 2988{
2989 if (pte_chain_cache)
2990 kmem_cache_destroy(pte_chain_cache);
2991 if (rmap_desc_cache)
2992 kmem_cache_destroy(rmap_desc_cache);
d3d25b04
AK		 2993 if (mmu_page_header_cache)
2994 kmem_cache_destroy(mmu_page_header_cache);
b5a33a75
AK		 2995}
2996
3ee16c81
IE		 2997void kvm_mmu_module_exit(void)
2998{
2999 mmu_destroy_caches();
3000 unregister_shrinker(&mmu_shrinker);
3001}
3002
b5a33a75
AK		 3003int kvm_mmu_module_init(void)
3004{
3005 pte_chain_cache = kmem_cache_create("kvm_pte_chain",
3006 sizeof(struct kvm_pte_chain),
20c2df83 3007 0, 0, NULL);
b5a33a75
AK		 3008 if (!pte_chain_cache)
3009 goto nomem;
3010 rmap_desc_cache = kmem_cache_create("kvm_rmap_desc",
3011 sizeof(struct kvm_rmap_desc),
20c2df83 3012 0, 0, NULL);
b5a33a75
AK		 3013 if (!rmap_desc_cache)
3014 goto nomem;
3015
d3d25b04
AK		 3016 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
3017 sizeof(struct kvm_mmu_page),
20c2df83 3018 0, 0, NULL);
d3d25b04
AK		 3019 if (!mmu_page_header_cache)
3020 goto nomem;
3021
3ee16c81
IE		 3022 register_shrinker(&mmu_shrinker);
3023
b5a33a75
AK		 3024 return 0;
3025
3026nomem:
3ee16c81 3027 mmu_destroy_caches();
b5a33a75
AK		 3028 return -ENOMEM;
3029}
3030
3ad82a7e
ZX		 3031/*
3032 * Caculate mmu pages needed for kvm.
3033 */
3034unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3035{
3036 int i;
3037 unsigned int nr_mmu_pages;
3038 unsigned int nr_pages = 0;
bc6678a3 3039 struct kvm_memslots *slots;
3ad82a7e 3040
90d83dc3
LJ		 3041 slots = kvm_memslots(kvm);
3042
bc6678a3
MT		 3043 for (i = 0; i < slots->nmemslots; i++)
3044 nr_pages += slots->memslots[i].npages;
3ad82a7e
ZX		 3045
3046 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3047 nr_mmu_pages = max(nr_mmu_pages,
3048 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
3049
3050 return nr_mmu_pages;
3051}
3052
2f333bcb
MT		 3053static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3054 unsigned len)
3055{
3056 if (len > buffer->len)
3057 return NULL;
3058 return buffer->ptr;
3059}
3060
3061static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3062 unsigned len)
3063{
3064 void *ret;
3065
3066 ret = pv_mmu_peek_buffer(buffer, len);
3067 if (!ret)
3068 return ret;
3069 buffer->ptr += len;
3070 buffer->len -= len;
3071 buffer->processed += len;
3072 return ret;
3073}
3074
3075static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
3076 gpa_t addr, gpa_t value)
3077{
3078 int bytes = 8;
3079 int r;
3080
3081 if (!is_long_mode(vcpu) && !is_pae(vcpu))
3082 bytes = 4;
3083
3084 r = mmu_topup_memory_caches(vcpu);
3085 if (r)
3086 return r;
3087
3200f405 3088 if (!emulator_write_phys(vcpu, addr, &value, bytes))
2f333bcb
MT		 3089 return -EFAULT;
3090
3091 return 1;
3092}
3093
3094static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3095{
a8cd0244 3096 kvm_set_cr3(vcpu, vcpu->arch.cr3);
2f333bcb
MT		 3097 return 1;
3098}
3099
3100static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
3101{
3102 spin_lock(&vcpu->kvm->mmu_lock);
3103 mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
3104 spin_unlock(&vcpu->kvm->mmu_lock);
3105 return 1;
3106}
3107
3108static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
3109 struct kvm_pv_mmu_op_buffer *buffer)
3110{
3111 struct kvm_mmu_op_header *header;
3112
3113 header = pv_mmu_peek_buffer(buffer, sizeof *header);
3114 if (!header)
3115 return 0;
3116 switch (header->op) {
3117 case KVM_MMU_OP_WRITE_PTE: {
3118 struct kvm_mmu_op_write_pte *wpte;
3119
3120 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
3121 if (!wpte)
3122 return 0;
3123 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
3124 wpte->pte_val);
3125 }
3126 case KVM_MMU_OP_FLUSH_TLB: {
3127 struct kvm_mmu_op_flush_tlb *ftlb;
3128
3129 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
3130 if (!ftlb)
3131 return 0;
3132 return kvm_pv_mmu_flush_tlb(vcpu);
3133 }
3134 case KVM_MMU_OP_RELEASE_PT: {
3135 struct kvm_mmu_op_release_pt *rpt;
3136
3137 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
3138 if (!rpt)
3139 return 0;
3140 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
3141 }
3142 default: return 0;
3143 }
3144}
3145
3146int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
3147 gpa_t addr, unsigned long *ret)
3148{
3149 int r;
6ad18fba 3150 struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
2f333bcb 3151
6ad18fba
DH		 3152 buffer->ptr = buffer->buf;
3153 buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
3154 buffer->processed = 0;
2f333bcb 3155
6ad18fba 3156 r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
2f333bcb
MT		 3157 if (r)
3158 goto out;
3159
6ad18fba
DH		 3160 while (buffer->len) {
3161 r = kvm_pv_mmu_op_one(vcpu, buffer);
2f333bcb
MT		 3162 if (r < 0)
3163 goto out;
3164 if (r == 0)
3165 break;
3166 }
3167
3168 r = 1;
3169out:
6ad18fba 3170 *ret = buffer->processed;
2f333bcb
MT		 3171 return r;
3172}
3173
94d8b056
MT		 3174int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
3175{
3176 struct kvm_shadow_walk_iterator iterator;
3177 int nr_sptes = 0;
3178
3179 spin_lock(&vcpu->kvm->mmu_lock);
3180 for_each_shadow_entry(vcpu, addr, iterator) {
3181 sptes[iterator.level-1] = *iterator.sptep;
3182 nr_sptes++;
3183 if (!is_shadow_present_pte(*iterator.sptep))
3184 break;
3185 }
3186 spin_unlock(&vcpu->kvm->mmu_lock);
3187
3188 return nr_sptes;
3189}
3190EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
3191
37a7d8b0
AK		 3192#ifdef AUDIT
3193
3194static const char *audit_msg;
3195
3196static gva_t canonicalize(gva_t gva)
3197{
3198#ifdef CONFIG_X86_64
3199 gva = (long long)(gva << 16) >> 16;
3200#endif
3201 return gva;
3202}
3203
08a3732b 3204
805d32de 3205typedef void (*inspect_spte_fn) (struct kvm *kvm, u64 *sptep);
08a3732b
MT		 3206
3207static void __mmu_spte_walk(struct kvm *kvm, struct kvm_mmu_page *sp,
3208 inspect_spte_fn fn)
3209{
3210 int i;
3211
3212 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3213 u64 ent = sp->spt[i];
3214
3215 if (is_shadow_present_pte(ent)) {
2920d728 3216 if (!is_last_spte(ent, sp->role.level)) {
08a3732b
MT		 3217 struct kvm_mmu_page *child;
3218 child = page_header(ent & PT64_BASE_ADDR_MASK);
3219 __mmu_spte_walk(kvm, child, fn);
2920d728 3220 } else
805d32de 3221 fn(kvm, &sp->spt[i]);
08a3732b
MT		 3222 }
3223 }
3224}
3225
3226static void mmu_spte_walk(struct kvm_vcpu *vcpu, inspect_spte_fn fn)
3227{
3228 int i;
3229 struct kvm_mmu_page *sp;
3230
3231 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3232 return;
3233 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3234 hpa_t root = vcpu->arch.mmu.root_hpa;
3235 sp = page_header(root);
3236 __mmu_spte_walk(vcpu->kvm, sp, fn);
3237 return;
3238 }
3239 for (i = 0; i < 4; ++i) {
3240 hpa_t root = vcpu->arch.mmu.pae_root[i];
3241
3242 if (root && VALID_PAGE(root)) {
3243 root &= PT64_BASE_ADDR_MASK;
3244 sp = page_header(root);
3245 __mmu_spte_walk(vcpu->kvm, sp, fn);
3246 }
3247 }
3248 return;
3249}
3250
37a7d8b0
AK		 3251static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte,
3252 gva_t va, int level)
3253{
3254 u64 *pt = __va(page_pte & PT64_BASE_ADDR_MASK);
3255 int i;
3256 gva_t va_delta = 1ul << (PAGE_SHIFT + 9 * (level - 1));
3257
3258 for (i = 0; i < PT64_ENT_PER_PAGE; ++i, va += va_delta) {
3259 u64 ent = pt[i];
3260
c7addb90 3261 if (ent == shadow_trap_nonpresent_pte)
37a7d8b0
AK		 3262 continue;
3263
3264 va = canonicalize(va);
2920d728
MT		 3265 if (is_shadow_present_pte(ent) && !is_last_spte(ent, level))
3266 audit_mappings_page(vcpu, ent, va, level - 1);
3267 else {
1871c602 3268 gpa_t gpa = kvm_mmu_gva_to_gpa_read(vcpu, va, NULL);
34382539
JK		 3269 gfn_t gfn = gpa >> PAGE_SHIFT;
3270 pfn_t pfn = gfn_to_pfn(vcpu->kvm, gfn);
3271 hpa_t hpa = (hpa_t)pfn << PAGE_SHIFT;
37a7d8b0 3272
2aaf65e8
MT		 3273 if (is_error_pfn(pfn)) {
3274 kvm_release_pfn_clean(pfn);
3275 continue;
3276 }
3277
c7addb90 3278 if (is_shadow_present_pte(ent)
37a7d8b0 3279 && (ent & PT64_BASE_ADDR_MASK) != hpa)
c7addb90
AK		 3280 printk(KERN_ERR "xx audit error: (%s) levels %d"
3281 " gva %lx gpa %llx hpa %llx ent %llx %d\n",
ad312c7c 3282 audit_msg, vcpu->arch.mmu.root_level,
d77c26fc
MD		 3283 va, gpa, hpa, ent,
3284 is_shadow_present_pte(ent));
c7addb90
AK		 3285 else if (ent == shadow_notrap_nonpresent_pte
3286 && !is_error_hpa(hpa))
3287 printk(KERN_ERR "audit: (%s) notrap shadow,"
3288 " valid guest gva %lx\n", audit_msg, va);
35149e21 3289 kvm_release_pfn_clean(pfn);
c7addb90 3290
37a7d8b0
AK		 3291 }
3292 }
3293}
3294
3295static void audit_mappings(struct kvm_vcpu *vcpu)
3296{
1ea252af 3297 unsigned i;
37a7d8b0 3298
ad312c7c
ZX		 3299 if (vcpu->arch.mmu.root_level == 4)
3300 audit_mappings_page(vcpu, vcpu->arch.mmu.root_hpa, 0, 4);
37a7d8b0
AK		 3301 else
3302 for (i = 0; i < 4; ++i)
ad312c7c 3303 if (vcpu->arch.mmu.pae_root[i] & PT_PRESENT_MASK)
37a7d8b0 3304 audit_mappings_page(vcpu,
ad312c7c 3305 vcpu->arch.mmu.pae_root[i],
37a7d8b0
AK		 3306 i << 30,
3307 2);
3308}
3309
3310static int count_rmaps(struct kvm_vcpu *vcpu)
3311{
805d32de
XG		 3312 struct kvm *kvm = vcpu->kvm;
3313 struct kvm_memslots *slots;
37a7d8b0 3314 int nmaps = 0;
bc6678a3 3315 int i, j, k, idx;
37a7d8b0 3316
bc6678a3 3317 idx = srcu_read_lock(&kvm->srcu);
90d83dc3 3318 slots = kvm_memslots(kvm);
37a7d8b0 3319 for (i = 0; i < KVM_MEMORY_SLOTS; ++i) {
bc6678a3 3320 struct kvm_memory_slot *m = &slots->memslots[i];
37a7d8b0
AK		 3321 struct kvm_rmap_desc *d;
3322
3323 for (j = 0; j < m->npages; ++j) {
290fc38d 3324 unsigned long *rmapp = &m->rmap[j];
37a7d8b0 3325
290fc38d 3326 if (!*rmapp)
37a7d8b0 3327 continue;
290fc38d 3328 if (!(*rmapp & 1)) {
37a7d8b0
AK		 3329 ++nmaps;
3330 continue;
3331 }
290fc38d 3332 d = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
37a7d8b0
AK		 3333 while (d) {
3334 for (k = 0; k < RMAP_EXT; ++k)
d555c333 3335 if (d->sptes[k])
37a7d8b0
AK		 3336 ++nmaps;
3337 else
3338 break;
3339 d = d->more;
3340 }
3341 }
3342 }
bc6678a3 3343 srcu_read_unlock(&kvm->srcu, idx);
37a7d8b0
AK		 3344 return nmaps;
3345}
3346
805d32de 3347void inspect_spte_has_rmap(struct kvm *kvm, u64 *sptep)
08a3732b
MT		 3348{
3349 unsigned long *rmapp;
3350 struct kvm_mmu_page *rev_sp;
3351 gfn_t gfn;
3352
3353 if (*sptep & PT_WRITABLE_MASK) {
3354 rev_sp = page_header(__pa(sptep));
3355 gfn = rev_sp->gfns[sptep - rev_sp->spt];
3356
3357 if (!gfn_to_memslot(kvm, gfn)) {
3358 if (!printk_ratelimit())
3359 return;
3360 printk(KERN_ERR "%s: no memslot for gfn %ld\n",
3361 audit_msg, gfn);
3362 printk(KERN_ERR "%s: index %ld of sp (gfn=%lx)\n",
805d32de 3363 audit_msg, (long int)(sptep - rev_sp->spt),
08a3732b
MT		 3364 rev_sp->gfn);
3365 dump_stack();
3366 return;
3367 }
3368
2920d728 3369 rmapp = gfn_to_rmap(kvm, rev_sp->gfns[sptep - rev_sp->spt],
805d32de 3370 rev_sp->role.level);
08a3732b
MT		 3371 if (!*rmapp) {
3372 if (!printk_ratelimit())
3373 return;
3374 printk(KERN_ERR "%s: no rmap for writable spte %llx\n",
3375 audit_msg, *sptep);
3376 dump_stack();
3377 }
3378 }
3379
3380}
3381
3382void audit_writable_sptes_have_rmaps(struct kvm_vcpu *vcpu)
3383{
3384 mmu_spte_walk(vcpu, inspect_spte_has_rmap);
3385}
3386
3387static void check_writable_mappings_rmap(struct kvm_vcpu *vcpu)
37a7d8b0 3388{
4db35314 3389 struct kvm_mmu_page *sp;
37a7d8b0
AK		 3390 int i;
3391
f05e70ac 3392 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
4db35314 3393 u64 *pt = sp->spt;
37a7d8b0 3394
4db35314 3395 if (sp->role.level != PT_PAGE_TABLE_LEVEL)
37a7d8b0
AK		 3396 continue;
3397
3398 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3399 u64 ent = pt[i];
3400
3401 if (!(ent & PT_PRESENT_MASK))
3402 continue;
3403 if (!(ent & PT_WRITABLE_MASK))
3404 continue;
805d32de 3405 inspect_spte_has_rmap(vcpu->kvm, &pt[i]);
37a7d8b0
AK		 3406 }
3407 }
08a3732b 3408 return;
37a7d8b0
AK		 3409}
3410
3411static void audit_rmap(struct kvm_vcpu *vcpu)
3412{
08a3732b
MT		 3413 check_writable_mappings_rmap(vcpu);
3414 count_rmaps(vcpu);
37a7d8b0
AK		 3415}
3416
3417static void audit_write_protection(struct kvm_vcpu *vcpu)
3418{
4db35314 3419 struct kvm_mmu_page *sp;
290fc38d
IE		 3420 struct kvm_memory_slot *slot;
3421 unsigned long *rmapp;
e58b0f9e 3422 u64 *spte;
290fc38d 3423 gfn_t gfn;
37a7d8b0 3424
f05e70ac 3425 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
f6e2c02b 3426 if (sp->role.direct)
37a7d8b0 3427 continue;
e58b0f9e
MT		 3428 if (sp->unsync)
3429 continue;
37a7d8b0 3430
4db35314 3431 gfn = unalias_gfn(vcpu->kvm, sp->gfn);
2843099f 3432 slot = gfn_to_memslot_unaliased(vcpu->kvm, sp->gfn);
290fc38d 3433 rmapp = &slot->rmap[gfn - slot->base_gfn];
e58b0f9e
MT		 3434
3435 spte = rmap_next(vcpu->kvm, rmapp, NULL);
3436 while (spte) {
3437 if (*spte & PT_WRITABLE_MASK)
3438 printk(KERN_ERR "%s: (%s) shadow page has "
3439 "writable mappings: gfn %lx role %x\n",
b8688d51 3440 __func__, audit_msg, sp->gfn,
4db35314 3441 sp->role.word);
e58b0f9e
MT		 3442 spte = rmap_next(vcpu->kvm, rmapp, spte);
3443 }
37a7d8b0
AK		 3444 }
3445}
3446
3447static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg)
3448{
3449 int olddbg = dbg;
3450
3451 dbg = 0;
3452 audit_msg = msg;
3453 audit_rmap(vcpu);
3454 audit_write_protection(vcpu);
2aaf65e8
MT		 3455 if (strcmp("pre pte write", audit_msg) != 0)
3456 audit_mappings(vcpu);
08a3732b 3457 audit_writable_sptes_have_rmaps(vcpu);
37a7d8b0
AK		 3458 dbg = olddbg;
3459}
3460
3461#endif
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