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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
af585b92 | 21 | #include "irq.h" |
1d737c8a | 22 | #include "mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
5f7dde7b | 25 | #include "cpuid.h" |
e495606d | 26 | |
edf88417 | 27 | #include <linux/kvm_host.h> |
6aa8b732 AK |
28 | #include <linux/types.h> |
29 | #include <linux/string.h> | |
6aa8b732 AK |
30 | #include <linux/mm.h> |
31 | #include <linux/highmem.h> | |
1767e931 PG |
32 | #include <linux/moduleparam.h> |
33 | #include <linux/export.h> | |
448353ca | 34 | #include <linux/swap.h> |
05da4558 | 35 | #include <linux/hugetlb.h> |
2f333bcb | 36 | #include <linux/compiler.h> |
bc6678a3 | 37 | #include <linux/srcu.h> |
5a0e3ad6 | 38 | #include <linux/slab.h> |
3f07c014 | 39 | #include <linux/sched/signal.h> |
bf998156 | 40 | #include <linux/uaccess.h> |
114df303 | 41 | #include <linux/hash.h> |
f160c7b7 | 42 | #include <linux/kern_levels.h> |
6aa8b732 | 43 | |
e495606d AK |
44 | #include <asm/page.h> |
45 | #include <asm/cmpxchg.h> | |
4e542370 | 46 | #include <asm/io.h> |
13673a90 | 47 | #include <asm/vmx.h> |
3d0c27ad | 48 | #include <asm/kvm_page_track.h> |
6aa8b732 | 49 | |
18552672 JR |
50 | /* |
51 | * When setting this variable to true it enables Two-Dimensional-Paging | |
52 | * where the hardware walks 2 page tables: | |
53 | * 1. the guest-virtual to guest-physical | |
54 | * 2. while doing 1. it walks guest-physical to host-physical | |
55 | * If the hardware supports that we don't need to do shadow paging. | |
56 | */ | |
2f333bcb | 57 | bool tdp_enabled = false; |
18552672 | 58 | |
8b1fe17c XG |
59 | enum { |
60 | AUDIT_PRE_PAGE_FAULT, | |
61 | AUDIT_POST_PAGE_FAULT, | |
62 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
63 | AUDIT_POST_PTE_WRITE, |
64 | AUDIT_PRE_SYNC, | |
65 | AUDIT_POST_SYNC | |
8b1fe17c | 66 | }; |
37a7d8b0 | 67 | |
8b1fe17c | 68 | #undef MMU_DEBUG |
37a7d8b0 AK |
69 | |
70 | #ifdef MMU_DEBUG | |
fa4a2c08 PB |
71 | static bool dbg = 0; |
72 | module_param(dbg, bool, 0644); | |
37a7d8b0 AK |
73 | |
74 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
75 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
fa4a2c08 | 76 | #define MMU_WARN_ON(x) WARN_ON(x) |
37a7d8b0 | 77 | #else |
37a7d8b0 AK |
78 | #define pgprintk(x...) do { } while (0) |
79 | #define rmap_printk(x...) do { } while (0) | |
fa4a2c08 | 80 | #define MMU_WARN_ON(x) do { } while (0) |
d6c69ee9 | 81 | #endif |
6aa8b732 | 82 | |
957ed9ef XG |
83 | #define PTE_PREFETCH_NUM 8 |
84 | ||
00763e41 | 85 | #define PT_FIRST_AVAIL_BITS_SHIFT 10 |
6aa8b732 AK |
86 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 |
87 | ||
6aa8b732 AK |
88 | #define PT64_LEVEL_BITS 9 |
89 | ||
90 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 91 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 | 92 | |
6aa8b732 AK |
93 | #define PT64_INDEX(address, level)\ |
94 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
95 | ||
96 | ||
97 | #define PT32_LEVEL_BITS 10 | |
98 | ||
99 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 100 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 101 | |
e04da980 JR |
102 | #define PT32_LVL_OFFSET_MASK(level) \ |
103 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
104 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
105 | |
106 | #define PT32_INDEX(address, level)\ | |
107 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
108 | ||
109 | ||
27aba766 | 110 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
111 | #define PT64_DIR_BASE_ADDR_MASK \ |
112 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
113 | #define PT64_LVL_ADDR_MASK(level) \ |
114 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
115 | * PT64_LEVEL_BITS))) - 1)) | |
116 | #define PT64_LVL_OFFSET_MASK(level) \ | |
117 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
118 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
119 | |
120 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
121 | #define PT32_DIR_BASE_ADDR_MASK \ | |
122 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
123 | #define PT32_LVL_ADDR_MASK(level) \ |
124 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
125 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 126 | |
53166229 GN |
127 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \ |
128 | | shadow_x_mask | shadow_nx_mask) | |
6aa8b732 | 129 | |
fe135d2c AK |
130 | #define ACC_EXEC_MASK 1 |
131 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
132 | #define ACC_USER_MASK PT_USER_MASK | |
133 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
134 | ||
f160c7b7 JS |
135 | /* The mask for the R/X bits in EPT PTEs */ |
136 | #define PT64_EPT_READABLE_MASK 0x1ull | |
137 | #define PT64_EPT_EXECUTABLE_MASK 0x4ull | |
138 | ||
90bb6fc5 AK |
139 | #include <trace/events/kvm.h> |
140 | ||
07420171 AK |
141 | #define CREATE_TRACE_POINTS |
142 | #include "mmutrace.h" | |
143 | ||
49fde340 XG |
144 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
145 | #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1)) | |
1403283a | 146 | |
135f8c2b AK |
147 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
148 | ||
220f773a TY |
149 | /* make pte_list_desc fit well in cache line */ |
150 | #define PTE_LIST_EXT 3 | |
151 | ||
53c07b18 XG |
152 | struct pte_list_desc { |
153 | u64 *sptes[PTE_LIST_EXT]; | |
154 | struct pte_list_desc *more; | |
cd4a4e53 AK |
155 | }; |
156 | ||
2d11123a AK |
157 | struct kvm_shadow_walk_iterator { |
158 | u64 addr; | |
159 | hpa_t shadow_addr; | |
2d11123a | 160 | u64 *sptep; |
dd3bfd59 | 161 | int level; |
2d11123a AK |
162 | unsigned index; |
163 | }; | |
164 | ||
165 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
166 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
167 | shadow_walk_okay(&(_walker)); \ | |
168 | shadow_walk_next(&(_walker))) | |
169 | ||
c2a2ac2b XG |
170 | #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ |
171 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
172 | shadow_walk_okay(&(_walker)) && \ | |
173 | ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \ | |
174 | __shadow_walk_next(&(_walker), spte)) | |
175 | ||
53c07b18 | 176 | static struct kmem_cache *pte_list_desc_cache; |
d3d25b04 | 177 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 178 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 179 | |
7b52345e SY |
180 | static u64 __read_mostly shadow_nx_mask; |
181 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
182 | static u64 __read_mostly shadow_user_mask; | |
183 | static u64 __read_mostly shadow_accessed_mask; | |
184 | static u64 __read_mostly shadow_dirty_mask; | |
ce88decf | 185 | static u64 __read_mostly shadow_mmio_mask; |
ffb128c8 | 186 | static u64 __read_mostly shadow_present_mask; |
ce88decf | 187 | |
f160c7b7 JS |
188 | /* |
189 | * The mask/value to distinguish a PTE that has been marked not-present for | |
190 | * access tracking purposes. | |
191 | * The mask would be either 0 if access tracking is disabled, or | |
192 | * SPTE_SPECIAL_MASK|VMX_EPT_RWX_MASK if access tracking is enabled. | |
193 | */ | |
194 | static u64 __read_mostly shadow_acc_track_mask; | |
195 | static const u64 shadow_acc_track_value = SPTE_SPECIAL_MASK; | |
196 | ||
197 | /* | |
198 | * The mask/shift to use for saving the original R/X bits when marking the PTE | |
199 | * as not-present for access tracking purposes. We do not save the W bit as the | |
200 | * PTEs being access tracked also need to be dirty tracked, so the W bit will be | |
201 | * restored only when a write is attempted to the page. | |
202 | */ | |
203 | static const u64 shadow_acc_track_saved_bits_mask = PT64_EPT_READABLE_MASK | | |
204 | PT64_EPT_EXECUTABLE_MASK; | |
205 | static const u64 shadow_acc_track_saved_bits_shift = PT64_SECOND_AVAIL_BITS_SHIFT; | |
206 | ||
ce88decf | 207 | static void mmu_spte_set(u64 *sptep, u64 spte); |
e676505a | 208 | static void mmu_free_roots(struct kvm_vcpu *vcpu); |
ce88decf XG |
209 | |
210 | void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask) | |
211 | { | |
312b616b | 212 | shadow_mmio_mask = mmio_mask | SPTE_SPECIAL_MASK; |
ce88decf XG |
213 | } |
214 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask); | |
215 | ||
f160c7b7 JS |
216 | static inline bool is_access_track_spte(u64 spte) |
217 | { | |
218 | /* Always false if shadow_acc_track_mask is zero. */ | |
219 | return (spte & shadow_acc_track_mask) == shadow_acc_track_value; | |
220 | } | |
221 | ||
f2fd125d | 222 | /* |
ee3d1570 DM |
223 | * the low bit of the generation number is always presumed to be zero. |
224 | * This disables mmio caching during memslot updates. The concept is | |
225 | * similar to a seqcount but instead of retrying the access we just punt | |
226 | * and ignore the cache. | |
227 | * | |
228 | * spte bits 3-11 are used as bits 1-9 of the generation number, | |
229 | * the bits 52-61 are used as bits 10-19 of the generation number. | |
f2fd125d | 230 | */ |
ee3d1570 | 231 | #define MMIO_SPTE_GEN_LOW_SHIFT 2 |
f2fd125d XG |
232 | #define MMIO_SPTE_GEN_HIGH_SHIFT 52 |
233 | ||
ee3d1570 DM |
234 | #define MMIO_GEN_SHIFT 20 |
235 | #define MMIO_GEN_LOW_SHIFT 10 | |
236 | #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2) | |
f8f55942 | 237 | #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1) |
f2fd125d XG |
238 | |
239 | static u64 generation_mmio_spte_mask(unsigned int gen) | |
240 | { | |
241 | u64 mask; | |
242 | ||
842bb26a | 243 | WARN_ON(gen & ~MMIO_GEN_MASK); |
f2fd125d XG |
244 | |
245 | mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT; | |
246 | mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT; | |
247 | return mask; | |
248 | } | |
249 | ||
250 | static unsigned int get_mmio_spte_generation(u64 spte) | |
251 | { | |
252 | unsigned int gen; | |
253 | ||
254 | spte &= ~shadow_mmio_mask; | |
255 | ||
256 | gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK; | |
257 | gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT; | |
258 | return gen; | |
259 | } | |
260 | ||
54bf36aa | 261 | static unsigned int kvm_current_mmio_generation(struct kvm_vcpu *vcpu) |
f8f55942 | 262 | { |
54bf36aa | 263 | return kvm_vcpu_memslots(vcpu)->generation & MMIO_GEN_MASK; |
f8f55942 XG |
264 | } |
265 | ||
54bf36aa | 266 | static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn, |
f2fd125d | 267 | unsigned access) |
ce88decf | 268 | { |
54bf36aa | 269 | unsigned int gen = kvm_current_mmio_generation(vcpu); |
f8f55942 | 270 | u64 mask = generation_mmio_spte_mask(gen); |
95b0430d | 271 | |
ce88decf | 272 | access &= ACC_WRITE_MASK | ACC_USER_MASK; |
f2fd125d | 273 | mask |= shadow_mmio_mask | access | gfn << PAGE_SHIFT; |
f2fd125d | 274 | |
f8f55942 | 275 | trace_mark_mmio_spte(sptep, gfn, access, gen); |
f2fd125d | 276 | mmu_spte_set(sptep, mask); |
ce88decf XG |
277 | } |
278 | ||
279 | static bool is_mmio_spte(u64 spte) | |
280 | { | |
281 | return (spte & shadow_mmio_mask) == shadow_mmio_mask; | |
282 | } | |
283 | ||
284 | static gfn_t get_mmio_spte_gfn(u64 spte) | |
285 | { | |
842bb26a | 286 | u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask; |
f2fd125d | 287 | return (spte & ~mask) >> PAGE_SHIFT; |
ce88decf XG |
288 | } |
289 | ||
290 | static unsigned get_mmio_spte_access(u64 spte) | |
291 | { | |
842bb26a | 292 | u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask; |
f2fd125d | 293 | return (spte & ~mask) & ~PAGE_MASK; |
ce88decf XG |
294 | } |
295 | ||
54bf36aa | 296 | static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
ba049e93 | 297 | kvm_pfn_t pfn, unsigned access) |
ce88decf XG |
298 | { |
299 | if (unlikely(is_noslot_pfn(pfn))) { | |
54bf36aa | 300 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
301 | return true; |
302 | } | |
303 | ||
304 | return false; | |
305 | } | |
c7addb90 | 306 | |
54bf36aa | 307 | static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte) |
f8f55942 | 308 | { |
089504c0 XG |
309 | unsigned int kvm_gen, spte_gen; |
310 | ||
54bf36aa | 311 | kvm_gen = kvm_current_mmio_generation(vcpu); |
089504c0 XG |
312 | spte_gen = get_mmio_spte_generation(spte); |
313 | ||
314 | trace_check_mmio_spte(spte, kvm_gen, spte_gen); | |
315 | return likely(kvm_gen == spte_gen); | |
f8f55942 XG |
316 | } |
317 | ||
7b52345e | 318 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
f160c7b7 JS |
319 | u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask, |
320 | u64 acc_track_mask) | |
7b52345e | 321 | { |
312b616b JS |
322 | if (acc_track_mask != 0) |
323 | acc_track_mask |= SPTE_SPECIAL_MASK; | |
324 | ||
7b52345e SY |
325 | shadow_user_mask = user_mask; |
326 | shadow_accessed_mask = accessed_mask; | |
327 | shadow_dirty_mask = dirty_mask; | |
328 | shadow_nx_mask = nx_mask; | |
329 | shadow_x_mask = x_mask; | |
ffb128c8 | 330 | shadow_present_mask = p_mask; |
f160c7b7 JS |
331 | shadow_acc_track_mask = acc_track_mask; |
332 | WARN_ON(shadow_accessed_mask != 0 && shadow_acc_track_mask != 0); | |
7b52345e SY |
333 | } |
334 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
335 | ||
f160c7b7 JS |
336 | void kvm_mmu_clear_all_pte_masks(void) |
337 | { | |
338 | shadow_user_mask = 0; | |
339 | shadow_accessed_mask = 0; | |
340 | shadow_dirty_mask = 0; | |
341 | shadow_nx_mask = 0; | |
342 | shadow_x_mask = 0; | |
343 | shadow_mmio_mask = 0; | |
344 | shadow_present_mask = 0; | |
345 | shadow_acc_track_mask = 0; | |
346 | } | |
347 | ||
6aa8b732 AK |
348 | static int is_cpuid_PSE36(void) |
349 | { | |
350 | return 1; | |
351 | } | |
352 | ||
73b1087e AK |
353 | static int is_nx(struct kvm_vcpu *vcpu) |
354 | { | |
f6801dff | 355 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
356 | } |
357 | ||
c7addb90 AK |
358 | static int is_shadow_present_pte(u64 pte) |
359 | { | |
f160c7b7 | 360 | return (pte != 0) && !is_mmio_spte(pte); |
c7addb90 AK |
361 | } |
362 | ||
05da4558 MT |
363 | static int is_large_pte(u64 pte) |
364 | { | |
365 | return pte & PT_PAGE_SIZE_MASK; | |
366 | } | |
367 | ||
776e6633 MT |
368 | static int is_last_spte(u64 pte, int level) |
369 | { | |
370 | if (level == PT_PAGE_TABLE_LEVEL) | |
371 | return 1; | |
852e3c19 | 372 | if (is_large_pte(pte)) |
776e6633 MT |
373 | return 1; |
374 | return 0; | |
375 | } | |
376 | ||
d3e328f2 JS |
377 | static bool is_executable_pte(u64 spte) |
378 | { | |
379 | return (spte & (shadow_x_mask | shadow_nx_mask)) == shadow_x_mask; | |
380 | } | |
381 | ||
ba049e93 | 382 | static kvm_pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 383 | { |
35149e21 | 384 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
385 | } |
386 | ||
da928521 AK |
387 | static gfn_t pse36_gfn_delta(u32 gpte) |
388 | { | |
389 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
390 | ||
391 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
392 | } | |
393 | ||
603e0651 | 394 | #ifdef CONFIG_X86_64 |
d555c333 | 395 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 396 | { |
b19ee2ff | 397 | WRITE_ONCE(*sptep, spte); |
e663ee64 AK |
398 | } |
399 | ||
603e0651 | 400 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
a9221dd5 | 401 | { |
b19ee2ff | 402 | WRITE_ONCE(*sptep, spte); |
603e0651 XG |
403 | } |
404 | ||
405 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
406 | { | |
407 | return xchg(sptep, spte); | |
408 | } | |
c2a2ac2b XG |
409 | |
410 | static u64 __get_spte_lockless(u64 *sptep) | |
411 | { | |
412 | return ACCESS_ONCE(*sptep); | |
413 | } | |
a9221dd5 | 414 | #else |
603e0651 XG |
415 | union split_spte { |
416 | struct { | |
417 | u32 spte_low; | |
418 | u32 spte_high; | |
419 | }; | |
420 | u64 spte; | |
421 | }; | |
a9221dd5 | 422 | |
c2a2ac2b XG |
423 | static void count_spte_clear(u64 *sptep, u64 spte) |
424 | { | |
425 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
426 | ||
427 | if (is_shadow_present_pte(spte)) | |
428 | return; | |
429 | ||
430 | /* Ensure the spte is completely set before we increase the count */ | |
431 | smp_wmb(); | |
432 | sp->clear_spte_count++; | |
433 | } | |
434 | ||
603e0651 XG |
435 | static void __set_spte(u64 *sptep, u64 spte) |
436 | { | |
437 | union split_spte *ssptep, sspte; | |
a9221dd5 | 438 | |
603e0651 XG |
439 | ssptep = (union split_spte *)sptep; |
440 | sspte = (union split_spte)spte; | |
441 | ||
442 | ssptep->spte_high = sspte.spte_high; | |
443 | ||
444 | /* | |
445 | * If we map the spte from nonpresent to present, We should store | |
446 | * the high bits firstly, then set present bit, so cpu can not | |
447 | * fetch this spte while we are setting the spte. | |
448 | */ | |
449 | smp_wmb(); | |
450 | ||
b19ee2ff | 451 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
a9221dd5 AK |
452 | } |
453 | ||
603e0651 XG |
454 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
455 | { | |
456 | union split_spte *ssptep, sspte; | |
457 | ||
458 | ssptep = (union split_spte *)sptep; | |
459 | sspte = (union split_spte)spte; | |
460 | ||
b19ee2ff | 461 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
603e0651 XG |
462 | |
463 | /* | |
464 | * If we map the spte from present to nonpresent, we should clear | |
465 | * present bit firstly to avoid vcpu fetch the old high bits. | |
466 | */ | |
467 | smp_wmb(); | |
468 | ||
469 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 470 | count_spte_clear(sptep, spte); |
603e0651 XG |
471 | } |
472 | ||
473 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
474 | { | |
475 | union split_spte *ssptep, sspte, orig; | |
476 | ||
477 | ssptep = (union split_spte *)sptep; | |
478 | sspte = (union split_spte)spte; | |
479 | ||
480 | /* xchg acts as a barrier before the setting of the high bits */ | |
481 | orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); | |
41bc3186 ZJ |
482 | orig.spte_high = ssptep->spte_high; |
483 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 484 | count_spte_clear(sptep, spte); |
603e0651 XG |
485 | |
486 | return orig.spte; | |
487 | } | |
c2a2ac2b XG |
488 | |
489 | /* | |
490 | * The idea using the light way get the spte on x86_32 guest is from | |
491 | * gup_get_pte(arch/x86/mm/gup.c). | |
accaefe0 XG |
492 | * |
493 | * An spte tlb flush may be pending, because kvm_set_pte_rmapp | |
494 | * coalesces them and we are running out of the MMU lock. Therefore | |
495 | * we need to protect against in-progress updates of the spte. | |
496 | * | |
497 | * Reading the spte while an update is in progress may get the old value | |
498 | * for the high part of the spte. The race is fine for a present->non-present | |
499 | * change (because the high part of the spte is ignored for non-present spte), | |
500 | * but for a present->present change we must reread the spte. | |
501 | * | |
502 | * All such changes are done in two steps (present->non-present and | |
503 | * non-present->present), hence it is enough to count the number of | |
504 | * present->non-present updates: if it changed while reading the spte, | |
505 | * we might have hit the race. This is done using clear_spte_count. | |
c2a2ac2b XG |
506 | */ |
507 | static u64 __get_spte_lockless(u64 *sptep) | |
508 | { | |
509 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
510 | union split_spte spte, *orig = (union split_spte *)sptep; | |
511 | int count; | |
512 | ||
513 | retry: | |
514 | count = sp->clear_spte_count; | |
515 | smp_rmb(); | |
516 | ||
517 | spte.spte_low = orig->spte_low; | |
518 | smp_rmb(); | |
519 | ||
520 | spte.spte_high = orig->spte_high; | |
521 | smp_rmb(); | |
522 | ||
523 | if (unlikely(spte.spte_low != orig->spte_low || | |
524 | count != sp->clear_spte_count)) | |
525 | goto retry; | |
526 | ||
527 | return spte.spte; | |
528 | } | |
603e0651 XG |
529 | #endif |
530 | ||
ea4114bc | 531 | static bool spte_can_locklessly_be_made_writable(u64 spte) |
c7ba5b48 | 532 | { |
feb3eb70 GN |
533 | return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) == |
534 | (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE); | |
c7ba5b48 XG |
535 | } |
536 | ||
8672b721 XG |
537 | static bool spte_has_volatile_bits(u64 spte) |
538 | { | |
f160c7b7 JS |
539 | if (!is_shadow_present_pte(spte)) |
540 | return false; | |
541 | ||
c7ba5b48 | 542 | /* |
6a6256f9 | 543 | * Always atomically update spte if it can be updated |
c7ba5b48 XG |
544 | * out of mmu-lock, it can ensure dirty bit is not lost, |
545 | * also, it can help us to get a stable is_writable_pte() | |
546 | * to ensure tlb flush is not missed. | |
547 | */ | |
f160c7b7 JS |
548 | if (spte_can_locklessly_be_made_writable(spte) || |
549 | is_access_track_spte(spte)) | |
c7ba5b48 XG |
550 | return true; |
551 | ||
f160c7b7 JS |
552 | if (shadow_accessed_mask) { |
553 | if ((spte & shadow_accessed_mask) == 0 || | |
554 | (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0)) | |
555 | return true; | |
556 | } | |
8672b721 | 557 | |
f160c7b7 | 558 | return false; |
8672b721 XG |
559 | } |
560 | ||
83ef6c81 | 561 | static bool is_accessed_spte(u64 spte) |
4132779b | 562 | { |
83ef6c81 | 563 | return shadow_accessed_mask ? spte & shadow_accessed_mask |
f160c7b7 | 564 | : !is_access_track_spte(spte); |
4132779b XG |
565 | } |
566 | ||
83ef6c81 | 567 | static bool is_dirty_spte(u64 spte) |
7e71a59b | 568 | { |
83ef6c81 JS |
569 | return shadow_dirty_mask ? spte & shadow_dirty_mask |
570 | : spte & PT_WRITABLE_MASK; | |
7e71a59b KH |
571 | } |
572 | ||
1df9f2dc XG |
573 | /* Rules for using mmu_spte_set: |
574 | * Set the sptep from nonpresent to present. | |
575 | * Note: the sptep being assigned *must* be either not present | |
576 | * or in a state where the hardware will not attempt to update | |
577 | * the spte. | |
578 | */ | |
579 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
580 | { | |
581 | WARN_ON(is_shadow_present_pte(*sptep)); | |
582 | __set_spte(sptep, new_spte); | |
583 | } | |
584 | ||
f39a058d JS |
585 | /* |
586 | * Update the SPTE (excluding the PFN), but do not track changes in its | |
587 | * accessed/dirty status. | |
1df9f2dc | 588 | */ |
f39a058d | 589 | static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte) |
b79b93f9 | 590 | { |
c7ba5b48 | 591 | u64 old_spte = *sptep; |
4132779b | 592 | |
afd28fe1 | 593 | WARN_ON(!is_shadow_present_pte(new_spte)); |
b79b93f9 | 594 | |
6e7d0354 XG |
595 | if (!is_shadow_present_pte(old_spte)) { |
596 | mmu_spte_set(sptep, new_spte); | |
f39a058d | 597 | return old_spte; |
6e7d0354 | 598 | } |
4132779b | 599 | |
c7ba5b48 | 600 | if (!spte_has_volatile_bits(old_spte)) |
603e0651 | 601 | __update_clear_spte_fast(sptep, new_spte); |
4132779b | 602 | else |
603e0651 | 603 | old_spte = __update_clear_spte_slow(sptep, new_spte); |
4132779b | 604 | |
83ef6c81 JS |
605 | WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte)); |
606 | ||
f39a058d JS |
607 | return old_spte; |
608 | } | |
609 | ||
610 | /* Rules for using mmu_spte_update: | |
611 | * Update the state bits, it means the mapped pfn is not changed. | |
612 | * | |
613 | * Whenever we overwrite a writable spte with a read-only one we | |
614 | * should flush remote TLBs. Otherwise rmap_write_protect | |
615 | * will find a read-only spte, even though the writable spte | |
616 | * might be cached on a CPU's TLB, the return value indicates this | |
617 | * case. | |
618 | * | |
619 | * Returns true if the TLB needs to be flushed | |
620 | */ | |
621 | static bool mmu_spte_update(u64 *sptep, u64 new_spte) | |
622 | { | |
623 | bool flush = false; | |
624 | u64 old_spte = mmu_spte_update_no_track(sptep, new_spte); | |
625 | ||
626 | if (!is_shadow_present_pte(old_spte)) | |
627 | return false; | |
628 | ||
c7ba5b48 XG |
629 | /* |
630 | * For the spte updated out of mmu-lock is safe, since | |
6a6256f9 | 631 | * we always atomically update it, see the comments in |
c7ba5b48 XG |
632 | * spte_has_volatile_bits(). |
633 | */ | |
ea4114bc | 634 | if (spte_can_locklessly_be_made_writable(old_spte) && |
7f31c959 | 635 | !is_writable_pte(new_spte)) |
83ef6c81 | 636 | flush = true; |
4132779b | 637 | |
7e71a59b | 638 | /* |
83ef6c81 | 639 | * Flush TLB when accessed/dirty states are changed in the page tables, |
7e71a59b KH |
640 | * to guarantee consistency between TLB and page tables. |
641 | */ | |
7e71a59b | 642 | |
83ef6c81 JS |
643 | if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) { |
644 | flush = true; | |
4132779b | 645 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); |
83ef6c81 JS |
646 | } |
647 | ||
648 | if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) { | |
649 | flush = true; | |
4132779b | 650 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); |
83ef6c81 | 651 | } |
6e7d0354 | 652 | |
83ef6c81 | 653 | return flush; |
b79b93f9 AK |
654 | } |
655 | ||
1df9f2dc XG |
656 | /* |
657 | * Rules for using mmu_spte_clear_track_bits: | |
658 | * It sets the sptep from present to nonpresent, and track the | |
659 | * state bits, it is used to clear the last level sptep. | |
83ef6c81 | 660 | * Returns non-zero if the PTE was previously valid. |
1df9f2dc XG |
661 | */ |
662 | static int mmu_spte_clear_track_bits(u64 *sptep) | |
663 | { | |
ba049e93 | 664 | kvm_pfn_t pfn; |
1df9f2dc XG |
665 | u64 old_spte = *sptep; |
666 | ||
667 | if (!spte_has_volatile_bits(old_spte)) | |
603e0651 | 668 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc | 669 | else |
603e0651 | 670 | old_spte = __update_clear_spte_slow(sptep, 0ull); |
1df9f2dc | 671 | |
afd28fe1 | 672 | if (!is_shadow_present_pte(old_spte)) |
1df9f2dc XG |
673 | return 0; |
674 | ||
675 | pfn = spte_to_pfn(old_spte); | |
86fde74c XG |
676 | |
677 | /* | |
678 | * KVM does not hold the refcount of the page used by | |
679 | * kvm mmu, before reclaiming the page, we should | |
680 | * unmap it from mmu first. | |
681 | */ | |
bf4bea8e | 682 | WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn))); |
86fde74c | 683 | |
83ef6c81 | 684 | if (is_accessed_spte(old_spte)) |
1df9f2dc | 685 | kvm_set_pfn_accessed(pfn); |
83ef6c81 JS |
686 | |
687 | if (is_dirty_spte(old_spte)) | |
1df9f2dc | 688 | kvm_set_pfn_dirty(pfn); |
83ef6c81 | 689 | |
1df9f2dc XG |
690 | return 1; |
691 | } | |
692 | ||
693 | /* | |
694 | * Rules for using mmu_spte_clear_no_track: | |
695 | * Directly clear spte without caring the state bits of sptep, | |
696 | * it is used to set the upper level spte. | |
697 | */ | |
698 | static void mmu_spte_clear_no_track(u64 *sptep) | |
699 | { | |
603e0651 | 700 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc XG |
701 | } |
702 | ||
c2a2ac2b XG |
703 | static u64 mmu_spte_get_lockless(u64 *sptep) |
704 | { | |
705 | return __get_spte_lockless(sptep); | |
706 | } | |
707 | ||
f160c7b7 JS |
708 | static u64 mark_spte_for_access_track(u64 spte) |
709 | { | |
710 | if (shadow_accessed_mask != 0) | |
711 | return spte & ~shadow_accessed_mask; | |
712 | ||
713 | if (shadow_acc_track_mask == 0 || is_access_track_spte(spte)) | |
714 | return spte; | |
715 | ||
716 | /* | |
20d65236 JS |
717 | * Making an Access Tracking PTE will result in removal of write access |
718 | * from the PTE. So, verify that we will be able to restore the write | |
719 | * access in the fast page fault path later on. | |
f160c7b7 JS |
720 | */ |
721 | WARN_ONCE((spte & PT_WRITABLE_MASK) && | |
722 | !spte_can_locklessly_be_made_writable(spte), | |
723 | "kvm: Writable SPTE is not locklessly dirty-trackable\n"); | |
724 | ||
725 | WARN_ONCE(spte & (shadow_acc_track_saved_bits_mask << | |
726 | shadow_acc_track_saved_bits_shift), | |
727 | "kvm: Access Tracking saved bit locations are not zero\n"); | |
728 | ||
729 | spte |= (spte & shadow_acc_track_saved_bits_mask) << | |
730 | shadow_acc_track_saved_bits_shift; | |
731 | spte &= ~shadow_acc_track_mask; | |
732 | spte |= shadow_acc_track_value; | |
733 | ||
734 | return spte; | |
735 | } | |
736 | ||
d3e328f2 JS |
737 | /* Restore an acc-track PTE back to a regular PTE */ |
738 | static u64 restore_acc_track_spte(u64 spte) | |
739 | { | |
740 | u64 new_spte = spte; | |
741 | u64 saved_bits = (spte >> shadow_acc_track_saved_bits_shift) | |
742 | & shadow_acc_track_saved_bits_mask; | |
743 | ||
744 | WARN_ON_ONCE(!is_access_track_spte(spte)); | |
745 | ||
746 | new_spte &= ~shadow_acc_track_mask; | |
747 | new_spte &= ~(shadow_acc_track_saved_bits_mask << | |
748 | shadow_acc_track_saved_bits_shift); | |
749 | new_spte |= saved_bits; | |
750 | ||
751 | return new_spte; | |
752 | } | |
753 | ||
f160c7b7 JS |
754 | /* Returns the Accessed status of the PTE and resets it at the same time. */ |
755 | static bool mmu_spte_age(u64 *sptep) | |
756 | { | |
757 | u64 spte = mmu_spte_get_lockless(sptep); | |
758 | ||
759 | if (!is_accessed_spte(spte)) | |
760 | return false; | |
761 | ||
762 | if (shadow_accessed_mask) { | |
763 | clear_bit((ffs(shadow_accessed_mask) - 1), | |
764 | (unsigned long *)sptep); | |
765 | } else { | |
766 | /* | |
767 | * Capture the dirty status of the page, so that it doesn't get | |
768 | * lost when the SPTE is marked for access tracking. | |
769 | */ | |
770 | if (is_writable_pte(spte)) | |
771 | kvm_set_pfn_dirty(spte_to_pfn(spte)); | |
772 | ||
773 | spte = mark_spte_for_access_track(spte); | |
774 | mmu_spte_update_no_track(sptep, spte); | |
775 | } | |
776 | ||
777 | return true; | |
778 | } | |
779 | ||
c2a2ac2b XG |
780 | static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu) |
781 | { | |
c142786c AK |
782 | /* |
783 | * Prevent page table teardown by making any free-er wait during | |
784 | * kvm_flush_remote_tlbs() IPI to all active vcpus. | |
785 | */ | |
786 | local_irq_disable(); | |
36ca7e0a | 787 | |
c142786c AK |
788 | /* |
789 | * Make sure a following spte read is not reordered ahead of the write | |
790 | * to vcpu->mode. | |
791 | */ | |
36ca7e0a | 792 | smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES); |
c2a2ac2b XG |
793 | } |
794 | ||
795 | static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu) | |
796 | { | |
c142786c AK |
797 | /* |
798 | * Make sure the write to vcpu->mode is not reordered in front of | |
799 | * reads to sptes. If it does, kvm_commit_zap_page() can see us | |
800 | * OUTSIDE_GUEST_MODE and proceed to free the shadow page table. | |
801 | */ | |
36ca7e0a | 802 | smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE); |
c142786c | 803 | local_irq_enable(); |
c2a2ac2b XG |
804 | } |
805 | ||
e2dec939 | 806 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 807 | struct kmem_cache *base_cache, int min) |
714b93da AK |
808 | { |
809 | void *obj; | |
810 | ||
811 | if (cache->nobjs >= min) | |
e2dec939 | 812 | return 0; |
714b93da | 813 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 814 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 815 | if (!obj) |
e2dec939 | 816 | return -ENOMEM; |
714b93da AK |
817 | cache->objects[cache->nobjs++] = obj; |
818 | } | |
e2dec939 | 819 | return 0; |
714b93da AK |
820 | } |
821 | ||
f759e2b4 XG |
822 | static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache) |
823 | { | |
824 | return cache->nobjs; | |
825 | } | |
826 | ||
e8ad9a70 XG |
827 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
828 | struct kmem_cache *cache) | |
714b93da AK |
829 | { |
830 | while (mc->nobjs) | |
e8ad9a70 | 831 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
832 | } |
833 | ||
c1158e63 | 834 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 835 | int min) |
c1158e63 | 836 | { |
842f22ed | 837 | void *page; |
c1158e63 AK |
838 | |
839 | if (cache->nobjs >= min) | |
840 | return 0; | |
841 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
842f22ed | 842 | page = (void *)__get_free_page(GFP_KERNEL); |
c1158e63 AK |
843 | if (!page) |
844 | return -ENOMEM; | |
842f22ed | 845 | cache->objects[cache->nobjs++] = page; |
c1158e63 AK |
846 | } |
847 | return 0; | |
848 | } | |
849 | ||
850 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
851 | { | |
852 | while (mc->nobjs) | |
c4d198d5 | 853 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
854 | } |
855 | ||
2e3e5882 | 856 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 857 | { |
e2dec939 AK |
858 | int r; |
859 | ||
53c07b18 | 860 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
67052b35 | 861 | pte_list_desc_cache, 8 + PTE_PREFETCH_NUM); |
d3d25b04 AK |
862 | if (r) |
863 | goto out; | |
ad312c7c | 864 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
865 | if (r) |
866 | goto out; | |
ad312c7c | 867 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 868 | mmu_page_header_cache, 4); |
e2dec939 AK |
869 | out: |
870 | return r; | |
714b93da AK |
871 | } |
872 | ||
873 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
874 | { | |
53c07b18 XG |
875 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
876 | pte_list_desc_cache); | |
ad312c7c | 877 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
878 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
879 | mmu_page_header_cache); | |
714b93da AK |
880 | } |
881 | ||
80feb89a | 882 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc) |
714b93da AK |
883 | { |
884 | void *p; | |
885 | ||
886 | BUG_ON(!mc->nobjs); | |
887 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
888 | return p; |
889 | } | |
890 | ||
53c07b18 | 891 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 892 | { |
80feb89a | 893 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache); |
714b93da AK |
894 | } |
895 | ||
53c07b18 | 896 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 897 | { |
53c07b18 | 898 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
899 | } |
900 | ||
2032a93d LJ |
901 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
902 | { | |
903 | if (!sp->role.direct) | |
904 | return sp->gfns[index]; | |
905 | ||
906 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
907 | } | |
908 | ||
909 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
910 | { | |
911 | if (sp->role.direct) | |
912 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
913 | else | |
914 | sp->gfns[index] = gfn; | |
915 | } | |
916 | ||
05da4558 | 917 | /* |
d4dbf470 TY |
918 | * Return the pointer to the large page information for a given gfn, |
919 | * handling slots that are not large page aligned. | |
05da4558 | 920 | */ |
d4dbf470 TY |
921 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
922 | struct kvm_memory_slot *slot, | |
923 | int level) | |
05da4558 MT |
924 | { |
925 | unsigned long idx; | |
926 | ||
fb03cb6f | 927 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
db3fe4eb | 928 | return &slot->arch.lpage_info[level - 2][idx]; |
05da4558 MT |
929 | } |
930 | ||
547ffaed XG |
931 | static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot, |
932 | gfn_t gfn, int count) | |
933 | { | |
934 | struct kvm_lpage_info *linfo; | |
935 | int i; | |
936 | ||
937 | for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { | |
938 | linfo = lpage_info_slot(gfn, slot, i); | |
939 | linfo->disallow_lpage += count; | |
940 | WARN_ON(linfo->disallow_lpage < 0); | |
941 | } | |
942 | } | |
943 | ||
944 | void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
945 | { | |
946 | update_gfn_disallow_lpage_count(slot, gfn, 1); | |
947 | } | |
948 | ||
949 | void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
950 | { | |
951 | update_gfn_disallow_lpage_count(slot, gfn, -1); | |
952 | } | |
953 | ||
3ed1a478 | 954 | static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 955 | { |
699023e2 | 956 | struct kvm_memslots *slots; |
d25797b2 | 957 | struct kvm_memory_slot *slot; |
3ed1a478 | 958 | gfn_t gfn; |
05da4558 | 959 | |
56ca57f9 | 960 | kvm->arch.indirect_shadow_pages++; |
3ed1a478 | 961 | gfn = sp->gfn; |
699023e2 PB |
962 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
963 | slot = __gfn_to_memslot(slots, gfn); | |
56ca57f9 XG |
964 | |
965 | /* the non-leaf shadow pages are keeping readonly. */ | |
966 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
967 | return kvm_slot_page_track_add_page(kvm, slot, gfn, | |
968 | KVM_PAGE_TRACK_WRITE); | |
969 | ||
547ffaed | 970 | kvm_mmu_gfn_disallow_lpage(slot, gfn); |
05da4558 MT |
971 | } |
972 | ||
3ed1a478 | 973 | static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 974 | { |
699023e2 | 975 | struct kvm_memslots *slots; |
d25797b2 | 976 | struct kvm_memory_slot *slot; |
3ed1a478 | 977 | gfn_t gfn; |
05da4558 | 978 | |
56ca57f9 | 979 | kvm->arch.indirect_shadow_pages--; |
3ed1a478 | 980 | gfn = sp->gfn; |
699023e2 PB |
981 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
982 | slot = __gfn_to_memslot(slots, gfn); | |
56ca57f9 XG |
983 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) |
984 | return kvm_slot_page_track_remove_page(kvm, slot, gfn, | |
985 | KVM_PAGE_TRACK_WRITE); | |
986 | ||
547ffaed | 987 | kvm_mmu_gfn_allow_lpage(slot, gfn); |
05da4558 MT |
988 | } |
989 | ||
92f94f1e XG |
990 | static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn, int level, |
991 | struct kvm_memory_slot *slot) | |
05da4558 | 992 | { |
d4dbf470 | 993 | struct kvm_lpage_info *linfo; |
05da4558 MT |
994 | |
995 | if (slot) { | |
d4dbf470 | 996 | linfo = lpage_info_slot(gfn, slot, level); |
92f94f1e | 997 | return !!linfo->disallow_lpage; |
05da4558 MT |
998 | } |
999 | ||
92f94f1e | 1000 | return true; |
05da4558 MT |
1001 | } |
1002 | ||
92f94f1e XG |
1003 | static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu *vcpu, gfn_t gfn, |
1004 | int level) | |
5225fdf8 TY |
1005 | { |
1006 | struct kvm_memory_slot *slot; | |
1007 | ||
1008 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); | |
92f94f1e | 1009 | return __mmu_gfn_lpage_is_disallowed(gfn, level, slot); |
5225fdf8 TY |
1010 | } |
1011 | ||
d25797b2 | 1012 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 1013 | { |
8f0b1ab6 | 1014 | unsigned long page_size; |
d25797b2 | 1015 | int i, ret = 0; |
05da4558 | 1016 | |
8f0b1ab6 | 1017 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 1018 | |
8a3d08f1 | 1019 | for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { |
d25797b2 JR |
1020 | if (page_size >= KVM_HPAGE_SIZE(i)) |
1021 | ret = i; | |
1022 | else | |
1023 | break; | |
1024 | } | |
1025 | ||
4c2155ce | 1026 | return ret; |
05da4558 MT |
1027 | } |
1028 | ||
d8aacf5d TY |
1029 | static inline bool memslot_valid_for_gpte(struct kvm_memory_slot *slot, |
1030 | bool no_dirty_log) | |
1031 | { | |
1032 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID) | |
1033 | return false; | |
1034 | if (no_dirty_log && slot->dirty_bitmap) | |
1035 | return false; | |
1036 | ||
1037 | return true; | |
1038 | } | |
1039 | ||
5d163b1c XG |
1040 | static struct kvm_memory_slot * |
1041 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
1042 | bool no_dirty_log) | |
05da4558 MT |
1043 | { |
1044 | struct kvm_memory_slot *slot; | |
5d163b1c | 1045 | |
54bf36aa | 1046 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
d8aacf5d | 1047 | if (!memslot_valid_for_gpte(slot, no_dirty_log)) |
5d163b1c XG |
1048 | slot = NULL; |
1049 | ||
1050 | return slot; | |
1051 | } | |
1052 | ||
fd136902 TY |
1053 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn, |
1054 | bool *force_pt_level) | |
936a5fe6 AA |
1055 | { |
1056 | int host_level, level, max_level; | |
d8aacf5d TY |
1057 | struct kvm_memory_slot *slot; |
1058 | ||
8c85ac1c TY |
1059 | if (unlikely(*force_pt_level)) |
1060 | return PT_PAGE_TABLE_LEVEL; | |
05da4558 | 1061 | |
8c85ac1c TY |
1062 | slot = kvm_vcpu_gfn_to_memslot(vcpu, large_gfn); |
1063 | *force_pt_level = !memslot_valid_for_gpte(slot, true); | |
fd136902 TY |
1064 | if (unlikely(*force_pt_level)) |
1065 | return PT_PAGE_TABLE_LEVEL; | |
1066 | ||
d25797b2 JR |
1067 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
1068 | ||
1069 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
1070 | return host_level; | |
1071 | ||
55dd98c3 | 1072 | max_level = min(kvm_x86_ops->get_lpage_level(), host_level); |
878403b7 SY |
1073 | |
1074 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
92f94f1e | 1075 | if (__mmu_gfn_lpage_is_disallowed(large_gfn, level, slot)) |
d25797b2 | 1076 | break; |
d25797b2 JR |
1077 | |
1078 | return level - 1; | |
05da4558 MT |
1079 | } |
1080 | ||
290fc38d | 1081 | /* |
018aabb5 | 1082 | * About rmap_head encoding: |
cd4a4e53 | 1083 | * |
018aabb5 TY |
1084 | * If the bit zero of rmap_head->val is clear, then it points to the only spte |
1085 | * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct | |
53c07b18 | 1086 | * pte_list_desc containing more mappings. |
018aabb5 TY |
1087 | */ |
1088 | ||
1089 | /* | |
1090 | * Returns the number of pointers in the rmap chain, not counting the new one. | |
cd4a4e53 | 1091 | */ |
53c07b18 | 1092 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
018aabb5 | 1093 | struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 1094 | { |
53c07b18 | 1095 | struct pte_list_desc *desc; |
53a27b39 | 1096 | int i, count = 0; |
cd4a4e53 | 1097 | |
018aabb5 | 1098 | if (!rmap_head->val) { |
53c07b18 | 1099 | rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte); |
018aabb5 TY |
1100 | rmap_head->val = (unsigned long)spte; |
1101 | } else if (!(rmap_head->val & 1)) { | |
53c07b18 XG |
1102 | rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte); |
1103 | desc = mmu_alloc_pte_list_desc(vcpu); | |
018aabb5 | 1104 | desc->sptes[0] = (u64 *)rmap_head->val; |
d555c333 | 1105 | desc->sptes[1] = spte; |
018aabb5 | 1106 | rmap_head->val = (unsigned long)desc | 1; |
cb16a7b3 | 1107 | ++count; |
cd4a4e53 | 1108 | } else { |
53c07b18 | 1109 | rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte); |
018aabb5 | 1110 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
53c07b18 | 1111 | while (desc->sptes[PTE_LIST_EXT-1] && desc->more) { |
cd4a4e53 | 1112 | desc = desc->more; |
53c07b18 | 1113 | count += PTE_LIST_EXT; |
53a27b39 | 1114 | } |
53c07b18 XG |
1115 | if (desc->sptes[PTE_LIST_EXT-1]) { |
1116 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
cd4a4e53 AK |
1117 | desc = desc->more; |
1118 | } | |
d555c333 | 1119 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 1120 | ++count; |
d555c333 | 1121 | desc->sptes[i] = spte; |
cd4a4e53 | 1122 | } |
53a27b39 | 1123 | return count; |
cd4a4e53 AK |
1124 | } |
1125 | ||
53c07b18 | 1126 | static void |
018aabb5 TY |
1127 | pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head, |
1128 | struct pte_list_desc *desc, int i, | |
1129 | struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
1130 | { |
1131 | int j; | |
1132 | ||
53c07b18 | 1133 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 1134 | ; |
d555c333 AK |
1135 | desc->sptes[i] = desc->sptes[j]; |
1136 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
1137 | if (j != 0) |
1138 | return; | |
1139 | if (!prev_desc && !desc->more) | |
018aabb5 | 1140 | rmap_head->val = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
1141 | else |
1142 | if (prev_desc) | |
1143 | prev_desc->more = desc->more; | |
1144 | else | |
018aabb5 | 1145 | rmap_head->val = (unsigned long)desc->more | 1; |
53c07b18 | 1146 | mmu_free_pte_list_desc(desc); |
cd4a4e53 AK |
1147 | } |
1148 | ||
018aabb5 | 1149 | static void pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 1150 | { |
53c07b18 XG |
1151 | struct pte_list_desc *desc; |
1152 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
1153 | int i; |
1154 | ||
018aabb5 | 1155 | if (!rmap_head->val) { |
53c07b18 | 1156 | printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte); |
cd4a4e53 | 1157 | BUG(); |
018aabb5 | 1158 | } else if (!(rmap_head->val & 1)) { |
53c07b18 | 1159 | rmap_printk("pte_list_remove: %p 1->0\n", spte); |
018aabb5 | 1160 | if ((u64 *)rmap_head->val != spte) { |
53c07b18 | 1161 | printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte); |
cd4a4e53 AK |
1162 | BUG(); |
1163 | } | |
018aabb5 | 1164 | rmap_head->val = 0; |
cd4a4e53 | 1165 | } else { |
53c07b18 | 1166 | rmap_printk("pte_list_remove: %p many->many\n", spte); |
018aabb5 | 1167 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
cd4a4e53 AK |
1168 | prev_desc = NULL; |
1169 | while (desc) { | |
018aabb5 | 1170 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) { |
d555c333 | 1171 | if (desc->sptes[i] == spte) { |
018aabb5 TY |
1172 | pte_list_desc_remove_entry(rmap_head, |
1173 | desc, i, prev_desc); | |
cd4a4e53 AK |
1174 | return; |
1175 | } | |
018aabb5 | 1176 | } |
cd4a4e53 AK |
1177 | prev_desc = desc; |
1178 | desc = desc->more; | |
1179 | } | |
53c07b18 | 1180 | pr_err("pte_list_remove: %p many->many\n", spte); |
cd4a4e53 AK |
1181 | BUG(); |
1182 | } | |
1183 | } | |
1184 | ||
018aabb5 TY |
1185 | static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level, |
1186 | struct kvm_memory_slot *slot) | |
53c07b18 | 1187 | { |
77d11309 | 1188 | unsigned long idx; |
53c07b18 | 1189 | |
77d11309 | 1190 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
d89cc617 | 1191 | return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx]; |
53c07b18 XG |
1192 | } |
1193 | ||
018aabb5 TY |
1194 | static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, |
1195 | struct kvm_mmu_page *sp) | |
9b9b1492 | 1196 | { |
699023e2 | 1197 | struct kvm_memslots *slots; |
9b9b1492 TY |
1198 | struct kvm_memory_slot *slot; |
1199 | ||
699023e2 PB |
1200 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
1201 | slot = __gfn_to_memslot(slots, gfn); | |
e4cd1da9 | 1202 | return __gfn_to_rmap(gfn, sp->role.level, slot); |
9b9b1492 TY |
1203 | } |
1204 | ||
f759e2b4 XG |
1205 | static bool rmap_can_add(struct kvm_vcpu *vcpu) |
1206 | { | |
1207 | struct kvm_mmu_memory_cache *cache; | |
1208 | ||
1209 | cache = &vcpu->arch.mmu_pte_list_desc_cache; | |
1210 | return mmu_memory_cache_free_objects(cache); | |
1211 | } | |
1212 | ||
53c07b18 XG |
1213 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
1214 | { | |
1215 | struct kvm_mmu_page *sp; | |
018aabb5 | 1216 | struct kvm_rmap_head *rmap_head; |
53c07b18 | 1217 | |
53c07b18 XG |
1218 | sp = page_header(__pa(spte)); |
1219 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); | |
018aabb5 TY |
1220 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
1221 | return pte_list_add(vcpu, spte, rmap_head); | |
53c07b18 XG |
1222 | } |
1223 | ||
53c07b18 XG |
1224 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
1225 | { | |
1226 | struct kvm_mmu_page *sp; | |
1227 | gfn_t gfn; | |
018aabb5 | 1228 | struct kvm_rmap_head *rmap_head; |
53c07b18 XG |
1229 | |
1230 | sp = page_header(__pa(spte)); | |
1231 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); | |
018aabb5 TY |
1232 | rmap_head = gfn_to_rmap(kvm, gfn, sp); |
1233 | pte_list_remove(spte, rmap_head); | |
53c07b18 XG |
1234 | } |
1235 | ||
1e3f42f0 TY |
1236 | /* |
1237 | * Used by the following functions to iterate through the sptes linked by a | |
1238 | * rmap. All fields are private and not assumed to be used outside. | |
1239 | */ | |
1240 | struct rmap_iterator { | |
1241 | /* private fields */ | |
1242 | struct pte_list_desc *desc; /* holds the sptep if not NULL */ | |
1243 | int pos; /* index of the sptep */ | |
1244 | }; | |
1245 | ||
1246 | /* | |
1247 | * Iteration must be started by this function. This should also be used after | |
1248 | * removing/dropping sptes from the rmap link because in such cases the | |
1249 | * information in the itererator may not be valid. | |
1250 | * | |
1251 | * Returns sptep if found, NULL otherwise. | |
1252 | */ | |
018aabb5 TY |
1253 | static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head, |
1254 | struct rmap_iterator *iter) | |
1e3f42f0 | 1255 | { |
77fbbbd2 TY |
1256 | u64 *sptep; |
1257 | ||
018aabb5 | 1258 | if (!rmap_head->val) |
1e3f42f0 TY |
1259 | return NULL; |
1260 | ||
018aabb5 | 1261 | if (!(rmap_head->val & 1)) { |
1e3f42f0 | 1262 | iter->desc = NULL; |
77fbbbd2 TY |
1263 | sptep = (u64 *)rmap_head->val; |
1264 | goto out; | |
1e3f42f0 TY |
1265 | } |
1266 | ||
018aabb5 | 1267 | iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
1e3f42f0 | 1268 | iter->pos = 0; |
77fbbbd2 TY |
1269 | sptep = iter->desc->sptes[iter->pos]; |
1270 | out: | |
1271 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1272 | return sptep; | |
1e3f42f0 TY |
1273 | } |
1274 | ||
1275 | /* | |
1276 | * Must be used with a valid iterator: e.g. after rmap_get_first(). | |
1277 | * | |
1278 | * Returns sptep if found, NULL otherwise. | |
1279 | */ | |
1280 | static u64 *rmap_get_next(struct rmap_iterator *iter) | |
1281 | { | |
77fbbbd2 TY |
1282 | u64 *sptep; |
1283 | ||
1e3f42f0 TY |
1284 | if (iter->desc) { |
1285 | if (iter->pos < PTE_LIST_EXT - 1) { | |
1e3f42f0 TY |
1286 | ++iter->pos; |
1287 | sptep = iter->desc->sptes[iter->pos]; | |
1288 | if (sptep) | |
77fbbbd2 | 1289 | goto out; |
1e3f42f0 TY |
1290 | } |
1291 | ||
1292 | iter->desc = iter->desc->more; | |
1293 | ||
1294 | if (iter->desc) { | |
1295 | iter->pos = 0; | |
1296 | /* desc->sptes[0] cannot be NULL */ | |
77fbbbd2 TY |
1297 | sptep = iter->desc->sptes[iter->pos]; |
1298 | goto out; | |
1e3f42f0 TY |
1299 | } |
1300 | } | |
1301 | ||
1302 | return NULL; | |
77fbbbd2 TY |
1303 | out: |
1304 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1305 | return sptep; | |
1e3f42f0 TY |
1306 | } |
1307 | ||
018aabb5 TY |
1308 | #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \ |
1309 | for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \ | |
77fbbbd2 | 1310 | _spte_; _spte_ = rmap_get_next(_iter_)) |
0d536790 | 1311 | |
c3707958 | 1312 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 1313 | { |
1df9f2dc | 1314 | if (mmu_spte_clear_track_bits(sptep)) |
eb45fda4 | 1315 | rmap_remove(kvm, sptep); |
be38d276 AK |
1316 | } |
1317 | ||
8e22f955 XG |
1318 | |
1319 | static bool __drop_large_spte(struct kvm *kvm, u64 *sptep) | |
1320 | { | |
1321 | if (is_large_pte(*sptep)) { | |
1322 | WARN_ON(page_header(__pa(sptep))->role.level == | |
1323 | PT_PAGE_TABLE_LEVEL); | |
1324 | drop_spte(kvm, sptep); | |
1325 | --kvm->stat.lpages; | |
1326 | return true; | |
1327 | } | |
1328 | ||
1329 | return false; | |
1330 | } | |
1331 | ||
1332 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) | |
1333 | { | |
1334 | if (__drop_large_spte(vcpu->kvm, sptep)) | |
1335 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1336 | } | |
1337 | ||
1338 | /* | |
49fde340 | 1339 | * Write-protect on the specified @sptep, @pt_protect indicates whether |
c126d94f | 1340 | * spte write-protection is caused by protecting shadow page table. |
49fde340 | 1341 | * |
b4619660 | 1342 | * Note: write protection is difference between dirty logging and spte |
49fde340 XG |
1343 | * protection: |
1344 | * - for dirty logging, the spte can be set to writable at anytime if | |
1345 | * its dirty bitmap is properly set. | |
1346 | * - for spte protection, the spte can be writable only after unsync-ing | |
1347 | * shadow page. | |
8e22f955 | 1348 | * |
c126d94f | 1349 | * Return true if tlb need be flushed. |
8e22f955 | 1350 | */ |
c4f138b4 | 1351 | static bool spte_write_protect(u64 *sptep, bool pt_protect) |
d13bc5b5 XG |
1352 | { |
1353 | u64 spte = *sptep; | |
1354 | ||
49fde340 | 1355 | if (!is_writable_pte(spte) && |
ea4114bc | 1356 | !(pt_protect && spte_can_locklessly_be_made_writable(spte))) |
d13bc5b5 XG |
1357 | return false; |
1358 | ||
1359 | rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep); | |
1360 | ||
49fde340 XG |
1361 | if (pt_protect) |
1362 | spte &= ~SPTE_MMU_WRITEABLE; | |
d13bc5b5 | 1363 | spte = spte & ~PT_WRITABLE_MASK; |
49fde340 | 1364 | |
c126d94f | 1365 | return mmu_spte_update(sptep, spte); |
d13bc5b5 XG |
1366 | } |
1367 | ||
018aabb5 TY |
1368 | static bool __rmap_write_protect(struct kvm *kvm, |
1369 | struct kvm_rmap_head *rmap_head, | |
245c3912 | 1370 | bool pt_protect) |
98348e95 | 1371 | { |
1e3f42f0 TY |
1372 | u64 *sptep; |
1373 | struct rmap_iterator iter; | |
d13bc5b5 | 1374 | bool flush = false; |
374cbac0 | 1375 | |
018aabb5 | 1376 | for_each_rmap_spte(rmap_head, &iter, sptep) |
c4f138b4 | 1377 | flush |= spte_write_protect(sptep, pt_protect); |
855149aa | 1378 | |
d13bc5b5 | 1379 | return flush; |
a0ed4607 TY |
1380 | } |
1381 | ||
c4f138b4 | 1382 | static bool spte_clear_dirty(u64 *sptep) |
f4b4b180 KH |
1383 | { |
1384 | u64 spte = *sptep; | |
1385 | ||
1386 | rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep); | |
1387 | ||
1388 | spte &= ~shadow_dirty_mask; | |
1389 | ||
1390 | return mmu_spte_update(sptep, spte); | |
1391 | } | |
1392 | ||
018aabb5 | 1393 | static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
f4b4b180 KH |
1394 | { |
1395 | u64 *sptep; | |
1396 | struct rmap_iterator iter; | |
1397 | bool flush = false; | |
1398 | ||
018aabb5 | 1399 | for_each_rmap_spte(rmap_head, &iter, sptep) |
c4f138b4 | 1400 | flush |= spte_clear_dirty(sptep); |
f4b4b180 KH |
1401 | |
1402 | return flush; | |
1403 | } | |
1404 | ||
c4f138b4 | 1405 | static bool spte_set_dirty(u64 *sptep) |
f4b4b180 KH |
1406 | { |
1407 | u64 spte = *sptep; | |
1408 | ||
1409 | rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep); | |
1410 | ||
1411 | spte |= shadow_dirty_mask; | |
1412 | ||
1413 | return mmu_spte_update(sptep, spte); | |
1414 | } | |
1415 | ||
018aabb5 | 1416 | static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
f4b4b180 KH |
1417 | { |
1418 | u64 *sptep; | |
1419 | struct rmap_iterator iter; | |
1420 | bool flush = false; | |
1421 | ||
018aabb5 | 1422 | for_each_rmap_spte(rmap_head, &iter, sptep) |
c4f138b4 | 1423 | flush |= spte_set_dirty(sptep); |
f4b4b180 KH |
1424 | |
1425 | return flush; | |
1426 | } | |
1427 | ||
5dc99b23 | 1428 | /** |
3b0f1d01 | 1429 | * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages |
5dc99b23 TY |
1430 | * @kvm: kvm instance |
1431 | * @slot: slot to protect | |
1432 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1433 | * @mask: indicates which pages we should protect | |
1434 | * | |
1435 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1436 | * logging we do not have any such mappings. | |
1437 | */ | |
3b0f1d01 | 1438 | static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, |
5dc99b23 TY |
1439 | struct kvm_memory_slot *slot, |
1440 | gfn_t gfn_offset, unsigned long mask) | |
a0ed4607 | 1441 | { |
018aabb5 | 1442 | struct kvm_rmap_head *rmap_head; |
a0ed4607 | 1443 | |
5dc99b23 | 1444 | while (mask) { |
018aabb5 TY |
1445 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1446 | PT_PAGE_TABLE_LEVEL, slot); | |
1447 | __rmap_write_protect(kvm, rmap_head, false); | |
05da4558 | 1448 | |
5dc99b23 TY |
1449 | /* clear the first set bit */ |
1450 | mask &= mask - 1; | |
1451 | } | |
374cbac0 AK |
1452 | } |
1453 | ||
f4b4b180 KH |
1454 | /** |
1455 | * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages | |
1456 | * @kvm: kvm instance | |
1457 | * @slot: slot to clear D-bit | |
1458 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1459 | * @mask: indicates which pages we should clear D-bit | |
1460 | * | |
1461 | * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap. | |
1462 | */ | |
1463 | void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, | |
1464 | struct kvm_memory_slot *slot, | |
1465 | gfn_t gfn_offset, unsigned long mask) | |
1466 | { | |
018aabb5 | 1467 | struct kvm_rmap_head *rmap_head; |
f4b4b180 KH |
1468 | |
1469 | while (mask) { | |
018aabb5 TY |
1470 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1471 | PT_PAGE_TABLE_LEVEL, slot); | |
1472 | __rmap_clear_dirty(kvm, rmap_head); | |
f4b4b180 KH |
1473 | |
1474 | /* clear the first set bit */ | |
1475 | mask &= mask - 1; | |
1476 | } | |
1477 | } | |
1478 | EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked); | |
1479 | ||
3b0f1d01 KH |
1480 | /** |
1481 | * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected | |
1482 | * PT level pages. | |
1483 | * | |
1484 | * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to | |
1485 | * enable dirty logging for them. | |
1486 | * | |
1487 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1488 | * logging we do not have any such mappings. | |
1489 | */ | |
1490 | void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm, | |
1491 | struct kvm_memory_slot *slot, | |
1492 | gfn_t gfn_offset, unsigned long mask) | |
1493 | { | |
88178fd4 KH |
1494 | if (kvm_x86_ops->enable_log_dirty_pt_masked) |
1495 | kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset, | |
1496 | mask); | |
1497 | else | |
1498 | kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask); | |
3b0f1d01 KH |
1499 | } |
1500 | ||
aeecee2e XG |
1501 | bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm, |
1502 | struct kvm_memory_slot *slot, u64 gfn) | |
95d4c16c | 1503 | { |
018aabb5 | 1504 | struct kvm_rmap_head *rmap_head; |
5dc99b23 | 1505 | int i; |
2f84569f | 1506 | bool write_protected = false; |
95d4c16c | 1507 | |
8a3d08f1 | 1508 | for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { |
018aabb5 | 1509 | rmap_head = __gfn_to_rmap(gfn, i, slot); |
aeecee2e | 1510 | write_protected |= __rmap_write_protect(kvm, rmap_head, true); |
5dc99b23 TY |
1511 | } |
1512 | ||
1513 | return write_protected; | |
95d4c16c TY |
1514 | } |
1515 | ||
aeecee2e XG |
1516 | static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn) |
1517 | { | |
1518 | struct kvm_memory_slot *slot; | |
1519 | ||
1520 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); | |
1521 | return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn); | |
1522 | } | |
1523 | ||
018aabb5 | 1524 | static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
e930bffe | 1525 | { |
1e3f42f0 TY |
1526 | u64 *sptep; |
1527 | struct rmap_iterator iter; | |
6a49f85c | 1528 | bool flush = false; |
e930bffe | 1529 | |
018aabb5 | 1530 | while ((sptep = rmap_get_first(rmap_head, &iter))) { |
6a49f85c | 1531 | rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep); |
1e3f42f0 TY |
1532 | |
1533 | drop_spte(kvm, sptep); | |
6a49f85c | 1534 | flush = true; |
e930bffe | 1535 | } |
1e3f42f0 | 1536 | |
6a49f85c XG |
1537 | return flush; |
1538 | } | |
1539 | ||
018aabb5 | 1540 | static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
6a49f85c XG |
1541 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1542 | unsigned long data) | |
1543 | { | |
018aabb5 | 1544 | return kvm_zap_rmapp(kvm, rmap_head); |
e930bffe AA |
1545 | } |
1546 | ||
018aabb5 | 1547 | static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1548 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1549 | unsigned long data) | |
3da0dd43 | 1550 | { |
1e3f42f0 TY |
1551 | u64 *sptep; |
1552 | struct rmap_iterator iter; | |
3da0dd43 | 1553 | int need_flush = 0; |
1e3f42f0 | 1554 | u64 new_spte; |
3da0dd43 | 1555 | pte_t *ptep = (pte_t *)data; |
ba049e93 | 1556 | kvm_pfn_t new_pfn; |
3da0dd43 IE |
1557 | |
1558 | WARN_ON(pte_huge(*ptep)); | |
1559 | new_pfn = pte_pfn(*ptep); | |
1e3f42f0 | 1560 | |
0d536790 | 1561 | restart: |
018aabb5 | 1562 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
8a9522d2 | 1563 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n", |
f160c7b7 | 1564 | sptep, *sptep, gfn, level); |
1e3f42f0 | 1565 | |
3da0dd43 | 1566 | need_flush = 1; |
1e3f42f0 | 1567 | |
3da0dd43 | 1568 | if (pte_write(*ptep)) { |
1e3f42f0 | 1569 | drop_spte(kvm, sptep); |
0d536790 | 1570 | goto restart; |
3da0dd43 | 1571 | } else { |
1e3f42f0 | 1572 | new_spte = *sptep & ~PT64_BASE_ADDR_MASK; |
3da0dd43 IE |
1573 | new_spte |= (u64)new_pfn << PAGE_SHIFT; |
1574 | ||
1575 | new_spte &= ~PT_WRITABLE_MASK; | |
1576 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
f160c7b7 JS |
1577 | |
1578 | new_spte = mark_spte_for_access_track(new_spte); | |
1e3f42f0 TY |
1579 | |
1580 | mmu_spte_clear_track_bits(sptep); | |
1581 | mmu_spte_set(sptep, new_spte); | |
3da0dd43 IE |
1582 | } |
1583 | } | |
1e3f42f0 | 1584 | |
3da0dd43 IE |
1585 | if (need_flush) |
1586 | kvm_flush_remote_tlbs(kvm); | |
1587 | ||
1588 | return 0; | |
1589 | } | |
1590 | ||
6ce1f4e2 XG |
1591 | struct slot_rmap_walk_iterator { |
1592 | /* input fields. */ | |
1593 | struct kvm_memory_slot *slot; | |
1594 | gfn_t start_gfn; | |
1595 | gfn_t end_gfn; | |
1596 | int start_level; | |
1597 | int end_level; | |
1598 | ||
1599 | /* output fields. */ | |
1600 | gfn_t gfn; | |
018aabb5 | 1601 | struct kvm_rmap_head *rmap; |
6ce1f4e2 XG |
1602 | int level; |
1603 | ||
1604 | /* private field. */ | |
018aabb5 | 1605 | struct kvm_rmap_head *end_rmap; |
6ce1f4e2 XG |
1606 | }; |
1607 | ||
1608 | static void | |
1609 | rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level) | |
1610 | { | |
1611 | iterator->level = level; | |
1612 | iterator->gfn = iterator->start_gfn; | |
1613 | iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot); | |
1614 | iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level, | |
1615 | iterator->slot); | |
1616 | } | |
1617 | ||
1618 | static void | |
1619 | slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator, | |
1620 | struct kvm_memory_slot *slot, int start_level, | |
1621 | int end_level, gfn_t start_gfn, gfn_t end_gfn) | |
1622 | { | |
1623 | iterator->slot = slot; | |
1624 | iterator->start_level = start_level; | |
1625 | iterator->end_level = end_level; | |
1626 | iterator->start_gfn = start_gfn; | |
1627 | iterator->end_gfn = end_gfn; | |
1628 | ||
1629 | rmap_walk_init_level(iterator, iterator->start_level); | |
1630 | } | |
1631 | ||
1632 | static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator) | |
1633 | { | |
1634 | return !!iterator->rmap; | |
1635 | } | |
1636 | ||
1637 | static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator) | |
1638 | { | |
1639 | if (++iterator->rmap <= iterator->end_rmap) { | |
1640 | iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level)); | |
1641 | return; | |
1642 | } | |
1643 | ||
1644 | if (++iterator->level > iterator->end_level) { | |
1645 | iterator->rmap = NULL; | |
1646 | return; | |
1647 | } | |
1648 | ||
1649 | rmap_walk_init_level(iterator, iterator->level); | |
1650 | } | |
1651 | ||
1652 | #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \ | |
1653 | _start_gfn, _end_gfn, _iter_) \ | |
1654 | for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \ | |
1655 | _end_level_, _start_gfn, _end_gfn); \ | |
1656 | slot_rmap_walk_okay(_iter_); \ | |
1657 | slot_rmap_walk_next(_iter_)) | |
1658 | ||
84504ef3 TY |
1659 | static int kvm_handle_hva_range(struct kvm *kvm, |
1660 | unsigned long start, | |
1661 | unsigned long end, | |
1662 | unsigned long data, | |
1663 | int (*handler)(struct kvm *kvm, | |
018aabb5 | 1664 | struct kvm_rmap_head *rmap_head, |
048212d0 | 1665 | struct kvm_memory_slot *slot, |
8a9522d2 ALC |
1666 | gfn_t gfn, |
1667 | int level, | |
84504ef3 | 1668 | unsigned long data)) |
e930bffe | 1669 | { |
bc6678a3 | 1670 | struct kvm_memslots *slots; |
be6ba0f0 | 1671 | struct kvm_memory_slot *memslot; |
6ce1f4e2 XG |
1672 | struct slot_rmap_walk_iterator iterator; |
1673 | int ret = 0; | |
9da0e4d5 | 1674 | int i; |
bc6678a3 | 1675 | |
9da0e4d5 PB |
1676 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1677 | slots = __kvm_memslots(kvm, i); | |
1678 | kvm_for_each_memslot(memslot, slots) { | |
1679 | unsigned long hva_start, hva_end; | |
1680 | gfn_t gfn_start, gfn_end; | |
e930bffe | 1681 | |
9da0e4d5 PB |
1682 | hva_start = max(start, memslot->userspace_addr); |
1683 | hva_end = min(end, memslot->userspace_addr + | |
1684 | (memslot->npages << PAGE_SHIFT)); | |
1685 | if (hva_start >= hva_end) | |
1686 | continue; | |
1687 | /* | |
1688 | * {gfn(page) | page intersects with [hva_start, hva_end)} = | |
1689 | * {gfn_start, gfn_start+1, ..., gfn_end-1}. | |
1690 | */ | |
1691 | gfn_start = hva_to_gfn_memslot(hva_start, memslot); | |
1692 | gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot); | |
1693 | ||
1694 | for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL, | |
1695 | PT_MAX_HUGEPAGE_LEVEL, | |
1696 | gfn_start, gfn_end - 1, | |
1697 | &iterator) | |
1698 | ret |= handler(kvm, iterator.rmap, memslot, | |
1699 | iterator.gfn, iterator.level, data); | |
1700 | } | |
e930bffe AA |
1701 | } |
1702 | ||
f395302e | 1703 | return ret; |
e930bffe AA |
1704 | } |
1705 | ||
84504ef3 TY |
1706 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
1707 | unsigned long data, | |
018aabb5 TY |
1708 | int (*handler)(struct kvm *kvm, |
1709 | struct kvm_rmap_head *rmap_head, | |
048212d0 | 1710 | struct kvm_memory_slot *slot, |
8a9522d2 | 1711 | gfn_t gfn, int level, |
84504ef3 TY |
1712 | unsigned long data)) |
1713 | { | |
1714 | return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler); | |
e930bffe AA |
1715 | } |
1716 | ||
1717 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
1718 | { | |
3da0dd43 IE |
1719 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
1720 | } | |
1721 | ||
b3ae2096 TY |
1722 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end) |
1723 | { | |
1724 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp); | |
1725 | } | |
1726 | ||
3da0dd43 IE |
1727 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) |
1728 | { | |
8a8365c5 | 1729 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
1730 | } |
1731 | ||
018aabb5 | 1732 | static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1733 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1734 | unsigned long data) | |
e930bffe | 1735 | { |
1e3f42f0 | 1736 | u64 *sptep; |
79f702a6 | 1737 | struct rmap_iterator uninitialized_var(iter); |
e930bffe AA |
1738 | int young = 0; |
1739 | ||
f160c7b7 JS |
1740 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1741 | young |= mmu_spte_age(sptep); | |
0d536790 | 1742 | |
8a9522d2 | 1743 | trace_kvm_age_page(gfn, level, slot, young); |
e930bffe AA |
1744 | return young; |
1745 | } | |
1746 | ||
018aabb5 | 1747 | static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1748 | struct kvm_memory_slot *slot, gfn_t gfn, |
1749 | int level, unsigned long data) | |
8ee53820 | 1750 | { |
1e3f42f0 TY |
1751 | u64 *sptep; |
1752 | struct rmap_iterator iter; | |
8ee53820 AA |
1753 | |
1754 | /* | |
f160c7b7 JS |
1755 | * If there's no access bit in the secondary pte set by the hardware and |
1756 | * fast access tracking is also not enabled, it's up to gup-fast/gup to | |
1757 | * set the access bit in the primary pte or in the page structure. | |
8ee53820 | 1758 | */ |
f160c7b7 | 1759 | if (!shadow_accessed_mask && !shadow_acc_track_mask) |
8ee53820 AA |
1760 | goto out; |
1761 | ||
83ef6c81 JS |
1762 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1763 | if (is_accessed_spte(*sptep)) | |
1764 | return 1; | |
8ee53820 | 1765 | out: |
83ef6c81 | 1766 | return 0; |
8ee53820 AA |
1767 | } |
1768 | ||
53a27b39 MT |
1769 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1770 | ||
852e3c19 | 1771 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 | 1772 | { |
018aabb5 | 1773 | struct kvm_rmap_head *rmap_head; |
852e3c19 JR |
1774 | struct kvm_mmu_page *sp; |
1775 | ||
1776 | sp = page_header(__pa(spte)); | |
53a27b39 | 1777 | |
018aabb5 | 1778 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
53a27b39 | 1779 | |
018aabb5 | 1780 | kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0); |
53a27b39 MT |
1781 | kvm_flush_remote_tlbs(vcpu->kvm); |
1782 | } | |
1783 | ||
57128468 | 1784 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end) |
e930bffe | 1785 | { |
57128468 ALC |
1786 | /* |
1787 | * In case of absence of EPT Access and Dirty Bits supports, | |
1788 | * emulate the accessed bit for EPT, by checking if this page has | |
1789 | * an EPT mapping, and clearing it if it does. On the next access, | |
1790 | * a new EPT mapping will be established. | |
1791 | * This has some overhead, but not as much as the cost of swapping | |
1792 | * out actively used pages or breaking up actively used hugepages. | |
1793 | */ | |
f160c7b7 | 1794 | if (!shadow_accessed_mask && !shadow_acc_track_mask) |
57128468 ALC |
1795 | return kvm_handle_hva_range(kvm, start, end, 0, |
1796 | kvm_unmap_rmapp); | |
57128468 ALC |
1797 | |
1798 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp); | |
e930bffe AA |
1799 | } |
1800 | ||
8ee53820 AA |
1801 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) |
1802 | { | |
1803 | return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp); | |
1804 | } | |
1805 | ||
d6c69ee9 | 1806 | #ifdef MMU_DEBUG |
47ad8e68 | 1807 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1808 | { |
139bdb2d AK |
1809 | u64 *pos; |
1810 | u64 *end; | |
1811 | ||
47ad8e68 | 1812 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1813 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1814 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1815 | pos, *pos); |
6aa8b732 | 1816 | return 0; |
139bdb2d | 1817 | } |
6aa8b732 AK |
1818 | return 1; |
1819 | } | |
d6c69ee9 | 1820 | #endif |
6aa8b732 | 1821 | |
45221ab6 DH |
1822 | /* |
1823 | * This value is the sum of all of the kvm instances's | |
1824 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1825 | * aggregate version in order to make the slab shrinker | |
1826 | * faster | |
1827 | */ | |
1828 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr) | |
1829 | { | |
1830 | kvm->arch.n_used_mmu_pages += nr; | |
1831 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
1832 | } | |
1833 | ||
834be0d8 | 1834 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) |
260746c0 | 1835 | { |
fa4a2c08 | 1836 | MMU_WARN_ON(!is_empty_shadow_page(sp->spt)); |
7775834a | 1837 | hlist_del(&sp->hash_link); |
bd4c86ea XG |
1838 | list_del(&sp->link); |
1839 | free_page((unsigned long)sp->spt); | |
834be0d8 GN |
1840 | if (!sp->role.direct) |
1841 | free_page((unsigned long)sp->gfns); | |
e8ad9a70 | 1842 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
1843 | } |
1844 | ||
cea0f0e7 AK |
1845 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1846 | { | |
114df303 | 1847 | return hash_64(gfn, KVM_MMU_HASH_SHIFT); |
cea0f0e7 AK |
1848 | } |
1849 | ||
714b93da | 1850 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1851 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1852 | { |
cea0f0e7 AK |
1853 | if (!parent_pte) |
1854 | return; | |
cea0f0e7 | 1855 | |
67052b35 | 1856 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1857 | } |
1858 | ||
4db35314 | 1859 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1860 | u64 *parent_pte) |
1861 | { | |
67052b35 | 1862 | pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1863 | } |
1864 | ||
bcdd9a93 XG |
1865 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
1866 | u64 *parent_pte) | |
1867 | { | |
1868 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 1869 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
1870 | } |
1871 | ||
47005792 | 1872 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct) |
ad8cfbe3 | 1873 | { |
67052b35 | 1874 | struct kvm_mmu_page *sp; |
7ddca7e4 | 1875 | |
80feb89a TY |
1876 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache); |
1877 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); | |
67052b35 | 1878 | if (!direct) |
80feb89a | 1879 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); |
67052b35 | 1880 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
5304b8d3 XG |
1881 | |
1882 | /* | |
1883 | * The active_mmu_pages list is the FIFO list, do not move the | |
1884 | * page until it is zapped. kvm_zap_obsolete_pages depends on | |
1885 | * this feature. See the comments in kvm_zap_obsolete_pages(). | |
1886 | */ | |
67052b35 | 1887 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
67052b35 XG |
1888 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); |
1889 | return sp; | |
ad8cfbe3 MT |
1890 | } |
1891 | ||
67052b35 | 1892 | static void mark_unsync(u64 *spte); |
1047df1f | 1893 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 1894 | { |
74c4e63a TY |
1895 | u64 *sptep; |
1896 | struct rmap_iterator iter; | |
1897 | ||
1898 | for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) { | |
1899 | mark_unsync(sptep); | |
1900 | } | |
0074ff63 MT |
1901 | } |
1902 | ||
67052b35 | 1903 | static void mark_unsync(u64 *spte) |
0074ff63 | 1904 | { |
67052b35 | 1905 | struct kvm_mmu_page *sp; |
1047df1f | 1906 | unsigned int index; |
0074ff63 | 1907 | |
67052b35 | 1908 | sp = page_header(__pa(spte)); |
1047df1f XG |
1909 | index = spte - sp->spt; |
1910 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1911 | return; |
1047df1f | 1912 | if (sp->unsync_children++) |
0074ff63 | 1913 | return; |
1047df1f | 1914 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1915 | } |
1916 | ||
e8bc217a | 1917 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1918 | struct kvm_mmu_page *sp) |
e8bc217a | 1919 | { |
1f50f1b3 | 1920 | return 0; |
e8bc217a MT |
1921 | } |
1922 | ||
a7052897 MT |
1923 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1924 | { | |
1925 | } | |
1926 | ||
0f53b5b1 XG |
1927 | static void nonpaging_update_pte(struct kvm_vcpu *vcpu, |
1928 | struct kvm_mmu_page *sp, u64 *spte, | |
7c562522 | 1929 | const void *pte) |
0f53b5b1 XG |
1930 | { |
1931 | WARN_ON(1); | |
1932 | } | |
1933 | ||
60c8aec6 MT |
1934 | #define KVM_PAGE_ARRAY_NR 16 |
1935 | ||
1936 | struct kvm_mmu_pages { | |
1937 | struct mmu_page_and_offset { | |
1938 | struct kvm_mmu_page *sp; | |
1939 | unsigned int idx; | |
1940 | } page[KVM_PAGE_ARRAY_NR]; | |
1941 | unsigned int nr; | |
1942 | }; | |
1943 | ||
cded19f3 HE |
1944 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1945 | int idx) | |
4731d4c7 | 1946 | { |
60c8aec6 | 1947 | int i; |
4731d4c7 | 1948 | |
60c8aec6 MT |
1949 | if (sp->unsync) |
1950 | for (i=0; i < pvec->nr; i++) | |
1951 | if (pvec->page[i].sp == sp) | |
1952 | return 0; | |
1953 | ||
1954 | pvec->page[pvec->nr].sp = sp; | |
1955 | pvec->page[pvec->nr].idx = idx; | |
1956 | pvec->nr++; | |
1957 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1958 | } | |
1959 | ||
fd951457 TY |
1960 | static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx) |
1961 | { | |
1962 | --sp->unsync_children; | |
1963 | WARN_ON((int)sp->unsync_children < 0); | |
1964 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1965 | } | |
1966 | ||
60c8aec6 MT |
1967 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, |
1968 | struct kvm_mmu_pages *pvec) | |
1969 | { | |
1970 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1971 | |
37178b8b | 1972 | for_each_set_bit(i, sp->unsync_child_bitmap, 512) { |
7a8f1a74 | 1973 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1974 | u64 ent = sp->spt[i]; |
1975 | ||
fd951457 TY |
1976 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) { |
1977 | clear_unsync_child_bit(sp, i); | |
1978 | continue; | |
1979 | } | |
7a8f1a74 XG |
1980 | |
1981 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
1982 | ||
1983 | if (child->unsync_children) { | |
1984 | if (mmu_pages_add(pvec, child, i)) | |
1985 | return -ENOSPC; | |
1986 | ||
1987 | ret = __mmu_unsync_walk(child, pvec); | |
fd951457 TY |
1988 | if (!ret) { |
1989 | clear_unsync_child_bit(sp, i); | |
1990 | continue; | |
1991 | } else if (ret > 0) { | |
7a8f1a74 | 1992 | nr_unsync_leaf += ret; |
fd951457 | 1993 | } else |
7a8f1a74 XG |
1994 | return ret; |
1995 | } else if (child->unsync) { | |
1996 | nr_unsync_leaf++; | |
1997 | if (mmu_pages_add(pvec, child, i)) | |
1998 | return -ENOSPC; | |
1999 | } else | |
fd951457 | 2000 | clear_unsync_child_bit(sp, i); |
4731d4c7 MT |
2001 | } |
2002 | ||
60c8aec6 MT |
2003 | return nr_unsync_leaf; |
2004 | } | |
2005 | ||
e23d3fef XG |
2006 | #define INVALID_INDEX (-1) |
2007 | ||
60c8aec6 MT |
2008 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, |
2009 | struct kvm_mmu_pages *pvec) | |
2010 | { | |
0a47cd85 | 2011 | pvec->nr = 0; |
60c8aec6 MT |
2012 | if (!sp->unsync_children) |
2013 | return 0; | |
2014 | ||
e23d3fef | 2015 | mmu_pages_add(pvec, sp, INVALID_INDEX); |
60c8aec6 | 2016 | return __mmu_unsync_walk(sp, pvec); |
4731d4c7 MT |
2017 | } |
2018 | ||
4731d4c7 MT |
2019 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
2020 | { | |
2021 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 2022 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
2023 | sp->unsync = 0; |
2024 | --kvm->stat.mmu_unsync; | |
2025 | } | |
2026 | ||
7775834a XG |
2027 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
2028 | struct list_head *invalid_list); | |
2029 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
2030 | struct list_head *invalid_list); | |
4731d4c7 | 2031 | |
f34d251d XG |
2032 | /* |
2033 | * NOTE: we should pay more attention on the zapped-obsolete page | |
2034 | * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk | |
2035 | * since it has been deleted from active_mmu_pages but still can be found | |
2036 | * at hast list. | |
2037 | * | |
f3414bc7 | 2038 | * for_each_valid_sp() has skipped that kind of pages. |
f34d251d | 2039 | */ |
f3414bc7 | 2040 | #define for_each_valid_sp(_kvm, _sp, _gfn) \ |
1044b030 TY |
2041 | hlist_for_each_entry(_sp, \ |
2042 | &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \ | |
f3414bc7 DM |
2043 | if (is_obsolete_sp((_kvm), (_sp)) || (_sp)->role.invalid) { \ |
2044 | } else | |
1044b030 TY |
2045 | |
2046 | #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \ | |
f3414bc7 DM |
2047 | for_each_valid_sp(_kvm, _sp, _gfn) \ |
2048 | if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else | |
7ae680eb | 2049 | |
f918b443 | 2050 | /* @sp->gfn should be write-protected at the call site */ |
1f50f1b3 PB |
2051 | static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
2052 | struct list_head *invalid_list) | |
4731d4c7 | 2053 | { |
5b7e0102 | 2054 | if (sp->role.cr4_pae != !!is_pae(vcpu)) { |
d98ba053 | 2055 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
1f50f1b3 | 2056 | return false; |
4731d4c7 MT |
2057 | } |
2058 | ||
1f50f1b3 | 2059 | if (vcpu->arch.mmu.sync_page(vcpu, sp) == 0) { |
d98ba053 | 2060 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
1f50f1b3 | 2061 | return false; |
4731d4c7 MT |
2062 | } |
2063 | ||
1f50f1b3 | 2064 | return true; |
4731d4c7 MT |
2065 | } |
2066 | ||
35a70510 PB |
2067 | static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu, |
2068 | struct list_head *invalid_list, | |
2069 | bool remote_flush, bool local_flush) | |
1d9dc7e0 | 2070 | { |
35a70510 PB |
2071 | if (!list_empty(invalid_list)) { |
2072 | kvm_mmu_commit_zap_page(vcpu->kvm, invalid_list); | |
2073 | return; | |
2074 | } | |
d98ba053 | 2075 | |
35a70510 PB |
2076 | if (remote_flush) |
2077 | kvm_flush_remote_tlbs(vcpu->kvm); | |
2078 | else if (local_flush) | |
2079 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); | |
1d9dc7e0 XG |
2080 | } |
2081 | ||
e37fa785 XG |
2082 | #ifdef CONFIG_KVM_MMU_AUDIT |
2083 | #include "mmu_audit.c" | |
2084 | #else | |
2085 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { } | |
2086 | static void mmu_audit_disable(void) { } | |
2087 | #endif | |
2088 | ||
46971a2f XG |
2089 | static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp) |
2090 | { | |
2091 | return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen); | |
2092 | } | |
2093 | ||
1f50f1b3 | 2094 | static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 2095 | struct list_head *invalid_list) |
1d9dc7e0 | 2096 | { |
9a43c5d9 PB |
2097 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
2098 | return __kvm_sync_page(vcpu, sp, invalid_list); | |
1d9dc7e0 XG |
2099 | } |
2100 | ||
9f1a122f | 2101 | /* @gfn should be write-protected at the call site */ |
2a74003a PB |
2102 | static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn, |
2103 | struct list_head *invalid_list) | |
9f1a122f | 2104 | { |
9f1a122f | 2105 | struct kvm_mmu_page *s; |
2a74003a | 2106 | bool ret = false; |
9f1a122f | 2107 | |
b67bfe0d | 2108 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
7ae680eb | 2109 | if (!s->unsync) |
9f1a122f XG |
2110 | continue; |
2111 | ||
2112 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
2a74003a | 2113 | ret |= kvm_sync_page(vcpu, s, invalid_list); |
9f1a122f XG |
2114 | } |
2115 | ||
2a74003a | 2116 | return ret; |
9f1a122f XG |
2117 | } |
2118 | ||
60c8aec6 | 2119 | struct mmu_page_path { |
0a47cd85 PB |
2120 | struct kvm_mmu_page *parent[PT64_ROOT_LEVEL]; |
2121 | unsigned int idx[PT64_ROOT_LEVEL]; | |
4731d4c7 MT |
2122 | }; |
2123 | ||
60c8aec6 | 2124 | #define for_each_sp(pvec, sp, parents, i) \ |
0a47cd85 | 2125 | for (i = mmu_pages_first(&pvec, &parents); \ |
60c8aec6 MT |
2126 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ |
2127 | i = mmu_pages_next(&pvec, &parents, i)) | |
2128 | ||
cded19f3 HE |
2129 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
2130 | struct mmu_page_path *parents, | |
2131 | int i) | |
60c8aec6 MT |
2132 | { |
2133 | int n; | |
2134 | ||
2135 | for (n = i+1; n < pvec->nr; n++) { | |
2136 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
0a47cd85 PB |
2137 | unsigned idx = pvec->page[n].idx; |
2138 | int level = sp->role.level; | |
60c8aec6 | 2139 | |
0a47cd85 PB |
2140 | parents->idx[level-1] = idx; |
2141 | if (level == PT_PAGE_TABLE_LEVEL) | |
2142 | break; | |
60c8aec6 | 2143 | |
0a47cd85 | 2144 | parents->parent[level-2] = sp; |
60c8aec6 MT |
2145 | } |
2146 | ||
2147 | return n; | |
2148 | } | |
2149 | ||
0a47cd85 PB |
2150 | static int mmu_pages_first(struct kvm_mmu_pages *pvec, |
2151 | struct mmu_page_path *parents) | |
2152 | { | |
2153 | struct kvm_mmu_page *sp; | |
2154 | int level; | |
2155 | ||
2156 | if (pvec->nr == 0) | |
2157 | return 0; | |
2158 | ||
e23d3fef XG |
2159 | WARN_ON(pvec->page[0].idx != INVALID_INDEX); |
2160 | ||
0a47cd85 PB |
2161 | sp = pvec->page[0].sp; |
2162 | level = sp->role.level; | |
2163 | WARN_ON(level == PT_PAGE_TABLE_LEVEL); | |
2164 | ||
2165 | parents->parent[level-2] = sp; | |
2166 | ||
2167 | /* Also set up a sentinel. Further entries in pvec are all | |
2168 | * children of sp, so this element is never overwritten. | |
2169 | */ | |
2170 | parents->parent[level-1] = NULL; | |
2171 | return mmu_pages_next(pvec, parents, 0); | |
2172 | } | |
2173 | ||
cded19f3 | 2174 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 2175 | { |
60c8aec6 MT |
2176 | struct kvm_mmu_page *sp; |
2177 | unsigned int level = 0; | |
2178 | ||
2179 | do { | |
2180 | unsigned int idx = parents->idx[level]; | |
60c8aec6 MT |
2181 | sp = parents->parent[level]; |
2182 | if (!sp) | |
2183 | return; | |
2184 | ||
e23d3fef | 2185 | WARN_ON(idx == INVALID_INDEX); |
fd951457 | 2186 | clear_unsync_child_bit(sp, idx); |
60c8aec6 | 2187 | level++; |
0a47cd85 | 2188 | } while (!sp->unsync_children); |
60c8aec6 | 2189 | } |
4731d4c7 | 2190 | |
60c8aec6 MT |
2191 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
2192 | struct kvm_mmu_page *parent) | |
2193 | { | |
2194 | int i; | |
2195 | struct kvm_mmu_page *sp; | |
2196 | struct mmu_page_path parents; | |
2197 | struct kvm_mmu_pages pages; | |
d98ba053 | 2198 | LIST_HEAD(invalid_list); |
50c9e6f3 | 2199 | bool flush = false; |
60c8aec6 | 2200 | |
60c8aec6 | 2201 | while (mmu_unsync_walk(parent, &pages)) { |
2f84569f | 2202 | bool protected = false; |
b1a36821 MT |
2203 | |
2204 | for_each_sp(pages, sp, parents, i) | |
54bf36aa | 2205 | protected |= rmap_write_protect(vcpu, sp->gfn); |
b1a36821 | 2206 | |
50c9e6f3 | 2207 | if (protected) { |
b1a36821 | 2208 | kvm_flush_remote_tlbs(vcpu->kvm); |
50c9e6f3 PB |
2209 | flush = false; |
2210 | } | |
b1a36821 | 2211 | |
60c8aec6 | 2212 | for_each_sp(pages, sp, parents, i) { |
1f50f1b3 | 2213 | flush |= kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
2214 | mmu_pages_clear_parents(&parents); |
2215 | } | |
50c9e6f3 PB |
2216 | if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) { |
2217 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
2218 | cond_resched_lock(&vcpu->kvm->mmu_lock); | |
2219 | flush = false; | |
2220 | } | |
60c8aec6 | 2221 | } |
50c9e6f3 PB |
2222 | |
2223 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
4731d4c7 MT |
2224 | } |
2225 | ||
a30f47cb XG |
2226 | static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp) |
2227 | { | |
e5691a81 | 2228 | atomic_set(&sp->write_flooding_count, 0); |
a30f47cb XG |
2229 | } |
2230 | ||
2231 | static void clear_sp_write_flooding_count(u64 *spte) | |
2232 | { | |
2233 | struct kvm_mmu_page *sp = page_header(__pa(spte)); | |
2234 | ||
2235 | __clear_sp_write_flooding_count(sp); | |
2236 | } | |
2237 | ||
cea0f0e7 AK |
2238 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
2239 | gfn_t gfn, | |
2240 | gva_t gaddr, | |
2241 | unsigned level, | |
f6e2c02b | 2242 | int direct, |
bb11c6c9 | 2243 | unsigned access) |
cea0f0e7 AK |
2244 | { |
2245 | union kvm_mmu_page_role role; | |
cea0f0e7 | 2246 | unsigned quadrant; |
9f1a122f | 2247 | struct kvm_mmu_page *sp; |
9f1a122f | 2248 | bool need_sync = false; |
2a74003a | 2249 | bool flush = false; |
f3414bc7 | 2250 | int collisions = 0; |
2a74003a | 2251 | LIST_HEAD(invalid_list); |
cea0f0e7 | 2252 | |
a770f6f2 | 2253 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 2254 | role.level = level; |
f6e2c02b | 2255 | role.direct = direct; |
84b0c8c6 | 2256 | if (role.direct) |
5b7e0102 | 2257 | role.cr4_pae = 0; |
41074d07 | 2258 | role.access = access; |
c5a78f2b JR |
2259 | if (!vcpu->arch.mmu.direct_map |
2260 | && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { | |
cea0f0e7 AK |
2261 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
2262 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
2263 | role.quadrant = quadrant; | |
2264 | } | |
f3414bc7 DM |
2265 | for_each_valid_sp(vcpu->kvm, sp, gfn) { |
2266 | if (sp->gfn != gfn) { | |
2267 | collisions++; | |
2268 | continue; | |
2269 | } | |
2270 | ||
7ae680eb XG |
2271 | if (!need_sync && sp->unsync) |
2272 | need_sync = true; | |
4731d4c7 | 2273 | |
7ae680eb XG |
2274 | if (sp->role.word != role.word) |
2275 | continue; | |
4731d4c7 | 2276 | |
2a74003a PB |
2277 | if (sp->unsync) { |
2278 | /* The page is good, but __kvm_sync_page might still end | |
2279 | * up zapping it. If so, break in order to rebuild it. | |
2280 | */ | |
2281 | if (!__kvm_sync_page(vcpu, sp, &invalid_list)) | |
2282 | break; | |
2283 | ||
2284 | WARN_ON(!list_empty(&invalid_list)); | |
2285 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); | |
2286 | } | |
e02aa901 | 2287 | |
98bba238 | 2288 | if (sp->unsync_children) |
a8eeb04a | 2289 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
e02aa901 | 2290 | |
a30f47cb | 2291 | __clear_sp_write_flooding_count(sp); |
7ae680eb | 2292 | trace_kvm_mmu_get_page(sp, false); |
f3414bc7 | 2293 | goto out; |
7ae680eb | 2294 | } |
47005792 | 2295 | |
dfc5aa00 | 2296 | ++vcpu->kvm->stat.mmu_cache_miss; |
47005792 TY |
2297 | |
2298 | sp = kvm_mmu_alloc_page(vcpu, direct); | |
2299 | ||
4db35314 AK |
2300 | sp->gfn = gfn; |
2301 | sp->role = role; | |
7ae680eb XG |
2302 | hlist_add_head(&sp->hash_link, |
2303 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 2304 | if (!direct) { |
56ca57f9 XG |
2305 | /* |
2306 | * we should do write protection before syncing pages | |
2307 | * otherwise the content of the synced shadow page may | |
2308 | * be inconsistent with guest page table. | |
2309 | */ | |
2310 | account_shadowed(vcpu->kvm, sp); | |
2311 | if (level == PT_PAGE_TABLE_LEVEL && | |
2312 | rmap_write_protect(vcpu, gfn)) | |
b1a36821 | 2313 | kvm_flush_remote_tlbs(vcpu->kvm); |
9f1a122f | 2314 | |
9f1a122f | 2315 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
2a74003a | 2316 | flush |= kvm_sync_pages(vcpu, gfn, &invalid_list); |
4731d4c7 | 2317 | } |
5304b8d3 | 2318 | sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen; |
77492664 | 2319 | clear_page(sp->spt); |
f691fe1d | 2320 | trace_kvm_mmu_get_page(sp, true); |
2a74003a PB |
2321 | |
2322 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
f3414bc7 DM |
2323 | out: |
2324 | if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions) | |
2325 | vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions; | |
4db35314 | 2326 | return sp; |
cea0f0e7 AK |
2327 | } |
2328 | ||
2d11123a AK |
2329 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
2330 | struct kvm_vcpu *vcpu, u64 addr) | |
2331 | { | |
2332 | iterator->addr = addr; | |
2333 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
2334 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
81407ca5 JR |
2335 | |
2336 | if (iterator->level == PT64_ROOT_LEVEL && | |
2337 | vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL && | |
2338 | !vcpu->arch.mmu.direct_map) | |
2339 | --iterator->level; | |
2340 | ||
2d11123a AK |
2341 | if (iterator->level == PT32E_ROOT_LEVEL) { |
2342 | iterator->shadow_addr | |
2343 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
2344 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
2345 | --iterator->level; | |
2346 | if (!iterator->shadow_addr) | |
2347 | iterator->level = 0; | |
2348 | } | |
2349 | } | |
2350 | ||
2351 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
2352 | { | |
2353 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
2354 | return false; | |
4d88954d | 2355 | |
2d11123a AK |
2356 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
2357 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
2358 | return true; | |
2359 | } | |
2360 | ||
c2a2ac2b XG |
2361 | static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator, |
2362 | u64 spte) | |
2d11123a | 2363 | { |
c2a2ac2b | 2364 | if (is_last_spte(spte, iterator->level)) { |
052331be XG |
2365 | iterator->level = 0; |
2366 | return; | |
2367 | } | |
2368 | ||
c2a2ac2b | 2369 | iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK; |
2d11123a AK |
2370 | --iterator->level; |
2371 | } | |
2372 | ||
c2a2ac2b XG |
2373 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) |
2374 | { | |
2375 | return __shadow_walk_next(iterator, *iterator->sptep); | |
2376 | } | |
2377 | ||
98bba238 TY |
2378 | static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep, |
2379 | struct kvm_mmu_page *sp) | |
32ef26a3 AK |
2380 | { |
2381 | u64 spte; | |
2382 | ||
ffb128c8 | 2383 | BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK); |
7a1638ce | 2384 | |
ffb128c8 | 2385 | spte = __pa(sp->spt) | shadow_present_mask | PT_WRITABLE_MASK | |
0e3d0648 | 2386 | shadow_user_mask | shadow_x_mask | shadow_accessed_mask; |
24db2734 | 2387 | |
1df9f2dc | 2388 | mmu_spte_set(sptep, spte); |
98bba238 TY |
2389 | |
2390 | mmu_page_add_parent_pte(vcpu, sp, sptep); | |
2391 | ||
2392 | if (sp->unsync_children || sp->unsync) | |
2393 | mark_unsync(sptep); | |
32ef26a3 AK |
2394 | } |
2395 | ||
a357bd22 AK |
2396 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
2397 | unsigned direct_access) | |
2398 | { | |
2399 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
2400 | struct kvm_mmu_page *child; | |
2401 | ||
2402 | /* | |
2403 | * For the direct sp, if the guest pte's dirty bit | |
2404 | * changed form clean to dirty, it will corrupt the | |
2405 | * sp's access: allow writable in the read-only sp, | |
2406 | * so we should update the spte at this point to get | |
2407 | * a new sp with the correct access. | |
2408 | */ | |
2409 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
2410 | if (child->role.access == direct_access) | |
2411 | return; | |
2412 | ||
bcdd9a93 | 2413 | drop_parent_pte(child, sptep); |
a357bd22 AK |
2414 | kvm_flush_remote_tlbs(vcpu->kvm); |
2415 | } | |
2416 | } | |
2417 | ||
505aef8f | 2418 | static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, |
38e3b2b2 XG |
2419 | u64 *spte) |
2420 | { | |
2421 | u64 pte; | |
2422 | struct kvm_mmu_page *child; | |
2423 | ||
2424 | pte = *spte; | |
2425 | if (is_shadow_present_pte(pte)) { | |
505aef8f | 2426 | if (is_last_spte(pte, sp->role.level)) { |
c3707958 | 2427 | drop_spte(kvm, spte); |
505aef8f XG |
2428 | if (is_large_pte(pte)) |
2429 | --kvm->stat.lpages; | |
2430 | } else { | |
38e3b2b2 | 2431 | child = page_header(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2432 | drop_parent_pte(child, spte); |
38e3b2b2 | 2433 | } |
505aef8f XG |
2434 | return true; |
2435 | } | |
2436 | ||
2437 | if (is_mmio_spte(pte)) | |
ce88decf | 2438 | mmu_spte_clear_no_track(spte); |
c3707958 | 2439 | |
505aef8f | 2440 | return false; |
38e3b2b2 XG |
2441 | } |
2442 | ||
90cb0529 | 2443 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 2444 | struct kvm_mmu_page *sp) |
a436036b | 2445 | { |
697fe2e2 | 2446 | unsigned i; |
697fe2e2 | 2447 | |
38e3b2b2 XG |
2448 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
2449 | mmu_page_zap_pte(kvm, sp, sp->spt + i); | |
a436036b AK |
2450 | } |
2451 | ||
31aa2b44 | 2452 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b | 2453 | { |
1e3f42f0 TY |
2454 | u64 *sptep; |
2455 | struct rmap_iterator iter; | |
a436036b | 2456 | |
018aabb5 | 2457 | while ((sptep = rmap_get_first(&sp->parent_ptes, &iter))) |
1e3f42f0 | 2458 | drop_parent_pte(sp, sptep); |
31aa2b44 AK |
2459 | } |
2460 | ||
60c8aec6 | 2461 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
2462 | struct kvm_mmu_page *parent, |
2463 | struct list_head *invalid_list) | |
4731d4c7 | 2464 | { |
60c8aec6 MT |
2465 | int i, zapped = 0; |
2466 | struct mmu_page_path parents; | |
2467 | struct kvm_mmu_pages pages; | |
4731d4c7 | 2468 | |
60c8aec6 | 2469 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2470 | return 0; |
60c8aec6 | 2471 | |
60c8aec6 MT |
2472 | while (mmu_unsync_walk(parent, &pages)) { |
2473 | struct kvm_mmu_page *sp; | |
2474 | ||
2475 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 2476 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 2477 | mmu_pages_clear_parents(&parents); |
77662e00 | 2478 | zapped++; |
60c8aec6 | 2479 | } |
60c8aec6 MT |
2480 | } |
2481 | ||
2482 | return zapped; | |
4731d4c7 MT |
2483 | } |
2484 | ||
7775834a XG |
2485 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
2486 | struct list_head *invalid_list) | |
31aa2b44 | 2487 | { |
4731d4c7 | 2488 | int ret; |
f691fe1d | 2489 | |
7775834a | 2490 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 2491 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 2492 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 2493 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 2494 | kvm_mmu_unlink_parents(kvm, sp); |
5304b8d3 | 2495 | |
f6e2c02b | 2496 | if (!sp->role.invalid && !sp->role.direct) |
3ed1a478 | 2497 | unaccount_shadowed(kvm, sp); |
5304b8d3 | 2498 | |
4731d4c7 MT |
2499 | if (sp->unsync) |
2500 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 2501 | if (!sp->root_count) { |
54a4f023 GJ |
2502 | /* Count self */ |
2503 | ret++; | |
7775834a | 2504 | list_move(&sp->link, invalid_list); |
aa6bd187 | 2505 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 2506 | } else { |
5b5c6a5a | 2507 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
05988d72 GN |
2508 | |
2509 | /* | |
2510 | * The obsolete pages can not be used on any vcpus. | |
2511 | * See the comments in kvm_mmu_invalidate_zap_all_pages(). | |
2512 | */ | |
2513 | if (!sp->role.invalid && !is_obsolete_sp(kvm, sp)) | |
2514 | kvm_reload_remote_mmus(kvm); | |
2e53d63a | 2515 | } |
7775834a XG |
2516 | |
2517 | sp->role.invalid = 1; | |
4731d4c7 | 2518 | return ret; |
a436036b AK |
2519 | } |
2520 | ||
7775834a XG |
2521 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
2522 | struct list_head *invalid_list) | |
2523 | { | |
945315b9 | 2524 | struct kvm_mmu_page *sp, *nsp; |
7775834a XG |
2525 | |
2526 | if (list_empty(invalid_list)) | |
2527 | return; | |
2528 | ||
c142786c | 2529 | /* |
9753f529 LT |
2530 | * We need to make sure everyone sees our modifications to |
2531 | * the page tables and see changes to vcpu->mode here. The barrier | |
2532 | * in the kvm_flush_remote_tlbs() achieves this. This pairs | |
2533 | * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end. | |
2534 | * | |
2535 | * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit | |
2536 | * guest mode and/or lockless shadow page table walks. | |
c142786c AK |
2537 | */ |
2538 | kvm_flush_remote_tlbs(kvm); | |
c2a2ac2b | 2539 | |
945315b9 | 2540 | list_for_each_entry_safe(sp, nsp, invalid_list, link) { |
7775834a | 2541 | WARN_ON(!sp->role.invalid || sp->root_count); |
aa6bd187 | 2542 | kvm_mmu_free_page(sp); |
945315b9 | 2543 | } |
7775834a XG |
2544 | } |
2545 | ||
5da59607 TY |
2546 | static bool prepare_zap_oldest_mmu_page(struct kvm *kvm, |
2547 | struct list_head *invalid_list) | |
2548 | { | |
2549 | struct kvm_mmu_page *sp; | |
2550 | ||
2551 | if (list_empty(&kvm->arch.active_mmu_pages)) | |
2552 | return false; | |
2553 | ||
d74c0e6b GT |
2554 | sp = list_last_entry(&kvm->arch.active_mmu_pages, |
2555 | struct kvm_mmu_page, link); | |
5da59607 TY |
2556 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
2557 | ||
2558 | return true; | |
2559 | } | |
2560 | ||
82ce2c96 IE |
2561 | /* |
2562 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 2563 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 2564 | */ |
49d5ca26 | 2565 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages) |
82ce2c96 | 2566 | { |
d98ba053 | 2567 | LIST_HEAD(invalid_list); |
82ce2c96 | 2568 | |
b34cb590 TY |
2569 | spin_lock(&kvm->mmu_lock); |
2570 | ||
49d5ca26 | 2571 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
5da59607 TY |
2572 | /* Need to free some mmu pages to achieve the goal. */ |
2573 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) | |
2574 | if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list)) | |
2575 | break; | |
82ce2c96 | 2576 | |
aa6bd187 | 2577 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
49d5ca26 | 2578 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 2579 | } |
82ce2c96 | 2580 | |
49d5ca26 | 2581 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
b34cb590 TY |
2582 | |
2583 | spin_unlock(&kvm->mmu_lock); | |
82ce2c96 IE |
2584 | } |
2585 | ||
1cb3f3ae | 2586 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 2587 | { |
4db35314 | 2588 | struct kvm_mmu_page *sp; |
d98ba053 | 2589 | LIST_HEAD(invalid_list); |
a436036b AK |
2590 | int r; |
2591 | ||
9ad17b10 | 2592 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 2593 | r = 0; |
1cb3f3ae | 2594 | spin_lock(&kvm->mmu_lock); |
b67bfe0d | 2595 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn) { |
9ad17b10 | 2596 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
2597 | sp->role.word); |
2598 | r = 1; | |
f41d335a | 2599 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 2600 | } |
d98ba053 | 2601 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
1cb3f3ae XG |
2602 | spin_unlock(&kvm->mmu_lock); |
2603 | ||
a436036b | 2604 | return r; |
cea0f0e7 | 2605 | } |
1cb3f3ae | 2606 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page); |
cea0f0e7 | 2607 | |
5c520e90 | 2608 | static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
9cf5cf5a XG |
2609 | { |
2610 | trace_kvm_mmu_unsync_page(sp); | |
2611 | ++vcpu->kvm->stat.mmu_unsync; | |
2612 | sp->unsync = 1; | |
2613 | ||
2614 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
2615 | } |
2616 | ||
3d0c27ad XG |
2617 | static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, |
2618 | bool can_unsync) | |
4731d4c7 | 2619 | { |
5c520e90 | 2620 | struct kvm_mmu_page *sp; |
4731d4c7 | 2621 | |
3d0c27ad XG |
2622 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) |
2623 | return true; | |
9cf5cf5a | 2624 | |
5c520e90 | 2625 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
36a2e677 | 2626 | if (!can_unsync) |
3d0c27ad | 2627 | return true; |
36a2e677 | 2628 | |
5c520e90 XG |
2629 | if (sp->unsync) |
2630 | continue; | |
9cf5cf5a | 2631 | |
5c520e90 XG |
2632 | WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL); |
2633 | kvm_unsync_page(vcpu, sp); | |
4731d4c7 | 2634 | } |
3d0c27ad XG |
2635 | |
2636 | return false; | |
4731d4c7 MT |
2637 | } |
2638 | ||
ba049e93 | 2639 | static bool kvm_is_mmio_pfn(kvm_pfn_t pfn) |
d1fe9219 PB |
2640 | { |
2641 | if (pfn_valid(pfn)) | |
2642 | return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)); | |
2643 | ||
2644 | return true; | |
2645 | } | |
2646 | ||
d555c333 | 2647 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
c2288505 | 2648 | unsigned pte_access, int level, |
ba049e93 | 2649 | gfn_t gfn, kvm_pfn_t pfn, bool speculative, |
9bdbba13 | 2650 | bool can_unsync, bool host_writable) |
1c4f1fd6 | 2651 | { |
ffb128c8 | 2652 | u64 spte = 0; |
1e73f9dd | 2653 | int ret = 0; |
64d4d521 | 2654 | |
54bf36aa | 2655 | if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access)) |
ce88decf XG |
2656 | return 0; |
2657 | ||
d95c5568 BD |
2658 | /* |
2659 | * For the EPT case, shadow_present_mask is 0 if hardware | |
2660 | * supports exec-only page table entries. In that case, | |
2661 | * ACC_USER_MASK and shadow_user_mask are used to represent | |
2662 | * read access. See FNAME(gpte_access) in paging_tmpl.h. | |
2663 | */ | |
ffb128c8 | 2664 | spte |= shadow_present_mask; |
947da538 | 2665 | if (!speculative) |
3201b5d9 | 2666 | spte |= shadow_accessed_mask; |
640d9b0d | 2667 | |
7b52345e SY |
2668 | if (pte_access & ACC_EXEC_MASK) |
2669 | spte |= shadow_x_mask; | |
2670 | else | |
2671 | spte |= shadow_nx_mask; | |
49fde340 | 2672 | |
1c4f1fd6 | 2673 | if (pte_access & ACC_USER_MASK) |
7b52345e | 2674 | spte |= shadow_user_mask; |
49fde340 | 2675 | |
852e3c19 | 2676 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 2677 | spte |= PT_PAGE_SIZE_MASK; |
b0bc3ee2 | 2678 | if (tdp_enabled) |
4b12f0de | 2679 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, |
d1fe9219 | 2680 | kvm_is_mmio_pfn(pfn)); |
1c4f1fd6 | 2681 | |
9bdbba13 | 2682 | if (host_writable) |
1403283a | 2683 | spte |= SPTE_HOST_WRITEABLE; |
f8e453b0 XG |
2684 | else |
2685 | pte_access &= ~ACC_WRITE_MASK; | |
1403283a | 2686 | |
35149e21 | 2687 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 | 2688 | |
c2288505 | 2689 | if (pte_access & ACC_WRITE_MASK) { |
1c4f1fd6 | 2690 | |
c2193463 | 2691 | /* |
7751babd XG |
2692 | * Other vcpu creates new sp in the window between |
2693 | * mapping_level() and acquiring mmu-lock. We can | |
2694 | * allow guest to retry the access, the mapping can | |
2695 | * be fixed if guest refault. | |
c2193463 | 2696 | */ |
852e3c19 | 2697 | if (level > PT_PAGE_TABLE_LEVEL && |
92f94f1e | 2698 | mmu_gfn_lpage_is_disallowed(vcpu, gfn, level)) |
be38d276 | 2699 | goto done; |
38187c83 | 2700 | |
49fde340 | 2701 | spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE; |
1c4f1fd6 | 2702 | |
ecc5589f MT |
2703 | /* |
2704 | * Optimization: for pte sync, if spte was writable the hash | |
2705 | * lookup is unnecessary (and expensive). Write protection | |
2706 | * is responsibility of mmu_get_page / kvm_sync_page. | |
2707 | * Same reasoning can be applied to dirty page accounting. | |
2708 | */ | |
8dae4445 | 2709 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
2710 | goto set_pte; |
2711 | ||
4731d4c7 | 2712 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
9ad17b10 | 2713 | pgprintk("%s: found shadow page for %llx, marking ro\n", |
b8688d51 | 2714 | __func__, gfn); |
1e73f9dd | 2715 | ret = 1; |
1c4f1fd6 | 2716 | pte_access &= ~ACC_WRITE_MASK; |
49fde340 | 2717 | spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE); |
1c4f1fd6 AK |
2718 | } |
2719 | } | |
2720 | ||
9b51a630 | 2721 | if (pte_access & ACC_WRITE_MASK) { |
54bf36aa | 2722 | kvm_vcpu_mark_page_dirty(vcpu, gfn); |
9b51a630 KH |
2723 | spte |= shadow_dirty_mask; |
2724 | } | |
1c4f1fd6 | 2725 | |
f160c7b7 JS |
2726 | if (speculative) |
2727 | spte = mark_spte_for_access_track(spte); | |
2728 | ||
38187c83 | 2729 | set_pte: |
6e7d0354 | 2730 | if (mmu_spte_update(sptep, spte)) |
b330aa0c | 2731 | kvm_flush_remote_tlbs(vcpu->kvm); |
be38d276 | 2732 | done: |
1e73f9dd MT |
2733 | return ret; |
2734 | } | |
2735 | ||
029499b4 | 2736 | static bool mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, unsigned pte_access, |
ba049e93 | 2737 | int write_fault, int level, gfn_t gfn, kvm_pfn_t pfn, |
029499b4 | 2738 | bool speculative, bool host_writable) |
1e73f9dd MT |
2739 | { |
2740 | int was_rmapped = 0; | |
53a27b39 | 2741 | int rmap_count; |
029499b4 | 2742 | bool emulate = false; |
1e73f9dd | 2743 | |
f7616203 XG |
2744 | pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__, |
2745 | *sptep, write_fault, gfn); | |
1e73f9dd | 2746 | |
afd28fe1 | 2747 | if (is_shadow_present_pte(*sptep)) { |
1e73f9dd MT |
2748 | /* |
2749 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2750 | * the parent of the now unreachable PTE. | |
2751 | */ | |
852e3c19 JR |
2752 | if (level > PT_PAGE_TABLE_LEVEL && |
2753 | !is_large_pte(*sptep)) { | |
1e73f9dd | 2754 | struct kvm_mmu_page *child; |
d555c333 | 2755 | u64 pte = *sptep; |
1e73f9dd MT |
2756 | |
2757 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
bcdd9a93 | 2758 | drop_parent_pte(child, sptep); |
3be2264b | 2759 | kvm_flush_remote_tlbs(vcpu->kvm); |
d555c333 | 2760 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2761 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2762 | spte_to_pfn(*sptep), pfn); |
c3707958 | 2763 | drop_spte(vcpu->kvm, sptep); |
91546356 | 2764 | kvm_flush_remote_tlbs(vcpu->kvm); |
6bed6b9e JR |
2765 | } else |
2766 | was_rmapped = 1; | |
1e73f9dd | 2767 | } |
852e3c19 | 2768 | |
c2288505 XG |
2769 | if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative, |
2770 | true, host_writable)) { | |
1e73f9dd | 2771 | if (write_fault) |
029499b4 | 2772 | emulate = true; |
77c3913b | 2773 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
a378b4e6 | 2774 | } |
1e73f9dd | 2775 | |
029499b4 TY |
2776 | if (unlikely(is_mmio_spte(*sptep))) |
2777 | emulate = true; | |
ce88decf | 2778 | |
d555c333 | 2779 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
9ad17b10 | 2780 | pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n", |
d555c333 | 2781 | is_large_pte(*sptep)? "2MB" : "4kB", |
f160c7b7 | 2782 | *sptep & PT_WRITABLE_MASK ? "RW" : "R", gfn, |
a205bc19 | 2783 | *sptep, sptep); |
d555c333 | 2784 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2785 | ++vcpu->kvm->stat.lpages; |
2786 | ||
ffb61bb3 | 2787 | if (is_shadow_present_pte(*sptep)) { |
ffb61bb3 XG |
2788 | if (!was_rmapped) { |
2789 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
2790 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
2791 | rmap_recycle(vcpu, sptep, gfn); | |
2792 | } | |
1c4f1fd6 | 2793 | } |
cb9aaa30 | 2794 | |
f3ac1a4b | 2795 | kvm_release_pfn_clean(pfn); |
029499b4 TY |
2796 | |
2797 | return emulate; | |
1c4f1fd6 AK |
2798 | } |
2799 | ||
ba049e93 | 2800 | static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
957ed9ef XG |
2801 | bool no_dirty_log) |
2802 | { | |
2803 | struct kvm_memory_slot *slot; | |
957ed9ef | 2804 | |
5d163b1c | 2805 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
903816fa | 2806 | if (!slot) |
6c8ee57b | 2807 | return KVM_PFN_ERR_FAULT; |
957ed9ef | 2808 | |
037d92dc | 2809 | return gfn_to_pfn_memslot_atomic(slot, gfn); |
957ed9ef XG |
2810 | } |
2811 | ||
2812 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
2813 | struct kvm_mmu_page *sp, | |
2814 | u64 *start, u64 *end) | |
2815 | { | |
2816 | struct page *pages[PTE_PREFETCH_NUM]; | |
d9ef13c2 | 2817 | struct kvm_memory_slot *slot; |
957ed9ef XG |
2818 | unsigned access = sp->role.access; |
2819 | int i, ret; | |
2820 | gfn_t gfn; | |
2821 | ||
2822 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
d9ef13c2 PB |
2823 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK); |
2824 | if (!slot) | |
957ed9ef XG |
2825 | return -1; |
2826 | ||
d9ef13c2 | 2827 | ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start); |
957ed9ef XG |
2828 | if (ret <= 0) |
2829 | return -1; | |
2830 | ||
2831 | for (i = 0; i < ret; i++, gfn++, start++) | |
029499b4 TY |
2832 | mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn, |
2833 | page_to_pfn(pages[i]), true, true); | |
957ed9ef XG |
2834 | |
2835 | return 0; | |
2836 | } | |
2837 | ||
2838 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2839 | struct kvm_mmu_page *sp, u64 *sptep) | |
2840 | { | |
2841 | u64 *spte, *start = NULL; | |
2842 | int i; | |
2843 | ||
2844 | WARN_ON(!sp->role.direct); | |
2845 | ||
2846 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2847 | spte = sp->spt + i; | |
2848 | ||
2849 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 2850 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
2851 | if (!start) |
2852 | continue; | |
2853 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2854 | break; | |
2855 | start = NULL; | |
2856 | } else if (!start) | |
2857 | start = spte; | |
2858 | } | |
2859 | } | |
2860 | ||
2861 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2862 | { | |
2863 | struct kvm_mmu_page *sp; | |
2864 | ||
2865 | /* | |
2866 | * Since it's no accessed bit on EPT, it's no way to | |
2867 | * distinguish between actually accessed translations | |
2868 | * and prefetched, so disable pte prefetch if EPT is | |
2869 | * enabled. | |
2870 | */ | |
2871 | if (!shadow_accessed_mask) | |
2872 | return; | |
2873 | ||
2874 | sp = page_header(__pa(sptep)); | |
2875 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
2876 | return; | |
2877 | ||
2878 | __direct_pte_prefetch(vcpu, sp, sptep); | |
2879 | } | |
2880 | ||
7ee0e5b2 | 2881 | static int __direct_map(struct kvm_vcpu *vcpu, int write, int map_writable, |
ba049e93 | 2882 | int level, gfn_t gfn, kvm_pfn_t pfn, bool prefault) |
140754bc | 2883 | { |
9f652d21 | 2884 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 2885 | struct kvm_mmu_page *sp; |
b90a0e6c | 2886 | int emulate = 0; |
140754bc | 2887 | gfn_t pseudo_gfn; |
6aa8b732 | 2888 | |
989c6b34 MT |
2889 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
2890 | return 0; | |
2891 | ||
9f652d21 | 2892 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 2893 | if (iterator.level == level) { |
029499b4 TY |
2894 | emulate = mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, |
2895 | write, level, gfn, pfn, prefault, | |
2896 | map_writable); | |
957ed9ef | 2897 | direct_pte_prefetch(vcpu, iterator.sptep); |
9f652d21 AK |
2898 | ++vcpu->stat.pf_fixed; |
2899 | break; | |
6aa8b732 AK |
2900 | } |
2901 | ||
404381c5 | 2902 | drop_large_spte(vcpu, iterator.sptep); |
c3707958 | 2903 | if (!is_shadow_present_pte(*iterator.sptep)) { |
c9fa0b3b LJ |
2904 | u64 base_addr = iterator.addr; |
2905 | ||
2906 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
2907 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 | 2908 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
bb11c6c9 | 2909 | iterator.level - 1, 1, ACC_ALL); |
140754bc | 2910 | |
98bba238 | 2911 | link_shadow_page(vcpu, iterator.sptep, sp); |
9f652d21 AK |
2912 | } |
2913 | } | |
b90a0e6c | 2914 | return emulate; |
6aa8b732 AK |
2915 | } |
2916 | ||
77db5cbd | 2917 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 2918 | { |
77db5cbd HY |
2919 | siginfo_t info; |
2920 | ||
2921 | info.si_signo = SIGBUS; | |
2922 | info.si_errno = 0; | |
2923 | info.si_code = BUS_MCEERR_AR; | |
2924 | info.si_addr = (void __user *)address; | |
2925 | info.si_addr_lsb = PAGE_SHIFT; | |
bf998156 | 2926 | |
77db5cbd | 2927 | send_sig_info(SIGBUS, &info, tsk); |
bf998156 HY |
2928 | } |
2929 | ||
ba049e93 | 2930 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn) |
bf998156 | 2931 | { |
4d8b81ab XG |
2932 | /* |
2933 | * Do not cache the mmio info caused by writing the readonly gfn | |
2934 | * into the spte otherwise read access on readonly gfn also can | |
2935 | * caused mmio page fault and treat it as mmio access. | |
2936 | * Return 1 to tell kvm to emulate it. | |
2937 | */ | |
2938 | if (pfn == KVM_PFN_ERR_RO_FAULT) | |
2939 | return 1; | |
2940 | ||
e6c1502b | 2941 | if (pfn == KVM_PFN_ERR_HWPOISON) { |
54bf36aa | 2942 | kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current); |
bf998156 | 2943 | return 0; |
d7c55201 | 2944 | } |
edba23e5 | 2945 | |
d7c55201 | 2946 | return -EFAULT; |
bf998156 HY |
2947 | } |
2948 | ||
936a5fe6 | 2949 | static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu, |
ba049e93 DW |
2950 | gfn_t *gfnp, kvm_pfn_t *pfnp, |
2951 | int *levelp) | |
936a5fe6 | 2952 | { |
ba049e93 | 2953 | kvm_pfn_t pfn = *pfnp; |
936a5fe6 AA |
2954 | gfn_t gfn = *gfnp; |
2955 | int level = *levelp; | |
2956 | ||
2957 | /* | |
2958 | * Check if it's a transparent hugepage. If this would be an | |
2959 | * hugetlbfs page, level wouldn't be set to | |
2960 | * PT_PAGE_TABLE_LEVEL and there would be no adjustment done | |
2961 | * here. | |
2962 | */ | |
bf4bea8e | 2963 | if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) && |
936a5fe6 | 2964 | level == PT_PAGE_TABLE_LEVEL && |
127393fb | 2965 | PageTransCompoundMap(pfn_to_page(pfn)) && |
92f94f1e | 2966 | !mmu_gfn_lpage_is_disallowed(vcpu, gfn, PT_DIRECTORY_LEVEL)) { |
936a5fe6 AA |
2967 | unsigned long mask; |
2968 | /* | |
2969 | * mmu_notifier_retry was successful and we hold the | |
2970 | * mmu_lock here, so the pmd can't become splitting | |
2971 | * from under us, and in turn | |
2972 | * __split_huge_page_refcount() can't run from under | |
2973 | * us and we can safely transfer the refcount from | |
2974 | * PG_tail to PG_head as we switch the pfn to tail to | |
2975 | * head. | |
2976 | */ | |
2977 | *levelp = level = PT_DIRECTORY_LEVEL; | |
2978 | mask = KVM_PAGES_PER_HPAGE(level) - 1; | |
2979 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
2980 | if (pfn & mask) { | |
2981 | gfn &= ~mask; | |
2982 | *gfnp = gfn; | |
2983 | kvm_release_pfn_clean(pfn); | |
2984 | pfn &= ~mask; | |
c3586667 | 2985 | kvm_get_pfn(pfn); |
936a5fe6 AA |
2986 | *pfnp = pfn; |
2987 | } | |
2988 | } | |
2989 | } | |
2990 | ||
d7c55201 | 2991 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, |
ba049e93 | 2992 | kvm_pfn_t pfn, unsigned access, int *ret_val) |
d7c55201 | 2993 | { |
d7c55201 | 2994 | /* The pfn is invalid, report the error! */ |
81c52c56 | 2995 | if (unlikely(is_error_pfn(pfn))) { |
d7c55201 | 2996 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); |
798e88b3 | 2997 | return true; |
d7c55201 XG |
2998 | } |
2999 | ||
ce88decf | 3000 | if (unlikely(is_noslot_pfn(pfn))) |
d7c55201 | 3001 | vcpu_cache_mmio_info(vcpu, gva, gfn, access); |
d7c55201 | 3002 | |
798e88b3 | 3003 | return false; |
d7c55201 XG |
3004 | } |
3005 | ||
e5552fd2 | 3006 | static bool page_fault_can_be_fast(u32 error_code) |
c7ba5b48 | 3007 | { |
1c118b82 XG |
3008 | /* |
3009 | * Do not fix the mmio spte with invalid generation number which | |
3010 | * need to be updated by slow page fault path. | |
3011 | */ | |
3012 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3013 | return false; | |
3014 | ||
f160c7b7 JS |
3015 | /* See if the page fault is due to an NX violation */ |
3016 | if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)) | |
3017 | == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)))) | |
3018 | return false; | |
3019 | ||
c7ba5b48 | 3020 | /* |
f160c7b7 JS |
3021 | * #PF can be fast if: |
3022 | * 1. The shadow page table entry is not present, which could mean that | |
3023 | * the fault is potentially caused by access tracking (if enabled). | |
3024 | * 2. The shadow page table entry is present and the fault | |
3025 | * is caused by write-protect, that means we just need change the W | |
3026 | * bit of the spte which can be done out of mmu-lock. | |
3027 | * | |
3028 | * However, if access tracking is disabled we know that a non-present | |
3029 | * page must be a genuine page fault where we have to create a new SPTE. | |
3030 | * So, if access tracking is disabled, we return true only for write | |
3031 | * accesses to a present page. | |
c7ba5b48 | 3032 | */ |
c7ba5b48 | 3033 | |
f160c7b7 JS |
3034 | return shadow_acc_track_mask != 0 || |
3035 | ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)) | |
3036 | == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)); | |
c7ba5b48 XG |
3037 | } |
3038 | ||
97dceba2 JS |
3039 | /* |
3040 | * Returns true if the SPTE was fixed successfully. Otherwise, | |
3041 | * someone else modified the SPTE from its original value. | |
3042 | */ | |
c7ba5b48 | 3043 | static bool |
92a476cb | 3044 | fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d3e328f2 | 3045 | u64 *sptep, u64 old_spte, u64 new_spte) |
c7ba5b48 | 3046 | { |
c7ba5b48 XG |
3047 | gfn_t gfn; |
3048 | ||
3049 | WARN_ON(!sp->role.direct); | |
3050 | ||
9b51a630 KH |
3051 | /* |
3052 | * Theoretically we could also set dirty bit (and flush TLB) here in | |
3053 | * order to eliminate unnecessary PML logging. See comments in | |
3054 | * set_spte. But fast_page_fault is very unlikely to happen with PML | |
3055 | * enabled, so we do not do this. This might result in the same GPA | |
3056 | * to be logged in PML buffer again when the write really happens, and | |
3057 | * eventually to be called by mark_page_dirty twice. But it's also no | |
3058 | * harm. This also avoids the TLB flush needed after setting dirty bit | |
3059 | * so non-PML cases won't be impacted. | |
3060 | * | |
3061 | * Compare with set_spte where instead shadow_dirty_mask is set. | |
3062 | */ | |
f160c7b7 | 3063 | if (cmpxchg64(sptep, old_spte, new_spte) != old_spte) |
97dceba2 JS |
3064 | return false; |
3065 | ||
d3e328f2 | 3066 | if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) { |
f160c7b7 JS |
3067 | /* |
3068 | * The gfn of direct spte is stable since it is | |
3069 | * calculated by sp->gfn. | |
3070 | */ | |
3071 | gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt); | |
3072 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
3073 | } | |
c7ba5b48 XG |
3074 | |
3075 | return true; | |
3076 | } | |
3077 | ||
d3e328f2 JS |
3078 | static bool is_access_allowed(u32 fault_err_code, u64 spte) |
3079 | { | |
3080 | if (fault_err_code & PFERR_FETCH_MASK) | |
3081 | return is_executable_pte(spte); | |
3082 | ||
3083 | if (fault_err_code & PFERR_WRITE_MASK) | |
3084 | return is_writable_pte(spte); | |
3085 | ||
3086 | /* Fault was on Read access */ | |
3087 | return spte & PT_PRESENT_MASK; | |
3088 | } | |
3089 | ||
c7ba5b48 XG |
3090 | /* |
3091 | * Return value: | |
3092 | * - true: let the vcpu to access on the same address again. | |
3093 | * - false: let the real page fault path to fix it. | |
3094 | */ | |
3095 | static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level, | |
3096 | u32 error_code) | |
3097 | { | |
3098 | struct kvm_shadow_walk_iterator iterator; | |
92a476cb | 3099 | struct kvm_mmu_page *sp; |
97dceba2 | 3100 | bool fault_handled = false; |
c7ba5b48 | 3101 | u64 spte = 0ull; |
97dceba2 | 3102 | uint retry_count = 0; |
c7ba5b48 | 3103 | |
37f6a4e2 MT |
3104 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3105 | return false; | |
3106 | ||
e5552fd2 | 3107 | if (!page_fault_can_be_fast(error_code)) |
c7ba5b48 XG |
3108 | return false; |
3109 | ||
3110 | walk_shadow_page_lockless_begin(vcpu); | |
c7ba5b48 | 3111 | |
97dceba2 | 3112 | do { |
d3e328f2 | 3113 | u64 new_spte; |
c7ba5b48 | 3114 | |
d162f30a JS |
3115 | for_each_shadow_entry_lockless(vcpu, gva, iterator, spte) |
3116 | if (!is_shadow_present_pte(spte) || | |
3117 | iterator.level < level) | |
3118 | break; | |
3119 | ||
97dceba2 JS |
3120 | sp = page_header(__pa(iterator.sptep)); |
3121 | if (!is_last_spte(spte, sp->role.level)) | |
3122 | break; | |
c7ba5b48 | 3123 | |
97dceba2 | 3124 | /* |
f160c7b7 JS |
3125 | * Check whether the memory access that caused the fault would |
3126 | * still cause it if it were to be performed right now. If not, | |
3127 | * then this is a spurious fault caused by TLB lazily flushed, | |
3128 | * or some other CPU has already fixed the PTE after the | |
3129 | * current CPU took the fault. | |
97dceba2 JS |
3130 | * |
3131 | * Need not check the access of upper level table entries since | |
3132 | * they are always ACC_ALL. | |
3133 | */ | |
d3e328f2 JS |
3134 | if (is_access_allowed(error_code, spte)) { |
3135 | fault_handled = true; | |
3136 | break; | |
3137 | } | |
f160c7b7 | 3138 | |
d3e328f2 JS |
3139 | new_spte = spte; |
3140 | ||
3141 | if (is_access_track_spte(spte)) | |
3142 | new_spte = restore_acc_track_spte(new_spte); | |
3143 | ||
3144 | /* | |
3145 | * Currently, to simplify the code, write-protection can | |
3146 | * be removed in the fast path only if the SPTE was | |
3147 | * write-protected for dirty-logging or access tracking. | |
3148 | */ | |
3149 | if ((error_code & PFERR_WRITE_MASK) && | |
3150 | spte_can_locklessly_be_made_writable(spte)) | |
3151 | { | |
3152 | new_spte |= PT_WRITABLE_MASK; | |
f160c7b7 JS |
3153 | |
3154 | /* | |
d3e328f2 JS |
3155 | * Do not fix write-permission on the large spte. Since |
3156 | * we only dirty the first page into the dirty-bitmap in | |
3157 | * fast_pf_fix_direct_spte(), other pages are missed | |
3158 | * if its slot has dirty logging enabled. | |
3159 | * | |
3160 | * Instead, we let the slow page fault path create a | |
3161 | * normal spte to fix the access. | |
3162 | * | |
3163 | * See the comments in kvm_arch_commit_memory_region(). | |
f160c7b7 | 3164 | */ |
d3e328f2 | 3165 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) |
f160c7b7 | 3166 | break; |
97dceba2 | 3167 | } |
c7ba5b48 | 3168 | |
f160c7b7 | 3169 | /* Verify that the fault can be handled in the fast path */ |
d3e328f2 JS |
3170 | if (new_spte == spte || |
3171 | !is_access_allowed(error_code, new_spte)) | |
97dceba2 JS |
3172 | break; |
3173 | ||
3174 | /* | |
3175 | * Currently, fast page fault only works for direct mapping | |
3176 | * since the gfn is not stable for indirect shadow page. See | |
3177 | * Documentation/virtual/kvm/locking.txt to get more detail. | |
3178 | */ | |
3179 | fault_handled = fast_pf_fix_direct_spte(vcpu, sp, | |
f160c7b7 | 3180 | iterator.sptep, spte, |
d3e328f2 | 3181 | new_spte); |
97dceba2 JS |
3182 | if (fault_handled) |
3183 | break; | |
3184 | ||
3185 | if (++retry_count > 4) { | |
3186 | printk_once(KERN_WARNING | |
3187 | "kvm: Fast #PF retrying more than 4 times.\n"); | |
3188 | break; | |
3189 | } | |
3190 | ||
97dceba2 | 3191 | } while (true); |
c126d94f | 3192 | |
a72faf25 | 3193 | trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep, |
97dceba2 | 3194 | spte, fault_handled); |
c7ba5b48 XG |
3195 | walk_shadow_page_lockless_end(vcpu); |
3196 | ||
97dceba2 | 3197 | return fault_handled; |
c7ba5b48 XG |
3198 | } |
3199 | ||
78b2c54a | 3200 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
ba049e93 | 3201 | gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable); |
450e0b41 | 3202 | static void make_mmu_pages_available(struct kvm_vcpu *vcpu); |
060c2abe | 3203 | |
c7ba5b48 XG |
3204 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code, |
3205 | gfn_t gfn, bool prefault) | |
10589a46 MT |
3206 | { |
3207 | int r; | |
852e3c19 | 3208 | int level; |
fd136902 | 3209 | bool force_pt_level = false; |
ba049e93 | 3210 | kvm_pfn_t pfn; |
e930bffe | 3211 | unsigned long mmu_seq; |
c7ba5b48 | 3212 | bool map_writable, write = error_code & PFERR_WRITE_MASK; |
aaee2c94 | 3213 | |
fd136902 | 3214 | level = mapping_level(vcpu, gfn, &force_pt_level); |
936a5fe6 | 3215 | if (likely(!force_pt_level)) { |
936a5fe6 AA |
3216 | /* |
3217 | * This path builds a PAE pagetable - so we can map | |
3218 | * 2mb pages at maximum. Therefore check if the level | |
3219 | * is larger than that. | |
3220 | */ | |
3221 | if (level > PT_DIRECTORY_LEVEL) | |
3222 | level = PT_DIRECTORY_LEVEL; | |
852e3c19 | 3223 | |
936a5fe6 | 3224 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
fd136902 | 3225 | } |
05da4558 | 3226 | |
c7ba5b48 XG |
3227 | if (fast_page_fault(vcpu, v, level, error_code)) |
3228 | return 0; | |
3229 | ||
e930bffe | 3230 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3231 | smp_rmb(); |
060c2abe | 3232 | |
78b2c54a | 3233 | if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable)) |
060c2abe | 3234 | return 0; |
aaee2c94 | 3235 | |
d7c55201 XG |
3236 | if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r)) |
3237 | return r; | |
d196e343 | 3238 | |
aaee2c94 | 3239 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 3240 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 3241 | goto out_unlock; |
450e0b41 | 3242 | make_mmu_pages_available(vcpu); |
936a5fe6 AA |
3243 | if (likely(!force_pt_level)) |
3244 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
7ee0e5b2 | 3245 | r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault); |
aaee2c94 MT |
3246 | spin_unlock(&vcpu->kvm->mmu_lock); |
3247 | ||
10589a46 | 3248 | return r; |
e930bffe AA |
3249 | |
3250 | out_unlock: | |
3251 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3252 | kvm_release_pfn_clean(pfn); | |
3253 | return 0; | |
10589a46 MT |
3254 | } |
3255 | ||
3256 | ||
17ac10ad AK |
3257 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
3258 | { | |
3259 | int i; | |
4db35314 | 3260 | struct kvm_mmu_page *sp; |
d98ba053 | 3261 | LIST_HEAD(invalid_list); |
17ac10ad | 3262 | |
ad312c7c | 3263 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 3264 | return; |
35af577a | 3265 | |
81407ca5 JR |
3266 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL && |
3267 | (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL || | |
3268 | vcpu->arch.mmu.direct_map)) { | |
ad312c7c | 3269 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 3270 | |
35af577a | 3271 | spin_lock(&vcpu->kvm->mmu_lock); |
4db35314 AK |
3272 | sp = page_header(root); |
3273 | --sp->root_count; | |
d98ba053 XG |
3274 | if (!sp->root_count && sp->role.invalid) { |
3275 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); | |
3276 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); | |
3277 | } | |
aaee2c94 | 3278 | spin_unlock(&vcpu->kvm->mmu_lock); |
35af577a | 3279 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
3280 | return; |
3281 | } | |
35af577a GN |
3282 | |
3283 | spin_lock(&vcpu->kvm->mmu_lock); | |
17ac10ad | 3284 | for (i = 0; i < 4; ++i) { |
ad312c7c | 3285 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 3286 | |
417726a3 | 3287 | if (root) { |
417726a3 | 3288 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
3289 | sp = page_header(root); |
3290 | --sp->root_count; | |
2e53d63a | 3291 | if (!sp->root_count && sp->role.invalid) |
d98ba053 XG |
3292 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
3293 | &invalid_list); | |
417726a3 | 3294 | } |
ad312c7c | 3295 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 3296 | } |
d98ba053 | 3297 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 3298 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 3299 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
3300 | } |
3301 | ||
8986ecc0 MT |
3302 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
3303 | { | |
3304 | int ret = 0; | |
3305 | ||
3306 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 3307 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
3308 | ret = 1; |
3309 | } | |
3310 | ||
3311 | return ret; | |
3312 | } | |
3313 | ||
651dd37a JR |
3314 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) |
3315 | { | |
3316 | struct kvm_mmu_page *sp; | |
7ebaf15e | 3317 | unsigned i; |
651dd37a JR |
3318 | |
3319 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
3320 | spin_lock(&vcpu->kvm->mmu_lock); | |
450e0b41 | 3321 | make_mmu_pages_available(vcpu); |
bb11c6c9 | 3322 | sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, 1, ACC_ALL); |
651dd37a JR |
3323 | ++sp->root_count; |
3324 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3325 | vcpu->arch.mmu.root_hpa = __pa(sp->spt); | |
3326 | } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) { | |
3327 | for (i = 0; i < 4; ++i) { | |
3328 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3329 | ||
fa4a2c08 | 3330 | MMU_WARN_ON(VALID_PAGE(root)); |
651dd37a | 3331 | spin_lock(&vcpu->kvm->mmu_lock); |
450e0b41 | 3332 | make_mmu_pages_available(vcpu); |
649497d1 | 3333 | sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT), |
bb11c6c9 | 3334 | i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL); |
651dd37a JR |
3335 | root = __pa(sp->spt); |
3336 | ++sp->root_count; | |
3337 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3338 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; | |
651dd37a | 3339 | } |
6292757f | 3340 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
651dd37a JR |
3341 | } else |
3342 | BUG(); | |
3343 | ||
3344 | return 0; | |
3345 | } | |
3346 | ||
3347 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 3348 | { |
4db35314 | 3349 | struct kvm_mmu_page *sp; |
81407ca5 JR |
3350 | u64 pdptr, pm_mask; |
3351 | gfn_t root_gfn; | |
3352 | int i; | |
3bb65a22 | 3353 | |
5777ed34 | 3354 | root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT; |
17ac10ad | 3355 | |
651dd37a JR |
3356 | if (mmu_check_root(vcpu, root_gfn)) |
3357 | return 1; | |
3358 | ||
3359 | /* | |
3360 | * Do we shadow a long mode page table? If so we need to | |
3361 | * write-protect the guests page table root. | |
3362 | */ | |
3363 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { | |
ad312c7c | 3364 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 3365 | |
fa4a2c08 | 3366 | MMU_WARN_ON(VALID_PAGE(root)); |
651dd37a | 3367 | |
8facbbff | 3368 | spin_lock(&vcpu->kvm->mmu_lock); |
450e0b41 | 3369 | make_mmu_pages_available(vcpu); |
651dd37a | 3370 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL, |
bb11c6c9 | 3371 | 0, ACC_ALL); |
4db35314 AK |
3372 | root = __pa(sp->spt); |
3373 | ++sp->root_count; | |
8facbbff | 3374 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 3375 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 3376 | return 0; |
17ac10ad | 3377 | } |
f87f9288 | 3378 | |
651dd37a JR |
3379 | /* |
3380 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
3381 | * or a PAE 3-level page table. In either case we need to be aware that |
3382 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 3383 | */ |
81407ca5 JR |
3384 | pm_mask = PT_PRESENT_MASK; |
3385 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) | |
3386 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; | |
3387 | ||
17ac10ad | 3388 | for (i = 0; i < 4; ++i) { |
ad312c7c | 3389 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 3390 | |
fa4a2c08 | 3391 | MMU_WARN_ON(VALID_PAGE(root)); |
ad312c7c | 3392 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 3393 | pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i); |
812f30b2 | 3394 | if (!(pdptr & PT_PRESENT_MASK)) { |
ad312c7c | 3395 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
3396 | continue; |
3397 | } | |
6de4f3ad | 3398 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
3399 | if (mmu_check_root(vcpu, root_gfn)) |
3400 | return 1; | |
5a7388c2 | 3401 | } |
8facbbff | 3402 | spin_lock(&vcpu->kvm->mmu_lock); |
450e0b41 | 3403 | make_mmu_pages_available(vcpu); |
bb11c6c9 TY |
3404 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL, |
3405 | 0, ACC_ALL); | |
4db35314 AK |
3406 | root = __pa(sp->spt); |
3407 | ++sp->root_count; | |
8facbbff AK |
3408 | spin_unlock(&vcpu->kvm->mmu_lock); |
3409 | ||
81407ca5 | 3410 | vcpu->arch.mmu.pae_root[i] = root | pm_mask; |
17ac10ad | 3411 | } |
6292757f | 3412 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
81407ca5 JR |
3413 | |
3414 | /* | |
3415 | * If we shadow a 32 bit page table with a long mode page | |
3416 | * table we enter this path. | |
3417 | */ | |
3418 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
3419 | if (vcpu->arch.mmu.lm_root == NULL) { | |
3420 | /* | |
3421 | * The additional page necessary for this is only | |
3422 | * allocated on demand. | |
3423 | */ | |
3424 | ||
3425 | u64 *lm_root; | |
3426 | ||
3427 | lm_root = (void*)get_zeroed_page(GFP_KERNEL); | |
3428 | if (lm_root == NULL) | |
3429 | return 1; | |
3430 | ||
3431 | lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask; | |
3432 | ||
3433 | vcpu->arch.mmu.lm_root = lm_root; | |
3434 | } | |
3435 | ||
3436 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root); | |
3437 | } | |
3438 | ||
8986ecc0 | 3439 | return 0; |
17ac10ad AK |
3440 | } |
3441 | ||
651dd37a JR |
3442 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
3443 | { | |
3444 | if (vcpu->arch.mmu.direct_map) | |
3445 | return mmu_alloc_direct_roots(vcpu); | |
3446 | else | |
3447 | return mmu_alloc_shadow_roots(vcpu); | |
3448 | } | |
3449 | ||
0ba73cda MT |
3450 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
3451 | { | |
3452 | int i; | |
3453 | struct kvm_mmu_page *sp; | |
3454 | ||
81407ca5 JR |
3455 | if (vcpu->arch.mmu.direct_map) |
3456 | return; | |
3457 | ||
0ba73cda MT |
3458 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3459 | return; | |
6903074c | 3460 | |
56f17dd3 | 3461 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); |
0375f7fa | 3462 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); |
81407ca5 | 3463 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { |
0ba73cda MT |
3464 | hpa_t root = vcpu->arch.mmu.root_hpa; |
3465 | sp = page_header(root); | |
3466 | mmu_sync_children(vcpu, sp); | |
0375f7fa | 3467 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
3468 | return; |
3469 | } | |
3470 | for (i = 0; i < 4; ++i) { | |
3471 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3472 | ||
8986ecc0 | 3473 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
3474 | root &= PT64_BASE_ADDR_MASK; |
3475 | sp = page_header(root); | |
3476 | mmu_sync_children(vcpu, sp); | |
3477 | } | |
3478 | } | |
0375f7fa | 3479 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
3480 | } |
3481 | ||
3482 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
3483 | { | |
3484 | spin_lock(&vcpu->kvm->mmu_lock); | |
3485 | mmu_sync_roots(vcpu); | |
6cffe8ca | 3486 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda | 3487 | } |
bfd0a56b | 3488 | EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots); |
0ba73cda | 3489 | |
1871c602 | 3490 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 | 3491 | u32 access, struct x86_exception *exception) |
6aa8b732 | 3492 | { |
ab9ae313 AK |
3493 | if (exception) |
3494 | exception->error_code = 0; | |
6aa8b732 AK |
3495 | return vaddr; |
3496 | } | |
3497 | ||
6539e738 | 3498 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
3499 | u32 access, |
3500 | struct x86_exception *exception) | |
6539e738 | 3501 | { |
ab9ae313 AK |
3502 | if (exception) |
3503 | exception->error_code = 0; | |
54987b7a | 3504 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception); |
6539e738 JR |
3505 | } |
3506 | ||
d625b155 XG |
3507 | static bool |
3508 | __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level) | |
3509 | { | |
3510 | int bit7 = (pte >> 7) & 1, low6 = pte & 0x3f; | |
3511 | ||
3512 | return (pte & rsvd_check->rsvd_bits_mask[bit7][level-1]) | | |
3513 | ((rsvd_check->bad_mt_xwr & (1ull << low6)) != 0); | |
3514 | } | |
3515 | ||
3516 | static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level) | |
3517 | { | |
3518 | return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level); | |
3519 | } | |
3520 | ||
3521 | static bool is_shadow_zero_bits_set(struct kvm_mmu *mmu, u64 spte, int level) | |
3522 | { | |
3523 | return __is_rsvd_bits_set(&mmu->shadow_zero_check, spte, level); | |
3524 | } | |
3525 | ||
ded58749 | 3526 | static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf XG |
3527 | { |
3528 | if (direct) | |
3529 | return vcpu_match_mmio_gpa(vcpu, addr); | |
3530 | ||
3531 | return vcpu_match_mmio_gva(vcpu, addr); | |
3532 | } | |
3533 | ||
47ab8751 XG |
3534 | /* return true if reserved bit is detected on spte. */ |
3535 | static bool | |
3536 | walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep) | |
ce88decf XG |
3537 | { |
3538 | struct kvm_shadow_walk_iterator iterator; | |
47ab8751 XG |
3539 | u64 sptes[PT64_ROOT_LEVEL], spte = 0ull; |
3540 | int root, leaf; | |
3541 | bool reserved = false; | |
ce88decf | 3542 | |
37f6a4e2 | 3543 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
47ab8751 | 3544 | goto exit; |
37f6a4e2 | 3545 | |
ce88decf | 3546 | walk_shadow_page_lockless_begin(vcpu); |
47ab8751 | 3547 | |
29ecd660 PB |
3548 | for (shadow_walk_init(&iterator, vcpu, addr), |
3549 | leaf = root = iterator.level; | |
47ab8751 XG |
3550 | shadow_walk_okay(&iterator); |
3551 | __shadow_walk_next(&iterator, spte)) { | |
47ab8751 XG |
3552 | spte = mmu_spte_get_lockless(iterator.sptep); |
3553 | ||
3554 | sptes[leaf - 1] = spte; | |
29ecd660 | 3555 | leaf--; |
47ab8751 | 3556 | |
ce88decf XG |
3557 | if (!is_shadow_present_pte(spte)) |
3558 | break; | |
47ab8751 XG |
3559 | |
3560 | reserved |= is_shadow_zero_bits_set(&vcpu->arch.mmu, spte, | |
58c95070 | 3561 | iterator.level); |
47ab8751 XG |
3562 | } |
3563 | ||
ce88decf XG |
3564 | walk_shadow_page_lockless_end(vcpu); |
3565 | ||
47ab8751 XG |
3566 | if (reserved) { |
3567 | pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n", | |
3568 | __func__, addr); | |
29ecd660 | 3569 | while (root > leaf) { |
47ab8751 XG |
3570 | pr_err("------ spte 0x%llx level %d.\n", |
3571 | sptes[root - 1], root); | |
3572 | root--; | |
3573 | } | |
3574 | } | |
3575 | exit: | |
3576 | *sptep = spte; | |
3577 | return reserved; | |
ce88decf XG |
3578 | } |
3579 | ||
450869d6 | 3580 | int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf XG |
3581 | { |
3582 | u64 spte; | |
47ab8751 | 3583 | bool reserved; |
ce88decf | 3584 | |
ded58749 | 3585 | if (mmio_info_in_cache(vcpu, addr, direct)) |
b37fbea6 | 3586 | return RET_MMIO_PF_EMULATE; |
ce88decf | 3587 | |
47ab8751 | 3588 | reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte); |
450869d6 | 3589 | if (WARN_ON(reserved)) |
47ab8751 | 3590 | return RET_MMIO_PF_BUG; |
ce88decf XG |
3591 | |
3592 | if (is_mmio_spte(spte)) { | |
3593 | gfn_t gfn = get_mmio_spte_gfn(spte); | |
3594 | unsigned access = get_mmio_spte_access(spte); | |
3595 | ||
54bf36aa | 3596 | if (!check_mmio_spte(vcpu, spte)) |
f8f55942 XG |
3597 | return RET_MMIO_PF_INVALID; |
3598 | ||
ce88decf XG |
3599 | if (direct) |
3600 | addr = 0; | |
4f022648 XG |
3601 | |
3602 | trace_handle_mmio_page_fault(addr, gfn, access); | |
ce88decf | 3603 | vcpu_cache_mmio_info(vcpu, addr, gfn, access); |
b37fbea6 | 3604 | return RET_MMIO_PF_EMULATE; |
ce88decf XG |
3605 | } |
3606 | ||
ce88decf XG |
3607 | /* |
3608 | * If the page table is zapped by other cpus, let CPU fault again on | |
3609 | * the address. | |
3610 | */ | |
b37fbea6 | 3611 | return RET_MMIO_PF_RETRY; |
ce88decf | 3612 | } |
450869d6 | 3613 | EXPORT_SYMBOL_GPL(handle_mmio_page_fault); |
ce88decf | 3614 | |
3d0c27ad XG |
3615 | static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu, |
3616 | u32 error_code, gfn_t gfn) | |
3617 | { | |
3618 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3619 | return false; | |
3620 | ||
3621 | if (!(error_code & PFERR_PRESENT_MASK) || | |
3622 | !(error_code & PFERR_WRITE_MASK)) | |
3623 | return false; | |
3624 | ||
3625 | /* | |
3626 | * guest is writing the page which is write tracked which can | |
3627 | * not be fixed by page fault handler. | |
3628 | */ | |
3629 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) | |
3630 | return true; | |
3631 | ||
3632 | return false; | |
3633 | } | |
3634 | ||
e5691a81 XG |
3635 | static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr) |
3636 | { | |
3637 | struct kvm_shadow_walk_iterator iterator; | |
3638 | u64 spte; | |
3639 | ||
3640 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
3641 | return; | |
3642 | ||
3643 | walk_shadow_page_lockless_begin(vcpu); | |
3644 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { | |
3645 | clear_sp_write_flooding_count(iterator.sptep); | |
3646 | if (!is_shadow_present_pte(spte)) | |
3647 | break; | |
3648 | } | |
3649 | walk_shadow_page_lockless_end(vcpu); | |
3650 | } | |
3651 | ||
6aa8b732 | 3652 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, |
78b2c54a | 3653 | u32 error_code, bool prefault) |
6aa8b732 | 3654 | { |
3d0c27ad | 3655 | gfn_t gfn = gva >> PAGE_SHIFT; |
e2dec939 | 3656 | int r; |
6aa8b732 | 3657 | |
b8688d51 | 3658 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
ce88decf | 3659 | |
3d0c27ad XG |
3660 | if (page_fault_handle_page_track(vcpu, error_code, gfn)) |
3661 | return 1; | |
ce88decf | 3662 | |
e2dec939 AK |
3663 | r = mmu_topup_memory_caches(vcpu); |
3664 | if (r) | |
3665 | return r; | |
714b93da | 3666 | |
fa4a2c08 | 3667 | MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 3668 | |
6aa8b732 | 3669 | |
e833240f | 3670 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
c7ba5b48 | 3671 | error_code, gfn, prefault); |
6aa8b732 AK |
3672 | } |
3673 | ||
7e1fbeac | 3674 | static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn) |
af585b92 GN |
3675 | { |
3676 | struct kvm_arch_async_pf arch; | |
fb67e14f | 3677 | |
7c90705b | 3678 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 3679 | arch.gfn = gfn; |
c4806acd | 3680 | arch.direct_map = vcpu->arch.mmu.direct_map; |
fb67e14f | 3681 | arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu); |
af585b92 | 3682 | |
54bf36aa | 3683 | return kvm_setup_async_pf(vcpu, gva, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch); |
af585b92 GN |
3684 | } |
3685 | ||
3686 | static bool can_do_async_pf(struct kvm_vcpu *vcpu) | |
3687 | { | |
35754c98 | 3688 | if (unlikely(!lapic_in_kernel(vcpu) || |
af585b92 GN |
3689 | kvm_event_needs_reinjection(vcpu))) |
3690 | return false; | |
3691 | ||
3692 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
3693 | } | |
3694 | ||
78b2c54a | 3695 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
ba049e93 | 3696 | gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable) |
af585b92 | 3697 | { |
3520469d | 3698 | struct kvm_memory_slot *slot; |
af585b92 GN |
3699 | bool async; |
3700 | ||
54bf36aa | 3701 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
3520469d PB |
3702 | async = false; |
3703 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable); | |
af585b92 GN |
3704 | if (!async) |
3705 | return false; /* *pfn has correct page already */ | |
3706 | ||
78b2c54a | 3707 | if (!prefault && can_do_async_pf(vcpu)) { |
c9b263d2 | 3708 | trace_kvm_try_async_get_page(gva, gfn); |
af585b92 GN |
3709 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
3710 | trace_kvm_async_pf_doublefault(gva, gfn); | |
3711 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
3712 | return true; | |
3713 | } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn)) | |
3714 | return true; | |
3715 | } | |
3716 | ||
3520469d | 3717 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable); |
af585b92 GN |
3718 | return false; |
3719 | } | |
3720 | ||
6a39bbc5 XG |
3721 | static bool |
3722 | check_hugepage_cache_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, int level) | |
3723 | { | |
3724 | int page_num = KVM_PAGES_PER_HPAGE(level); | |
3725 | ||
3726 | gfn &= ~(page_num - 1); | |
3727 | ||
3728 | return kvm_mtrr_check_gfn_range_consistency(vcpu, gfn, page_num); | |
3729 | } | |
3730 | ||
56028d08 | 3731 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code, |
78b2c54a | 3732 | bool prefault) |
fb72d167 | 3733 | { |
ba049e93 | 3734 | kvm_pfn_t pfn; |
fb72d167 | 3735 | int r; |
852e3c19 | 3736 | int level; |
cd1872f0 | 3737 | bool force_pt_level; |
05da4558 | 3738 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 3739 | unsigned long mmu_seq; |
612819c3 MT |
3740 | int write = error_code & PFERR_WRITE_MASK; |
3741 | bool map_writable; | |
fb72d167 | 3742 | |
fa4a2c08 | 3743 | MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
fb72d167 | 3744 | |
3d0c27ad XG |
3745 | if (page_fault_handle_page_track(vcpu, error_code, gfn)) |
3746 | return 1; | |
ce88decf | 3747 | |
fb72d167 JR |
3748 | r = mmu_topup_memory_caches(vcpu); |
3749 | if (r) | |
3750 | return r; | |
3751 | ||
fd136902 TY |
3752 | force_pt_level = !check_hugepage_cache_consistency(vcpu, gfn, |
3753 | PT_DIRECTORY_LEVEL); | |
3754 | level = mapping_level(vcpu, gfn, &force_pt_level); | |
936a5fe6 | 3755 | if (likely(!force_pt_level)) { |
6a39bbc5 XG |
3756 | if (level > PT_DIRECTORY_LEVEL && |
3757 | !check_hugepage_cache_consistency(vcpu, gfn, level)) | |
3758 | level = PT_DIRECTORY_LEVEL; | |
936a5fe6 | 3759 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
fd136902 | 3760 | } |
852e3c19 | 3761 | |
c7ba5b48 XG |
3762 | if (fast_page_fault(vcpu, gpa, level, error_code)) |
3763 | return 0; | |
3764 | ||
e930bffe | 3765 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3766 | smp_rmb(); |
af585b92 | 3767 | |
78b2c54a | 3768 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable)) |
af585b92 GN |
3769 | return 0; |
3770 | ||
d7c55201 XG |
3771 | if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r)) |
3772 | return r; | |
3773 | ||
fb72d167 | 3774 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 3775 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 3776 | goto out_unlock; |
450e0b41 | 3777 | make_mmu_pages_available(vcpu); |
936a5fe6 AA |
3778 | if (likely(!force_pt_level)) |
3779 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
7ee0e5b2 | 3780 | r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault); |
fb72d167 | 3781 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
3782 | |
3783 | return r; | |
e930bffe AA |
3784 | |
3785 | out_unlock: | |
3786 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3787 | kvm_release_pfn_clean(pfn); | |
3788 | return 0; | |
fb72d167 JR |
3789 | } |
3790 | ||
8a3c1a33 PB |
3791 | static void nonpaging_init_context(struct kvm_vcpu *vcpu, |
3792 | struct kvm_mmu *context) | |
6aa8b732 | 3793 | { |
6aa8b732 | 3794 | context->page_fault = nonpaging_page_fault; |
6aa8b732 | 3795 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
e8bc217a | 3796 | context->sync_page = nonpaging_sync_page; |
a7052897 | 3797 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 3798 | context->update_pte = nonpaging_update_pte; |
cea0f0e7 | 3799 | context->root_level = 0; |
6aa8b732 | 3800 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 3801 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3802 | context->direct_map = true; |
2d48a985 | 3803 | context->nx = false; |
6aa8b732 AK |
3804 | } |
3805 | ||
d8d173da | 3806 | void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu) |
6aa8b732 | 3807 | { |
cea0f0e7 | 3808 | mmu_free_roots(vcpu); |
6aa8b732 AK |
3809 | } |
3810 | ||
5777ed34 JR |
3811 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
3812 | { | |
9f8fe504 | 3813 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
3814 | } |
3815 | ||
6389ee94 AK |
3816 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
3817 | struct x86_exception *fault) | |
6aa8b732 | 3818 | { |
6389ee94 | 3819 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
6aa8b732 AK |
3820 | } |
3821 | ||
54bf36aa | 3822 | static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
f2fd125d | 3823 | unsigned access, int *nr_present) |
ce88decf XG |
3824 | { |
3825 | if (unlikely(is_mmio_spte(*sptep))) { | |
3826 | if (gfn != get_mmio_spte_gfn(*sptep)) { | |
3827 | mmu_spte_clear_no_track(sptep); | |
3828 | return true; | |
3829 | } | |
3830 | ||
3831 | (*nr_present)++; | |
54bf36aa | 3832 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
3833 | return true; |
3834 | } | |
3835 | ||
3836 | return false; | |
3837 | } | |
3838 | ||
6bb69c9b PB |
3839 | static inline bool is_last_gpte(struct kvm_mmu *mmu, |
3840 | unsigned level, unsigned gpte) | |
6fd01b71 | 3841 | { |
6bb69c9b PB |
3842 | /* |
3843 | * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set | |
3844 | * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means | |
3845 | * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then. | |
3846 | */ | |
3847 | gpte |= level - PT_PAGE_TABLE_LEVEL - 1; | |
6fd01b71 | 3848 | |
6bb69c9b PB |
3849 | /* |
3850 | * The RHS has bit 7 set iff level < mmu->last_nonleaf_level. | |
3851 | * If it is clear, there are no large pages at this level, so clear | |
3852 | * PT_PAGE_SIZE_MASK in gpte if that is the case. | |
3853 | */ | |
3854 | gpte &= level - mmu->last_nonleaf_level; | |
3855 | ||
3856 | return gpte & PT_PAGE_SIZE_MASK; | |
6fd01b71 AK |
3857 | } |
3858 | ||
37406aaa NHE |
3859 | #define PTTYPE_EPT 18 /* arbitrary */ |
3860 | #define PTTYPE PTTYPE_EPT | |
3861 | #include "paging_tmpl.h" | |
3862 | #undef PTTYPE | |
3863 | ||
6aa8b732 AK |
3864 | #define PTTYPE 64 |
3865 | #include "paging_tmpl.h" | |
3866 | #undef PTTYPE | |
3867 | ||
3868 | #define PTTYPE 32 | |
3869 | #include "paging_tmpl.h" | |
3870 | #undef PTTYPE | |
3871 | ||
6dc98b86 XG |
3872 | static void |
3873 | __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, | |
3874 | struct rsvd_bits_validate *rsvd_check, | |
3875 | int maxphyaddr, int level, bool nx, bool gbpages, | |
6fec2144 | 3876 | bool pse, bool amd) |
82725b20 | 3877 | { |
82725b20 | 3878 | u64 exb_bit_rsvd = 0; |
5f7dde7b | 3879 | u64 gbpages_bit_rsvd = 0; |
a0c0feb5 | 3880 | u64 nonleaf_bit8_rsvd = 0; |
82725b20 | 3881 | |
a0a64f50 | 3882 | rsvd_check->bad_mt_xwr = 0; |
25d92081 | 3883 | |
6dc98b86 | 3884 | if (!nx) |
82725b20 | 3885 | exb_bit_rsvd = rsvd_bits(63, 63); |
6dc98b86 | 3886 | if (!gbpages) |
5f7dde7b | 3887 | gbpages_bit_rsvd = rsvd_bits(7, 7); |
a0c0feb5 PB |
3888 | |
3889 | /* | |
3890 | * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for | |
3891 | * leaf entries) on AMD CPUs only. | |
3892 | */ | |
6fec2144 | 3893 | if (amd) |
a0c0feb5 PB |
3894 | nonleaf_bit8_rsvd = rsvd_bits(8, 8); |
3895 | ||
6dc98b86 | 3896 | switch (level) { |
82725b20 DE |
3897 | case PT32_ROOT_LEVEL: |
3898 | /* no rsvd bits for 2 level 4K page table entries */ | |
a0a64f50 XG |
3899 | rsvd_check->rsvd_bits_mask[0][1] = 0; |
3900 | rsvd_check->rsvd_bits_mask[0][0] = 0; | |
3901 | rsvd_check->rsvd_bits_mask[1][0] = | |
3902 | rsvd_check->rsvd_bits_mask[0][0]; | |
f815bce8 | 3903 | |
6dc98b86 | 3904 | if (!pse) { |
a0a64f50 | 3905 | rsvd_check->rsvd_bits_mask[1][1] = 0; |
f815bce8 XG |
3906 | break; |
3907 | } | |
3908 | ||
82725b20 DE |
3909 | if (is_cpuid_PSE36()) |
3910 | /* 36bits PSE 4MB page */ | |
a0a64f50 | 3911 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); |
82725b20 DE |
3912 | else |
3913 | /* 32 bits PSE 4MB page */ | |
a0a64f50 | 3914 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); |
82725b20 DE |
3915 | break; |
3916 | case PT32E_ROOT_LEVEL: | |
a0a64f50 | 3917 | rsvd_check->rsvd_bits_mask[0][2] = |
20c466b5 | 3918 | rsvd_bits(maxphyaddr, 63) | |
cd9ae5fe | 3919 | rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */ |
a0a64f50 | 3920 | rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 3921 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
a0a64f50 | 3922 | rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
82725b20 | 3923 | rsvd_bits(maxphyaddr, 62); /* PTE */ |
a0a64f50 | 3924 | rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
82725b20 DE |
3925 | rsvd_bits(maxphyaddr, 62) | |
3926 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
3927 | rsvd_check->rsvd_bits_mask[1][0] = |
3928 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 DE |
3929 | break; |
3930 | case PT64_ROOT_LEVEL: | |
a0a64f50 XG |
3931 | rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd | |
3932 | nonleaf_bit8_rsvd | rsvd_bits(7, 7) | | |
4c26b4cd | 3933 | rsvd_bits(maxphyaddr, 51); |
a0a64f50 XG |
3934 | rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd | |
3935 | nonleaf_bit8_rsvd | gbpages_bit_rsvd | | |
82725b20 | 3936 | rsvd_bits(maxphyaddr, 51); |
a0a64f50 XG |
3937 | rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
3938 | rsvd_bits(maxphyaddr, 51); | |
3939 | rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd | | |
3940 | rsvd_bits(maxphyaddr, 51); | |
3941 | rsvd_check->rsvd_bits_mask[1][3] = | |
3942 | rsvd_check->rsvd_bits_mask[0][3]; | |
3943 | rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd | | |
5f7dde7b | 3944 | gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) | |
e04da980 | 3945 | rsvd_bits(13, 29); |
a0a64f50 | 3946 | rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
3947 | rsvd_bits(maxphyaddr, 51) | |
3948 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
3949 | rsvd_check->rsvd_bits_mask[1][0] = |
3950 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 DE |
3951 | break; |
3952 | } | |
3953 | } | |
3954 | ||
6dc98b86 XG |
3955 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
3956 | struct kvm_mmu *context) | |
3957 | { | |
3958 | __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check, | |
3959 | cpuid_maxphyaddr(vcpu), context->root_level, | |
3960 | context->nx, guest_cpuid_has_gbpages(vcpu), | |
6fec2144 | 3961 | is_pse(vcpu), guest_cpuid_is_amd(vcpu)); |
6dc98b86 XG |
3962 | } |
3963 | ||
81b8eebb XG |
3964 | static void |
3965 | __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check, | |
3966 | int maxphyaddr, bool execonly) | |
25d92081 | 3967 | { |
951f9fd7 | 3968 | u64 bad_mt_xwr; |
25d92081 | 3969 | |
a0a64f50 | 3970 | rsvd_check->rsvd_bits_mask[0][3] = |
25d92081 | 3971 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7); |
a0a64f50 | 3972 | rsvd_check->rsvd_bits_mask[0][2] = |
25d92081 | 3973 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); |
a0a64f50 | 3974 | rsvd_check->rsvd_bits_mask[0][1] = |
25d92081 | 3975 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); |
a0a64f50 | 3976 | rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51); |
25d92081 YZ |
3977 | |
3978 | /* large page */ | |
a0a64f50 XG |
3979 | rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3]; |
3980 | rsvd_check->rsvd_bits_mask[1][2] = | |
25d92081 | 3981 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29); |
a0a64f50 | 3982 | rsvd_check->rsvd_bits_mask[1][1] = |
25d92081 | 3983 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20); |
a0a64f50 | 3984 | rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0]; |
25d92081 | 3985 | |
951f9fd7 PB |
3986 | bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */ |
3987 | bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */ | |
3988 | bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */ | |
3989 | bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */ | |
3990 | bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */ | |
3991 | if (!execonly) { | |
3992 | /* bits 0..2 must not be 100 unless VMX capabilities allow it */ | |
3993 | bad_mt_xwr |= REPEAT_BYTE(1ull << 4); | |
25d92081 | 3994 | } |
951f9fd7 | 3995 | rsvd_check->bad_mt_xwr = bad_mt_xwr; |
25d92081 YZ |
3996 | } |
3997 | ||
81b8eebb XG |
3998 | static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu, |
3999 | struct kvm_mmu *context, bool execonly) | |
4000 | { | |
4001 | __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check, | |
4002 | cpuid_maxphyaddr(vcpu), execonly); | |
4003 | } | |
4004 | ||
c258b62b XG |
4005 | /* |
4006 | * the page table on host is the shadow page table for the page | |
4007 | * table in guest or amd nested guest, its mmu features completely | |
4008 | * follow the features in guest. | |
4009 | */ | |
4010 | void | |
4011 | reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context) | |
4012 | { | |
5f0b8199 PB |
4013 | bool uses_nx = context->nx || context->base_role.smep_andnot_wp; |
4014 | ||
6fec2144 PB |
4015 | /* |
4016 | * Passing "true" to the last argument is okay; it adds a check | |
4017 | * on bit 8 of the SPTEs which KVM doesn't use anyway. | |
4018 | */ | |
c258b62b XG |
4019 | __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check, |
4020 | boot_cpu_data.x86_phys_bits, | |
5f0b8199 | 4021 | context->shadow_root_level, uses_nx, |
6fec2144 PB |
4022 | guest_cpuid_has_gbpages(vcpu), is_pse(vcpu), |
4023 | true); | |
c258b62b XG |
4024 | } |
4025 | EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask); | |
4026 | ||
6fec2144 PB |
4027 | static inline bool boot_cpu_is_amd(void) |
4028 | { | |
4029 | WARN_ON_ONCE(!tdp_enabled); | |
4030 | return shadow_x_mask == 0; | |
4031 | } | |
4032 | ||
c258b62b XG |
4033 | /* |
4034 | * the direct page table on host, use as much mmu features as | |
4035 | * possible, however, kvm currently does not do execution-protection. | |
4036 | */ | |
4037 | static void | |
4038 | reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4039 | struct kvm_mmu *context) | |
4040 | { | |
6fec2144 | 4041 | if (boot_cpu_is_amd()) |
c258b62b XG |
4042 | __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check, |
4043 | boot_cpu_data.x86_phys_bits, | |
4044 | context->shadow_root_level, false, | |
b8291adc BP |
4045 | boot_cpu_has(X86_FEATURE_GBPAGES), |
4046 | true, true); | |
c258b62b XG |
4047 | else |
4048 | __reset_rsvds_bits_mask_ept(&context->shadow_zero_check, | |
4049 | boot_cpu_data.x86_phys_bits, | |
4050 | false); | |
4051 | ||
4052 | } | |
4053 | ||
4054 | /* | |
4055 | * as the comments in reset_shadow_zero_bits_mask() except it | |
4056 | * is the shadow page table for intel nested guest. | |
4057 | */ | |
4058 | static void | |
4059 | reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4060 | struct kvm_mmu *context, bool execonly) | |
4061 | { | |
4062 | __reset_rsvds_bits_mask_ept(&context->shadow_zero_check, | |
4063 | boot_cpu_data.x86_phys_bits, execonly); | |
4064 | } | |
4065 | ||
edc90b7d XG |
4066 | static void update_permission_bitmask(struct kvm_vcpu *vcpu, |
4067 | struct kvm_mmu *mmu, bool ept) | |
97d64b78 AK |
4068 | { |
4069 | unsigned bit, byte, pfec; | |
4070 | u8 map; | |
66386ade | 4071 | bool fault, x, w, u, wf, uf, ff, smapf, cr4_smap, cr4_smep, smap = 0; |
97d64b78 | 4072 | |
66386ade | 4073 | cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
97ec8c06 | 4074 | cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP); |
97d64b78 AK |
4075 | for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) { |
4076 | pfec = byte << 1; | |
4077 | map = 0; | |
4078 | wf = pfec & PFERR_WRITE_MASK; | |
4079 | uf = pfec & PFERR_USER_MASK; | |
4080 | ff = pfec & PFERR_FETCH_MASK; | |
97ec8c06 FW |
4081 | /* |
4082 | * PFERR_RSVD_MASK bit is set in PFEC if the access is not | |
4083 | * subject to SMAP restrictions, and cleared otherwise. The | |
4084 | * bit is only meaningful if the SMAP bit is set in CR4. | |
4085 | */ | |
4086 | smapf = !(pfec & PFERR_RSVD_MASK); | |
97d64b78 AK |
4087 | for (bit = 0; bit < 8; ++bit) { |
4088 | x = bit & ACC_EXEC_MASK; | |
4089 | w = bit & ACC_WRITE_MASK; | |
4090 | u = bit & ACC_USER_MASK; | |
4091 | ||
25d92081 YZ |
4092 | if (!ept) { |
4093 | /* Not really needed: !nx will cause pte.nx to fault */ | |
4094 | x |= !mmu->nx; | |
4095 | /* Allow supervisor writes if !cr0.wp */ | |
4096 | w |= !is_write_protection(vcpu) && !uf; | |
4097 | /* Disallow supervisor fetches of user code if cr4.smep */ | |
66386ade | 4098 | x &= !(cr4_smep && u && !uf); |
97ec8c06 FW |
4099 | |
4100 | /* | |
4101 | * SMAP:kernel-mode data accesses from user-mode | |
4102 | * mappings should fault. A fault is considered | |
4103 | * as a SMAP violation if all of the following | |
4104 | * conditions are ture: | |
4105 | * - X86_CR4_SMAP is set in CR4 | |
9332ef9d | 4106 | * - A user page is accessed |
97ec8c06 FW |
4107 | * - Page fault in kernel mode |
4108 | * - if CPL = 3 or X86_EFLAGS_AC is clear | |
4109 | * | |
4110 | * Here, we cover the first three conditions. | |
4111 | * The fourth is computed dynamically in | |
4112 | * permission_fault() and is in smapf. | |
4113 | * | |
4114 | * Also, SMAP does not affect instruction | |
4115 | * fetches, add the !ff check here to make it | |
4116 | * clearer. | |
4117 | */ | |
4118 | smap = cr4_smap && u && !uf && !ff; | |
d95c5568 | 4119 | } |
97d64b78 | 4120 | |
97ec8c06 FW |
4121 | fault = (ff && !x) || (uf && !u) || (wf && !w) || |
4122 | (smapf && smap); | |
97d64b78 AK |
4123 | map |= fault << bit; |
4124 | } | |
4125 | mmu->permissions[byte] = map; | |
4126 | } | |
4127 | } | |
4128 | ||
2d344105 HH |
4129 | /* |
4130 | * PKU is an additional mechanism by which the paging controls access to | |
4131 | * user-mode addresses based on the value in the PKRU register. Protection | |
4132 | * key violations are reported through a bit in the page fault error code. | |
4133 | * Unlike other bits of the error code, the PK bit is not known at the | |
4134 | * call site of e.g. gva_to_gpa; it must be computed directly in | |
4135 | * permission_fault based on two bits of PKRU, on some machine state (CR4, | |
4136 | * CR0, EFER, CPL), and on other bits of the error code and the page tables. | |
4137 | * | |
4138 | * In particular the following conditions come from the error code, the | |
4139 | * page tables and the machine state: | |
4140 | * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1 | |
4141 | * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch) | |
4142 | * - PK is always zero if U=0 in the page tables | |
4143 | * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access. | |
4144 | * | |
4145 | * The PKRU bitmask caches the result of these four conditions. The error | |
4146 | * code (minus the P bit) and the page table's U bit form an index into the | |
4147 | * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed | |
4148 | * with the two bits of the PKRU register corresponding to the protection key. | |
4149 | * For the first three conditions above the bits will be 00, thus masking | |
4150 | * away both AD and WD. For all reads or if the last condition holds, WD | |
4151 | * only will be masked away. | |
4152 | */ | |
4153 | static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
4154 | bool ept) | |
4155 | { | |
4156 | unsigned bit; | |
4157 | bool wp; | |
4158 | ||
4159 | if (ept) { | |
4160 | mmu->pkru_mask = 0; | |
4161 | return; | |
4162 | } | |
4163 | ||
4164 | /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */ | |
4165 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) { | |
4166 | mmu->pkru_mask = 0; | |
4167 | return; | |
4168 | } | |
4169 | ||
4170 | wp = is_write_protection(vcpu); | |
4171 | ||
4172 | for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) { | |
4173 | unsigned pfec, pkey_bits; | |
4174 | bool check_pkey, check_write, ff, uf, wf, pte_user; | |
4175 | ||
4176 | pfec = bit << 1; | |
4177 | ff = pfec & PFERR_FETCH_MASK; | |
4178 | uf = pfec & PFERR_USER_MASK; | |
4179 | wf = pfec & PFERR_WRITE_MASK; | |
4180 | ||
4181 | /* PFEC.RSVD is replaced by ACC_USER_MASK. */ | |
4182 | pte_user = pfec & PFERR_RSVD_MASK; | |
4183 | ||
4184 | /* | |
4185 | * Only need to check the access which is not an | |
4186 | * instruction fetch and is to a user page. | |
4187 | */ | |
4188 | check_pkey = (!ff && pte_user); | |
4189 | /* | |
4190 | * write access is controlled by PKRU if it is a | |
4191 | * user access or CR0.WP = 1. | |
4192 | */ | |
4193 | check_write = check_pkey && wf && (uf || wp); | |
4194 | ||
4195 | /* PKRU.AD stops both read and write access. */ | |
4196 | pkey_bits = !!check_pkey; | |
4197 | /* PKRU.WD stops write access. */ | |
4198 | pkey_bits |= (!!check_write) << 1; | |
4199 | ||
4200 | mmu->pkru_mask |= (pkey_bits & 3) << pfec; | |
4201 | } | |
4202 | } | |
4203 | ||
6bb69c9b | 4204 | static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
6fd01b71 | 4205 | { |
6bb69c9b PB |
4206 | unsigned root_level = mmu->root_level; |
4207 | ||
4208 | mmu->last_nonleaf_level = root_level; | |
4209 | if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu)) | |
4210 | mmu->last_nonleaf_level++; | |
6fd01b71 AK |
4211 | } |
4212 | ||
8a3c1a33 PB |
4213 | static void paging64_init_context_common(struct kvm_vcpu *vcpu, |
4214 | struct kvm_mmu *context, | |
4215 | int level) | |
6aa8b732 | 4216 | { |
2d48a985 | 4217 | context->nx = is_nx(vcpu); |
4d6931c3 | 4218 | context->root_level = level; |
2d48a985 | 4219 | |
4d6931c3 | 4220 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 4221 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4222 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4223 | update_last_nonleaf_level(vcpu, context); |
6aa8b732 | 4224 | |
fa4a2c08 | 4225 | MMU_WARN_ON(!is_pae(vcpu)); |
6aa8b732 | 4226 | context->page_fault = paging64_page_fault; |
6aa8b732 | 4227 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 4228 | context->sync_page = paging64_sync_page; |
a7052897 | 4229 | context->invlpg = paging64_invlpg; |
0f53b5b1 | 4230 | context->update_pte = paging64_update_pte; |
17ac10ad | 4231 | context->shadow_root_level = level; |
17c3ba9d | 4232 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 4233 | context->direct_map = false; |
6aa8b732 AK |
4234 | } |
4235 | ||
8a3c1a33 PB |
4236 | static void paging64_init_context(struct kvm_vcpu *vcpu, |
4237 | struct kvm_mmu *context) | |
17ac10ad | 4238 | { |
8a3c1a33 | 4239 | paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL); |
17ac10ad AK |
4240 | } |
4241 | ||
8a3c1a33 PB |
4242 | static void paging32_init_context(struct kvm_vcpu *vcpu, |
4243 | struct kvm_mmu *context) | |
6aa8b732 | 4244 | { |
2d48a985 | 4245 | context->nx = false; |
4d6931c3 | 4246 | context->root_level = PT32_ROOT_LEVEL; |
2d48a985 | 4247 | |
4d6931c3 | 4248 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 4249 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4250 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4251 | update_last_nonleaf_level(vcpu, context); |
6aa8b732 | 4252 | |
6aa8b732 | 4253 | context->page_fault = paging32_page_fault; |
6aa8b732 | 4254 | context->gva_to_gpa = paging32_gva_to_gpa; |
e8bc217a | 4255 | context->sync_page = paging32_sync_page; |
a7052897 | 4256 | context->invlpg = paging32_invlpg; |
0f53b5b1 | 4257 | context->update_pte = paging32_update_pte; |
6aa8b732 | 4258 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 4259 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 4260 | context->direct_map = false; |
6aa8b732 AK |
4261 | } |
4262 | ||
8a3c1a33 PB |
4263 | static void paging32E_init_context(struct kvm_vcpu *vcpu, |
4264 | struct kvm_mmu *context) | |
6aa8b732 | 4265 | { |
8a3c1a33 | 4266 | paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
4267 | } |
4268 | ||
8a3c1a33 | 4269 | static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 4270 | { |
ad896af0 | 4271 | struct kvm_mmu *context = &vcpu->arch.mmu; |
fb72d167 | 4272 | |
c445f8ef | 4273 | context->base_role.word = 0; |
699023e2 | 4274 | context->base_role.smm = is_smm(vcpu); |
fb72d167 | 4275 | context->page_fault = tdp_page_fault; |
e8bc217a | 4276 | context->sync_page = nonpaging_sync_page; |
a7052897 | 4277 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 4278 | context->update_pte = nonpaging_update_pte; |
67253af5 | 4279 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); |
fb72d167 | 4280 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 4281 | context->direct_map = true; |
1c97f0a0 | 4282 | context->set_cr3 = kvm_x86_ops->set_tdp_cr3; |
5777ed34 | 4283 | context->get_cr3 = get_cr3; |
e4e517b4 | 4284 | context->get_pdptr = kvm_pdptr_read; |
cb659db8 | 4285 | context->inject_page_fault = kvm_inject_page_fault; |
fb72d167 JR |
4286 | |
4287 | if (!is_paging(vcpu)) { | |
2d48a985 | 4288 | context->nx = false; |
fb72d167 JR |
4289 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
4290 | context->root_level = 0; | |
4291 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 4292 | context->nx = is_nx(vcpu); |
fb72d167 | 4293 | context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 DB |
4294 | reset_rsvds_bits_mask(vcpu, context); |
4295 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4296 | } else if (is_pae(vcpu)) { |
2d48a985 | 4297 | context->nx = is_nx(vcpu); |
fb72d167 | 4298 | context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 DB |
4299 | reset_rsvds_bits_mask(vcpu, context); |
4300 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4301 | } else { |
2d48a985 | 4302 | context->nx = false; |
fb72d167 | 4303 | context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 DB |
4304 | reset_rsvds_bits_mask(vcpu, context); |
4305 | context->gva_to_gpa = paging32_gva_to_gpa; | |
fb72d167 JR |
4306 | } |
4307 | ||
25d92081 | 4308 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4309 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4310 | update_last_nonleaf_level(vcpu, context); |
c258b62b | 4311 | reset_tdp_shadow_zero_bits_mask(vcpu, context); |
fb72d167 JR |
4312 | } |
4313 | ||
ad896af0 | 4314 | void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu) |
6aa8b732 | 4315 | { |
411c588d | 4316 | bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
edc90b7d | 4317 | bool smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP); |
ad896af0 PB |
4318 | struct kvm_mmu *context = &vcpu->arch.mmu; |
4319 | ||
fa4a2c08 | 4320 | MMU_WARN_ON(VALID_PAGE(context->root_hpa)); |
6aa8b732 AK |
4321 | |
4322 | if (!is_paging(vcpu)) | |
8a3c1a33 | 4323 | nonpaging_init_context(vcpu, context); |
a9058ecd | 4324 | else if (is_long_mode(vcpu)) |
8a3c1a33 | 4325 | paging64_init_context(vcpu, context); |
6aa8b732 | 4326 | else if (is_pae(vcpu)) |
8a3c1a33 | 4327 | paging32E_init_context(vcpu, context); |
6aa8b732 | 4328 | else |
8a3c1a33 | 4329 | paging32_init_context(vcpu, context); |
a770f6f2 | 4330 | |
ad896af0 PB |
4331 | context->base_role.nxe = is_nx(vcpu); |
4332 | context->base_role.cr4_pae = !!is_pae(vcpu); | |
4333 | context->base_role.cr0_wp = is_write_protection(vcpu); | |
4334 | context->base_role.smep_andnot_wp | |
411c588d | 4335 | = smep && !is_write_protection(vcpu); |
edc90b7d XG |
4336 | context->base_role.smap_andnot_wp |
4337 | = smap && !is_write_protection(vcpu); | |
699023e2 | 4338 | context->base_role.smm = is_smm(vcpu); |
c258b62b | 4339 | reset_shadow_zero_bits_mask(vcpu, context); |
52fde8df JR |
4340 | } |
4341 | EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); | |
4342 | ||
ad896af0 | 4343 | void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly) |
155a97a3 | 4344 | { |
ad896af0 PB |
4345 | struct kvm_mmu *context = &vcpu->arch.mmu; |
4346 | ||
fa4a2c08 | 4347 | MMU_WARN_ON(VALID_PAGE(context->root_hpa)); |
155a97a3 NHE |
4348 | |
4349 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); | |
4350 | ||
4351 | context->nx = true; | |
155a97a3 NHE |
4352 | context->page_fault = ept_page_fault; |
4353 | context->gva_to_gpa = ept_gva_to_gpa; | |
4354 | context->sync_page = ept_sync_page; | |
4355 | context->invlpg = ept_invlpg; | |
4356 | context->update_pte = ept_update_pte; | |
155a97a3 NHE |
4357 | context->root_level = context->shadow_root_level; |
4358 | context->root_hpa = INVALID_PAGE; | |
4359 | context->direct_map = false; | |
4360 | ||
4361 | update_permission_bitmask(vcpu, context, true); | |
2d344105 | 4362 | update_pkru_bitmask(vcpu, context, true); |
155a97a3 | 4363 | reset_rsvds_bits_mask_ept(vcpu, context, execonly); |
c258b62b | 4364 | reset_ept_shadow_zero_bits_mask(vcpu, context, execonly); |
155a97a3 NHE |
4365 | } |
4366 | EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu); | |
4367 | ||
8a3c1a33 | 4368 | static void init_kvm_softmmu(struct kvm_vcpu *vcpu) |
52fde8df | 4369 | { |
ad896af0 PB |
4370 | struct kvm_mmu *context = &vcpu->arch.mmu; |
4371 | ||
4372 | kvm_init_shadow_mmu(vcpu); | |
4373 | context->set_cr3 = kvm_x86_ops->set_cr3; | |
4374 | context->get_cr3 = get_cr3; | |
4375 | context->get_pdptr = kvm_pdptr_read; | |
4376 | context->inject_page_fault = kvm_inject_page_fault; | |
6aa8b732 AK |
4377 | } |
4378 | ||
8a3c1a33 | 4379 | static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
02f59dc9 JR |
4380 | { |
4381 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; | |
4382 | ||
4383 | g_context->get_cr3 = get_cr3; | |
e4e517b4 | 4384 | g_context->get_pdptr = kvm_pdptr_read; |
02f59dc9 JR |
4385 | g_context->inject_page_fault = kvm_inject_page_fault; |
4386 | ||
4387 | /* | |
0af2593b DM |
4388 | * Note that arch.mmu.gva_to_gpa translates l2_gpa to l1_gpa using |
4389 | * L1's nested page tables (e.g. EPT12). The nested translation | |
4390 | * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using | |
4391 | * L2's page tables as the first level of translation and L1's | |
4392 | * nested page tables as the second level of translation. Basically | |
4393 | * the gva_to_gpa functions between mmu and nested_mmu are swapped. | |
02f59dc9 JR |
4394 | */ |
4395 | if (!is_paging(vcpu)) { | |
2d48a985 | 4396 | g_context->nx = false; |
02f59dc9 JR |
4397 | g_context->root_level = 0; |
4398 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
4399 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 4400 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 4401 | g_context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 | 4402 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4403 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
4404 | } else if (is_pae(vcpu)) { | |
2d48a985 | 4405 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 4406 | g_context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 | 4407 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4408 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
4409 | } else { | |
2d48a985 | 4410 | g_context->nx = false; |
02f59dc9 | 4411 | g_context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 | 4412 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4413 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; |
4414 | } | |
4415 | ||
25d92081 | 4416 | update_permission_bitmask(vcpu, g_context, false); |
2d344105 | 4417 | update_pkru_bitmask(vcpu, g_context, false); |
6bb69c9b | 4418 | update_last_nonleaf_level(vcpu, g_context); |
02f59dc9 JR |
4419 | } |
4420 | ||
8a3c1a33 | 4421 | static void init_kvm_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 4422 | { |
02f59dc9 | 4423 | if (mmu_is_nested(vcpu)) |
e0c6db3e | 4424 | init_kvm_nested_mmu(vcpu); |
02f59dc9 | 4425 | else if (tdp_enabled) |
e0c6db3e | 4426 | init_kvm_tdp_mmu(vcpu); |
fb72d167 | 4427 | else |
e0c6db3e | 4428 | init_kvm_softmmu(vcpu); |
fb72d167 JR |
4429 | } |
4430 | ||
8a3c1a33 | 4431 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu) |
6aa8b732 | 4432 | { |
95f93af4 | 4433 | kvm_mmu_unload(vcpu); |
8a3c1a33 | 4434 | init_kvm_mmu(vcpu); |
17c3ba9d | 4435 | } |
8668a3c4 | 4436 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
4437 | |
4438 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 4439 | { |
714b93da AK |
4440 | int r; |
4441 | ||
e2dec939 | 4442 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
4443 | if (r) |
4444 | goto out; | |
8986ecc0 | 4445 | r = mmu_alloc_roots(vcpu); |
e2858b4a | 4446 | kvm_mmu_sync_roots(vcpu); |
8986ecc0 MT |
4447 | if (r) |
4448 | goto out; | |
3662cb1c | 4449 | /* set_cr3() should ensure TLB has been flushed */ |
f43addd4 | 4450 | vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
4451 | out: |
4452 | return r; | |
6aa8b732 | 4453 | } |
17c3ba9d AK |
4454 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
4455 | ||
4456 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
4457 | { | |
4458 | mmu_free_roots(vcpu); | |
95f93af4 | 4459 | WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
17c3ba9d | 4460 | } |
4b16184c | 4461 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 4462 | |
0028425f | 4463 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
7c562522 XG |
4464 | struct kvm_mmu_page *sp, u64 *spte, |
4465 | const void *new) | |
0028425f | 4466 | { |
30945387 | 4467 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
4468 | ++vcpu->kvm->stat.mmu_pde_zapped; |
4469 | return; | |
30945387 | 4470 | } |
0028425f | 4471 | |
4cee5764 | 4472 | ++vcpu->kvm->stat.mmu_pte_updated; |
7c562522 | 4473 | vcpu->arch.mmu.update_pte(vcpu, sp, spte, new); |
0028425f AK |
4474 | } |
4475 | ||
79539cec AK |
4476 | static bool need_remote_flush(u64 old, u64 new) |
4477 | { | |
4478 | if (!is_shadow_present_pte(old)) | |
4479 | return false; | |
4480 | if (!is_shadow_present_pte(new)) | |
4481 | return true; | |
4482 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
4483 | return true; | |
53166229 GN |
4484 | old ^= shadow_nx_mask; |
4485 | new ^= shadow_nx_mask; | |
79539cec AK |
4486 | return (old & ~new & PT64_PERM_MASK) != 0; |
4487 | } | |
4488 | ||
889e5cbc XG |
4489 | static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, |
4490 | const u8 *new, int *bytes) | |
da4a00f0 | 4491 | { |
889e5cbc XG |
4492 | u64 gentry; |
4493 | int r; | |
72016f3a | 4494 | |
72016f3a AK |
4495 | /* |
4496 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
4497 | * as the current vcpu paging mode since we update the sptes only |
4498 | * when they have the same mode. | |
72016f3a | 4499 | */ |
889e5cbc | 4500 | if (is_pae(vcpu) && *bytes == 4) { |
72016f3a | 4501 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
889e5cbc XG |
4502 | *gpa &= ~(gpa_t)7; |
4503 | *bytes = 8; | |
54bf36aa | 4504 | r = kvm_vcpu_read_guest(vcpu, *gpa, &gentry, 8); |
72016f3a AK |
4505 | if (r) |
4506 | gentry = 0; | |
08e850c6 AK |
4507 | new = (const u8 *)&gentry; |
4508 | } | |
4509 | ||
889e5cbc | 4510 | switch (*bytes) { |
08e850c6 AK |
4511 | case 4: |
4512 | gentry = *(const u32 *)new; | |
4513 | break; | |
4514 | case 8: | |
4515 | gentry = *(const u64 *)new; | |
4516 | break; | |
4517 | default: | |
4518 | gentry = 0; | |
4519 | break; | |
72016f3a AK |
4520 | } |
4521 | ||
889e5cbc XG |
4522 | return gentry; |
4523 | } | |
4524 | ||
4525 | /* | |
4526 | * If we're seeing too many writes to a page, it may no longer be a page table, | |
4527 | * or we may be forking, in which case it is better to unmap the page. | |
4528 | */ | |
a138fe75 | 4529 | static bool detect_write_flooding(struct kvm_mmu_page *sp) |
889e5cbc | 4530 | { |
a30f47cb XG |
4531 | /* |
4532 | * Skip write-flooding detected for the sp whose level is 1, because | |
4533 | * it can become unsync, then the guest page is not write-protected. | |
4534 | */ | |
f71fa31f | 4535 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) |
a30f47cb | 4536 | return false; |
3246af0e | 4537 | |
e5691a81 XG |
4538 | atomic_inc(&sp->write_flooding_count); |
4539 | return atomic_read(&sp->write_flooding_count) >= 3; | |
889e5cbc XG |
4540 | } |
4541 | ||
4542 | /* | |
4543 | * Misaligned accesses are too much trouble to fix up; also, they usually | |
4544 | * indicate a page is not used as a page table. | |
4545 | */ | |
4546 | static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa, | |
4547 | int bytes) | |
4548 | { | |
4549 | unsigned offset, pte_size, misaligned; | |
4550 | ||
4551 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
4552 | gpa, bytes, sp->role.word); | |
4553 | ||
4554 | offset = offset_in_page(gpa); | |
4555 | pte_size = sp->role.cr4_pae ? 8 : 4; | |
5d9ca30e XG |
4556 | |
4557 | /* | |
4558 | * Sometimes, the OS only writes the last one bytes to update status | |
4559 | * bits, for example, in linux, andb instruction is used in clear_bit(). | |
4560 | */ | |
4561 | if (!(offset & (pte_size - 1)) && bytes == 1) | |
4562 | return false; | |
4563 | ||
889e5cbc XG |
4564 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
4565 | misaligned |= bytes < 4; | |
4566 | ||
4567 | return misaligned; | |
4568 | } | |
4569 | ||
4570 | static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte) | |
4571 | { | |
4572 | unsigned page_offset, quadrant; | |
4573 | u64 *spte; | |
4574 | int level; | |
4575 | ||
4576 | page_offset = offset_in_page(gpa); | |
4577 | level = sp->role.level; | |
4578 | *nspte = 1; | |
4579 | if (!sp->role.cr4_pae) { | |
4580 | page_offset <<= 1; /* 32->64 */ | |
4581 | /* | |
4582 | * A 32-bit pde maps 4MB while the shadow pdes map | |
4583 | * only 2MB. So we need to double the offset again | |
4584 | * and zap two pdes instead of one. | |
4585 | */ | |
4586 | if (level == PT32_ROOT_LEVEL) { | |
4587 | page_offset &= ~7; /* kill rounding error */ | |
4588 | page_offset <<= 1; | |
4589 | *nspte = 2; | |
4590 | } | |
4591 | quadrant = page_offset >> PAGE_SHIFT; | |
4592 | page_offset &= ~PAGE_MASK; | |
4593 | if (quadrant != sp->role.quadrant) | |
4594 | return NULL; | |
4595 | } | |
4596 | ||
4597 | spte = &sp->spt[page_offset / sizeof(*spte)]; | |
4598 | return spte; | |
4599 | } | |
4600 | ||
13d268ca | 4601 | static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
d126363d JS |
4602 | const u8 *new, int bytes, |
4603 | struct kvm_page_track_notifier_node *node) | |
889e5cbc XG |
4604 | { |
4605 | gfn_t gfn = gpa >> PAGE_SHIFT; | |
889e5cbc | 4606 | struct kvm_mmu_page *sp; |
889e5cbc XG |
4607 | LIST_HEAD(invalid_list); |
4608 | u64 entry, gentry, *spte; | |
4609 | int npte; | |
b8c67b7a | 4610 | bool remote_flush, local_flush; |
4141259b AM |
4611 | union kvm_mmu_page_role mask = { }; |
4612 | ||
4613 | mask.cr0_wp = 1; | |
4614 | mask.cr4_pae = 1; | |
4615 | mask.nxe = 1; | |
4616 | mask.smep_andnot_wp = 1; | |
4617 | mask.smap_andnot_wp = 1; | |
699023e2 | 4618 | mask.smm = 1; |
889e5cbc XG |
4619 | |
4620 | /* | |
4621 | * If we don't have indirect shadow pages, it means no page is | |
4622 | * write-protected, so we can exit simply. | |
4623 | */ | |
4624 | if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) | |
4625 | return; | |
4626 | ||
b8c67b7a | 4627 | remote_flush = local_flush = false; |
889e5cbc XG |
4628 | |
4629 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); | |
4630 | ||
4631 | gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes); | |
4632 | ||
4633 | /* | |
4634 | * No need to care whether allocation memory is successful | |
4635 | * or not since pte prefetch is skiped if it does not have | |
4636 | * enough objects in the cache. | |
4637 | */ | |
4638 | mmu_topup_memory_caches(vcpu); | |
4639 | ||
4640 | spin_lock(&vcpu->kvm->mmu_lock); | |
4641 | ++vcpu->kvm->stat.mmu_pte_write; | |
0375f7fa | 4642 | kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
889e5cbc | 4643 | |
b67bfe0d | 4644 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
a30f47cb | 4645 | if (detect_write_misaligned(sp, gpa, bytes) || |
a138fe75 | 4646 | detect_write_flooding(sp)) { |
b8c67b7a | 4647 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
4cee5764 | 4648 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
4649 | continue; |
4650 | } | |
889e5cbc XG |
4651 | |
4652 | spte = get_written_sptes(sp, gpa, &npte); | |
4653 | if (!spte) | |
4654 | continue; | |
4655 | ||
0671a8e7 | 4656 | local_flush = true; |
ac1b714e | 4657 | while (npte--) { |
79539cec | 4658 | entry = *spte; |
38e3b2b2 | 4659 | mmu_page_zap_pte(vcpu->kvm, sp, spte); |
fa1de2bf XG |
4660 | if (gentry && |
4661 | !((sp->role.word ^ vcpu->arch.mmu.base_role.word) | |
f759e2b4 | 4662 | & mask.word) && rmap_can_add(vcpu)) |
7c562522 | 4663 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
9bb4f6b1 | 4664 | if (need_remote_flush(entry, *spte)) |
0671a8e7 | 4665 | remote_flush = true; |
ac1b714e | 4666 | ++spte; |
9b7a0325 | 4667 | } |
9b7a0325 | 4668 | } |
b8c67b7a | 4669 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush); |
0375f7fa | 4670 | kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 4671 | spin_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
4672 | } |
4673 | ||
a436036b AK |
4674 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
4675 | { | |
10589a46 MT |
4676 | gpa_t gpa; |
4677 | int r; | |
a436036b | 4678 | |
c5a78f2b | 4679 | if (vcpu->arch.mmu.direct_map) |
60f24784 AK |
4680 | return 0; |
4681 | ||
1871c602 | 4682 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 4683 | |
10589a46 | 4684 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
1cb3f3ae | 4685 | |
10589a46 | 4686 | return r; |
a436036b | 4687 | } |
577bdc49 | 4688 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 4689 | |
81f4f76b | 4690 | static void make_mmu_pages_available(struct kvm_vcpu *vcpu) |
ebeace86 | 4691 | { |
d98ba053 | 4692 | LIST_HEAD(invalid_list); |
103ad25a | 4693 | |
81f4f76b TY |
4694 | if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES)) |
4695 | return; | |
4696 | ||
5da59607 TY |
4697 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) { |
4698 | if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list)) | |
4699 | break; | |
ebeace86 | 4700 | |
4cee5764 | 4701 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 | 4702 | } |
aa6bd187 | 4703 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
ebeace86 | 4704 | } |
ebeace86 | 4705 | |
14727754 | 4706 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u64 error_code, |
dc25e89e | 4707 | void *insn, int insn_len) |
3067714c | 4708 | { |
1cb3f3ae | 4709 | int r, emulation_type = EMULTYPE_RETRY; |
3067714c | 4710 | enum emulation_result er; |
ded58749 | 4711 | bool direct = vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu); |
3067714c | 4712 | |
e9ee956e TY |
4713 | if (unlikely(error_code & PFERR_RSVD_MASK)) { |
4714 | r = handle_mmio_page_fault(vcpu, cr2, direct); | |
4715 | if (r == RET_MMIO_PF_EMULATE) { | |
4716 | emulation_type = 0; | |
4717 | goto emulate; | |
4718 | } | |
4719 | if (r == RET_MMIO_PF_RETRY) | |
4720 | return 1; | |
4721 | if (r < 0) | |
4722 | return r; | |
4723 | } | |
3067714c | 4724 | |
14727754 TL |
4725 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, lower_32_bits(error_code), |
4726 | false); | |
3067714c | 4727 | if (r < 0) |
e9ee956e TY |
4728 | return r; |
4729 | if (!r) | |
4730 | return 1; | |
3067714c | 4731 | |
14727754 TL |
4732 | /* |
4733 | * Before emulating the instruction, check if the error code | |
4734 | * was due to a RO violation while translating the guest page. | |
4735 | * This can occur when using nested virtualization with nested | |
4736 | * paging in both guests. If true, we simply unprotect the page | |
4737 | * and resume the guest. | |
4738 | * | |
4739 | * Note: AMD only (since it supports the PFERR_GUEST_PAGE_MASK used | |
4740 | * in PFERR_NEXT_GUEST_PAGE) | |
4741 | */ | |
4742 | if (error_code == PFERR_NESTED_GUEST_PAGE) { | |
4743 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2)); | |
4744 | return 1; | |
4745 | } | |
4746 | ||
ded58749 | 4747 | if (mmio_info_in_cache(vcpu, cr2, direct)) |
1cb3f3ae | 4748 | emulation_type = 0; |
e9ee956e | 4749 | emulate: |
1cb3f3ae | 4750 | er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len); |
3067714c AK |
4751 | |
4752 | switch (er) { | |
4753 | case EMULATE_DONE: | |
4754 | return 1; | |
ac0a48c3 | 4755 | case EMULATE_USER_EXIT: |
3067714c | 4756 | ++vcpu->stat.mmio_exits; |
6d77dbfc | 4757 | /* fall through */ |
3067714c | 4758 | case EMULATE_FAIL: |
3f5d18a9 | 4759 | return 0; |
3067714c AK |
4760 | default: |
4761 | BUG(); | |
4762 | } | |
3067714c AK |
4763 | } |
4764 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
4765 | ||
a7052897 MT |
4766 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
4767 | { | |
a7052897 | 4768 | vcpu->arch.mmu.invlpg(vcpu, gva); |
77c3913b | 4769 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
a7052897 MT |
4770 | ++vcpu->stat.invlpg; |
4771 | } | |
4772 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
4773 | ||
18552672 JR |
4774 | void kvm_enable_tdp(void) |
4775 | { | |
4776 | tdp_enabled = true; | |
4777 | } | |
4778 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
4779 | ||
5f4cb662 JR |
4780 | void kvm_disable_tdp(void) |
4781 | { | |
4782 | tdp_enabled = false; | |
4783 | } | |
4784 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
4785 | ||
6aa8b732 AK |
4786 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
4787 | { | |
ad312c7c | 4788 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
81407ca5 JR |
4789 | if (vcpu->arch.mmu.lm_root != NULL) |
4790 | free_page((unsigned long)vcpu->arch.mmu.lm_root); | |
6aa8b732 AK |
4791 | } |
4792 | ||
4793 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
4794 | { | |
17ac10ad | 4795 | struct page *page; |
6aa8b732 AK |
4796 | int i; |
4797 | ||
17ac10ad AK |
4798 | /* |
4799 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
4800 | * Therefore we need to allocate shadow page tables in the first | |
4801 | * 4GB of memory, which happens to fit the DMA32 zone. | |
4802 | */ | |
4803 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
4804 | if (!page) | |
d7fa6ab2 WY |
4805 | return -ENOMEM; |
4806 | ||
ad312c7c | 4807 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 4808 | for (i = 0; i < 4; ++i) |
ad312c7c | 4809 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 4810 | |
6aa8b732 | 4811 | return 0; |
6aa8b732 AK |
4812 | } |
4813 | ||
8018c27b | 4814 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 4815 | { |
e459e322 XG |
4816 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; |
4817 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; | |
4818 | vcpu->arch.mmu.translate_gpa = translate_gpa; | |
4819 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; | |
6aa8b732 | 4820 | |
8018c27b IM |
4821 | return alloc_mmu_pages(vcpu); |
4822 | } | |
6aa8b732 | 4823 | |
8a3c1a33 | 4824 | void kvm_mmu_setup(struct kvm_vcpu *vcpu) |
8018c27b | 4825 | { |
fa4a2c08 | 4826 | MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 4827 | |
8a3c1a33 | 4828 | init_kvm_mmu(vcpu); |
6aa8b732 AK |
4829 | } |
4830 | ||
b5f5fdca | 4831 | static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm, |
d126363d JS |
4832 | struct kvm_memory_slot *slot, |
4833 | struct kvm_page_track_notifier_node *node) | |
b5f5fdca XC |
4834 | { |
4835 | kvm_mmu_invalidate_zap_all_pages(kvm); | |
4836 | } | |
4837 | ||
13d268ca XG |
4838 | void kvm_mmu_init_vm(struct kvm *kvm) |
4839 | { | |
4840 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; | |
4841 | ||
4842 | node->track_write = kvm_mmu_pte_write; | |
b5f5fdca | 4843 | node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot; |
13d268ca XG |
4844 | kvm_page_track_register_notifier(kvm, node); |
4845 | } | |
4846 | ||
4847 | void kvm_mmu_uninit_vm(struct kvm *kvm) | |
4848 | { | |
4849 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; | |
4850 | ||
4851 | kvm_page_track_unregister_notifier(kvm, node); | |
4852 | } | |
4853 | ||
1bad2b2a | 4854 | /* The return value indicates if tlb flush on all vcpus is needed. */ |
018aabb5 | 4855 | typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head); |
1bad2b2a XG |
4856 | |
4857 | /* The caller should hold mmu-lock before calling this function. */ | |
4858 | static bool | |
4859 | slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
4860 | slot_level_handler fn, int start_level, int end_level, | |
4861 | gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb) | |
4862 | { | |
4863 | struct slot_rmap_walk_iterator iterator; | |
4864 | bool flush = false; | |
4865 | ||
4866 | for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn, | |
4867 | end_gfn, &iterator) { | |
4868 | if (iterator.rmap) | |
4869 | flush |= fn(kvm, iterator.rmap); | |
4870 | ||
4871 | if (need_resched() || spin_needbreak(&kvm->mmu_lock)) { | |
4872 | if (flush && lock_flush_tlb) { | |
4873 | kvm_flush_remote_tlbs(kvm); | |
4874 | flush = false; | |
4875 | } | |
4876 | cond_resched_lock(&kvm->mmu_lock); | |
4877 | } | |
4878 | } | |
4879 | ||
4880 | if (flush && lock_flush_tlb) { | |
4881 | kvm_flush_remote_tlbs(kvm); | |
4882 | flush = false; | |
4883 | } | |
4884 | ||
4885 | return flush; | |
4886 | } | |
4887 | ||
4888 | static bool | |
4889 | slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
4890 | slot_level_handler fn, int start_level, int end_level, | |
4891 | bool lock_flush_tlb) | |
4892 | { | |
4893 | return slot_handle_level_range(kvm, memslot, fn, start_level, | |
4894 | end_level, memslot->base_gfn, | |
4895 | memslot->base_gfn + memslot->npages - 1, | |
4896 | lock_flush_tlb); | |
4897 | } | |
4898 | ||
4899 | static bool | |
4900 | slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
4901 | slot_level_handler fn, bool lock_flush_tlb) | |
4902 | { | |
4903 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL, | |
4904 | PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb); | |
4905 | } | |
4906 | ||
4907 | static bool | |
4908 | slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
4909 | slot_level_handler fn, bool lock_flush_tlb) | |
4910 | { | |
4911 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1, | |
4912 | PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb); | |
4913 | } | |
4914 | ||
4915 | static bool | |
4916 | slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
4917 | slot_level_handler fn, bool lock_flush_tlb) | |
4918 | { | |
4919 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL, | |
4920 | PT_PAGE_TABLE_LEVEL, lock_flush_tlb); | |
4921 | } | |
4922 | ||
efdfe536 XG |
4923 | void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end) |
4924 | { | |
4925 | struct kvm_memslots *slots; | |
4926 | struct kvm_memory_slot *memslot; | |
9da0e4d5 | 4927 | int i; |
efdfe536 XG |
4928 | |
4929 | spin_lock(&kvm->mmu_lock); | |
9da0e4d5 PB |
4930 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
4931 | slots = __kvm_memslots(kvm, i); | |
4932 | kvm_for_each_memslot(memslot, slots) { | |
4933 | gfn_t start, end; | |
4934 | ||
4935 | start = max(gfn_start, memslot->base_gfn); | |
4936 | end = min(gfn_end, memslot->base_gfn + memslot->npages); | |
4937 | if (start >= end) | |
4938 | continue; | |
efdfe536 | 4939 | |
9da0e4d5 PB |
4940 | slot_handle_level_range(kvm, memslot, kvm_zap_rmapp, |
4941 | PT_PAGE_TABLE_LEVEL, PT_MAX_HUGEPAGE_LEVEL, | |
4942 | start, end - 1, true); | |
4943 | } | |
efdfe536 XG |
4944 | } |
4945 | ||
4946 | spin_unlock(&kvm->mmu_lock); | |
4947 | } | |
4948 | ||
018aabb5 TY |
4949 | static bool slot_rmap_write_protect(struct kvm *kvm, |
4950 | struct kvm_rmap_head *rmap_head) | |
d77aa73c | 4951 | { |
018aabb5 | 4952 | return __rmap_write_protect(kvm, rmap_head, false); |
d77aa73c XG |
4953 | } |
4954 | ||
1c91cad4 KH |
4955 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, |
4956 | struct kvm_memory_slot *memslot) | |
6aa8b732 | 4957 | { |
d77aa73c | 4958 | bool flush; |
6aa8b732 | 4959 | |
9d1beefb | 4960 | spin_lock(&kvm->mmu_lock); |
d77aa73c XG |
4961 | flush = slot_handle_all_level(kvm, memslot, slot_rmap_write_protect, |
4962 | false); | |
9d1beefb | 4963 | spin_unlock(&kvm->mmu_lock); |
198c74f4 XG |
4964 | |
4965 | /* | |
4966 | * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log() | |
4967 | * which do tlb flush out of mmu-lock should be serialized by | |
4968 | * kvm->slots_lock otherwise tlb flush would be missed. | |
4969 | */ | |
4970 | lockdep_assert_held(&kvm->slots_lock); | |
4971 | ||
4972 | /* | |
4973 | * We can flush all the TLBs out of the mmu lock without TLB | |
4974 | * corruption since we just change the spte from writable to | |
4975 | * readonly so that we only need to care the case of changing | |
4976 | * spte from present to present (changing the spte from present | |
4977 | * to nonpresent will flush all the TLBs immediately), in other | |
4978 | * words, the only case we care is mmu_spte_update() where we | |
4979 | * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE | |
4980 | * instead of PT_WRITABLE_MASK, that means it does not depend | |
4981 | * on PT_WRITABLE_MASK anymore. | |
4982 | */ | |
d91ffee9 KH |
4983 | if (flush) |
4984 | kvm_flush_remote_tlbs(kvm); | |
6aa8b732 | 4985 | } |
37a7d8b0 | 4986 | |
3ea3b7fa | 4987 | static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm, |
018aabb5 | 4988 | struct kvm_rmap_head *rmap_head) |
3ea3b7fa WL |
4989 | { |
4990 | u64 *sptep; | |
4991 | struct rmap_iterator iter; | |
4992 | int need_tlb_flush = 0; | |
ba049e93 | 4993 | kvm_pfn_t pfn; |
3ea3b7fa WL |
4994 | struct kvm_mmu_page *sp; |
4995 | ||
0d536790 | 4996 | restart: |
018aabb5 | 4997 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
3ea3b7fa WL |
4998 | sp = page_header(__pa(sptep)); |
4999 | pfn = spte_to_pfn(*sptep); | |
5000 | ||
5001 | /* | |
decf6333 XG |
5002 | * We cannot do huge page mapping for indirect shadow pages, |
5003 | * which are found on the last rmap (level = 1) when not using | |
5004 | * tdp; such shadow pages are synced with the page table in | |
5005 | * the guest, and the guest page table is using 4K page size | |
5006 | * mapping if the indirect sp has level = 1. | |
3ea3b7fa WL |
5007 | */ |
5008 | if (sp->role.direct && | |
5009 | !kvm_is_reserved_pfn(pfn) && | |
127393fb | 5010 | PageTransCompoundMap(pfn_to_page(pfn))) { |
3ea3b7fa | 5011 | drop_spte(kvm, sptep); |
3ea3b7fa | 5012 | need_tlb_flush = 1; |
0d536790 XG |
5013 | goto restart; |
5014 | } | |
3ea3b7fa WL |
5015 | } |
5016 | ||
5017 | return need_tlb_flush; | |
5018 | } | |
5019 | ||
5020 | void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, | |
f36f3f28 | 5021 | const struct kvm_memory_slot *memslot) |
3ea3b7fa | 5022 | { |
f36f3f28 | 5023 | /* FIXME: const-ify all uses of struct kvm_memory_slot. */ |
3ea3b7fa | 5024 | spin_lock(&kvm->mmu_lock); |
f36f3f28 PB |
5025 | slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot, |
5026 | kvm_mmu_zap_collapsible_spte, true); | |
3ea3b7fa WL |
5027 | spin_unlock(&kvm->mmu_lock); |
5028 | } | |
5029 | ||
f4b4b180 KH |
5030 | void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, |
5031 | struct kvm_memory_slot *memslot) | |
5032 | { | |
d77aa73c | 5033 | bool flush; |
f4b4b180 KH |
5034 | |
5035 | spin_lock(&kvm->mmu_lock); | |
d77aa73c | 5036 | flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false); |
f4b4b180 KH |
5037 | spin_unlock(&kvm->mmu_lock); |
5038 | ||
5039 | lockdep_assert_held(&kvm->slots_lock); | |
5040 | ||
5041 | /* | |
5042 | * It's also safe to flush TLBs out of mmu lock here as currently this | |
5043 | * function is only used for dirty logging, in which case flushing TLB | |
5044 | * out of mmu lock also guarantees no dirty pages will be lost in | |
5045 | * dirty_bitmap. | |
5046 | */ | |
5047 | if (flush) | |
5048 | kvm_flush_remote_tlbs(kvm); | |
5049 | } | |
5050 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty); | |
5051 | ||
5052 | void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, | |
5053 | struct kvm_memory_slot *memslot) | |
5054 | { | |
d77aa73c | 5055 | bool flush; |
f4b4b180 KH |
5056 | |
5057 | spin_lock(&kvm->mmu_lock); | |
d77aa73c XG |
5058 | flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect, |
5059 | false); | |
f4b4b180 KH |
5060 | spin_unlock(&kvm->mmu_lock); |
5061 | ||
5062 | /* see kvm_mmu_slot_remove_write_access */ | |
5063 | lockdep_assert_held(&kvm->slots_lock); | |
5064 | ||
5065 | if (flush) | |
5066 | kvm_flush_remote_tlbs(kvm); | |
5067 | } | |
5068 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access); | |
5069 | ||
5070 | void kvm_mmu_slot_set_dirty(struct kvm *kvm, | |
5071 | struct kvm_memory_slot *memslot) | |
5072 | { | |
d77aa73c | 5073 | bool flush; |
f4b4b180 KH |
5074 | |
5075 | spin_lock(&kvm->mmu_lock); | |
d77aa73c | 5076 | flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false); |
f4b4b180 KH |
5077 | spin_unlock(&kvm->mmu_lock); |
5078 | ||
5079 | lockdep_assert_held(&kvm->slots_lock); | |
5080 | ||
5081 | /* see kvm_mmu_slot_leaf_clear_dirty */ | |
5082 | if (flush) | |
5083 | kvm_flush_remote_tlbs(kvm); | |
5084 | } | |
5085 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty); | |
5086 | ||
e7d11c7a | 5087 | #define BATCH_ZAP_PAGES 10 |
5304b8d3 XG |
5088 | static void kvm_zap_obsolete_pages(struct kvm *kvm) |
5089 | { | |
5090 | struct kvm_mmu_page *sp, *node; | |
e7d11c7a | 5091 | int batch = 0; |
5304b8d3 XG |
5092 | |
5093 | restart: | |
5094 | list_for_each_entry_safe_reverse(sp, node, | |
5095 | &kvm->arch.active_mmu_pages, link) { | |
e7d11c7a XG |
5096 | int ret; |
5097 | ||
5304b8d3 XG |
5098 | /* |
5099 | * No obsolete page exists before new created page since | |
5100 | * active_mmu_pages is the FIFO list. | |
5101 | */ | |
5102 | if (!is_obsolete_sp(kvm, sp)) | |
5103 | break; | |
5104 | ||
5105 | /* | |
5304b8d3 XG |
5106 | * Since we are reversely walking the list and the invalid |
5107 | * list will be moved to the head, skip the invalid page | |
5108 | * can help us to avoid the infinity list walking. | |
5109 | */ | |
5110 | if (sp->role.invalid) | |
5111 | continue; | |
5112 | ||
f34d251d XG |
5113 | /* |
5114 | * Need not flush tlb since we only zap the sp with invalid | |
5115 | * generation number. | |
5116 | */ | |
e7d11c7a | 5117 | if (batch >= BATCH_ZAP_PAGES && |
f34d251d | 5118 | cond_resched_lock(&kvm->mmu_lock)) { |
e7d11c7a | 5119 | batch = 0; |
5304b8d3 XG |
5120 | goto restart; |
5121 | } | |
5122 | ||
365c8868 XG |
5123 | ret = kvm_mmu_prepare_zap_page(kvm, sp, |
5124 | &kvm->arch.zapped_obsolete_pages); | |
e7d11c7a XG |
5125 | batch += ret; |
5126 | ||
5127 | if (ret) | |
5304b8d3 XG |
5128 | goto restart; |
5129 | } | |
5130 | ||
f34d251d XG |
5131 | /* |
5132 | * Should flush tlb before free page tables since lockless-walking | |
5133 | * may use the pages. | |
5134 | */ | |
365c8868 | 5135 | kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages); |
5304b8d3 XG |
5136 | } |
5137 | ||
5138 | /* | |
5139 | * Fast invalidate all shadow pages and use lock-break technique | |
5140 | * to zap obsolete pages. | |
5141 | * | |
5142 | * It's required when memslot is being deleted or VM is being | |
5143 | * destroyed, in these cases, we should ensure that KVM MMU does | |
5144 | * not use any resource of the being-deleted slot or all slots | |
5145 | * after calling the function. | |
5146 | */ | |
5147 | void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm) | |
5148 | { | |
5149 | spin_lock(&kvm->mmu_lock); | |
35006126 | 5150 | trace_kvm_mmu_invalidate_zap_all_pages(kvm); |
5304b8d3 XG |
5151 | kvm->arch.mmu_valid_gen++; |
5152 | ||
f34d251d XG |
5153 | /* |
5154 | * Notify all vcpus to reload its shadow page table | |
5155 | * and flush TLB. Then all vcpus will switch to new | |
5156 | * shadow page table with the new mmu_valid_gen. | |
5157 | * | |
5158 | * Note: we should do this under the protection of | |
5159 | * mmu-lock, otherwise, vcpu would purge shadow page | |
5160 | * but miss tlb flush. | |
5161 | */ | |
5162 | kvm_reload_remote_mmus(kvm); | |
5163 | ||
5304b8d3 XG |
5164 | kvm_zap_obsolete_pages(kvm); |
5165 | spin_unlock(&kvm->mmu_lock); | |
5166 | } | |
5167 | ||
365c8868 XG |
5168 | static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm) |
5169 | { | |
5170 | return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages)); | |
5171 | } | |
5172 | ||
54bf36aa | 5173 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots) |
f8f55942 XG |
5174 | { |
5175 | /* | |
5176 | * The very rare case: if the generation-number is round, | |
5177 | * zap all shadow pages. | |
f8f55942 | 5178 | */ |
54bf36aa | 5179 | if (unlikely((slots->generation & MMIO_GEN_MASK) == 0)) { |
ae0f5499 | 5180 | kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n"); |
a8eca9dc | 5181 | kvm_mmu_invalidate_zap_all_pages(kvm); |
7a2e8aaf | 5182 | } |
f8f55942 XG |
5183 | } |
5184 | ||
70534a73 DC |
5185 | static unsigned long |
5186 | mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) | |
3ee16c81 IE |
5187 | { |
5188 | struct kvm *kvm; | |
1495f230 | 5189 | int nr_to_scan = sc->nr_to_scan; |
70534a73 | 5190 | unsigned long freed = 0; |
3ee16c81 | 5191 | |
2f303b74 | 5192 | spin_lock(&kvm_lock); |
3ee16c81 IE |
5193 | |
5194 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
3d56cbdf | 5195 | int idx; |
d98ba053 | 5196 | LIST_HEAD(invalid_list); |
3ee16c81 | 5197 | |
35f2d16b TY |
5198 | /* |
5199 | * Never scan more than sc->nr_to_scan VM instances. | |
5200 | * Will not hit this condition practically since we do not try | |
5201 | * to shrink more than one VM and it is very unlikely to see | |
5202 | * !n_used_mmu_pages so many times. | |
5203 | */ | |
5204 | if (!nr_to_scan--) | |
5205 | break; | |
19526396 GN |
5206 | /* |
5207 | * n_used_mmu_pages is accessed without holding kvm->mmu_lock | |
5208 | * here. We may skip a VM instance errorneosly, but we do not | |
5209 | * want to shrink a VM that only started to populate its MMU | |
5210 | * anyway. | |
5211 | */ | |
365c8868 XG |
5212 | if (!kvm->arch.n_used_mmu_pages && |
5213 | !kvm_has_zapped_obsolete_pages(kvm)) | |
19526396 | 5214 | continue; |
19526396 | 5215 | |
f656ce01 | 5216 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 5217 | spin_lock(&kvm->mmu_lock); |
3ee16c81 | 5218 | |
365c8868 XG |
5219 | if (kvm_has_zapped_obsolete_pages(kvm)) { |
5220 | kvm_mmu_commit_zap_page(kvm, | |
5221 | &kvm->arch.zapped_obsolete_pages); | |
5222 | goto unlock; | |
5223 | } | |
5224 | ||
70534a73 DC |
5225 | if (prepare_zap_oldest_mmu_page(kvm, &invalid_list)) |
5226 | freed++; | |
d98ba053 | 5227 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
19526396 | 5228 | |
365c8868 | 5229 | unlock: |
3ee16c81 | 5230 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 5231 | srcu_read_unlock(&kvm->srcu, idx); |
19526396 | 5232 | |
70534a73 DC |
5233 | /* |
5234 | * unfair on small ones | |
5235 | * per-vm shrinkers cry out | |
5236 | * sadness comes quickly | |
5237 | */ | |
19526396 GN |
5238 | list_move_tail(&kvm->vm_list, &vm_list); |
5239 | break; | |
3ee16c81 | 5240 | } |
3ee16c81 | 5241 | |
2f303b74 | 5242 | spin_unlock(&kvm_lock); |
70534a73 | 5243 | return freed; |
70534a73 DC |
5244 | } |
5245 | ||
5246 | static unsigned long | |
5247 | mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc) | |
5248 | { | |
45221ab6 | 5249 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); |
3ee16c81 IE |
5250 | } |
5251 | ||
5252 | static struct shrinker mmu_shrinker = { | |
70534a73 DC |
5253 | .count_objects = mmu_shrink_count, |
5254 | .scan_objects = mmu_shrink_scan, | |
3ee16c81 IE |
5255 | .seeks = DEFAULT_SEEKS * 10, |
5256 | }; | |
5257 | ||
2ddfd20e | 5258 | static void mmu_destroy_caches(void) |
b5a33a75 | 5259 | { |
53c07b18 XG |
5260 | if (pte_list_desc_cache) |
5261 | kmem_cache_destroy(pte_list_desc_cache); | |
d3d25b04 AK |
5262 | if (mmu_page_header_cache) |
5263 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
5264 | } |
5265 | ||
5266 | int kvm_mmu_module_init(void) | |
5267 | { | |
f160c7b7 JS |
5268 | kvm_mmu_clear_all_pte_masks(); |
5269 | ||
53c07b18 XG |
5270 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
5271 | sizeof(struct pte_list_desc), | |
20c2df83 | 5272 | 0, 0, NULL); |
53c07b18 | 5273 | if (!pte_list_desc_cache) |
b5a33a75 AK |
5274 | goto nomem; |
5275 | ||
d3d25b04 AK |
5276 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
5277 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 5278 | 0, 0, NULL); |
d3d25b04 AK |
5279 | if (!mmu_page_header_cache) |
5280 | goto nomem; | |
5281 | ||
908c7f19 | 5282 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL)) |
45bf21a8 WY |
5283 | goto nomem; |
5284 | ||
3ee16c81 IE |
5285 | register_shrinker(&mmu_shrinker); |
5286 | ||
b5a33a75 AK |
5287 | return 0; |
5288 | ||
5289 | nomem: | |
3ee16c81 | 5290 | mmu_destroy_caches(); |
b5a33a75 AK |
5291 | return -ENOMEM; |
5292 | } | |
5293 | ||
3ad82a7e ZX |
5294 | /* |
5295 | * Caculate mmu pages needed for kvm. | |
5296 | */ | |
5297 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
5298 | { | |
3ad82a7e ZX |
5299 | unsigned int nr_mmu_pages; |
5300 | unsigned int nr_pages = 0; | |
bc6678a3 | 5301 | struct kvm_memslots *slots; |
be6ba0f0 | 5302 | struct kvm_memory_slot *memslot; |
9da0e4d5 | 5303 | int i; |
3ad82a7e | 5304 | |
9da0e4d5 PB |
5305 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
5306 | slots = __kvm_memslots(kvm, i); | |
90d83dc3 | 5307 | |
9da0e4d5 PB |
5308 | kvm_for_each_memslot(memslot, slots) |
5309 | nr_pages += memslot->npages; | |
5310 | } | |
3ad82a7e ZX |
5311 | |
5312 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
5313 | nr_mmu_pages = max(nr_mmu_pages, | |
9da0e4d5 | 5314 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); |
3ad82a7e ZX |
5315 | |
5316 | return nr_mmu_pages; | |
5317 | } | |
5318 | ||
c42fffe3 XG |
5319 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
5320 | { | |
95f93af4 | 5321 | kvm_mmu_unload(vcpu); |
c42fffe3 XG |
5322 | free_mmu_pages(vcpu); |
5323 | mmu_free_memory_caches(vcpu); | |
b034cf01 XG |
5324 | } |
5325 | ||
b034cf01 XG |
5326 | void kvm_mmu_module_exit(void) |
5327 | { | |
5328 | mmu_destroy_caches(); | |
5329 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
5330 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
5331 | mmu_audit_disable(); |
5332 | } |